opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bd (unsigned long, long, int, const char **);
  46 static long extract_bd (unsigned long, int, int *);
  47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  48 static long extract_bdm (unsigned long, int, int *);
  49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  50 static long extract_bdp (unsigned long, int, int *);
  51 static unsigned long insert_bo (unsigned long, long, int, const char **);
  52 static long extract_bo (unsigned long, int, int *);
  53 static unsigned long insert_boe (unsigned long, long, int, const char **);
  54 static long extract_boe (unsigned long, int, int *);
  55 static unsigned long insert_dq (unsigned long, long, int, const char **);
  56 static long extract_dq (unsigned long, int, int *);
  57 static unsigned long insert_ds (unsigned long, long, int, const char **);
  58 static long extract_ds (unsigned long, int, int *);
  59 static unsigned long insert_de (unsigned long, long, int, const char **);
  60 static long extract_de (unsigned long, int, int *);
  61 static unsigned long insert_des (unsigned long, long, int, const char **);
  62 static long extract_des (unsigned long, int, int *);
  63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  64 static long extract_fxm (unsigned long, int, int *);
  65 static unsigned long insert_li (unsigned long, long, int, const char **);
  66 static long extract_li (unsigned long, int, int *);
  67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  68 static long extract_mbe (unsigned long, int, int *);
  69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  70 static long extract_mb6 (unsigned long, int, int *);
  71 static unsigned long insert_nb (unsigned long, long, int, const char **);
  72 static long extract_nb (unsigned long, int, int *);
  73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  74 static long extract_nsi (unsigned long, int, int *);
  75 static unsigned long insert_ral (unsigned long, long, int, const char **);
  76 static unsigned long insert_ram (unsigned long, long, int, const char **);
  77 static unsigned long insert_raq (unsigned long, long, int, const char **);
  78 static unsigned long insert_ras (unsigned long, long, int, const char **);
  79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  80 static long extract_rbs (unsigned long, int, int *);
  81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
  82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
  83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  84 static long extract_sh6 (unsigned long, int, int *);
  85 static unsigned long insert_spr (unsigned long, long, int, const char **);
  86 static long extract_spr (unsigned long, int, int *);
  87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  88 static long extract_tbr (unsigned long, int, int *);
  89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
  90 static long extract_ev2 (unsigned long, int, int *);
  91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
  92 static long extract_ev4 (unsigned long, int, int *);
  93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
  94 static long extract_ev8 (unsigned long, int, int *);
  95 \f
  96 /* The operands table.
  97
  98    The fields are bits, shift, insert, extract, flags.
  99
 100    We used to put parens around the various additions, like the one
 101    for BA just below.  However, that caused trouble with feeble
 102    compilers with a limit on depth of a parenthesized expression, like
 103    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 104    omit the parens, since the macros are never used in a context where
 105    the addition will be ambiguous.  */
 106
 107 const struct powerpc_operand powerpc_operands[] =
 108 {
 109   /* The zero index is used to indicate the end of the list of
 110      operands.  */
 111 #define UNUSED 0
 112   { 0, 0, 0, 0, 0 },
 113
 114   /* The BA field in an XL form instruction.  */
 115 #define BA UNUSED + 1
 116 #define BA_MASK (0x1f << 16)
 117   { 5, 16, 0, 0, PPC_OPERAND_CR },
 118
 119   /* The BA field in an XL form instruction when it must be the same
 120      as the BT field in the same instruction.  */
 121 #define BAT BA + 1
 122   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 123
 124   /* The BB field in an XL form instruction.  */
 125 #define BB BAT + 1
 126 #define BB_MASK (0x1f << 11)
 127   { 5, 11, 0, 0, PPC_OPERAND_CR },
 128
 129   /* The BB field in an XL form instruction when it must be the same
 130      as the BA field in the same instruction.  */
 131 #define BBA BB + 1
 132   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 133
 134   /* The BD field in a B form instruction.  The lower two bits are
 135      forced to zero.  */
 136 #define BD BBA + 1
 137   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when absolute addressing is
 140      used.  */
 141 #define BDA BD + 1
 142   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the - modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDM BDA + 1
 147   { 16, 0, insert_bdm, extract_bdm,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the - modifier is used
 151      and absolute address is used.  */
 152 #define BDMA BDM + 1
 153   { 16, 0, insert_bdm, extract_bdm,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BD field in a B form instruction when the + modifier is used.
 157      This sets the y bit of the BO field appropriately.  */
 158 #define BDP BDMA + 1
 159   { 16, 0, insert_bdp, extract_bdp,
 160       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 161
 162   /* The BD field in a B form instruction when the + modifier is used
 163      and absolute addressing is used.  */
 164 #define BDPA BDP + 1
 165   { 16, 0, insert_bdp, extract_bdp,
 166       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 167
 168   /* The BF field in an X or XL form instruction.  */
 169 #define BF BDPA + 1
 170   { 3, 23, 0, 0, PPC_OPERAND_CR },
 171
 172   /* An optional BF field.  This is used for comparison instructions,
 173      in which an omitted BF field is taken as zero.  */
 174 #define OBF BF + 1
 175   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 176
 177   /* The BFA field in an X or XL form instruction.  */
 178 #define BFA OBF + 1
 179   { 3, 18, 0, 0, PPC_OPERAND_CR },
 180
 181   /* The BI field in a B form or XL form instruction.  */
 182 #define BI BFA + 1
 183 #define BI_MASK (0x1f << 16)
 184   { 5, 16, 0, 0, PPC_OPERAND_CR },
 185
 186   /* The BO field in a B form instruction.  Certain values are
 187      illegal.  */
 188 #define BO BI + 1
 189 #define BO_MASK (0x1f << 21)
 190   { 5, 21, insert_bo, extract_bo, 0 },
 191
 192   /* The BO field in a B form instruction when the + or - modifier is
 193      used.  This is like the BO field, but it must be even.  */
 194 #define BOE BO + 1
 195   { 5, 21, insert_boe, extract_boe, 0 },
 196
 197   /* The BT field in an X or XL form instruction.  */
 198 #define BT BOE + 1
 199   { 5, 21, 0, 0, PPC_OPERAND_CR },
 200
 201   /* The condition register number portion of the BI field in a B form
 202      or XL form instruction.  This is used for the extended
 203      conditional branch mnemonics, which set the lower two bits of the
 204      BI field.  This field is optional.  */
 205 #define CR BT + 1
 206   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 207
 208   /* The CRB field in an X form instruction.  */
 209 #define CRB CR + 1
 210   { 5, 6, 0, 0, 0 },
 211
 212   /* The CRFD field in an X form instruction.  */
 213 #define CRFD CRB + 1
 214   { 3, 23, 0, 0, PPC_OPERAND_CR },
 215
 216   /* The CRFS field in an X form instruction.  */
 217 #define CRFS CRFD + 1
 218   { 3, 0, 0, 0, PPC_OPERAND_CR },
 219
 220   /* The CT field in an X form instruction.  */
 221 #define CT CRFS + 1
 222   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 223
 224   /* The D field in a D form instruction.  This is a displacement off
 225      a register, and implies that the next operand is a register in
 226      parentheses.  */
 227 #define D CT + 1
 228   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 229
 230   /* The DE field in a DE form instruction.  This is like D, but is 12
 231      bits only.  */
 232 #define DE D + 1
 233   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 234
 235   /* The DES field in a DES form instruction.  This is like DS, but is 14
 236      bits only (12 stored.)  */
 237 #define DES DE + 1
 238   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 239
 240   /* The DQ field in a DQ form instruction.  This is like D, but the
 241      lower four bits are forced to zero. */
 242 #define DQ DES + 1
 243   { 16, 0, insert_dq, extract_dq,
 244       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 245
 246   /* The DS field in a DS form instruction.  This is like D, but the
 247      lower two bits are forced to zero.  */
 248 #define DS DQ + 1
 249   { 16, 0, insert_ds, extract_ds,
 250       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 251
 252   /* The E field in a wrteei instruction.  */
 253 #define E DS + 1
 254   { 1, 15, 0, 0, 0 },
 255
 256   /* The FL1 field in a POWER SC form instruction.  */
 257 #define FL1 E + 1
 258   { 4, 12, 0, 0, 0 },
 259
 260   /* The FL2 field in a POWER SC form instruction.  */
 261 #define FL2 FL1 + 1
 262   { 3, 2, 0, 0, 0 },
 263
 264   /* The FLM field in an XFL form instruction.  */
 265 #define FLM FL2 + 1
 266   { 8, 17, 0, 0, 0 },
 267
 268   /* The FRA field in an X or A form instruction.  */
 269 #define FRA FLM + 1
 270 #define FRA_MASK (0x1f << 16)
 271   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 272
 273   /* The FRB field in an X or A form instruction.  */
 274 #define FRB FRA + 1
 275 #define FRB_MASK (0x1f << 11)
 276   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 277
 278   /* The FRC field in an A form instruction.  */
 279 #define FRC FRB + 1
 280 #define FRC_MASK (0x1f << 6)
 281   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 282
 283   /* The FRS field in an X form instruction or the FRT field in a D, X
 284      or A form instruction.  */
 285 #define FRS FRC + 1
 286 #define FRT FRS
 287   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 288
 289   /* The FXM field in an XFX instruction.  */
 290 #define FXM FRS + 1
 291 #define FXM_MASK (0xff << 12)
 292   { 8, 12, insert_fxm, extract_fxm, 0 },
 293
 294   /* Power4 version for mfcr.  */
 295 #define FXM4 FXM + 1
 296   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 297
 298   /* The L field in a D or X form instruction.  */
 299 #define L FXM4 + 1
 300   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 301
 302   /* The LEV field in a POWER SC form instruction.  */
 303 #define LEV L + 1
 304   { 7, 5, 0, 0, 0 },
 305
 306   /* The LI field in an I form instruction.  The lower two bits are
 307      forced to zero.  */
 308 #define LI LEV + 1
 309   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 310
 311   /* The LI field in an I form instruction when used as an absolute
 312      address.  */
 313 #define LIA LI + 1
 314   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 315
 316   /* The LS field in an X (sync) form instruction.  */
 317 #define LS LIA + 1
 318   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 319
 320   /* The MB field in an M form instruction.  */
 321 #define MB LS + 1
 322 #define MB_MASK (0x1f << 6)
 323   { 5, 6, 0, 0, 0 },
 324
 325   /* The ME field in an M form instruction.  */
 326 #define ME MB + 1
 327 #define ME_MASK (0x1f << 1)
 328   { 5, 1, 0, 0, 0 },
 329
 330   /* The MB and ME fields in an M form instruction expressed a single
 331      operand which is a bitmask indicating which bits to select.  This
 332      is a two operand form using PPC_OPERAND_NEXT.  See the
 333      description in opcode/ppc.h for what this means.  */
 334 #define MBE ME + 1
 335   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 336   { 32, 0, insert_mbe, extract_mbe, 0 },
 337
 338   /* The MB or ME field in an MD or MDS form instruction.  The high
 339      bit is wrapped to the low end.  */
 340 #define MB6 MBE + 2
 341 #define ME6 MB6
 342 #define MB6_MASK (0x3f << 5)
 343   { 6, 5, insert_mb6, extract_mb6, 0 },
 344
 345   /* The MO field in an mbar instruction.  */
 346 #define MO MB6 + 1
 347   { 5, 21, 0, 0, 0 },
 348
 349   /* The NB field in an X form instruction.  The value 32 is stored as
 350      0.  */
 351 #define NB MO + 1
 352   { 6, 11, insert_nb, extract_nb, 0 },
 353
 354   /* The NSI field in a D form instruction.  This is the same as the
 355      SI field, only negated.  */
 356 #define NSI NB + 1
 357   { 16, 0, insert_nsi, extract_nsi,
 358       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 359
 360   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 361 #define RA NSI + 1
 362 #define RA_MASK (0x1f << 16)
 363   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 364
 365   /* The RA field in the DQ form lq instruction, which has special
 366      value restrictions.  */
 367 #define RAQ RA + 1
 368   { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
 369
 370   /* The RA field in a D or X form instruction which is an updating
 371      load, which means that the RA field may not be zero and may not
 372      equal the RT field.  */
 373 #define RAL RAQ + 1
 374   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 375
 376   /* The RA field in an lmw instruction, which has special value
 377      restrictions.  */
 378 #define RAM RAL + 1
 379   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 380
 381   /* The RA field in a D or X form instruction which is an updating
 382      store or an updating floating point load, which means that the RA
 383      field may not be zero.  */
 384 #define RAS RAM + 1
 385   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 386
 387   /* The RB field in an X, XO, M, or MDS form instruction.  */
 388 #define RB RAS + 1
 389 #define RB_MASK (0x1f << 11)
 390   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 391
 392   /* The RB field in an X form instruction when it must be the same as
 393      the RS field in the instruction.  This is used for extended
 394      mnemonics like mr.  */
 395 #define RBS RB + 1
 396   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 397
 398   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 399      instruction or the RT field in a D, DS, X, XFX or XO form
 400      instruction.  */
 401 #define RS RBS + 1
 402 #define RT RS
 403 #define RT_MASK (0x1f << 21)
 404   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 405
 406   /* The RS field of the DS form stq instruction, which has special
 407      value restrictions.  */
 408 #define RSQ RS + 1
 409   { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
 410
 411   /* The RT field of the DQ form lq instruction, which has special
 412      value restrictions.  */
 413 #define RTQ RSQ + 1
 414   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
 415
 416   /* The SH field in an X or M form instruction.  */
 417 #define SH RTQ + 1
 418 #define SH_MASK (0x1f << 11)
 419   { 5, 11, 0, 0, 0 },
 420
 421   /* The SH field in an MD form instruction.  This is split.  */
 422 #define SH6 SH + 1
 423 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 424   { 6, 1, insert_sh6, extract_sh6, 0 },
 425
 426   /* The SI field in a D form instruction.  */
 427 #define SI SH6 + 1
 428   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 429
 430   /* The SI field in a D form instruction when we accept a wide range
 431      of positive values.  */
 432 #define SISIGNOPT SI + 1
 433   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 434
 435   /* The SPR field in an XFX form instruction.  This is flipped--the
 436      lower 5 bits are stored in the upper 5 and vice- versa.  */
 437 #define SPR SISIGNOPT + 1
 438 #define PMR SPR
 439 #define SPR_MASK (0x3ff << 11)
 440   { 10, 11, insert_spr, extract_spr, 0 },
 441
 442   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 443 #define SPRBAT SPR + 1
 444 #define SPRBAT_MASK (0x3 << 17)
 445   { 2, 17, 0, 0, 0 },
 446
 447   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 448 #define SPRG SPRBAT + 1
 449 #define SPRG_MASK (0x3 << 16)
 450   { 2, 16, 0, 0, 0 },
 451
 452   /* The SR field in an X form instruction.  */
 453 #define SR SPRG + 1
 454   { 4, 16, 0, 0, 0 },
 455
 456   /* The STRM field in an X AltiVec form instruction.  */
 457 #define STRM SR + 1
 458 #define STRM_MASK (0x3 << 21)
 459   { 2, 21, 0, 0, 0 },
 460
 461   /* The SV field in a POWER SC form instruction.  */
 462 #define SV STRM + 1
 463   { 14, 2, 0, 0, 0 },
 464
 465   /* The TBR field in an XFX form instruction.  This is like the SPR
 466      field, but it is optional.  */
 467 #define TBR SV + 1
 468   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 469
 470   /* The TO field in a D or X form instruction.  */
 471 #define TO TBR + 1
 472 #define TO_MASK (0x1f << 21)
 473   { 5, 21, 0, 0, 0 },
 474
 475   /* The U field in an X form instruction.  */
 476 #define U TO + 1
 477   { 4, 12, 0, 0, 0 },
 478
 479   /* The UI field in a D form instruction.  */
 480 #define UI U + 1
 481   { 16, 0, 0, 0, 0 },
 482
 483   /* The VA field in a VA, VX or VXR form instruction.  */
 484 #define VA UI + 1
 485 #define VA_MASK (0x1f << 16)
 486   { 5, 16, 0, 0, PPC_OPERAND_VR },
 487
 488   /* The VB field in a VA, VX or VXR form instruction.  */
 489 #define VB VA + 1
 490 #define VB_MASK (0x1f << 11)
 491   { 5, 11, 0, 0, PPC_OPERAND_VR },
 492
 493   /* The VC field in a VA form instruction.  */
 494 #define VC VB + 1
 495 #define VC_MASK (0x1f << 6)
 496   { 5, 6, 0, 0, PPC_OPERAND_VR },
 497
 498   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 499 #define VD VC + 1
 500 #define VS VD
 501 #define VD_MASK (0x1f << 21)
 502   { 5, 21, 0, 0, PPC_OPERAND_VR },
 503
 504   /* The SIMM field in a VX form instruction.  */
 505 #define SIMM VD + 1
 506   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 507
 508   /* The UIMM field in a VX form instruction.  */
 509 #define UIMM SIMM + 1
 510   { 5, 16, 0, 0, 0 },
 511
 512   /* The SHB field in a VA form instruction.  */
 513 #define SHB UIMM + 1
 514   { 4, 6, 0, 0, 0 },
 515
 516   /* The other UIMM field in a EVX form instruction.  */
 517 #define EVUIMM SHB + 1
 518   { 5, 11, 0, 0, 0 },
 519
 520   /* The other UIMM field in a half word EVX form instruction.  */
 521 #define EVUIMM_2 EVUIMM + 1
 522   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 523
 524   /* The other UIMM field in a word EVX form instruction.  */
 525 #define EVUIMM_4 EVUIMM_2 + 1
 526   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 527
 528   /* The other UIMM field in a double EVX form instruction.  */
 529 #define EVUIMM_8 EVUIMM_4 + 1
 530   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 531
 532   /* The WS field.  */
 533 #define WS EVUIMM_8 + 1
 534 #define WS_MASK (0x7 << 11)
 535   { 3, 11, 0, 0, 0 },
 536
 537   /* The L field in an mtmsrd instruction */
 538 #define MTMSRD_L WS + 1
 539   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 540
 541 };
 542
 543 /* The functions used to insert and extract complicated operands.  */
 544
 545 /* The BA field in an XL form instruction when it must be the same as
 546    the BT field in the same instruction.  This operand is marked FAKE.
 547    The insertion function just copies the BT field into the BA field,
 548    and the extraction function just checks that the fields are the
 549    same.  */
 550
 551 static unsigned long
 552 insert_bat (unsigned long insn,
 553             long value ATTRIBUTE_UNUSED,
 554             int dialect ATTRIBUTE_UNUSED,
 555             const char **errmsg ATTRIBUTE_UNUSED)
 556 {
 557   return insn | (((insn >> 21) & 0x1f) << 16);
 558 }
 559
 560 static long
 561 extract_bat (unsigned long insn,
 562              int dialect ATTRIBUTE_UNUSED,
 563              int *invalid)
 564 {
 565   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 566     *invalid = 1;
 567   return 0;
 568 }
 569
 570 /* The BB field in an XL form instruction when it must be the same as
 571    the BA field in the same instruction.  This operand is marked FAKE.
 572    The insertion function just copies the BA field into the BB field,
 573    and the extraction function just checks that the fields are the
 574    same.  */
 575
 576 static unsigned long
 577 insert_bba (unsigned long insn,
 578             long value ATTRIBUTE_UNUSED,
 579             int dialect ATTRIBUTE_UNUSED,
 580             const char **errmsg ATTRIBUTE_UNUSED)
 581 {
 582   return insn | (((insn >> 16) & 0x1f) << 11);
 583 }
 584
 585 static long
 586 extract_bba (unsigned long insn,
 587              int dialect ATTRIBUTE_UNUSED,
 588              int *invalid)
 589 {
 590   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 591     *invalid = 1;
 592   return 0;
 593 }
 594
 595 /* The BD field in a B form instruction.  The lower two bits are
 596    forced to zero.  */
 597
 598 static unsigned long
 599 insert_bd (unsigned long insn,
 600            long value,
 601            int dialect ATTRIBUTE_UNUSED,
 602            const char **errmsg ATTRIBUTE_UNUSED)
 603 {
 604   return insn | (value & 0xfffc);
 605 }
 606
 607 static long
 608 extract_bd (unsigned long insn,
 609             int dialect ATTRIBUTE_UNUSED,
 610             int *invalid ATTRIBUTE_UNUSED)
 611 {
 612   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 613 }
 614
 615 /* The BD field in a B form instruction when the - modifier is used.
 616    This modifier means that the branch is not expected to be taken.
 617    For chips built to versions of the architecture prior to version 2
 618    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 619    if the offset is negative.  When extracting, we require that the y
 620    bit be 1 and that the offset be positive, since if the y bit is 0
 621    we just want to print the normal form of the instruction.
 622    Power4 compatible targets use two bits, "a", and "t", instead of
 623    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 624    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 625    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 626    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 627
 628 static unsigned long
 629 insert_bdm (unsigned long insn,
 630             long value,
 631             int dialect,
 632             const char **errmsg ATTRIBUTE_UNUSED)
 633 {
 634   if ((dialect & PPC_OPCODE_POWER4) == 0)
 635     {
 636       if ((value & 0x8000) != 0)
 637         insn |= 1 << 21;
 638     }
 639   else
 640     {
 641       if ((insn & (0x14 << 21)) == (0x04 << 21))
 642         insn |= 0x02 << 21;
 643       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 644         insn |= 0x08 << 21;
 645     }
 646   return insn | (value & 0xfffc);
 647 }
 648
 649 static long
 650 extract_bdm (unsigned long insn,
 651              int dialect,
 652              int *invalid)
 653 {
 654   if ((dialect & PPC_OPCODE_POWER4) == 0)
 655     {
 656       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 657         *invalid = 1;
 658     }
 659   else
 660     {
 661       if ((insn & (0x17 << 21)) != (0x06 << 21)
 662           && (insn & (0x1d << 21)) != (0x18 << 21))
 663         *invalid = 1;
 664     }
 665
 666   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 667 }
 668
 669 /* The BD field in a B form instruction when the + modifier is used.
 670    This is like BDM, above, except that the branch is expected to be
 671    taken.  */
 672
 673 static unsigned long
 674 insert_bdp (unsigned long insn,
 675             long value,
 676             int dialect,
 677             const char **errmsg ATTRIBUTE_UNUSED)
 678 {
 679   if ((dialect & PPC_OPCODE_POWER4) == 0)
 680     {
 681       if ((value & 0x8000) == 0)
 682         insn |= 1 << 21;
 683     }
 684   else
 685     {
 686       if ((insn & (0x14 << 21)) == (0x04 << 21))
 687         insn |= 0x03 << 21;
 688       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 689         insn |= 0x09 << 21;
 690     }
 691   return insn | (value & 0xfffc);
 692 }
 693
 694 static long
 695 extract_bdp (unsigned long insn,
 696              int dialect,
 697              int *invalid)
 698 {
 699   if ((dialect & PPC_OPCODE_POWER4) == 0)
 700     {
 701       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 702         *invalid = 1;
 703     }
 704   else
 705     {
 706       if ((insn & (0x17 << 21)) != (0x07 << 21)
 707           && (insn & (0x1d << 21)) != (0x19 << 21))
 708         *invalid = 1;
 709     }
 710
 711   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 712 }
 713
 714 /* Check for legal values of a BO field.  */
 715
 716 static int
 717 valid_bo (long value, int dialect)
 718 {
 719   if ((dialect & PPC_OPCODE_POWER4) == 0)
 720     {
 721       /* Certain encodings have bits that are required to be zero.
 722          These are (z must be zero, y may be anything):
 723              001zy
 724              011zy
 725              1z00y
 726              1z01y
 727              1z1zz
 728       */
 729       switch (value & 0x14)
 730         {
 731         default:
 732         case 0:
 733           return 1;
 734         case 0x4:
 735           return (value & 0x2) == 0;
 736         case 0x10:
 737           return (value & 0x8) == 0;
 738         case 0x14:
 739           return value == 0x14;
 740         }
 741     }
 742   else
 743     {
 744       /* Certain encodings have bits that are required to be zero.
 745          These are (z must be zero, a & t may be anything):
 746              0000z
 747              0001z
 748              0100z
 749              0101z
 750              001at
 751              011at
 752              1a00t
 753              1a01t
 754              1z1zz
 755       */
 756       if ((value & 0x14) == 0)
 757         return (value & 0x1) == 0;
 758       else if ((value & 0x14) == 0x14)
 759         return value == 0x14;
 760       else
 761         return 1;
 762     }
 763 }
 764
 765 /* The BO field in a B form instruction.  Warn about attempts to set
 766    the field to an illegal value.  */
 767
 768 static unsigned long
 769 insert_bo (unsigned long insn,
 770            long value,
 771            int dialect,
 772            const char **errmsg)
 773 {
 774   if (!valid_bo (value, dialect))
 775     *errmsg = _("invalid conditional option");
 776   return insn | ((value & 0x1f) << 21);
 777 }
 778
 779 static long
 780 extract_bo (unsigned long insn,
 781             int dialect,
 782             int *invalid)
 783 {
 784   long value;
 785
 786   value = (insn >> 21) & 0x1f;
 787   if (!valid_bo (value, dialect))
 788     *invalid = 1;
 789   return value;
 790 }
 791
 792 /* The BO field in a B form instruction when the + or - modifier is
 793    used.  This is like the BO field, but it must be even.  When
 794    extracting it, we force it to be even.  */
 795
 796 static unsigned long
 797 insert_boe (unsigned long insn,
 798             long value,
 799             int dialect,
 800             const char **errmsg)
 801 {
 802   if (!valid_bo (value, dialect))
 803     *errmsg = _("invalid conditional option");
 804   else if ((value & 1) != 0)
 805     *errmsg = _("attempt to set y bit when using + or - modifier");
 806
 807   return insn | ((value & 0x1f) << 21);
 808 }
 809
 810 static long
 811 extract_boe (unsigned long insn,
 812              int dialect,
 813              int *invalid)
 814 {
 815   long value;
 816
 817   value = (insn >> 21) & 0x1f;
 818   if (!valid_bo (value, dialect))
 819     *invalid = 1;
 820   return value & 0x1e;
 821 }
 822
 823 /* The DQ field in a DQ form instruction.  This is like D, but the
 824    lower four bits are forced to zero. */
 825
 826 static unsigned long
 827 insert_dq (unsigned long insn,
 828            long value,
 829            int dialect ATTRIBUTE_UNUSED,
 830            const char **errmsg)
 831 {
 832   if ((value & 0xf) != 0)
 833     *errmsg = _("offset not a multiple of 16");
 834   return insn | (value & 0xfff0);
 835 }
 836
 837 static long
 838 extract_dq (unsigned long insn,
 839             int dialect ATTRIBUTE_UNUSED,
 840             int *invalid ATTRIBUTE_UNUSED)
 841 {
 842   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
 843 }
 844
 845 static unsigned long
 846 insert_ev2 (unsigned long insn,
 847             long value,
 848             int dialect ATTRIBUTE_UNUSED,
 849             const char **errmsg)
 850 {
 851   if ((value & 1) != 0)
 852     *errmsg = _("offset not a multiple of 2");
 853   if ((value > 62) != 0)
 854     *errmsg = _("offset greater than 62");
 855   return insn | ((value & 0x3e) << 10);
 856 }
 857
 858 static long
 859 extract_ev2 (unsigned long insn,
 860              int dialect ATTRIBUTE_UNUSED,
 861              int *invalid ATTRIBUTE_UNUSED)
 862 {
 863   return (insn >> 10) & 0x3e;
 864 }
 865
 866 static unsigned long
 867 insert_ev4 (unsigned long insn,
 868             long value,
 869             int dialect ATTRIBUTE_UNUSED,
 870             const char **errmsg)
 871 {
 872   if ((value & 3) != 0)
 873     *errmsg = _("offset not a multiple of 4");
 874   if ((value > 124) != 0)
 875     *errmsg = _("offset greater than 124");
 876   return insn | ((value & 0x7c) << 9);
 877 }
 878
 879 static long
 880 extract_ev4 (unsigned long insn,
 881              int dialect ATTRIBUTE_UNUSED,
 882              int *invalid ATTRIBUTE_UNUSED)
 883 {
 884   return (insn >> 9) & 0x7c;
 885 }
 886
 887 static unsigned long
 888 insert_ev8 (unsigned long insn,
 889             long value,
 890             int dialect ATTRIBUTE_UNUSED,
 891             const char **errmsg)
 892 {
 893   if ((value & 7) != 0)
 894     *errmsg = _("offset not a multiple of 8");
 895   if ((value > 248) != 0)
 896     *errmsg = _("offset greater than 248");
 897   return insn | ((value & 0xf8) << 8);
 898 }
 899
 900 static long
 901 extract_ev8 (unsigned long insn,
 902              int dialect ATTRIBUTE_UNUSED,
 903              int *invalid ATTRIBUTE_UNUSED)
 904 {
 905   return (insn >> 8) & 0xf8;
 906 }
 907
 908 /* The DS field in a DS form instruction.  This is like D, but the
 909    lower two bits are forced to zero.  */
 910
 911 static unsigned long
 912 insert_ds (unsigned long insn,
 913            long value,
 914            int dialect ATTRIBUTE_UNUSED,
 915            const char **errmsg)
 916 {
 917   if ((value & 3) != 0)
 918     *errmsg = _("offset not a multiple of 4");
 919   return insn | (value & 0xfffc);
 920 }
 921
 922 static long
 923 extract_ds (unsigned long insn,
 924             int dialect ATTRIBUTE_UNUSED,
 925             int *invalid ATTRIBUTE_UNUSED)
 926 {
 927   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 928 }
 929
 930 /* The DE field in a DE form instruction.  */
 931
 932 static unsigned long
 933 insert_de (unsigned long insn,
 934            long value,
 935            int dialect ATTRIBUTE_UNUSED,
 936            const char **errmsg)
 937 {
 938   if (value > 2047 || value < -2048)
 939     *errmsg = _("offset not between -2048 and 2047");
 940   return insn | ((value << 4) & 0xfff0);
 941 }
 942
 943 static long
 944 extract_de (unsigned long insn,
 945             int dialect ATTRIBUTE_UNUSED,
 946             int *invalid ATTRIBUTE_UNUSED)
 947 {
 948   return (insn & 0xfff0) >> 4;
 949 }
 950
 951 /* The DES field in a DES form instruction.  */
 952
 953 static unsigned long
 954 insert_des (unsigned long insn,
 955             long value,
 956             int dialect ATTRIBUTE_UNUSED,
 957             const char **errmsg)
 958 {
 959   if (value > 8191 || value < -8192)
 960     *errmsg = _("offset not between -8192 and 8191");
 961   else if ((value & 3) != 0)
 962     *errmsg = _("offset not a multiple of 4");
 963   return insn | ((value << 2) & 0xfff0);
 964 }
 965
 966 static long
 967 extract_des (unsigned long insn,
 968              int dialect ATTRIBUTE_UNUSED,
 969              int *invalid ATTRIBUTE_UNUSED)
 970 {
 971   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 972 }
 973
 974 /* FXM mask in mfcr and mtcrf instructions.  */
 975
 976 static unsigned long
 977 insert_fxm (unsigned long insn,
 978             long value,
 979             int dialect,
 980             const char **errmsg)
 981 {
 982   /* If the optional field on mfcr is missing that means we want to use
 983      the old form of the instruction that moves the whole cr.  In that
 984      case we'll have VALUE zero.  There doesn't seem to be a way to
 985      distinguish this from the case where someone writes mfcr %r3,0.  */
 986   if (value == 0)
 987     ;
 988
 989   /* If only one bit of the FXM field is set, we can use the new form
 990      of the instruction, which is faster.  Unlike the Power4 branch hint
 991      encoding, this is not backward compatible.  */
 992   else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
 993     insn |= 1 << 20;
 994
 995   /* Any other value on mfcr is an error.  */
 996   else if ((insn & (0x3ff << 1)) == 19 << 1)
 997     {
 998       *errmsg = _("ignoring invalid mfcr mask");
 999       value = 0;
1000     }
1001
1002   return insn | ((value & 0xff) << 12);
1003 }
1004
1005 static long
1006 extract_fxm (unsigned long insn,
1007              int dialect,
1008              int *invalid)
1009 {
1010   long mask = (insn >> 12) & 0xff;
1011
1012   /* Is this a Power4 insn?  */
1013   if ((insn & (1 << 20)) != 0)
1014     {
1015       if ((dialect & PPC_OPCODE_POWER4) == 0)
1016         *invalid = 1;
1017       else
1018         {
1019           /* Exactly one bit of MASK should be set.  */
1020           if (mask == 0 || (mask & -mask) != mask)
1021             *invalid = 1;
1022         }
1023     }
1024
1025   /* Check that non-power4 form of mfcr has a zero MASK.  */
1026   else if ((insn & (0x3ff << 1)) == 19 << 1)
1027     {
1028       if (mask != 0)
1029         *invalid = 1;
1030     }
1031
1032   return mask;
1033 }
1034
1035 /* The LI field in an I form instruction.  The lower two bits are
1036    forced to zero.  */
1037
1038 static unsigned long
1039 insert_li (unsigned long insn,
1040            long value,
1041            int dialect ATTRIBUTE_UNUSED,
1042            const char **errmsg)
1043 {
1044   if ((value & 3) != 0)
1045     *errmsg = _("ignoring least significant bits in branch offset");
1046   return insn | (value & 0x3fffffc);
1047 }
1048
1049 static long
1050 extract_li (unsigned long insn,
1051             int dialect ATTRIBUTE_UNUSED,
1052             int *invalid ATTRIBUTE_UNUSED)
1053 {
1054   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1055 }
1056
1057 /* The MB and ME fields in an M form instruction expressed as a single
1058    operand which is itself a bitmask.  The extraction function always
1059    marks it as invalid, since we never want to recognize an
1060    instruction which uses a field of this type.  */
1061
1062 static unsigned long
1063 insert_mbe (unsigned long insn,
1064             long value,
1065             int dialect ATTRIBUTE_UNUSED,
1066             const char **errmsg)
1067 {
1068   unsigned long uval, mask;
1069   int mb, me, mx, count, last;
1070
1071   uval = value;
1072
1073   if (uval == 0)
1074     {
1075       *errmsg = _("illegal bitmask");
1076       return insn;
1077     }
1078
1079   mb = 0;
1080   me = 32;
1081   if ((uval & 1) != 0)
1082     last = 1;
1083   else
1084     last = 0;
1085   count = 0;
1086
1087   /* mb: location of last 0->1 transition */
1088   /* me: location of last 1->0 transition */
1089   /* count: # transitions */
1090
1091   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1092     {
1093       if ((uval & mask) && !last)
1094         {
1095           ++count;
1096           mb = mx;
1097           last = 1;
1098         }
1099       else if (!(uval & mask) && last)
1100         {
1101           ++count;
1102           me = mx;
1103           last = 0;
1104         }
1105     }
1106   if (me == 0)
1107     me = 32;
1108
1109   if (count != 2 && (count != 0 || ! last))
1110     *errmsg = _("illegal bitmask");
1111
1112   return insn | (mb << 6) | ((me - 1) << 1);
1113 }
1114
1115 static long
1116 extract_mbe (unsigned long insn,
1117              int dialect ATTRIBUTE_UNUSED,
1118              int *invalid)
1119 {
1120   long ret;
1121   int mb, me;
1122   int i;
1123
1124   *invalid = 1;
1125
1126   mb = (insn >> 6) & 0x1f;
1127   me = (insn >> 1) & 0x1f;
1128   if (mb < me + 1)
1129     {
1130       ret = 0;
1131       for (i = mb; i <= me; i++)
1132         ret |= 1L << (31 - i);
1133     }
1134   else if (mb == me + 1)
1135     ret = ~0;
1136   else /* (mb > me + 1) */
1137     {
1138       ret = ~0;
1139       for (i = me + 1; i < mb; i++)
1140         ret &= ~(1L << (31 - i));
1141     }
1142   return ret;
1143 }
1144
1145 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1146    is wrapped to the low end.  */
1147
1148 static unsigned long
1149 insert_mb6 (unsigned long insn,
1150             long value,
1151             int dialect ATTRIBUTE_UNUSED,
1152             const char **errmsg ATTRIBUTE_UNUSED)
1153 {
1154   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1155 }
1156
1157 static long
1158 extract_mb6 (unsigned long insn,
1159              int dialect ATTRIBUTE_UNUSED,
1160              int *invalid ATTRIBUTE_UNUSED)
1161 {
1162   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1163 }
1164
1165 /* The NB field in an X form instruction.  The value 32 is stored as
1166    0.  */
1167
1168 static unsigned long
1169 insert_nb (unsigned long insn,
1170            long value,
1171            int dialect ATTRIBUTE_UNUSED,
1172            const char **errmsg)
1173 {
1174   if (value < 0 || value > 32)
1175     *errmsg = _("value out of range");
1176   if (value == 32)
1177     value = 0;
1178   return insn | ((value & 0x1f) << 11);
1179 }
1180
1181 static long
1182 extract_nb (unsigned long insn,
1183             int dialect ATTRIBUTE_UNUSED,
1184             int *invalid ATTRIBUTE_UNUSED)
1185 {
1186   long ret;
1187
1188   ret = (insn >> 11) & 0x1f;
1189   if (ret == 0)
1190     ret = 32;
1191   return ret;
1192 }
1193
1194 /* The NSI field in a D form instruction.  This is the same as the SI
1195    field, only negated.  The extraction function always marks it as
1196    invalid, since we never want to recognize an instruction which uses
1197    a field of this type.  */
1198
1199 static unsigned long
1200 insert_nsi (unsigned long insn,
1201             long value,
1202             int dialect ATTRIBUTE_UNUSED,
1203             const char **errmsg ATTRIBUTE_UNUSED)
1204 {
1205   return insn | (-value & 0xffff);
1206 }
1207
1208 static long
1209 extract_nsi (unsigned long insn,
1210              int dialect ATTRIBUTE_UNUSED,
1211              int *invalid)
1212 {
1213   *invalid = 1;
1214   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1215 }
1216
1217 /* The RA field in a D or X form instruction which is an updating
1218    load, which means that the RA field may not be zero and may not
1219    equal the RT field.  */
1220
1221 static unsigned long
1222 insert_ral (unsigned long insn,
1223             long value,
1224             int dialect ATTRIBUTE_UNUSED,
1225             const char **errmsg)
1226 {
1227   if (value == 0
1228       || (unsigned long) value == ((insn >> 21) & 0x1f))
1229     *errmsg = "invalid register operand when updating";
1230   return insn | ((value & 0x1f) << 16);
1231 }
1232
1233 /* The RA field in an lmw instruction, which has special value
1234    restrictions.  */
1235
1236 static unsigned long
1237 insert_ram (unsigned long insn,
1238             long value,
1239             int dialect ATTRIBUTE_UNUSED,
1240             const char **errmsg)
1241 {
1242   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1243     *errmsg = _("index register in load range");
1244   return insn | ((value & 0x1f) << 16);
1245 }
1246
1247 /* The RA field in the DQ form lq instruction, which has special
1248    value restrictions.  */
1249
1250 static unsigned long
1251 insert_raq (unsigned long insn,
1252             long value,
1253             int dialect ATTRIBUTE_UNUSED,
1254             const char **errmsg)
1255 {
1256   long rtvalue = (insn & RT_MASK) >> 21;
1257
1258   if (value == rtvalue)
1259     *errmsg = _("source and target register operands must be different");
1260   return insn | ((value & 0x1f) << 16);
1261 }
1262
1263 /* The RA field in a D or X form instruction which is an updating
1264    store or an updating floating point load, which means that the RA
1265    field may not be zero.  */
1266
1267 static unsigned long
1268 insert_ras (unsigned long insn,
1269             long value,
1270             int dialect ATTRIBUTE_UNUSED,
1271             const char **errmsg)
1272 {
1273   if (value == 0)
1274     *errmsg = _("invalid register operand when updating");
1275   return insn | ((value & 0x1f) << 16);
1276 }
1277
1278 /* The RB field in an X form instruction when it must be the same as
1279    the RS field in the instruction.  This is used for extended
1280    mnemonics like mr.  This operand is marked FAKE.  The insertion
1281    function just copies the BT field into the BA field, and the
1282    extraction function just checks that the fields are the same.  */
1283
1284 static unsigned long
1285 insert_rbs (unsigned long insn,
1286             long value ATTRIBUTE_UNUSED,
1287             int dialect ATTRIBUTE_UNUSED,
1288             const char **errmsg ATTRIBUTE_UNUSED)
1289 {
1290   return insn | (((insn >> 21) & 0x1f) << 11);
1291 }
1292
1293 static long
1294 extract_rbs (unsigned long insn,
1295              int dialect ATTRIBUTE_UNUSED,
1296              int *invalid)
1297 {
1298   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1299     *invalid = 1;
1300   return 0;
1301 }
1302
1303 /* The RT field of the DQ form lq instruction, which has special
1304    value restrictions.  */
1305
1306 static unsigned long
1307 insert_rtq (unsigned long insn,
1308             long value,
1309             int dialect ATTRIBUTE_UNUSED,
1310             const char **errmsg)
1311 {
1312   if ((value & 1) != 0)
1313     *errmsg = _("target register operand must be even");
1314   return insn | ((value & 0x1f) << 21);
1315 }
1316
1317 /* The RS field of the DS form stq instruction, which has special
1318    value restrictions.  */
1319
1320 static unsigned long
1321 insert_rsq (unsigned long insn,
1322             long value ATTRIBUTE_UNUSED,
1323             int dialect ATTRIBUTE_UNUSED,
1324             const char **errmsg)
1325 {
1326   if ((value & 1) != 0)
1327     *errmsg = _("source register operand must be even");
1328   return insn | ((value & 0x1f) << 21);
1329 }
1330
1331 /* The SH field in an MD form instruction.  This is split.  */
1332
1333 static unsigned long
1334 insert_sh6 (unsigned long insn,
1335             long value,
1336             int dialect ATTRIBUTE_UNUSED,
1337             const char **errmsg ATTRIBUTE_UNUSED)
1338 {
1339   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1340 }
1341
1342 static long
1343 extract_sh6 (unsigned long insn,
1344              int dialect ATTRIBUTE_UNUSED,
1345              int *invalid ATTRIBUTE_UNUSED)
1346 {
1347   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1348 }
1349
1350 /* The SPR field in an XFX form instruction.  This is flipped--the
1351    lower 5 bits are stored in the upper 5 and vice- versa.  */
1352
1353 static unsigned long
1354 insert_spr (unsigned long insn,
1355             long value,
1356             int dialect ATTRIBUTE_UNUSED,
1357             const char **errmsg ATTRIBUTE_UNUSED)
1358 {
1359   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1360 }
1361
1362 static long
1363 extract_spr (unsigned long insn,
1364              int dialect ATTRIBUTE_UNUSED,
1365              int *invalid ATTRIBUTE_UNUSED)
1366 {
1367   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1368 }
1369
1370 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1371    is optional.  When TBR is omitted, it must be inserted as 268 (the
1372    magic number of the TB register).  These functions treat 0
1373    (indicating an omitted optional operand) as 268.  This means that
1374    ``mftb 4,0'' is not handled correctly.  This does not matter very
1375    much, since the architecture manual does not define mftb as
1376    accepting any values other than 268 or 269.  */
1377
1378 #define TB (268)
1379
1380 static unsigned long
1381 insert_tbr (unsigned long insn,
1382             long value,
1383             int dialect ATTRIBUTE_UNUSED,
1384             const char **errmsg ATTRIBUTE_UNUSED)
1385 {
1386   if (value == 0)
1387     value = TB;
1388   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1389 }
1390
1391 static long
1392 extract_tbr (unsigned long insn,
1393              int dialect ATTRIBUTE_UNUSED,
1394              int *invalid ATTRIBUTE_UNUSED)
1395 {
1396   long ret;
1397
1398   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1399   if (ret == TB)
1400     ret = 0;
1401   return ret;
1402 }
1403 \f
1404 /* Macros used to form opcodes.  */
1405
1406 /* The main opcode.  */
1407 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1408 #define OP_MASK OP (0x3f)
1409
1410 /* The main opcode combined with a trap code in the TO field of a D
1411    form instruction.  Used for extended mnemonics for the trap
1412    instructions.  */
1413 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1414 #define OPTO_MASK (OP_MASK | TO_MASK)
1415
1416 /* The main opcode combined with a comparison size bit in the L field
1417    of a D form or X form instruction.  Used for extended mnemonics for
1418    the comparison instructions.  */
1419 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1420 #define OPL_MASK OPL (0x3f,1)
1421
1422 /* An A form instruction.  */
1423 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1424 #define A_MASK A (0x3f, 0x1f, 1)
1425
1426 /* An A_MASK with the FRB field fixed.  */
1427 #define AFRB_MASK (A_MASK | FRB_MASK)
1428
1429 /* An A_MASK with the FRC field fixed.  */
1430 #define AFRC_MASK (A_MASK | FRC_MASK)
1431
1432 /* An A_MASK with the FRA and FRC fields fixed.  */
1433 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1434
1435 /* A B form instruction.  */
1436 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1437 #define B_MASK B (0x3f, 1, 1)
1438
1439 /* A B form instruction setting the BO field.  */
1440 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1441 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1442
1443 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1444    matching a conditional branch regardless of the setting of the y
1445    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1446 #define Y_MASK   (((unsigned long) 1) << 21)
1447 #define AT1_MASK (((unsigned long) 3) << 21)
1448 #define AT2_MASK (((unsigned long) 9) << 21)
1449 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1450 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1451
1452 /* A B form instruction setting the BO field and the condition bits of
1453    the BI field.  */
1454 #define BBOCB(op, bo, cb, aa, lk) \
1455   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1456 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1457
1458 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1459 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1460 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1461 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1462
1463 /* A BBOYCB_MASK in which the BI field is fixed.  */
1464 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1465 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1466
1467 /* An Context form instruction.  */
1468 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1469 #define CTX_MASK       CTX(0x3f, 0x7)
1470
1471 /* An User Context form instruction.  */
1472 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1473 #define UCTX_MASK      UCTX(0x3f, 0x1f)
1474
1475 /* The main opcode mask with the RA field clear.  */
1476 #define DRA_MASK (OP_MASK | RA_MASK)
1477
1478 /* A DS form instruction.  */
1479 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1480 #define DS_MASK DSO (0x3f, 3)
1481
1482 /* A DE form instruction.  */
1483 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1484 #define DE_MASK DEO (0x3e, 0xf)
1485
1486 /* An EVSEL form instruction.  */
1487 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1488 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1489
1490 /* An M form instruction.  */
1491 #define M(op, rc) (OP (op) | ((rc) & 1))
1492 #define M_MASK M (0x3f, 1)
1493
1494 /* An M form instruction with the ME field specified.  */
1495 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1496
1497 /* An M_MASK with the MB and ME fields fixed.  */
1498 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1499
1500 /* An M_MASK with the SH and ME fields fixed.  */
1501 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1502
1503 /* An MD form instruction.  */
1504 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1505 #define MD_MASK MD (0x3f, 0x7, 1)
1506
1507 /* An MD_MASK with the MB field fixed.  */
1508 #define MDMB_MASK (MD_MASK | MB6_MASK)
1509
1510 /* An MD_MASK with the SH field fixed.  */
1511 #define MDSH_MASK (MD_MASK | SH6_MASK)
1512
1513 /* An MDS form instruction.  */
1514 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1515 #define MDS_MASK MDS (0x3f, 0xf, 1)
1516
1517 /* An MDS_MASK with the MB field fixed.  */
1518 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1519
1520 /* An SC form instruction.  */
1521 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1522 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1523
1524 /* An VX form instruction.  */
1525 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1526
1527 /* The mask for an VX form instruction.  */
1528 #define VX_MASK VX(0x3f, 0x7ff)
1529
1530 /* An VA form instruction.  */
1531 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1532
1533 /* The mask for an VA form instruction.  */
1534 #define VXA_MASK VXA(0x3f, 0x3f)
1535
1536 /* An VXR form instruction.  */
1537 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1538
1539 /* The mask for a VXR form instruction.  */
1540 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1541
1542 /* An X form instruction.  */
1543 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1544
1545 /* An X form instruction with the RC bit specified.  */
1546 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1547
1548 /* The mask for an X form instruction.  */
1549 #define X_MASK XRC (0x3f, 0x3ff, 1)
1550
1551 /* An X_MASK with the RA field fixed.  */
1552 #define XRA_MASK (X_MASK | RA_MASK)
1553
1554 /* An X_MASK with the RB field fixed.  */
1555 #define XRB_MASK (X_MASK | RB_MASK)
1556
1557 /* An X_MASK with the RT field fixed.  */
1558 #define XRT_MASK (X_MASK | RT_MASK)
1559
1560 /* An X_MASK with the RA and RB fields fixed.  */
1561 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1562
1563 /* An XRARB_MASK, but with the L bit clear.  */
1564 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1565
1566 /* An X_MASK with the RT and RA fields fixed.  */
1567 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1568
1569 /* An XRTRA_MASK, but with L bit clear.  */
1570 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1571
1572 /* An X form comparison instruction.  */
1573 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1574
1575 /* The mask for an X form comparison instruction.  */
1576 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1577
1578 /* The mask for an X form comparison instruction with the L field
1579    fixed.  */
1580 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1581
1582 /* An X form trap instruction with the TO field specified.  */
1583 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1584 #define XTO_MASK (X_MASK | TO_MASK)
1585
1586 /* An X form tlb instruction with the SH field specified.  */
1587 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1588 #define XTLB_MASK (X_MASK | SH_MASK)
1589
1590 /* An X form sync instruction.  */
1591 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1592
1593 /* An X form sync instruction with everything filled in except the LS field.  */
1594 #define XSYNC_MASK (0xff9fffff)
1595
1596 /* An X form AltiVec dss instruction.  */
1597 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1598 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1599
1600 /* An XFL form instruction.  */
1601 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1602 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1603
1604 /* An X form isel instruction.  */
1605 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1606 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1607
1608 /* An XL form instruction with the LK field set to 0.  */
1609 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1610
1611 /* An XL form instruction which uses the LK field.  */
1612 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1613
1614 /* The mask for an XL form instruction.  */
1615 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1616
1617 /* An XL form instruction which explicitly sets the BO field.  */
1618 #define XLO(op, bo, xop, lk) \
1619   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1620 #define XLO_MASK (XL_MASK | BO_MASK)
1621
1622 /* An XL form instruction which explicitly sets the y bit of the BO
1623    field.  */
1624 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1625 #define XLYLK_MASK (XL_MASK | Y_MASK)
1626
1627 /* An XL form instruction which sets the BO field and the condition
1628    bits of the BI field.  */
1629 #define XLOCB(op, bo, cb, xop, lk) \
1630   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1631 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1632
1633 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1634 #define XLBB_MASK (XL_MASK | BB_MASK)
1635 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1636 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1637
1638 /* An XL_MASK with the BO and BB fields fixed.  */
1639 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1640
1641 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1642 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1643
1644 /* An XO form instruction.  */
1645 #define XO(op, xop, oe, rc) \
1646   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1647 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1648
1649 /* An XO_MASK with the RB field fixed.  */
1650 #define XORB_MASK (XO_MASK | RB_MASK)
1651
1652 /* An XS form instruction.  */
1653 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1654 #define XS_MASK XS (0x3f, 0x1ff, 1)
1655
1656 /* A mask for the FXM version of an XFX form instruction.  */
1657 #define XFXFXM_MASK (X_MASK | (1 << 11))
1658
1659 /* An XFX form instruction with the FXM field filled in.  */
1660 #define XFXM(op, xop, fxm) \
1661   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1662
1663 /* An XFX form instruction with the SPR field filled in.  */
1664 #define XSPR(op, xop, spr) \
1665   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1666 #define XSPR_MASK (X_MASK | SPR_MASK)
1667
1668 /* An XFX form instruction with the SPR field filled in except for the
1669    SPRBAT field.  */
1670 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1671
1672 /* An XFX form instruction with the SPR field filled in except for the
1673    SPRG field.  */
1674 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1675
1676 /* An X form instruction with everything filled in except the E field.  */
1677 #define XE_MASK (0xffff7fff)
1678
1679 /* An X form user context instruction.  */
1680 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1681 #define XUC_MASK      XUC(0x3f, 0x1f)
1682
1683 /* The BO encodings used in extended conditional branch mnemonics.  */
1684 #define BODNZF  (0x0)
1685 #define BODNZFP (0x1)
1686 #define BODZF   (0x2)
1687 #define BODZFP  (0x3)
1688 #define BODNZT  (0x8)
1689 #define BODNZTP (0x9)
1690 #define BODZT   (0xa)
1691 #define BODZTP  (0xb)
1692
1693 #define BOF     (0x4)
1694 #define BOFP    (0x5)
1695 #define BOFM4   (0x6)
1696 #define BOFP4   (0x7)
1697 #define BOT     (0xc)
1698 #define BOTP    (0xd)
1699 #define BOTM4   (0xe)
1700 #define BOTP4   (0xf)
1701
1702 #define BODNZ   (0x10)
1703 #define BODNZP  (0x11)
1704 #define BODZ    (0x12)
1705 #define BODZP   (0x13)
1706 #define BODNZM4 (0x18)
1707 #define BODNZP4 (0x19)
1708 #define BODZM4  (0x1a)
1709 #define BODZP4  (0x1b)
1710
1711 #define BOU     (0x14)
1712
1713 /* The BI condition bit encodings used in extended conditional branch
1714    mnemonics.  */
1715 #define CBLT    (0)
1716 #define CBGT    (1)
1717 #define CBEQ    (2)
1718 #define CBSO    (3)
1719
1720 /* The TO encodings used in extended trap mnemonics.  */
1721 #define TOLGT   (0x1)
1722 #define TOLLT   (0x2)
1723 #define TOEQ    (0x4)
1724 #define TOLGE   (0x5)
1725 #define TOLNL   (0x5)
1726 #define TOLLE   (0x6)
1727 #define TOLNG   (0x6)
1728 #define TOGT    (0x8)
1729 #define TOGE    (0xc)
1730 #define TONL    (0xc)
1731 #define TOLT    (0x10)
1732 #define TOLE    (0x14)
1733 #define TONG    (0x14)
1734 #define TONE    (0x18)
1735 #define TOU     (0x1f)
1736 \f
1737 /* Smaller names for the flags so each entry in the opcodes table will
1738    fit on a single line.  */
1739 #undef  PPC
1740 #define PPC     PPC_OPCODE_PPC
1741 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1742 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1743 #define POWER4  PPC_OPCODE_POWER4
1744 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1745 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1746 #define PPC403  PPC_OPCODE_403
1747 #define PPC405  PPC403
1748 #define PPC440  PPC_OPCODE_440
1749 #define PPC750  PPC
1750 #define PPC860  PPC
1751 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1752 #define POWER   PPC_OPCODE_POWER
1753 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1754 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1755 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1756 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1757 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1758 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1759 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1760 #define MFDEC1  PPC_OPCODE_POWER
1761 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1762 #define BOOKE   PPC_OPCODE_BOOKE
1763 #define BOOKE64 PPC_OPCODE_BOOKE64
1764 #define CLASSIC PPC_OPCODE_CLASSIC
1765 #define PPCSPE  PPC_OPCODE_SPE
1766 #define PPCISEL PPC_OPCODE_ISEL
1767 #define PPCEFS  PPC_OPCODE_EFS
1768 #define PPCBRLK PPC_OPCODE_BRLOCK
1769 #define PPCPMR  PPC_OPCODE_PMR
1770 #define PPCCHLK PPC_OPCODE_CACHELCK
1771 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1772 #define PPCRFMCI        PPC_OPCODE_RFMCI
1773 \f
1774 /* The opcode table.
1775
1776    The format of the opcode table is:
1777
1778    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1779
1780    NAME is the name of the instruction.
1781    OPCODE is the instruction opcode.
1782    MASK is the opcode mask; this is used to tell the disassembler
1783      which bits in the actual opcode must match OPCODE.
1784    FLAGS are flags indicated what processors support the instruction.
1785    OPERANDS is the list of operands.
1786
1787    The disassembler reads the table in order and prints the first
1788    instruction which matches, so this table is sorted to put more
1789    specific instructions before more general instructions.  It is also
1790    sorted by major opcode.  */
1791
1792 const struct powerpc_opcode powerpc_opcodes[] = {
1793 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1794 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1795 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1796 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1797 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1798 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1799 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1800 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1801 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1802 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1803 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1804 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1805 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1806 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1807 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1808 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1809
1810 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1811 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1812 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1813 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1814 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1815 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1816 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1817 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1818 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1819 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1820 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1821 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1822 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1823 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1824 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1825 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1826 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1827 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1828 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1829 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1830 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1831 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1832 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1833 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1834 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1835 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1836 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1837 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1838 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1839 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1840
1841 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1842 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1843 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1844 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1845 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1846 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1847 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1848 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1849 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1850 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1851 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1852 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1853 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1854 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1855 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1856 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1857 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1858 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1859 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1860 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1861 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1862 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1863 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1864 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1865 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1866 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1867 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1868 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1869 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1870 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1871 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1872 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1873 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1874 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1875 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1876 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1877 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1878 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1879 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1880 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1881 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1882 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1883 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1884 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1885 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1886 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1887 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1888 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1889 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1890 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1891 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1892 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1893 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1894 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1895 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1896 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1897 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1898 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1899 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1900 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1901 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1902 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1903 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1904 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1905 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1906 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1907 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1908 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1909 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1910 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1911 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1912 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1913 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1914 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1915 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1916 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1917 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1918 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1919 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1920 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1921 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1922 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1923 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1924 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1925 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1926 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1927 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1928 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1929 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1930 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1931 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1932 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1933 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1934 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1935 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1936 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1937 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1938 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1939 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1940 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1941 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1942 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1943 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1944 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1945 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1946 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1947 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1948 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1949 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1950 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1951 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1952 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1953 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1954 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1955 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1956 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1957 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1958 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1959 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1960 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1961 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1962 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1963 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1964 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1965 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1966 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1967 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1968 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1969 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1970 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1971 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1972 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1973 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1974 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1975 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1976 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1977 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1978 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1979 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1980 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1981 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1982 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1983 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1984 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1985 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1986 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1987 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1988 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1989 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1990 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1991 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1992 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1993 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1994 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1995 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1996 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1997 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1998 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1999 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2000 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2001 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2002 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2003 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2004 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2005 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2006 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2007 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2008 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2010 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2011 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2012 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2013 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2014 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2015 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2016 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2017 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2018 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2019 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2020 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2021 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2022 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2023 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2024 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2025 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2026 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2027 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2028 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2029 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2030 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2031 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2032 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2033 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2034 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2035 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2036 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2037 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2038 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2039 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2040 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2041 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2042 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2043 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2044 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2045 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2046 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2047 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2048 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2049 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2050 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2051 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2052 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2053 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2054 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2055 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2056 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2057 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2058 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2059 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2060 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2061 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2062 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2063 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2064 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2065 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2066 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2067 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2068 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2069 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2070 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2071 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2072 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2073 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2074 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2075 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2076 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2077 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2078 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2079 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2080 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2081 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2082
2083 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2084 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2085 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2086 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2087 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2088 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2089 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2090 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2091 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2092 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2093 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2094 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2095 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2096
2097 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2098
2099 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2100 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2101 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2102 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2103 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2104 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2105 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2106 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2107 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2108 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2109
2110 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2111 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2112 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2113 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2114 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2115 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2116 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2117 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2118 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2119 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2120 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2121 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2122 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2123 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2124
2125 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2126 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2127 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2128 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2129 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2130 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2131
2132 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2133 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2134 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2135 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2136 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2137 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2138 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2139 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2140 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2141 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2142 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2143 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2144 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2145 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2146 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2147 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2148 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2149 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2150 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2151 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2152 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2153 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2154
2155 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2156 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2157 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2158 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2159 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2160 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2161 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2162 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2163 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2164 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2165 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2166 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2167 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2168 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2169
2170 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2171 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2172 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2173 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2174 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2175 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2176 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2177 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2178 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2179 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2180 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2181 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2182 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2183 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2184 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2185 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2186 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2187 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2188 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2189 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2190 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2191 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2192 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2193
2194 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2195 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2196 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2197 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2198 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2199 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2200 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2201 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2202 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2203 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2204 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2205 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2206 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2207 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2208 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2209 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2210 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2211 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2212 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2213 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2214 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2215 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2216 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2217
2218 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2219 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2220 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2221 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2222 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2223 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2224 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2225 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2226 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2227 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2228 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2229 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2230 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2231 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2232 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2233 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2234
2235 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2236 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2237 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2238 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2239 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2240 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2241 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2242 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2243 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2244 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2245 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2246 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2247
2248 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2249 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2250 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2251 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2252 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2253 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2254 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2255 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2256 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2257 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2258 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2259 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2260
2261 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2262 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2263 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2264 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2265 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2266 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2267
2268 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2269 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2270 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2271 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2272 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2273 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2274
2275 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2276 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2277 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2278 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2279 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2280 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2281 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2282 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2283
2284 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2285 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2286
2287 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2288 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2289 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2290 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2291
2292 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2293 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2294 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2295 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2296
2297 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2298 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2299 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2300 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2301 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2302 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2303 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2304 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2305
2306 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2307 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2308 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2309 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2310
2311 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2312 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2313 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2314 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2315
2316 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2317 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2318 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2319 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2320
2321 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2322 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2323 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2324 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2325
2326 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2327
2328 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2329 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2330
2331 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2332 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2333
2334 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2335 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2336
2337 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2338
2339 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2340 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2341 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2342 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2343
2344 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2345 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2346 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2347 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2348
2349 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2350 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2351 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2352 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2353
2354 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2355 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2356 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2357
2358 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2359 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2360 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2361
2362 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2363 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2364 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2365 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2366 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2367 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
2368
2369 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2370 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2371 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
2372 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
2373 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2374
2375 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2376 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2377 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2378 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2379 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2380 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2381 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2382 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2383 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2384 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2385 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2386 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2387 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2388 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2389 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2390 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2391 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2392 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2393 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2394 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2395 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2396 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2397 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2398 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2399 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2400 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2401 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2402 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2403 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2404 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2405 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2406 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2407 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2408 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2409 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2410 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2411 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2412 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2413 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2414 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2415 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2416 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2417 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2418 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2419 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2420 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2421 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2422 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2423 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2424 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2425 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2426 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2427 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2428 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2429 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2430 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2431 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2432 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2433 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2434 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2435 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2436 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2437 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2438 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2439 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2440 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2441 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2442 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2443 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2444 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2445 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2446 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2447 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2448 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2449 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2450 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2451 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2452 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2453 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2454 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2455 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2456 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2457 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2458 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2459 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2460 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2461 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2462 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2463 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2464 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2465 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2466 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2467 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2468 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2469 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2470 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2471 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2472 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2473 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2474 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2475 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2476 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2477 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2478 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2479 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2480 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2481 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2482 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2483 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2484 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2485 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2486 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2487 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2488 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2489 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2490 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2491 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2492 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2493 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2494 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2495 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2496 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2497 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2498 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2499 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2500 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2501 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2502 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2503 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2504 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2505 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2506 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2507 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2508 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2509 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2510 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2511 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2512 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2513 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2514 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2515 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2516 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2517 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2518 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2519 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2520 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2521 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2522 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2523 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2524 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2525 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2526 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2527 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2528 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2529 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2530 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2531 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2532 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2533 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2534 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2535 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2536 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2537 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2538 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2539 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2540 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2541 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2542 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2543 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2544 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2545 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2546 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2547 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2548 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2549 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2550 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2551 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2552 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2553 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2554 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2555 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2556 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2557 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2558 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2559 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2560 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2561 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2562 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2563 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2564 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2565 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2566 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2567 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2568 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2569 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2570 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2571 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2572 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2573 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2574 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2575 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2576 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2577 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2578 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2579 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2580 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2581 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2582 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2583 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2584 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2585 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2586 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2587 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2588 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2589 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2590 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2591 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2592 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2593 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2594 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2595 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2596 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2597 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2598 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2599 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2600 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2601 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2602 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2603 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2604 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2605 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2606 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2607 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2608 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2609 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2610 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2611 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2612 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2613 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2614 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2615 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2616 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2617 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2618 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2619 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2620 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2621 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2622 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2623 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2624 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2625 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2626 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2627 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2628 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2629 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2630 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2631 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2632 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2633 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2634 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2635 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2636 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2637 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2638 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2639
2640 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2641 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2642 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2643 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2644 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2645
2646 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2647 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2648 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2649 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2650
2651 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2652
2653 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2654 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2655 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2656 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2657 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2658 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2659 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2660 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2661 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2662 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2663 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2664 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2665 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2666 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2667 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2668 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2669 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2670 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2671 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2672 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2673 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2674 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2675 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2676 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2677 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2678 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2679 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2680 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2681 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2682 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2683 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2684 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2685 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2686 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2687 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2688 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2689 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2690 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2691 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2692 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2693 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2694 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2695 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2696 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2698 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2699 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2700 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2701 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2702 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2704 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2705 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2706 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2707 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2708 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2711 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2712 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2713 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2714 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2717 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2718 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2719 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2720 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2723 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2724 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2725 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2726 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2729 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2730 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2731 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2733 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2734 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2735 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2736 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2738 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2741 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2742 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2746 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2747 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2748 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2753 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2754 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2759 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2760 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2765 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2766 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2771 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2772 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2777 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2778 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2781 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2783 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2784 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2787 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2788 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2789 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2790 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2793 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2794 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2795 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2796 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2799 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2800 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2801 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2802 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2805 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2806 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2807 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2808 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2811 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2812 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2813 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2816 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2817 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2818 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2819 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2820 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2821 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2822 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2823 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2824 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2825 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2826 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2827 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2828 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2829 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2830 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2831 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2832 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2833 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2834 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2835 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2836 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2837 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2838 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2839 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2840 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2841 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2842 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2843 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2844 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2845 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2846 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2847 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2848 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2849 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2850 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2851 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2852 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2853 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2854 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2855 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2856 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2857 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2858 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2860 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2861 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2862 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2863 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2864 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2866 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2867 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2868 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2869 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2870 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2871 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2872 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2873 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2874 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2875
2876 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2877
2878 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2879 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2880 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2881
2882 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2883 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2884
2885 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2886
2887 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2888
2889 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2890 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2891
2892 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2893 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2894
2895 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2896
2897 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2898
2899 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2900 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2901
2902 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2903
2904 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2905 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2906
2907 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2908 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2909 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2910 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2911 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2912 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2913 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2914 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2915 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2916 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2917 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2918 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2919 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2920 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2921 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2922 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2923 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2924 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2925 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2926 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2927 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2930 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2931 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2932 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2933 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2934 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2935 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2936 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2937 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2940 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2941 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2942 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2944 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2945 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2946 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2947 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2950 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2951 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2952 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2954 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2955 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2956 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2957 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2960 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2961 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2962 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2964 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2965 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2966 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2967 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2970 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2971 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2972 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2974 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2975 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2980 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2985 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2990 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2995 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2996 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2997 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3000 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3001 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3002 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3005 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3010 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3011 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3012 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3015 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3020 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3021 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3022 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3025 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3026 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3027 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3030 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3031 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3032 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3033 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3034 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3035 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3036 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3037 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3038 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3039 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3040 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3041 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3042 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3043 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3044 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3045 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3046 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3047 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3048 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3049 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3050 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3051 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3052 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3053 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3054 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3055 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3056 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3057 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3058 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3059
3060 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3061 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3062
3063 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3064 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3065
3066 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3067 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3068 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3069 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3070 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3071 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3072 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3073 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3074
3075 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3076 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3077
3078 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3079 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3080 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3081 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3082
3083 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3084 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3085 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3086 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3087 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3088 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3089
3090 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3091 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3092 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3093
3094 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3095 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3096
3097 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3098 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3099
3100 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3101 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3102
3103 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3104 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3105
3106 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3107 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3108
3109 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3110 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3111 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3112 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3113 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3114 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3115
3116 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3117 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3118
3119 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3120 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3121
3122 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3123 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3124
3125 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3126 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3127 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3128 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3129
3130 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3131 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3132
3133 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
3134 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3135 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3136 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3137
3138 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3139 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3140 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3141 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3142 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3143 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3144 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3145 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3146 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3147 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3148 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3149 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3150 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3151 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3152 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3153 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3154 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3155 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3156 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3157 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3158 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3159 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3160 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3161 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3162 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3163 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3164 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3165 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3166 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3167 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3168 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3169
3170 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3171 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3172 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3173 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3174 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3175 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3176 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3177 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3178 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3179 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3180 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3181 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3182
3183 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3184 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3185
3186 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3187 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3188 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3189 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3190 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3191 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3192 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3193 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3194
3195 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3196 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3197
3198 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3199 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3200 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3201 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3202
3203 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
3204 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3205
3206 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
3207
3208 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
3209
3210 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3211 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3212
3213 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
3214 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3215
3216 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3217 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3218 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3219 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3220
3221 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3222 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3223 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3224 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3225
3226 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3227 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3228
3229 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3230 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3231
3232 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3233 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3234
3235 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3236
3237 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3238
3239 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
3240 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
3241 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3242 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3243
3244 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3245 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3246 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3247 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3248 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3249 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3250 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3251 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3252
3253 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3254
3255 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3256
3257 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3258 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3259
3260 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3261
3262 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3263
3264 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3265 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3266
3267 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3268 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3269
3270 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3271 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3272 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3273 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3274 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3275 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3276 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3277 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3278 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3279 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3280 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3281 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3282 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3283 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3284 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3285
3286 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3287 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3288
3289 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3290 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3291
3292 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3293 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3294
3295 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3296
3297 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3298
3299 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
3300
3301 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3302
3303 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
3304
3305 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3306
3307 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3308
3309 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3310 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3311 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3312 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3313
3314 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3315 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3316 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3317 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3318
3319 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3320
3321 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3322
3323 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3324
3325 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3326 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3327 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3328 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3329
3330 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
3331
3332 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3333
3334 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3335
3336 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3337
3338 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3339 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3340 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3341 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3342 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3343 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3344 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3345 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3346
3347 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3348 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3349 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3350 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3351 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3352 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3353 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3354 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3355
3356 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3357
3358 { "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,        { RS }},
3359 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3360
3361 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3362
3363 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
3364
3365 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
3366
3367 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
3368 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3369
3370 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3371
3372 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
3373
3374 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3375 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3376
3377 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3378 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3379
3380 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3381
3382 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3383 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3384
3385 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3386
3387 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3388
3389 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3390 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
3391
3392 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3393 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3394
3395 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3396
3397 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3398 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3399 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3400 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3401 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3402 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3403 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3404 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3405
3406 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3407 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3408 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3409 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3410 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3411 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3412 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3413 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3414
3415 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3416
3417 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
3418
3419 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
3420
3421 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3422 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3423
3424 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3425 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3426
3427 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
3428
3429 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3430
3431 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3432 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3433 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3434 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3435 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3436 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3437 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3438 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3439
3440 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3441 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3442 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3443 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3444
3445 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3446 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3447 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3448 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3449 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3450 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3451 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3452 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3453
3454 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3455 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3456 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3457 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3458 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3459 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3460 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3461 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3462
3463 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3464 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3465 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3466
3467 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
3468
3469 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3470
3471 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3472 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3473
3474 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3475
3476 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3477
3478 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3479
3480 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3481 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3482 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3483 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3484
3485 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3486 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3487 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3488 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3489 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3490 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3491 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3492 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3493
3494 { "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
3495
3496 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3497
3498 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3499 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3500
3501 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
3502
3503 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
3504
3505 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3506 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3507
3508 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3509
3510 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
3511
3512 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3513 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
3514
3515 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3516
3517 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3518
3519 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3520 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3521
3522 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3523
3524 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3525 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3526 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3527 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3528 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3529 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3530 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3531 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3532 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3533 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3534 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3535 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3536 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3537 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3538 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3539 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3540 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3541 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3542 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3543 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3544 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3545 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3546 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3547 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3548 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3549 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3550 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3551 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3552 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3553 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3554 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3555 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3556 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3557 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3558 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3559
3560 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3561 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3562 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3563 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3564
3565 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3566
3567 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3568 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3569 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3570 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3571 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3572 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3573 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3574 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3575 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3576 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3577 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3578 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3579 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3580 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3581 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3582 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3583 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3584 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3585 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3586 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3587 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3588 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3589 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3590 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3591 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3592 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3593 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3594 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3595 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3596 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3597 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3598 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3599 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3600 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3601 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3602 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3603 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3604 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3605 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3606 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3607 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3608 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3609 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
3610 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
3611 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
3612 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
3613 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3614 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3615 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3616 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3617 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3618 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3619 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
3620 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3621 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3622 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3623 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3624 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3625 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3626 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3627 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3628 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3629 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3630 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3631 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3632 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3633 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3634 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3635 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3636 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3637 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3638 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3639 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3640 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3641 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3642 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3643 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3644 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3645 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3646 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3647 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3648 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3649 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3650 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3651 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3652 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3653 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3654 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3655 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3656 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3657 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3658 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3659 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3660 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3661 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3662 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3663 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3664 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3665 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3666 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3667 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3668 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3669 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3670 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3671 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3672 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3673 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3674 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3675 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3676 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3677 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3678 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3679 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3680 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3681 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3682 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3683 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3684 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3685 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3686 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3687 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3688 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3689 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3690 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3691 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3692 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3693 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3694 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3695 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3696 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3697 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3698 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3699 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3700 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3701 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3702 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3703 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3704 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3705 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3706 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3707 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3708 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3709 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3710 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3711 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3712 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3713 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3714 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3715 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3716 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3717 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3718 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3719 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3720 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3721 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3722 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3723 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3724 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3725 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3726 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3727 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3728 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3729 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3730 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3731 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3732 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3733 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3734 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3735 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3736 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3737 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3738 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3739 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3740 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3741 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3742 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3743 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3744 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3745 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3746 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3747 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3748 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3749
3750 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
3751
3752 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3753 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3754
3755 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
3756
3757 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
3758
3759 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3760 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3761
3762 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3763
3764 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3765 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3766 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3767 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3768
3769 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3770 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3771 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3772 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3773
3774 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3775
3776 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3777
3778 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3779
3780 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3781
3782 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3783
3784 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3785
3786 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3787 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3788
3789 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3790 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3791
3792 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3793
3794 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3795
3796 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3797
3798 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3799
3800 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3801
3802 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3803
3804 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3805
3806 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3807 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3808
3809 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3810 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3811
3812 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3813
3814 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3815
3816 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3817
3818 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3819
3820 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3821
3822 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3823 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3824 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3825 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3826
3827 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3828 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3829 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3830 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3831 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3832 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3833 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3834 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3835 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3836 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3837 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3838 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3839 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3840 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3841 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3842 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3843 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3844 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3845 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3846 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3847 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3848 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3849 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3850 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3851 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3852 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3853 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3854 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3855 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3856 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3857 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3858 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3859 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3860 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3861 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3862
3863 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3864 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3865
3866 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3867 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3868 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3869 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3870
3871 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3872 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3873
3874 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3875 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3876 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3877 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3878
3879 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3880 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3881 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3882 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3883 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3884 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3885 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3886 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3887 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3888 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3889 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3890 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3891 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3892 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3893 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3894 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3895 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3896 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3897 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3898 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3899 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3900 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3901 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3902 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3903 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3904 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3905 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3906 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3907 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3908 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3909 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3910 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3911 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3912 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3913 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3914 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3915 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3916 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3917 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3918 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3919 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3920 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3921 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
3922 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3923 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3924 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3925 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3926 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3927 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3928 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3929 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3930 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3931 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3932 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3933 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3934 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3935 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3936 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3937 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3938 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3939 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3940 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3941 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3942 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3943 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3944 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3945 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3946 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3947 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3948 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3949 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3950 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3951 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3952 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3953 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3954 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3955 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3956 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3957 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3958 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3959 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3960 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3961 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3962 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3963 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
3964 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
3965 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
3966 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
3967 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
3968 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
3969 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
3970 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
3971 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
3972 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
3973 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
3974 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
3975 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
3976 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
3977 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
3978 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
3979 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
3980 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3981 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3982 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3983 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3984 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
3985 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
3986 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
3987 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
3988 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
3989 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
3990 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
3991 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
3992 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
3993 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
3994 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
3995 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
3996 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
3997 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
3998 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
3999 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
4000 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4001 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
4002 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4003 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
4004 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4005 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4006 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4007 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
4008 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
4009 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
4010 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
4011 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
4012 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
4013 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
4014 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
4015 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4016 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
4017 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
4018 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4019 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
4020 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4021 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
4022 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4023 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
4024 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4025 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
4026 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4027
4028 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4029
4030 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4031 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4032
4033 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4034
4035 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4036
4037 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4038
4039 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4040
4041 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4042 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4043 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4044 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4045 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4046 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4047
4048 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4049 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4050 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4051 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4052
4053 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4054 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4055
4056 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4057 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4058 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4059 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4060
4061 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4062
4063 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4064
4065 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4066
4067 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4068
4069 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4070
4071 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4072 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4073
4074 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4075
4076 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
4077 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4078
4079 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
4080 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4081
4082 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
4083
4084 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4085 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4086 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4087 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4088
4089 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4090 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4091
4092 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4093 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4094
4095 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4096 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4097
4098 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
4099
4100 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4101
4102 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4103 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4104
4105 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4106
4107 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4108
4109 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4110
4111 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
4112 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
4113
4114 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4115 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4116 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4117 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4118 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4119
4120 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
4121
4122 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4123
4124 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4125
4126 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4127
4128 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4129
4130 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4131
4132 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4133
4134 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
4135 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
4136
4137 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
4138 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
4139
4140 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
4141
4142 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4143 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4144
4145 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4146 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4147
4148 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
4149
4150 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4151
4152 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4153
4154 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4155 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4156
4157 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4158
4159 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
4160 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
4161
4162 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
4163
4164 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4165 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4166
4167 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4168 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4169
4170 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4171
4172 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4173
4174 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4175
4176 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4177 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4178
4179 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4180
4181 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4182
4183 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4184 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4185
4186 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
4187
4188 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4189 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4190 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4191 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4192
4193 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4194 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4195
4196 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
4197
4198 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
4199 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
4200
4201 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4202
4203 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4204 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4205
4206 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4207 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4208 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4209 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4210
4211 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4212
4213 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4214 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4215
4216 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
4217 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
4218 { "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
4219 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
4220 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4221 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4222
4223 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4224
4225 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
4226
4227 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4228 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4229
4230 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4231 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4232
4233 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4234 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4235 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4236 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4237
4238 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
4239
4240 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
4241
4242 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4243 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4244 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
4245 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RS, RA, SH } },
4246
4247 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4248 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4249
4250 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4251 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4252
4253 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4254
4255 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4256
4257 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4258 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4259 { "tlbwe",   X(31,978), X_MASK,         BOOKE,          { 0 } },
4260 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
4261 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4262
4263 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4264
4265 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
4266
4267 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4268 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4269
4270 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4271
4272 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4273 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4274
4275 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4276
4277 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4278 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4279
4280 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4281
4282 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4283 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4284 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4285 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4286 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4287 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4288 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4289 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4290 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4291 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4292 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4293 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4294
4295 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
4296 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4297
4298 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4299 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4300
4301 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
4302
4303 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4304
4305 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4306 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4307
4308 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4309 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4310
4311 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
4312
4313 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4314
4315 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
4316
4317 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4318
4319 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
4320
4321 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4322
4323 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
4324
4325 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4326
4327 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4328 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4329
4330 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4331 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4332
4333 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
4334
4335 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4336
4337 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
4338
4339 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4340
4341 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
4342
4343 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4344
4345 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
4346
4347 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4348
4349 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4350
4351 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
4352
4353 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
4354
4355 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4356 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4357 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4358 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4359 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4360 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4361 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4362 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4363 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
4364 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4365 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4366 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4367 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4368 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4369
4370 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
4371
4372 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4373
4374 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
4375
4376 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4377 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4378
4379 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4380 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4381
4382 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4383 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4384
4385 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4386 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4387
4388 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4389 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4390
4391 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4392 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4393
4394 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4395 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4396
4397 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4398 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4399
4400 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4401 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4402
4403 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4404 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4405
4406 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4407
4408 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4409
4410 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4411 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4412 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4413 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4414 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4415 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4416 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
4417 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4418 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4419 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4420 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4421 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4422
4423 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
4424
4425 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4426
4427 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA } },
4428
4429 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4430
4431 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4432 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4433
4434 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4435 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4436 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4437 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4438
4439 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4440 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4441 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4442 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4443
4444 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4445 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4446 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4447 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4448
4449 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4450 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4451 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4452 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4453
4454 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4455 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4456 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4457 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4458
4459 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4460 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4461
4462 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4463 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4464
4465 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4466 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4467 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4468 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4469
4470 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4471 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4472
4473 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4474 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4475 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4476 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4477
4478 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4479 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4480 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4481 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4482
4483 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4484 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4485 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4486 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4487
4488 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4489 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4490 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4491 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4492
4493 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4494
4495 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4496 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4497
4498 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4499 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4500
4501 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4502
4503 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4504 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4505
4506 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4507 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4508
4509 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4510 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4511
4512 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4513 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4514
4515 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4516 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4517
4518 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4519 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4520
4521 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4522 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4523
4524 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4525 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4526
4527 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4528 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4529
4530 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4531 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4532
4533 };
4534
4535 const int powerpc_num_opcodes =
4536   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4537 \f
4538 /* The macro table.  This is only used by the assembler.  */
4539
4540 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4541    when x=0; 32-x when x is between 1 and 31; are negative if x is
4542    negative; and are 32 or more otherwise.  This is what you want
4543    when, for instance, you are emulating a right shift by a
4544    rotate-left-and-mask, because the underlying instructions support
4545    shifts of size 0 but not shifts of size 32.  By comparison, when
4546    extracting x bits from some word you want to use just 32-x, because
4547    the underlying instructions don't support extracting 0 bits but do
4548    support extracting the whole word (32 bits in this case).  */
4549
4550 const struct powerpc_macro powerpc_macros[] = {
4551 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4552 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4553 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4554 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4555 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4556 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4557 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4558 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4559 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4560 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4561 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4562 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4563 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4564 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4565 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4566 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4567
4568 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4569 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4570 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4571 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4572 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4573 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4574 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4575 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4576 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4577 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4578 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4579 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4580 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4581 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4582 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4583 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4584 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4585 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4586 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4587 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4588 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4589 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4590 };
4591
4592 const int powerpc_num_macros =
4593   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);