opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bd (unsigned long, long, int, const char **);
  46 static long extract_bd (unsigned long, int, int *);
  47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  48 static long extract_bdm (unsigned long, int, int *);
  49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  50 static long extract_bdp (unsigned long, int, int *);
  51 static unsigned long insert_bo (unsigned long, long, int, const char **);
  52 static long extract_bo (unsigned long, int, int *);
  53 static unsigned long insert_boe (unsigned long, long, int, const char **);
  54 static long extract_boe (unsigned long, int, int *);
  55 static unsigned long insert_dq (unsigned long, long, int, const char **);
  56 static long extract_dq (unsigned long, int, int *);
  57 static unsigned long insert_ds (unsigned long, long, int, const char **);
  58 static long extract_ds (unsigned long, int, int *);
  59 static unsigned long insert_de (unsigned long, long, int, const char **);
  60 static long extract_de (unsigned long, int, int *);
  61 static unsigned long insert_des (unsigned long, long, int, const char **);
  62 static long extract_des (unsigned long, int, int *);
  63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  64 static long extract_fxm (unsigned long, int, int *);
  65 static unsigned long insert_li (unsigned long, long, int, const char **);
  66 static long extract_li (unsigned long, int, int *);
  67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  68 static long extract_mbe (unsigned long, int, int *);
  69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  70 static long extract_mb6 (unsigned long, int, int *);
  71 static unsigned long insert_nb (unsigned long, long, int, const char **);
  72 static long extract_nb (unsigned long, int, int *);
  73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  74 static long extract_nsi (unsigned long, int, int *);
  75 static unsigned long insert_ral (unsigned long, long, int, const char **);
  76 static unsigned long insert_ram (unsigned long, long, int, const char **);
  77 static unsigned long insert_raq (unsigned long, long, int, const char **);
  78 static unsigned long insert_ras (unsigned long, long, int, const char **);
  79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  80 static long extract_rbs (unsigned long, int, int *);
  81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
  82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
  83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  84 static long extract_sh6 (unsigned long, int, int *);
  85 static unsigned long insert_spr (unsigned long, long, int, const char **);
  86 static long extract_spr (unsigned long, int, int *);
  87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  88 static long extract_tbr (unsigned long, int, int *);
  89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
  90 static long extract_ev2 (unsigned long, int, int *);
  91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
  92 static long extract_ev4 (unsigned long, int, int *);
  93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
  94 static long extract_ev8 (unsigned long, int, int *);
  95 \f
  96 /* The operands table.
  97
  98    The fields are bits, shift, insert, extract, flags.
  99
 100    We used to put parens around the various additions, like the one
 101    for BA just below.  However, that caused trouble with feeble
 102    compilers with a limit on depth of a parenthesized expression, like
 103    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 104    omit the parens, since the macros are never used in a context where
 105    the addition will be ambiguous.  */
 106
 107 const struct powerpc_operand powerpc_operands[] =
 108 {
 109   /* The zero index is used to indicate the end of the list of
 110      operands.  */
 111 #define UNUSED 0
 112   { 0, 0, 0, 0, 0 },
 113
 114   /* The BA field in an XL form instruction.  */
 115 #define BA UNUSED + 1
 116 #define BA_MASK (0x1f << 16)
 117   { 5, 16, 0, 0, PPC_OPERAND_CR },
 118
 119   /* The BA field in an XL form instruction when it must be the same
 120      as the BT field in the same instruction.  */
 121 #define BAT BA + 1
 122   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 123
 124   /* The BB field in an XL form instruction.  */
 125 #define BB BAT + 1
 126 #define BB_MASK (0x1f << 11)
 127   { 5, 11, 0, 0, PPC_OPERAND_CR },
 128
 129   /* The BB field in an XL form instruction when it must be the same
 130      as the BA field in the same instruction.  */
 131 #define BBA BB + 1
 132   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 133
 134   /* The BD field in a B form instruction.  The lower two bits are
 135      forced to zero.  */
 136 #define BD BBA + 1
 137   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when absolute addressing is
 140      used.  */
 141 #define BDA BD + 1
 142   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the - modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDM BDA + 1
 147   { 16, 0, insert_bdm, extract_bdm,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the - modifier is used
 151      and absolute address is used.  */
 152 #define BDMA BDM + 1
 153   { 16, 0, insert_bdm, extract_bdm,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BD field in a B form instruction when the + modifier is used.
 157      This sets the y bit of the BO field appropriately.  */
 158 #define BDP BDMA + 1
 159   { 16, 0, insert_bdp, extract_bdp,
 160       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 161
 162   /* The BD field in a B form instruction when the + modifier is used
 163      and absolute addressing is used.  */
 164 #define BDPA BDP + 1
 165   { 16, 0, insert_bdp, extract_bdp,
 166       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 167
 168   /* The BF field in an X or XL form instruction.  */
 169 #define BF BDPA + 1
 170   { 3, 23, 0, 0, PPC_OPERAND_CR },
 171
 172   /* An optional BF field.  This is used for comparison instructions,
 173      in which an omitted BF field is taken as zero.  */
 174 #define OBF BF + 1
 175   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 176
 177   /* The BFA field in an X or XL form instruction.  */
 178 #define BFA OBF + 1
 179   { 3, 18, 0, 0, PPC_OPERAND_CR },
 180
 181   /* The BI field in a B form or XL form instruction.  */
 182 #define BI BFA + 1
 183 #define BI_MASK (0x1f << 16)
 184   { 5, 16, 0, 0, PPC_OPERAND_CR },
 185
 186   /* The BO field in a B form instruction.  Certain values are
 187      illegal.  */
 188 #define BO BI + 1
 189 #define BO_MASK (0x1f << 21)
 190   { 5, 21, insert_bo, extract_bo, 0 },
 191
 192   /* The BO field in a B form instruction when the + or - modifier is
 193      used.  This is like the BO field, but it must be even.  */
 194 #define BOE BO + 1
 195   { 5, 21, insert_boe, extract_boe, 0 },
 196
 197   /* The BT field in an X or XL form instruction.  */
 198 #define BT BOE + 1
 199   { 5, 21, 0, 0, PPC_OPERAND_CR },
 200
 201   /* The condition register number portion of the BI field in a B form
 202      or XL form instruction.  This is used for the extended
 203      conditional branch mnemonics, which set the lower two bits of the
 204      BI field.  This field is optional.  */
 205 #define CR BT + 1
 206   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 207
 208   /* The CRB field in an X form instruction.  */
 209 #define CRB CR + 1
 210   { 5, 6, 0, 0, 0 },
 211
 212   /* The CRFD field in an X form instruction.  */
 213 #define CRFD CRB + 1
 214   { 3, 23, 0, 0, PPC_OPERAND_CR },
 215
 216   /* The CRFS field in an X form instruction.  */
 217 #define CRFS CRFD + 1
 218   { 3, 0, 0, 0, PPC_OPERAND_CR },
 219
 220   /* The CT field in an X form instruction.  */
 221 #define CT CRFS + 1
 222   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 223
 224   /* The D field in a D form instruction.  This is a displacement off
 225      a register, and implies that the next operand is a register in
 226      parentheses.  */
 227 #define D CT + 1
 228   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 229
 230   /* The DE field in a DE form instruction.  This is like D, but is 12
 231      bits only.  */
 232 #define DE D + 1
 233   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 234
 235   /* The DES field in a DES form instruction.  This is like DS, but is 14
 236      bits only (12 stored.)  */
 237 #define DES DE + 1
 238   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 239
 240   /* The DQ field in a DQ form instruction.  This is like D, but the
 241      lower four bits are forced to zero. */
 242 #define DQ DES + 1
 243   { 16, 0, insert_dq, extract_dq,
 244       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 245
 246   /* The DS field in a DS form instruction.  This is like D, but the
 247      lower two bits are forced to zero.  */
 248 #define DS DQ + 1
 249   { 16, 0, insert_ds, extract_ds,
 250       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 251
 252   /* The E field in a wrteei instruction.  */
 253 #define E DS + 1
 254   { 1, 15, 0, 0, 0 },
 255
 256   /* The FL1 field in a POWER SC form instruction.  */
 257 #define FL1 E + 1
 258   { 4, 12, 0, 0, 0 },
 259
 260   /* The FL2 field in a POWER SC form instruction.  */
 261 #define FL2 FL1 + 1
 262   { 3, 2, 0, 0, 0 },
 263
 264   /* The FLM field in an XFL form instruction.  */
 265 #define FLM FL2 + 1
 266   { 8, 17, 0, 0, 0 },
 267
 268   /* The FRA field in an X or A form instruction.  */
 269 #define FRA FLM + 1
 270 #define FRA_MASK (0x1f << 16)
 271   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 272
 273   /* The FRB field in an X or A form instruction.  */
 274 #define FRB FRA + 1
 275 #define FRB_MASK (0x1f << 11)
 276   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 277
 278   /* The FRC field in an A form instruction.  */
 279 #define FRC FRB + 1
 280 #define FRC_MASK (0x1f << 6)
 281   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 282
 283   /* The FRS field in an X form instruction or the FRT field in a D, X
 284      or A form instruction.  */
 285 #define FRS FRC + 1
 286 #define FRT FRS
 287   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 288
 289   /* The FXM field in an XFX instruction.  */
 290 #define FXM FRS + 1
 291 #define FXM_MASK (0xff << 12)
 292   { 8, 12, insert_fxm, extract_fxm, 0 },
 293
 294   /* Power4 version for mfcr.  */
 295 #define FXM4 FXM + 1
 296   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 297
 298   /* The L field in a D or X form instruction.  */
 299 #define L FXM4 + 1
 300   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 301
 302   /* The LEV field in a POWER SC form instruction.  */
 303 #define LEV L + 1
 304   { 7, 5, 0, 0, 0 },
 305
 306   /* The LI field in an I form instruction.  The lower two bits are
 307      forced to zero.  */
 308 #define LI LEV + 1
 309   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 310
 311   /* The LI field in an I form instruction when used as an absolute
 312      address.  */
 313 #define LIA LI + 1
 314   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 315
 316   /* The LS field in an X (sync) form instruction.  */
 317 #define LS LIA + 1
 318   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 319
 320   /* The MB field in an M form instruction.  */
 321 #define MB LS + 1
 322 #define MB_MASK (0x1f << 6)
 323   { 5, 6, 0, 0, 0 },
 324
 325   /* The ME field in an M form instruction.  */
 326 #define ME MB + 1
 327 #define ME_MASK (0x1f << 1)
 328   { 5, 1, 0, 0, 0 },
 329
 330   /* The MB and ME fields in an M form instruction expressed a single
 331      operand which is a bitmask indicating which bits to select.  This
 332      is a two operand form using PPC_OPERAND_NEXT.  See the
 333      description in opcode/ppc.h for what this means.  */
 334 #define MBE ME + 1
 335   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 336   { 32, 0, insert_mbe, extract_mbe, 0 },
 337
 338   /* The MB or ME field in an MD or MDS form instruction.  The high
 339      bit is wrapped to the low end.  */
 340 #define MB6 MBE + 2
 341 #define ME6 MB6
 342 #define MB6_MASK (0x3f << 5)
 343   { 6, 5, insert_mb6, extract_mb6, 0 },
 344
 345   /* The MO field in an mbar instruction.  */
 346 #define MO MB6 + 1
 347   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 348
 349   /* The NB field in an X form instruction.  The value 32 is stored as
 350      0.  */
 351 #define NB MO + 1
 352   { 6, 11, insert_nb, extract_nb, 0 },
 353
 354   /* The NSI field in a D form instruction.  This is the same as the
 355      SI field, only negated.  */
 356 #define NSI NB + 1
 357   { 16, 0, insert_nsi, extract_nsi,
 358       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 359
 360   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 361 #define RA NSI + 1
 362 #define RA_MASK (0x1f << 16)
 363   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 364
 365   /* The RA field in the DQ form lq instruction, which has special
 366      value restrictions.  */
 367 #define RAQ RA + 1
 368   { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
 369
 370   /* The RA field in a D or X form instruction which is an updating
 371      load, which means that the RA field may not be zero and may not
 372      equal the RT field.  */
 373 #define RAL RAQ + 1
 374   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 375
 376   /* The RA field in an lmw instruction, which has special value
 377      restrictions.  */
 378 #define RAM RAL + 1
 379   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 380
 381   /* The RA field in a D or X form instruction which is an updating
 382      store or an updating floating point load, which means that the RA
 383      field may not be zero.  */
 384 #define RAS RAM + 1
 385   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 386
 387   /* The RA field of the tlbwe instruction, which is optional.  */
 388 #define RAO RAS + 1
 389   { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
 390
 391   /* The RB field in an X, XO, M, or MDS form instruction.  */
 392 #define RB RAO + 1
 393 #define RB_MASK (0x1f << 11)
 394   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 395
 396   /* The RB field in an X form instruction when it must be the same as
 397      the RS field in the instruction.  This is used for extended
 398      mnemonics like mr.  */
 399 #define RBS RB + 1
 400   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 401
 402   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 403      instruction or the RT field in a D, DS, X, XFX or XO form
 404      instruction.  */
 405 #define RS RBS + 1
 406 #define RT RS
 407 #define RT_MASK (0x1f << 21)
 408   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 409
 410   /* The RS field of the DS form stq instruction, which has special
 411      value restrictions.  */
 412 #define RSQ RS + 1
 413   { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
 414
 415   /* The RT field of the DQ form lq instruction, which has special
 416      value restrictions.  */
 417 #define RTQ RSQ + 1
 418   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
 419
 420   /* The RS field of the tlbwe instruction, which is optional.  */
 421 #define RSO RTQ + 1
 422   { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
 423
 424   /* The SH field in an X or M form instruction.  */
 425 #define SH RSO + 1
 426 #define SH_MASK (0x1f << 11)
 427   { 5, 11, 0, 0, 0 },
 428
 429   /* The SH field in an MD form instruction.  This is split.  */
 430 #define SH6 SH + 1
 431 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 432   { 6, 1, insert_sh6, extract_sh6, 0 },
 433
 434   /* The SH field of the tlbwe instruction, which is optional.  */
 435 #define SHO SH6 + 1
 436   { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
 437
 438   /* The SI field in a D form instruction.  */
 439 #define SI SHO + 1
 440   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 441
 442   /* The SI field in a D form instruction when we accept a wide range
 443      of positive values.  */
 444 #define SISIGNOPT SI + 1
 445   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 446
 447   /* The SPR field in an XFX form instruction.  This is flipped--the
 448      lower 5 bits are stored in the upper 5 and vice- versa.  */
 449 #define SPR SISIGNOPT + 1
 450 #define PMR SPR
 451 #define SPR_MASK (0x3ff << 11)
 452   { 10, 11, insert_spr, extract_spr, 0 },
 453
 454   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 455 #define SPRBAT SPR + 1
 456 #define SPRBAT_MASK (0x3 << 17)
 457   { 2, 17, 0, 0, 0 },
 458
 459   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 460 #define SPRG SPRBAT + 1
 461 #define SPRG_MASK (0x3 << 16)
 462   { 2, 16, 0, 0, 0 },
 463
 464   /* The SR field in an X form instruction.  */
 465 #define SR SPRG + 1
 466   { 4, 16, 0, 0, 0 },
 467
 468   /* The STRM field in an X AltiVec form instruction.  */
 469 #define STRM SR + 1
 470 #define STRM_MASK (0x3 << 21)
 471   { 2, 21, 0, 0, 0 },
 472
 473   /* The SV field in a POWER SC form instruction.  */
 474 #define SV STRM + 1
 475   { 14, 2, 0, 0, 0 },
 476
 477   /* The TBR field in an XFX form instruction.  This is like the SPR
 478      field, but it is optional.  */
 479 #define TBR SV + 1
 480   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 481
 482   /* The TO field in a D or X form instruction.  */
 483 #define TO TBR + 1
 484 #define TO_MASK (0x1f << 21)
 485   { 5, 21, 0, 0, 0 },
 486
 487   /* The U field in an X form instruction.  */
 488 #define U TO + 1
 489   { 4, 12, 0, 0, 0 },
 490
 491   /* The UI field in a D form instruction.  */
 492 #define UI U + 1
 493   { 16, 0, 0, 0, 0 },
 494
 495   /* The VA field in a VA, VX or VXR form instruction.  */
 496 #define VA UI + 1
 497 #define VA_MASK (0x1f << 16)
 498   { 5, 16, 0, 0, PPC_OPERAND_VR },
 499
 500   /* The VB field in a VA, VX or VXR form instruction.  */
 501 #define VB VA + 1
 502 #define VB_MASK (0x1f << 11)
 503   { 5, 11, 0, 0, PPC_OPERAND_VR },
 504
 505   /* The VC field in a VA form instruction.  */
 506 #define VC VB + 1
 507 #define VC_MASK (0x1f << 6)
 508   { 5, 6, 0, 0, PPC_OPERAND_VR },
 509
 510   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 511 #define VD VC + 1
 512 #define VS VD
 513 #define VD_MASK (0x1f << 21)
 514   { 5, 21, 0, 0, PPC_OPERAND_VR },
 515
 516   /* The SIMM field in a VX form instruction.  */
 517 #define SIMM VD + 1
 518   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 519
 520   /* The UIMM field in a VX form instruction.  */
 521 #define UIMM SIMM + 1
 522   { 5, 16, 0, 0, 0 },
 523
 524   /* The SHB field in a VA form instruction.  */
 525 #define SHB UIMM + 1
 526   { 4, 6, 0, 0, 0 },
 527
 528   /* The other UIMM field in a EVX form instruction.  */
 529 #define EVUIMM SHB + 1
 530   { 5, 11, 0, 0, 0 },
 531
 532   /* The other UIMM field in a half word EVX form instruction.  */
 533 #define EVUIMM_2 EVUIMM + 1
 534   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 535
 536   /* The other UIMM field in a word EVX form instruction.  */
 537 #define EVUIMM_4 EVUIMM_2 + 1
 538   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 539
 540   /* The other UIMM field in a double EVX form instruction.  */
 541 #define EVUIMM_8 EVUIMM_4 + 1
 542   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 543
 544   /* The WS field.  */
 545 #define WS EVUIMM_8 + 1
 546 #define WS_MASK (0x7 << 11)
 547   { 3, 11, 0, 0, 0 },
 548
 549   /* The L field in an mtmsrd instruction */
 550 #define MTMSRD_L WS + 1
 551   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 552
 553 };
 554
 555 /* The functions used to insert and extract complicated operands.  */
 556
 557 /* The BA field in an XL form instruction when it must be the same as
 558    the BT field in the same instruction.  This operand is marked FAKE.
 559    The insertion function just copies the BT field into the BA field,
 560    and the extraction function just checks that the fields are the
 561    same.  */
 562
 563 static unsigned long
 564 insert_bat (unsigned long insn,
 565             long value ATTRIBUTE_UNUSED,
 566             int dialect ATTRIBUTE_UNUSED,
 567             const char **errmsg ATTRIBUTE_UNUSED)
 568 {
 569   return insn | (((insn >> 21) & 0x1f) << 16);
 570 }
 571
 572 static long
 573 extract_bat (unsigned long insn,
 574              int dialect ATTRIBUTE_UNUSED,
 575              int *invalid)
 576 {
 577   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 578     *invalid = 1;
 579   return 0;
 580 }
 581
 582 /* The BB field in an XL form instruction when it must be the same as
 583    the BA field in the same instruction.  This operand is marked FAKE.
 584    The insertion function just copies the BA field into the BB field,
 585    and the extraction function just checks that the fields are the
 586    same.  */
 587
 588 static unsigned long
 589 insert_bba (unsigned long insn,
 590             long value ATTRIBUTE_UNUSED,
 591             int dialect ATTRIBUTE_UNUSED,
 592             const char **errmsg ATTRIBUTE_UNUSED)
 593 {
 594   return insn | (((insn >> 16) & 0x1f) << 11);
 595 }
 596
 597 static long
 598 extract_bba (unsigned long insn,
 599              int dialect ATTRIBUTE_UNUSED,
 600              int *invalid)
 601 {
 602   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 603     *invalid = 1;
 604   return 0;
 605 }
 606
 607 /* The BD field in a B form instruction.  The lower two bits are
 608    forced to zero.  */
 609
 610 static unsigned long
 611 insert_bd (unsigned long insn,
 612            long value,
 613            int dialect ATTRIBUTE_UNUSED,
 614            const char **errmsg ATTRIBUTE_UNUSED)
 615 {
 616   return insn | (value & 0xfffc);
 617 }
 618
 619 static long
 620 extract_bd (unsigned long insn,
 621             int dialect ATTRIBUTE_UNUSED,
 622             int *invalid ATTRIBUTE_UNUSED)
 623 {
 624   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 625 }
 626
 627 /* The BD field in a B form instruction when the - modifier is used.
 628    This modifier means that the branch is not expected to be taken.
 629    For chips built to versions of the architecture prior to version 2
 630    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 631    if the offset is negative.  When extracting, we require that the y
 632    bit be 1 and that the offset be positive, since if the y bit is 0
 633    we just want to print the normal form of the instruction.
 634    Power4 compatible targets use two bits, "a", and "t", instead of
 635    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 636    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 637    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 638    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 639
 640 static unsigned long
 641 insert_bdm (unsigned long insn,
 642             long value,
 643             int dialect,
 644             const char **errmsg ATTRIBUTE_UNUSED)
 645 {
 646   if ((dialect & PPC_OPCODE_POWER4) == 0)
 647     {
 648       if ((value & 0x8000) != 0)
 649         insn |= 1 << 21;
 650     }
 651   else
 652     {
 653       if ((insn & (0x14 << 21)) == (0x04 << 21))
 654         insn |= 0x02 << 21;
 655       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 656         insn |= 0x08 << 21;
 657     }
 658   return insn | (value & 0xfffc);
 659 }
 660
 661 static long
 662 extract_bdm (unsigned long insn,
 663              int dialect,
 664              int *invalid)
 665 {
 666   if ((dialect & PPC_OPCODE_POWER4) == 0)
 667     {
 668       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 669         *invalid = 1;
 670     }
 671   else
 672     {
 673       if ((insn & (0x17 << 21)) != (0x06 << 21)
 674           && (insn & (0x1d << 21)) != (0x18 << 21))
 675         *invalid = 1;
 676     }
 677
 678   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 679 }
 680
 681 /* The BD field in a B form instruction when the + modifier is used.
 682    This is like BDM, above, except that the branch is expected to be
 683    taken.  */
 684
 685 static unsigned long
 686 insert_bdp (unsigned long insn,
 687             long value,
 688             int dialect,
 689             const char **errmsg ATTRIBUTE_UNUSED)
 690 {
 691   if ((dialect & PPC_OPCODE_POWER4) == 0)
 692     {
 693       if ((value & 0x8000) == 0)
 694         insn |= 1 << 21;
 695     }
 696   else
 697     {
 698       if ((insn & (0x14 << 21)) == (0x04 << 21))
 699         insn |= 0x03 << 21;
 700       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 701         insn |= 0x09 << 21;
 702     }
 703   return insn | (value & 0xfffc);
 704 }
 705
 706 static long
 707 extract_bdp (unsigned long insn,
 708              int dialect,
 709              int *invalid)
 710 {
 711   if ((dialect & PPC_OPCODE_POWER4) == 0)
 712     {
 713       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 714         *invalid = 1;
 715     }
 716   else
 717     {
 718       if ((insn & (0x17 << 21)) != (0x07 << 21)
 719           && (insn & (0x1d << 21)) != (0x19 << 21))
 720         *invalid = 1;
 721     }
 722
 723   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 724 }
 725
 726 /* Check for legal values of a BO field.  */
 727
 728 static int
 729 valid_bo (long value, int dialect)
 730 {
 731   if ((dialect & PPC_OPCODE_POWER4) == 0)
 732     {
 733       /* Certain encodings have bits that are required to be zero.
 734          These are (z must be zero, y may be anything):
 735              001zy
 736              011zy
 737              1z00y
 738              1z01y
 739              1z1zz
 740       */
 741       switch (value & 0x14)
 742         {
 743         default:
 744         case 0:
 745           return 1;
 746         case 0x4:
 747           return (value & 0x2) == 0;
 748         case 0x10:
 749           return (value & 0x8) == 0;
 750         case 0x14:
 751           return value == 0x14;
 752         }
 753     }
 754   else
 755     {
 756       /* Certain encodings have bits that are required to be zero.
 757          These are (z must be zero, a & t may be anything):
 758              0000z
 759              0001z
 760              0100z
 761              0101z
 762              001at
 763              011at
 764              1a00t
 765              1a01t
 766              1z1zz
 767       */
 768       if ((value & 0x14) == 0)
 769         return (value & 0x1) == 0;
 770       else if ((value & 0x14) == 0x14)
 771         return value == 0x14;
 772       else
 773         return 1;
 774     }
 775 }
 776
 777 /* The BO field in a B form instruction.  Warn about attempts to set
 778    the field to an illegal value.  */
 779
 780 static unsigned long
 781 insert_bo (unsigned long insn,
 782            long value,
 783            int dialect,
 784            const char **errmsg)
 785 {
 786   if (!valid_bo (value, dialect))
 787     *errmsg = _("invalid conditional option");
 788   return insn | ((value & 0x1f) << 21);
 789 }
 790
 791 static long
 792 extract_bo (unsigned long insn,
 793             int dialect,
 794             int *invalid)
 795 {
 796   long value;
 797
 798   value = (insn >> 21) & 0x1f;
 799   if (!valid_bo (value, dialect))
 800     *invalid = 1;
 801   return value;
 802 }
 803
 804 /* The BO field in a B form instruction when the + or - modifier is
 805    used.  This is like the BO field, but it must be even.  When
 806    extracting it, we force it to be even.  */
 807
 808 static unsigned long
 809 insert_boe (unsigned long insn,
 810             long value,
 811             int dialect,
 812             const char **errmsg)
 813 {
 814   if (!valid_bo (value, dialect))
 815     *errmsg = _("invalid conditional option");
 816   else if ((value & 1) != 0)
 817     *errmsg = _("attempt to set y bit when using + or - modifier");
 818
 819   return insn | ((value & 0x1f) << 21);
 820 }
 821
 822 static long
 823 extract_boe (unsigned long insn,
 824              int dialect,
 825              int *invalid)
 826 {
 827   long value;
 828
 829   value = (insn >> 21) & 0x1f;
 830   if (!valid_bo (value, dialect))
 831     *invalid = 1;
 832   return value & 0x1e;
 833 }
 834
 835 /* The DQ field in a DQ form instruction.  This is like D, but the
 836    lower four bits are forced to zero. */
 837
 838 static unsigned long
 839 insert_dq (unsigned long insn,
 840            long value,
 841            int dialect ATTRIBUTE_UNUSED,
 842            const char **errmsg)
 843 {
 844   if ((value & 0xf) != 0)
 845     *errmsg = _("offset not a multiple of 16");
 846   return insn | (value & 0xfff0);
 847 }
 848
 849 static long
 850 extract_dq (unsigned long insn,
 851             int dialect ATTRIBUTE_UNUSED,
 852             int *invalid ATTRIBUTE_UNUSED)
 853 {
 854   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
 855 }
 856
 857 static unsigned long
 858 insert_ev2 (unsigned long insn,
 859             long value,
 860             int dialect ATTRIBUTE_UNUSED,
 861             const char **errmsg)
 862 {
 863   if ((value & 1) != 0)
 864     *errmsg = _("offset not a multiple of 2");
 865   if ((value > 62) != 0)
 866     *errmsg = _("offset greater than 62");
 867   return insn | ((value & 0x3e) << 10);
 868 }
 869
 870 static long
 871 extract_ev2 (unsigned long insn,
 872              int dialect ATTRIBUTE_UNUSED,
 873              int *invalid ATTRIBUTE_UNUSED)
 874 {
 875   return (insn >> 10) & 0x3e;
 876 }
 877
 878 static unsigned long
 879 insert_ev4 (unsigned long insn,
 880             long value,
 881             int dialect ATTRIBUTE_UNUSED,
 882             const char **errmsg)
 883 {
 884   if ((value & 3) != 0)
 885     *errmsg = _("offset not a multiple of 4");
 886   if ((value > 124) != 0)
 887     *errmsg = _("offset greater than 124");
 888   return insn | ((value & 0x7c) << 9);
 889 }
 890
 891 static long
 892 extract_ev4 (unsigned long insn,
 893              int dialect ATTRIBUTE_UNUSED,
 894              int *invalid ATTRIBUTE_UNUSED)
 895 {
 896   return (insn >> 9) & 0x7c;
 897 }
 898
 899 static unsigned long
 900 insert_ev8 (unsigned long insn,
 901             long value,
 902             int dialect ATTRIBUTE_UNUSED,
 903             const char **errmsg)
 904 {
 905   if ((value & 7) != 0)
 906     *errmsg = _("offset not a multiple of 8");
 907   if ((value > 248) != 0)
 908     *errmsg = _("offset greater than 248");
 909   return insn | ((value & 0xf8) << 8);
 910 }
 911
 912 static long
 913 extract_ev8 (unsigned long insn,
 914              int dialect ATTRIBUTE_UNUSED,
 915              int *invalid ATTRIBUTE_UNUSED)
 916 {
 917   return (insn >> 8) & 0xf8;
 918 }
 919
 920 /* The DS field in a DS form instruction.  This is like D, but the
 921    lower two bits are forced to zero.  */
 922
 923 static unsigned long
 924 insert_ds (unsigned long insn,
 925            long value,
 926            int dialect ATTRIBUTE_UNUSED,
 927            const char **errmsg)
 928 {
 929   if ((value & 3) != 0)
 930     *errmsg = _("offset not a multiple of 4");
 931   return insn | (value & 0xfffc);
 932 }
 933
 934 static long
 935 extract_ds (unsigned long insn,
 936             int dialect ATTRIBUTE_UNUSED,
 937             int *invalid ATTRIBUTE_UNUSED)
 938 {
 939   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 940 }
 941
 942 /* The DE field in a DE form instruction.  */
 943
 944 static unsigned long
 945 insert_de (unsigned long insn,
 946            long value,
 947            int dialect ATTRIBUTE_UNUSED,
 948            const char **errmsg)
 949 {
 950   if (value > 2047 || value < -2048)
 951     *errmsg = _("offset not between -2048 and 2047");
 952   return insn | ((value << 4) & 0xfff0);
 953 }
 954
 955 static long
 956 extract_de (unsigned long insn,
 957             int dialect ATTRIBUTE_UNUSED,
 958             int *invalid ATTRIBUTE_UNUSED)
 959 {
 960   return (insn & 0xfff0) >> 4;
 961 }
 962
 963 /* The DES field in a DES form instruction.  */
 964
 965 static unsigned long
 966 insert_des (unsigned long insn,
 967             long value,
 968             int dialect ATTRIBUTE_UNUSED,
 969             const char **errmsg)
 970 {
 971   if (value > 8191 || value < -8192)
 972     *errmsg = _("offset not between -8192 and 8191");
 973   else if ((value & 3) != 0)
 974     *errmsg = _("offset not a multiple of 4");
 975   return insn | ((value << 2) & 0xfff0);
 976 }
 977
 978 static long
 979 extract_des (unsigned long insn,
 980              int dialect ATTRIBUTE_UNUSED,
 981              int *invalid ATTRIBUTE_UNUSED)
 982 {
 983   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 984 }
 985
 986 /* FXM mask in mfcr and mtcrf instructions.  */
 987
 988 static unsigned long
 989 insert_fxm (unsigned long insn,
 990             long value,
 991             int dialect,
 992             const char **errmsg)
 993 {
 994   /* If the optional field on mfcr is missing that means we want to use
 995      the old form of the instruction that moves the whole cr.  In that
 996      case we'll have VALUE zero.  There doesn't seem to be a way to
 997      distinguish this from the case where someone writes mfcr %r3,0.  */
 998   if (value == 0)
 999     ;
1000
1001   /* If only one bit of the FXM field is set, we can use the new form
1002      of the instruction, which is faster.  Unlike the Power4 branch hint
1003      encoding, this is not backward compatible.  */
1004   else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1005     insn |= 1 << 20;
1006
1007   /* Any other value on mfcr is an error.  */
1008   else if ((insn & (0x3ff << 1)) == 19 << 1)
1009     {
1010       *errmsg = _("ignoring invalid mfcr mask");
1011       value = 0;
1012     }
1013
1014   return insn | ((value & 0xff) << 12);
1015 }
1016
1017 static long
1018 extract_fxm (unsigned long insn,
1019              int dialect,
1020              int *invalid)
1021 {
1022   long mask = (insn >> 12) & 0xff;
1023
1024   /* Is this a Power4 insn?  */
1025   if ((insn & (1 << 20)) != 0)
1026     {
1027       if ((dialect & PPC_OPCODE_POWER4) == 0)
1028         *invalid = 1;
1029       else
1030         {
1031           /* Exactly one bit of MASK should be set.  */
1032           if (mask == 0 || (mask & -mask) != mask)
1033             *invalid = 1;
1034         }
1035     }
1036
1037   /* Check that non-power4 form of mfcr has a zero MASK.  */
1038   else if ((insn & (0x3ff << 1)) == 19 << 1)
1039     {
1040       if (mask != 0)
1041         *invalid = 1;
1042     }
1043
1044   return mask;
1045 }
1046
1047 /* The LI field in an I form instruction.  The lower two bits are
1048    forced to zero.  */
1049
1050 static unsigned long
1051 insert_li (unsigned long insn,
1052            long value,
1053            int dialect ATTRIBUTE_UNUSED,
1054            const char **errmsg)
1055 {
1056   if ((value & 3) != 0)
1057     *errmsg = _("ignoring least significant bits in branch offset");
1058   return insn | (value & 0x3fffffc);
1059 }
1060
1061 static long
1062 extract_li (unsigned long insn,
1063             int dialect ATTRIBUTE_UNUSED,
1064             int *invalid ATTRIBUTE_UNUSED)
1065 {
1066   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1067 }
1068
1069 /* The MB and ME fields in an M form instruction expressed as a single
1070    operand which is itself a bitmask.  The extraction function always
1071    marks it as invalid, since we never want to recognize an
1072    instruction which uses a field of this type.  */
1073
1074 static unsigned long
1075 insert_mbe (unsigned long insn,
1076             long value,
1077             int dialect ATTRIBUTE_UNUSED,
1078             const char **errmsg)
1079 {
1080   unsigned long uval, mask;
1081   int mb, me, mx, count, last;
1082
1083   uval = value;
1084
1085   if (uval == 0)
1086     {
1087       *errmsg = _("illegal bitmask");
1088       return insn;
1089     }
1090
1091   mb = 0;
1092   me = 32;
1093   if ((uval & 1) != 0)
1094     last = 1;
1095   else
1096     last = 0;
1097   count = 0;
1098
1099   /* mb: location of last 0->1 transition */
1100   /* me: location of last 1->0 transition */
1101   /* count: # transitions */
1102
1103   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1104     {
1105       if ((uval & mask) && !last)
1106         {
1107           ++count;
1108           mb = mx;
1109           last = 1;
1110         }
1111       else if (!(uval & mask) && last)
1112         {
1113           ++count;
1114           me = mx;
1115           last = 0;
1116         }
1117     }
1118   if (me == 0)
1119     me = 32;
1120
1121   if (count != 2 && (count != 0 || ! last))
1122     *errmsg = _("illegal bitmask");
1123
1124   return insn | (mb << 6) | ((me - 1) << 1);
1125 }
1126
1127 static long
1128 extract_mbe (unsigned long insn,
1129              int dialect ATTRIBUTE_UNUSED,
1130              int *invalid)
1131 {
1132   long ret;
1133   int mb, me;
1134   int i;
1135
1136   *invalid = 1;
1137
1138   mb = (insn >> 6) & 0x1f;
1139   me = (insn >> 1) & 0x1f;
1140   if (mb < me + 1)
1141     {
1142       ret = 0;
1143       for (i = mb; i <= me; i++)
1144         ret |= 1L << (31 - i);
1145     }
1146   else if (mb == me + 1)
1147     ret = ~0;
1148   else /* (mb > me + 1) */
1149     {
1150       ret = ~0;
1151       for (i = me + 1; i < mb; i++)
1152         ret &= ~(1L << (31 - i));
1153     }
1154   return ret;
1155 }
1156
1157 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1158    is wrapped to the low end.  */
1159
1160 static unsigned long
1161 insert_mb6 (unsigned long insn,
1162             long value,
1163             int dialect ATTRIBUTE_UNUSED,
1164             const char **errmsg ATTRIBUTE_UNUSED)
1165 {
1166   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1167 }
1168
1169 static long
1170 extract_mb6 (unsigned long insn,
1171              int dialect ATTRIBUTE_UNUSED,
1172              int *invalid ATTRIBUTE_UNUSED)
1173 {
1174   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1175 }
1176
1177 /* The NB field in an X form instruction.  The value 32 is stored as
1178    0.  */
1179
1180 static unsigned long
1181 insert_nb (unsigned long insn,
1182            long value,
1183            int dialect ATTRIBUTE_UNUSED,
1184            const char **errmsg)
1185 {
1186   if (value < 0 || value > 32)
1187     *errmsg = _("value out of range");
1188   if (value == 32)
1189     value = 0;
1190   return insn | ((value & 0x1f) << 11);
1191 }
1192
1193 static long
1194 extract_nb (unsigned long insn,
1195             int dialect ATTRIBUTE_UNUSED,
1196             int *invalid ATTRIBUTE_UNUSED)
1197 {
1198   long ret;
1199
1200   ret = (insn >> 11) & 0x1f;
1201   if (ret == 0)
1202     ret = 32;
1203   return ret;
1204 }
1205
1206 /* The NSI field in a D form instruction.  This is the same as the SI
1207    field, only negated.  The extraction function always marks it as
1208    invalid, since we never want to recognize an instruction which uses
1209    a field of this type.  */
1210
1211 static unsigned long
1212 insert_nsi (unsigned long insn,
1213             long value,
1214             int dialect ATTRIBUTE_UNUSED,
1215             const char **errmsg ATTRIBUTE_UNUSED)
1216 {
1217   return insn | (-value & 0xffff);
1218 }
1219
1220 static long
1221 extract_nsi (unsigned long insn,
1222              int dialect ATTRIBUTE_UNUSED,
1223              int *invalid)
1224 {
1225   *invalid = 1;
1226   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1227 }
1228
1229 /* The RA field in a D or X form instruction which is an updating
1230    load, which means that the RA field may not be zero and may not
1231    equal the RT field.  */
1232
1233 static unsigned long
1234 insert_ral (unsigned long insn,
1235             long value,
1236             int dialect ATTRIBUTE_UNUSED,
1237             const char **errmsg)
1238 {
1239   if (value == 0
1240       || (unsigned long) value == ((insn >> 21) & 0x1f))
1241     *errmsg = "invalid register operand when updating";
1242   return insn | ((value & 0x1f) << 16);
1243 }
1244
1245 /* The RA field in an lmw instruction, which has special value
1246    restrictions.  */
1247
1248 static unsigned long
1249 insert_ram (unsigned long insn,
1250             long value,
1251             int dialect ATTRIBUTE_UNUSED,
1252             const char **errmsg)
1253 {
1254   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1255     *errmsg = _("index register in load range");
1256   return insn | ((value & 0x1f) << 16);
1257 }
1258
1259 /* The RA field in the DQ form lq instruction, which has special
1260    value restrictions.  */
1261
1262 static unsigned long
1263 insert_raq (unsigned long insn,
1264             long value,
1265             int dialect ATTRIBUTE_UNUSED,
1266             const char **errmsg)
1267 {
1268   long rtvalue = (insn & RT_MASK) >> 21;
1269
1270   if (value == rtvalue)
1271     *errmsg = _("source and target register operands must be different");
1272   return insn | ((value & 0x1f) << 16);
1273 }
1274
1275 /* The RA field in a D or X form instruction which is an updating
1276    store or an updating floating point load, which means that the RA
1277    field may not be zero.  */
1278
1279 static unsigned long
1280 insert_ras (unsigned long insn,
1281             long value,
1282             int dialect ATTRIBUTE_UNUSED,
1283             const char **errmsg)
1284 {
1285   if (value == 0)
1286     *errmsg = _("invalid register operand when updating");
1287   return insn | ((value & 0x1f) << 16);
1288 }
1289
1290 /* The RB field in an X form instruction when it must be the same as
1291    the RS field in the instruction.  This is used for extended
1292    mnemonics like mr.  This operand is marked FAKE.  The insertion
1293    function just copies the BT field into the BA field, and the
1294    extraction function just checks that the fields are the same.  */
1295
1296 static unsigned long
1297 insert_rbs (unsigned long insn,
1298             long value ATTRIBUTE_UNUSED,
1299             int dialect ATTRIBUTE_UNUSED,
1300             const char **errmsg ATTRIBUTE_UNUSED)
1301 {
1302   return insn | (((insn >> 21) & 0x1f) << 11);
1303 }
1304
1305 static long
1306 extract_rbs (unsigned long insn,
1307              int dialect ATTRIBUTE_UNUSED,
1308              int *invalid)
1309 {
1310   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1311     *invalid = 1;
1312   return 0;
1313 }
1314
1315 /* The RT field of the DQ form lq instruction, which has special
1316    value restrictions.  */
1317
1318 static unsigned long
1319 insert_rtq (unsigned long insn,
1320             long value,
1321             int dialect ATTRIBUTE_UNUSED,
1322             const char **errmsg)
1323 {
1324   if ((value & 1) != 0)
1325     *errmsg = _("target register operand must be even");
1326   return insn | ((value & 0x1f) << 21);
1327 }
1328
1329 /* The RS field of the DS form stq instruction, which has special
1330    value restrictions.  */
1331
1332 static unsigned long
1333 insert_rsq (unsigned long insn,
1334             long value ATTRIBUTE_UNUSED,
1335             int dialect ATTRIBUTE_UNUSED,
1336             const char **errmsg)
1337 {
1338   if ((value & 1) != 0)
1339     *errmsg = _("source register operand must be even");
1340   return insn | ((value & 0x1f) << 21);
1341 }
1342
1343 /* The SH field in an MD form instruction.  This is split.  */
1344
1345 static unsigned long
1346 insert_sh6 (unsigned long insn,
1347             long value,
1348             int dialect ATTRIBUTE_UNUSED,
1349             const char **errmsg ATTRIBUTE_UNUSED)
1350 {
1351   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1352 }
1353
1354 static long
1355 extract_sh6 (unsigned long insn,
1356              int dialect ATTRIBUTE_UNUSED,
1357              int *invalid ATTRIBUTE_UNUSED)
1358 {
1359   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1360 }
1361
1362 /* The SPR field in an XFX form instruction.  This is flipped--the
1363    lower 5 bits are stored in the upper 5 and vice- versa.  */
1364
1365 static unsigned long
1366 insert_spr (unsigned long insn,
1367             long value,
1368             int dialect ATTRIBUTE_UNUSED,
1369             const char **errmsg ATTRIBUTE_UNUSED)
1370 {
1371   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1372 }
1373
1374 static long
1375 extract_spr (unsigned long insn,
1376              int dialect ATTRIBUTE_UNUSED,
1377              int *invalid ATTRIBUTE_UNUSED)
1378 {
1379   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1380 }
1381
1382 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1383    is optional.  When TBR is omitted, it must be inserted as 268 (the
1384    magic number of the TB register).  These functions treat 0
1385    (indicating an omitted optional operand) as 268.  This means that
1386    ``mftb 4,0'' is not handled correctly.  This does not matter very
1387    much, since the architecture manual does not define mftb as
1388    accepting any values other than 268 or 269.  */
1389
1390 #define TB (268)
1391
1392 static unsigned long
1393 insert_tbr (unsigned long insn,
1394             long value,
1395             int dialect ATTRIBUTE_UNUSED,
1396             const char **errmsg ATTRIBUTE_UNUSED)
1397 {
1398   if (value == 0)
1399     value = TB;
1400   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1401 }
1402
1403 static long
1404 extract_tbr (unsigned long insn,
1405              int dialect ATTRIBUTE_UNUSED,
1406              int *invalid ATTRIBUTE_UNUSED)
1407 {
1408   long ret;
1409
1410   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1411   if (ret == TB)
1412     ret = 0;
1413   return ret;
1414 }
1415 \f
1416 /* Macros used to form opcodes.  */
1417
1418 /* The main opcode.  */
1419 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1420 #define OP_MASK OP (0x3f)
1421
1422 /* The main opcode combined with a trap code in the TO field of a D
1423    form instruction.  Used for extended mnemonics for the trap
1424    instructions.  */
1425 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1426 #define OPTO_MASK (OP_MASK | TO_MASK)
1427
1428 /* The main opcode combined with a comparison size bit in the L field
1429    of a D form or X form instruction.  Used for extended mnemonics for
1430    the comparison instructions.  */
1431 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1432 #define OPL_MASK OPL (0x3f,1)
1433
1434 /* An A form instruction.  */
1435 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1436 #define A_MASK A (0x3f, 0x1f, 1)
1437
1438 /* An A_MASK with the FRB field fixed.  */
1439 #define AFRB_MASK (A_MASK | FRB_MASK)
1440
1441 /* An A_MASK with the FRC field fixed.  */
1442 #define AFRC_MASK (A_MASK | FRC_MASK)
1443
1444 /* An A_MASK with the FRA and FRC fields fixed.  */
1445 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1446
1447 /* A B form instruction.  */
1448 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1449 #define B_MASK B (0x3f, 1, 1)
1450
1451 /* A B form instruction setting the BO field.  */
1452 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1453 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1454
1455 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1456    matching a conditional branch regardless of the setting of the y
1457    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1458 #define Y_MASK   (((unsigned long) 1) << 21)
1459 #define AT1_MASK (((unsigned long) 3) << 21)
1460 #define AT2_MASK (((unsigned long) 9) << 21)
1461 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1462 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1463
1464 /* A B form instruction setting the BO field and the condition bits of
1465    the BI field.  */
1466 #define BBOCB(op, bo, cb, aa, lk) \
1467   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1468 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1469
1470 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1471 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1472 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1473 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1474
1475 /* A BBOYCB_MASK in which the BI field is fixed.  */
1476 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1477 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1478
1479 /* An Context form instruction.  */
1480 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1481 #define CTX_MASK       CTX(0x3f, 0x7)
1482
1483 /* An User Context form instruction.  */
1484 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1485 #define UCTX_MASK      UCTX(0x3f, 0x1f)
1486
1487 /* The main opcode mask with the RA field clear.  */
1488 #define DRA_MASK (OP_MASK | RA_MASK)
1489
1490 /* A DS form instruction.  */
1491 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1492 #define DS_MASK DSO (0x3f, 3)
1493
1494 /* A DE form instruction.  */
1495 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1496 #define DE_MASK DEO (0x3e, 0xf)
1497
1498 /* An EVSEL form instruction.  */
1499 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1500 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1501
1502 /* An M form instruction.  */
1503 #define M(op, rc) (OP (op) | ((rc) & 1))
1504 #define M_MASK M (0x3f, 1)
1505
1506 /* An M form instruction with the ME field specified.  */
1507 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1508
1509 /* An M_MASK with the MB and ME fields fixed.  */
1510 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1511
1512 /* An M_MASK with the SH and ME fields fixed.  */
1513 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1514
1515 /* An MD form instruction.  */
1516 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1517 #define MD_MASK MD (0x3f, 0x7, 1)
1518
1519 /* An MD_MASK with the MB field fixed.  */
1520 #define MDMB_MASK (MD_MASK | MB6_MASK)
1521
1522 /* An MD_MASK with the SH field fixed.  */
1523 #define MDSH_MASK (MD_MASK | SH6_MASK)
1524
1525 /* An MDS form instruction.  */
1526 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1527 #define MDS_MASK MDS (0x3f, 0xf, 1)
1528
1529 /* An MDS_MASK with the MB field fixed.  */
1530 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1531
1532 /* An SC form instruction.  */
1533 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1534 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1535
1536 /* An VX form instruction.  */
1537 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1538
1539 /* The mask for an VX form instruction.  */
1540 #define VX_MASK VX(0x3f, 0x7ff)
1541
1542 /* An VA form instruction.  */
1543 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1544
1545 /* The mask for an VA form instruction.  */
1546 #define VXA_MASK VXA(0x3f, 0x3f)
1547
1548 /* An VXR form instruction.  */
1549 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1550
1551 /* The mask for a VXR form instruction.  */
1552 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1553
1554 /* An X form instruction.  */
1555 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1556
1557 /* An X form instruction with the RC bit specified.  */
1558 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1559
1560 /* The mask for an X form instruction.  */
1561 #define X_MASK XRC (0x3f, 0x3ff, 1)
1562
1563 /* An X_MASK with the RA field fixed.  */
1564 #define XRA_MASK (X_MASK | RA_MASK)
1565
1566 /* An X_MASK with the RB field fixed.  */
1567 #define XRB_MASK (X_MASK | RB_MASK)
1568
1569 /* An X_MASK with the RT field fixed.  */
1570 #define XRT_MASK (X_MASK | RT_MASK)
1571
1572 /* An X_MASK with the RA and RB fields fixed.  */
1573 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1574
1575 /* An XRARB_MASK, but with the L bit clear.  */
1576 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1577
1578 /* An X_MASK with the RT and RA fields fixed.  */
1579 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1580
1581 /* An XRTRA_MASK, but with L bit clear.  */
1582 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1583
1584 /* An X form comparison instruction.  */
1585 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1586
1587 /* The mask for an X form comparison instruction.  */
1588 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1589
1590 /* The mask for an X form comparison instruction with the L field
1591    fixed.  */
1592 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1593
1594 /* An X form trap instruction with the TO field specified.  */
1595 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1596 #define XTO_MASK (X_MASK | TO_MASK)
1597
1598 /* An X form tlb instruction with the SH field specified.  */
1599 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1600 #define XTLB_MASK (X_MASK | SH_MASK)
1601
1602 /* An X form sync instruction.  */
1603 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1604
1605 /* An X form sync instruction with everything filled in except the LS field.  */
1606 #define XSYNC_MASK (0xff9fffff)
1607
1608 /* An X form AltiVec dss instruction.  */
1609 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1610 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1611
1612 /* An XFL form instruction.  */
1613 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1614 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1615
1616 /* An X form isel instruction.  */
1617 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1618 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1619
1620 /* An XL form instruction with the LK field set to 0.  */
1621 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1622
1623 /* An XL form instruction which uses the LK field.  */
1624 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1625
1626 /* The mask for an XL form instruction.  */
1627 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1628
1629 /* An XL form instruction which explicitly sets the BO field.  */
1630 #define XLO(op, bo, xop, lk) \
1631   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1632 #define XLO_MASK (XL_MASK | BO_MASK)
1633
1634 /* An XL form instruction which explicitly sets the y bit of the BO
1635    field.  */
1636 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1637 #define XLYLK_MASK (XL_MASK | Y_MASK)
1638
1639 /* An XL form instruction which sets the BO field and the condition
1640    bits of the BI field.  */
1641 #define XLOCB(op, bo, cb, xop, lk) \
1642   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1643 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1644
1645 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1646 #define XLBB_MASK (XL_MASK | BB_MASK)
1647 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1648 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1649
1650 /* An XL_MASK with the BO and BB fields fixed.  */
1651 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1652
1653 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1654 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1655
1656 /* An XO form instruction.  */
1657 #define XO(op, xop, oe, rc) \
1658   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1659 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1660
1661 /* An XO_MASK with the RB field fixed.  */
1662 #define XORB_MASK (XO_MASK | RB_MASK)
1663
1664 /* An XS form instruction.  */
1665 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1666 #define XS_MASK XS (0x3f, 0x1ff, 1)
1667
1668 /* A mask for the FXM version of an XFX form instruction.  */
1669 #define XFXFXM_MASK (X_MASK | (1 << 11))
1670
1671 /* An XFX form instruction with the FXM field filled in.  */
1672 #define XFXM(op, xop, fxm) \
1673   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1674
1675 /* An XFX form instruction with the SPR field filled in.  */
1676 #define XSPR(op, xop, spr) \
1677   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1678 #define XSPR_MASK (X_MASK | SPR_MASK)
1679
1680 /* An XFX form instruction with the SPR field filled in except for the
1681    SPRBAT field.  */
1682 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1683
1684 /* An XFX form instruction with the SPR field filled in except for the
1685    SPRG field.  */
1686 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1687
1688 /* An X form instruction with everything filled in except the E field.  */
1689 #define XE_MASK (0xffff7fff)
1690
1691 /* An X form user context instruction.  */
1692 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1693 #define XUC_MASK      XUC(0x3f, 0x1f)
1694
1695 /* The BO encodings used in extended conditional branch mnemonics.  */
1696 #define BODNZF  (0x0)
1697 #define BODNZFP (0x1)
1698 #define BODZF   (0x2)
1699 #define BODZFP  (0x3)
1700 #define BODNZT  (0x8)
1701 #define BODNZTP (0x9)
1702 #define BODZT   (0xa)
1703 #define BODZTP  (0xb)
1704
1705 #define BOF     (0x4)
1706 #define BOFP    (0x5)
1707 #define BOFM4   (0x6)
1708 #define BOFP4   (0x7)
1709 #define BOT     (0xc)
1710 #define BOTP    (0xd)
1711 #define BOTM4   (0xe)
1712 #define BOTP4   (0xf)
1713
1714 #define BODNZ   (0x10)
1715 #define BODNZP  (0x11)
1716 #define BODZ    (0x12)
1717 #define BODZP   (0x13)
1718 #define BODNZM4 (0x18)
1719 #define BODNZP4 (0x19)
1720 #define BODZM4  (0x1a)
1721 #define BODZP4  (0x1b)
1722
1723 #define BOU     (0x14)
1724
1725 /* The BI condition bit encodings used in extended conditional branch
1726    mnemonics.  */
1727 #define CBLT    (0)
1728 #define CBGT    (1)
1729 #define CBEQ    (2)
1730 #define CBSO    (3)
1731
1732 /* The TO encodings used in extended trap mnemonics.  */
1733 #define TOLGT   (0x1)
1734 #define TOLLT   (0x2)
1735 #define TOEQ    (0x4)
1736 #define TOLGE   (0x5)
1737 #define TOLNL   (0x5)
1738 #define TOLLE   (0x6)
1739 #define TOLNG   (0x6)
1740 #define TOGT    (0x8)
1741 #define TOGE    (0xc)
1742 #define TONL    (0xc)
1743 #define TOLT    (0x10)
1744 #define TOLE    (0x14)
1745 #define TONG    (0x14)
1746 #define TONE    (0x18)
1747 #define TOU     (0x1f)
1748 \f
1749 /* Smaller names for the flags so each entry in the opcodes table will
1750    fit on a single line.  */
1751 #undef  PPC
1752 #define PPC     PPC_OPCODE_PPC
1753 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1754 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1755 #define POWER4  PPC_OPCODE_POWER4
1756 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1757 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1758 #define PPC403  PPC_OPCODE_403
1759 #define PPC405  PPC403
1760 #define PPC440  PPC_OPCODE_440
1761 #define PPC750  PPC
1762 #define PPC860  PPC
1763 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1764 #define POWER   PPC_OPCODE_POWER
1765 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1766 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1767 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1768 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1769 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1770 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1771 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1772 #define MFDEC1  PPC_OPCODE_POWER
1773 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1774 #define BOOKE   PPC_OPCODE_BOOKE
1775 #define BOOKE64 PPC_OPCODE_BOOKE64
1776 #define CLASSIC PPC_OPCODE_CLASSIC
1777 #define PPCSPE  PPC_OPCODE_SPE
1778 #define PPCISEL PPC_OPCODE_ISEL
1779 #define PPCEFS  PPC_OPCODE_EFS
1780 #define PPCBRLK PPC_OPCODE_BRLOCK
1781 #define PPCPMR  PPC_OPCODE_PMR
1782 #define PPCCHLK PPC_OPCODE_CACHELCK
1783 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1784 #define PPCRFMCI        PPC_OPCODE_RFMCI
1785 \f
1786 /* The opcode table.
1787
1788    The format of the opcode table is:
1789
1790    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1791
1792    NAME is the name of the instruction.
1793    OPCODE is the instruction opcode.
1794    MASK is the opcode mask; this is used to tell the disassembler
1795      which bits in the actual opcode must match OPCODE.
1796    FLAGS are flags indicated what processors support the instruction.
1797    OPERANDS is the list of operands.
1798
1799    The disassembler reads the table in order and prints the first
1800    instruction which matches, so this table is sorted to put more
1801    specific instructions before more general instructions.  It is also
1802    sorted by major opcode.  */
1803
1804 const struct powerpc_opcode powerpc_opcodes[] = {
1805 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1806 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1807 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1808 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1809 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1810 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1811 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1812 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1813 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1814 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1815 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1816 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1817 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1818 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1819 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1820 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1821
1822 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1823 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1824 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1825 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1826 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1827 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1828 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1829 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1830 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1831 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1832 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1833 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1834 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1835 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1836 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1837 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1838 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1839 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1840 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1841 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1842 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1843 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1844 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1845 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1846 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1847 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1848 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1849 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1850 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1851 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1852
1853 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1854 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1855 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1856 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1857 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1858 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1859 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1860 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1861 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1862 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1863 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1864 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1865 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1866 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1867 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1868 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1869 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1870 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1871 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1872 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1873 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1874 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1875 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1876 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1877 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1878 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1879 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1880 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1881 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1882 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1883 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1884 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1885 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1886 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1887 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1888 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1889 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1890 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1891 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1892 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1893 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1894 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1895 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1896 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1897 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1898 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1899 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1900 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1901 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1902 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1903 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1904 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1905 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1906 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1907 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1908 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1909 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1910 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1911 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1912 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1913 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1914 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1915 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1916 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1917 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1918 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1919 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1920 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1921 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1922 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1923 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1924 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1925 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1926 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1927 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1928 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1929 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1930 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1931 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1932 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1933 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1934 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1935 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1936 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1937 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1938 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1939 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1940 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1941 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1942 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1943 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1944 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1945 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1946 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1947 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1948 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1949 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1950 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1951 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1952 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1953 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1954 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1955 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1956 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1957 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1958 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1959 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1960 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1961 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1962 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1963 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1964 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1965 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1966 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1967 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1968 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1969 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1970 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1971 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1972 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1973 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1974 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1975 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1976 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1977 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1978 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1979 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1980 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1981 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1982 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1983 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1984 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1985 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1986 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1987 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1988 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1989 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1990 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1991 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1992 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1993 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1994 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1995 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1996 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1997 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1998 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1999 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2000 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2001 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2002 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2003 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2004 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2005 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2006 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2007 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2008 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2010 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2011 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2012 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2013 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2014 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2015 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2016 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2017 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2018 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2019 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2020 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2021 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2022 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2023 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2024 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2025 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2026 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2027 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2028 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2029 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2030 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2031 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2032 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2033 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2034 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2035 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2036 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2037 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2038 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2039 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2040 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2041 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2042 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2043 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2044 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2045 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2046 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2047 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2048 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2049 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2050 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2051 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2052 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2053 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2054 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2055 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2056 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2057 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2058 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2059 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2060 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2061 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2062 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2063 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2064 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2065 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2066 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2067 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2068 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2069 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2070 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2071 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2072 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2073 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2074 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2075 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2076 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2077 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2078 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2079 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2080 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2081 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2082 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2083 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2084 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2085 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2086 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2087 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2088 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2089 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2090 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2091 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2092 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2093 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2094
2095 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2096 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2097 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2098 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2099 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2100 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2101 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2102 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2103 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2104 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2105 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2106 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2107 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2108
2109 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2110
2111 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2112 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2113 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2114 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2115 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2116 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2117 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2118 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2119 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2120 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2121
2122 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2123 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2124 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2125 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2126 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2127 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2128 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2129 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2130 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2131 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2132 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2133 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2134 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2135 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2136
2137 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2138 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2139 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2140 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2141 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2142 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2143
2144 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2145 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2146 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2147 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2148 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2149 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2150 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2151 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2152 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2153 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2154 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2155 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2156 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2157 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2158 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2159 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2160 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2161 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2162 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2163 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2164 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2165 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2166
2167 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2168 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2169 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2170 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2171 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2172 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2173 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2174 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2175 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2176 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2177 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2178 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2179 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2180 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2181
2182 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2183 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2184 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2185 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2186 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2187 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2188 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2189 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2190 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2191 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2192 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2193 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2194 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2195 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2196 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2197 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2198 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2199 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2200 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2201 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2202 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2203 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2204 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2205
2206 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2207 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2208 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2209 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2210 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2211 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2212 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2213 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2214 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2215 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2216 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2217 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2218 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2219 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2220 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2221 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2222 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2223 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2224 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2225 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2226 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2227 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2228 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2229
2230 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2231 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2232 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2233 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2234 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2235 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2236 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2237 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2238 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2239 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2240 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2241 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2242 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2243 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2244 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2245 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2246
2247 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2248 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2249 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2250 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2251 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2252 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2253 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2254 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2255 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2256 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2257 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2258 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2259
2260 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2261 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2262 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2263 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2264 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2265 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2266 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2267 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2268 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2269 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2270 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2271 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2272
2273 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2274 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2275 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2276 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2277 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2278 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2279
2280 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2281 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2282 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2283 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2284 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2285 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2286
2287 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2288 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2289 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2290 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2291 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2292 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2293 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2294 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2295
2296 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2297 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2298
2299 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2300 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2301 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2302 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2303
2304 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2305 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2306 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2307 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2308
2309 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2310 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2311 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2312 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2313 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2314 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2315 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2316 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2317
2318 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2319 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2320 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2321 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2322
2323 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2324 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2325 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2326 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2327
2328 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2329 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2330 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2331 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2332
2333 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2334 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2335 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2336 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2337
2338 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2339
2340 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2341 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2342
2343 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2344 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2345
2346 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2347 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2348
2349 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2350
2351 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2352 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2353 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2354 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2355
2356 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2357 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2358 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2359 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2360
2361 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2362 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2363 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2364 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2365
2366 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2367 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2368 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2369
2370 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2371 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2372 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2373
2374 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2375 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2376 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2377 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2378 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2379 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
2380
2381 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2382 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2383 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
2384 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
2385 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2386
2387 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2388 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2389 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2390 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2391 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2392 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2393 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2394 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2395 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2396 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2397 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2398 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2399 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2400 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2401 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2402 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2403 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2404 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2405 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2406 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2407 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2408 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2409 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2410 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2411 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2412 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2413 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2414 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2415 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2416 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2417 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2418 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2419 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2420 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2421 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2422 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2423 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2424 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2425 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2426 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2427 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2428 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2429 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2430 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2431 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2432 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2433 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2434 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2435 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2436 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2437 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2438 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2439 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2440 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2441 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2442 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2443 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2444 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2445 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2446 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2447 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2448 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2449 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2450 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2451 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2452 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2453 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2454 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2455 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2456 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2457 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2458 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2459 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2460 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2461 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2462 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2463 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2464 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2465 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2466 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2467 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2468 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2469 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2470 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2471 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2472 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2473 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2474 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2475 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2476 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2477 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2478 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2479 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2480 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2481 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2482 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2483 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2484 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2485 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2486 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2487 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2488 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2489 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2490 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2491 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2492 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2493 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2494 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2495 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2496 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2497 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2498 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2499 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2500 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2501 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2502 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2503 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2504 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2505 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2506 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2507 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2508 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2509 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2510 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2511 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2512 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2513 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2514 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2515 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2516 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2517 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2518 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2519 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2520 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2521 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2522 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2523 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2524 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2525 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2526 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2527 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2528 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2529 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2530 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2531 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2532 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2533 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2534 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2535 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2536 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2537 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2538 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2539 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2540 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2541 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2542 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2543 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2544 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2545 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2546 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2547 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2548 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2549 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2550 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2551 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2552 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2553 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2554 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2555 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2556 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2557 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2558 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2559 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2560 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2561 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2562 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2563 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2564 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2565 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2566 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2567 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2568 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2569 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2570 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2571 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2572 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2573 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2574 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2575 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2576 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2577 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2578 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2579 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2580 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2581 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2582 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2583 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2584 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2585 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2586 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2587 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2588 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2589 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2590 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2591 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2592 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2593 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2594 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2595 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2596 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2597 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2598 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2599 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2600 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2601 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2602 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2603 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2604 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2605 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2606 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2607 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2608 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2609 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2610 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2611 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2612 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2613 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2614 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2615 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2616 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2617 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2618 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2619 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2620 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2621 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2622 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2623 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2624 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2625 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2626 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2627 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2628 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2629 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2630 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2631 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2632 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2633 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2634 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2635 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2636 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2637 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2638 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2639 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2640 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2641 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2642 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2643 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2644 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2645 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2646 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2647 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2648 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2649 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2650 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2651
2652 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2653 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2654 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2655 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2656 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2657
2658 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2659 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2660 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2661 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2662
2663 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2664
2665 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2666 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2667 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2668 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2669 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2670 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2671 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2672 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2673 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2674 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2675 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2676 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2677 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2678 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2679 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2680 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2681 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2682 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2683 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2684 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2685 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2686 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2687 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2688 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2689 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2690 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2691 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2692 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2693 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2694 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2695 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2696 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2698 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2699 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2700 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2701 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2702 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2704 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2705 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2706 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2707 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2708 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2711 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2712 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2713 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2714 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2717 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2718 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2719 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2720 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2723 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2724 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2725 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2726 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2729 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2730 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2731 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2732 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2734 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2735 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2736 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2737 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2738 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2741 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2742 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2743 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2745 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2746 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2747 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2748 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2753 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2754 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2759 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2760 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2765 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2766 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2771 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2772 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2777 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2778 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2781 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2783 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2784 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2787 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2788 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2789 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2790 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2793 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2794 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2795 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2796 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2799 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2800 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2801 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2802 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2805 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2806 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2807 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2808 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2811 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2812 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2813 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2814 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2817 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2818 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2819 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2820 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2823 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2824 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2825 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2828 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2829 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2830 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2831 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2832 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2833 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2834 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2835 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2836 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2837 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2838 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2839 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2840 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2841 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2842 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2843 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2844 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2845 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2846 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2847 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2848 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2849 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2850 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2851 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2852 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2853 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2854 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2855 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2856 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2857 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2858 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2860 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2861 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2862 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2863 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2864 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2866 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2867 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2868 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2869 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2870 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2872 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2875 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2876 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2878 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2879 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2880 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2881 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2882 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2883 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2884 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2885 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2886 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2887
2888 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2889
2890 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2891 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2892 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2893
2894 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2895 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2896
2897 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2898
2899 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2900
2901 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2902 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2903
2904 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2905 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2906
2907 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2908
2909 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2910
2911 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2912 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2913
2914 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2915
2916 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2917 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2918
2919 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2920 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2921 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2922 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2923 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2924 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2926 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2927 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2931 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2932 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2933 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2934 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2936 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2937 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2942 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2943 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2944 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2946 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2947 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2951 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2952 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2953 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2954 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2956 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2957 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2962 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2963 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2964 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2966 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2967 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2972 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2973 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2974 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2976 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2977 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2982 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2986 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2987 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2991 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2992 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2996 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2997 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3002 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3006 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3007 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3012 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3016 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3017 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3021 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3022 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3027 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3032 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3037 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3042 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3043 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3044 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3045 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3046 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3047 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3048 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3049 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3050 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3051 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3052 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3053 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3054 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3055 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3056 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3057 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3058 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3059 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3060 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3061 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3062 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3063 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3064 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3065 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3066 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3067 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3068 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3069 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3070 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3071
3072 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3073 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3074
3075 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3076 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3077
3078 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3079 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3080 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3081 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3082 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3083 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3084 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3085 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3086
3087 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3088 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3089
3090 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3091 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3092 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3093 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3094
3095 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3096 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3097 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3098 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3099 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3100 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3101
3102 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3103 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3104 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3105
3106 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3107 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3108
3109 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3110 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3111
3112 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3113 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3114
3115 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3116 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3117
3118 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3119 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3120
3121 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3122 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3123 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3124 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3125 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3126 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3127
3128 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3129 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3130
3131 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3132 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3133
3134 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3135 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3136
3137 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3138 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3139 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3140 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3141
3142 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3143 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3144
3145 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
3146 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3147 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3148 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3149
3150 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3151 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3152 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3153 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3154 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3155 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3156 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3157 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3158 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3159 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3160 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3161 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3162 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3163 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3164 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3165 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3166 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3167 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3168 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3169 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3170 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3171 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3172 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3173 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3174 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3175 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3176 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3177 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3178 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3179 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3180 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3181
3182 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3183 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3184 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3185 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3186 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3187 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3188 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3189 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3190 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3191 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3192 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3193 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3194
3195 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3196 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3197
3198 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3199 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3200 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3201 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3202 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3203 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3204 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3205 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3206
3207 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3208 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3209
3210 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3211 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3212 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3213 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3214
3215 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
3216 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3217
3218 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
3219
3220 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
3221
3222 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3223 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3224
3225 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
3226 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3227
3228 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3229 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3230 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3231 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3232
3233 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3234 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3235 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3236 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3237
3238 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3239 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3240
3241 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3242 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3243
3244 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3245 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3246
3247 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3248
3249 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3250
3251 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
3252 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
3253 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3254 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3255
3256 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3257 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3258 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3259 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3260 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3261 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3262 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3263 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3264
3265 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3266
3267 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3268
3269 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3270 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3271
3272 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3273
3274 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3275
3276 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3277 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3278
3279 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3280 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3281
3282 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3283 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3284 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3285 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3286 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3287 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3288 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3289 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3290 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3291 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3292 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3293 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3294 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3295 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3296 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3297
3298 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3299 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3300
3301 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3302 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3303
3304 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3305 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3306
3307 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3308
3309 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3310
3311 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
3312
3313 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3314
3315 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
3316
3317 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3318
3319 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3320
3321 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3322 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3323 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3324 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3325
3326 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3327 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3328 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3329 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3330
3331 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3332
3333 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3334
3335 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3336
3337 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3338 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3339 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3340 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3341
3342 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
3343
3344 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3345
3346 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3347
3348 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3349
3350 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3351 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3352 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3353 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3354 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3355 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3356 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3357 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3358
3359 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3360 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3361 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3362 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3363 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3364 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3365 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3366 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3367
3368 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3369
3370 { "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,        { RS }},
3371 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3372
3373 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3374
3375 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
3376
3377 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
3378
3379 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
3380 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3381
3382 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3383
3384 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
3385
3386 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3387 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3388
3389 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3390 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3391
3392 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3393
3394 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3395 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3396
3397 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3398
3399 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3400
3401 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3402 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
3403
3404 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3405 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3406
3407 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3408
3409 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3410 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3411 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3412 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3413 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3414 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3415 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3416 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3417
3418 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3419 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3420 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3421 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3422 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3423 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3424 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3425 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3426
3427 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3428
3429 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
3430
3431 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
3432
3433 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3434 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3435
3436 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3437 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3438
3439 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
3440
3441 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3442
3443 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3444 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3445 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3446 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3447 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3448 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3449 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3450 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3451
3452 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3453 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3454 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3455 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3456
3457 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3458 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3459 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3460 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3461 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3462 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3463 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3464 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3465
3466 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3467 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3468 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3469 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3470 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3471 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3472 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3473 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3474
3475 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3476 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3477 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3478
3479 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
3480
3481 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3482
3483 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3484 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3485
3486 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3487
3488 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3489
3490 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3491
3492 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3493 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3494 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3495 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3496
3497 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3498 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3499 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3500 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3501 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3502 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3503 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3504 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3505
3506 { "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
3507
3508 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3509
3510 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3511 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3512
3513 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
3514
3515 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
3516
3517 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3518 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3519
3520 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3521
3522 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
3523
3524 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3525 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
3526
3527 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3528
3529 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3530
3531 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3532 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3533
3534 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3535
3536 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3537 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3538 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3539 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3540 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3541 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3542 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3543 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3544 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3545 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3546 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3547 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3548 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3549 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3550 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3551 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3552 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3553 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3554 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3555 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3556 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3557 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3558 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3559 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3560 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3561 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3562 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3563 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3564 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3565 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3566 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3567 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3568 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3569 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3570 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3571
3572 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3573 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3574 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3575 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3576
3577 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3578
3579 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3580 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3581 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3582 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3583 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3584 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3585 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3586 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3587 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3588 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3589 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3590 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3591 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3592 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3593 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3594 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3595 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3596 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3597 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3598 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3599 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3600 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3601 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3602 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3603 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3604 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3605 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3606 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3607 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3608 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3609 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3610 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3611 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3612 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3613 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3614 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3615 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3616 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3617 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3618 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3619 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3620 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3621 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
3622 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
3623 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
3624 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
3625 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3626 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3627 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3628 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3629 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3630 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3631 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
3632 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3633 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3634 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3635 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3636 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3637 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3638 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3639 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3640 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3641 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3642 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3643 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3644 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3645 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3646 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3647 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3648 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3649 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3650 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3651 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3652 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3653 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3654 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3655 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3656 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3657 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3658 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3659 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3660 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3661 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3662 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3663 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3664 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3665 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3666 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3667 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3668 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3669 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3670 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3671 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3672 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3673 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3674 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3675 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3676 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3677 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3678 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3679 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3680 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3681 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3682 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3683 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3684 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3685 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3686 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3687 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3688 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3689 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3690 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3691 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3692 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3693 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3694 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3695 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3696 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3697 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3698 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3699 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3700 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3701 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3702 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3703 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3704 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3705 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3706 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3707 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3708 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3709 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3710 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3711 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3712 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3713 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3714 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3715 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3716 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3717 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3718 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3719 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3720 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3721 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3722 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3723 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3724 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3725 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3726 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3727 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3728 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3729 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3730 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3731 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3732 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3733 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3734 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3735 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3736 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3737 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3738 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3739 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3740 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3741 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3742 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3743 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3744 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3745 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3746 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3747 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3748 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3749 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3750 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3751 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3752 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3753 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3754 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3755 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3756 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3757 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3758 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3759 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3760 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3761 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3762 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3763 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3764 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3765
3766 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
3767
3768 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3769 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3770
3771 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
3772
3773 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
3774
3775 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3776 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3777
3778 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3779
3780 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3781 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3782 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3783 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3784
3785 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3786 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3787 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3788 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3789
3790 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3791
3792 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3793
3794 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3795
3796 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3797
3798 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3799
3800 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3801
3802 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3803 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3804
3805 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3806 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3807
3808 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3809
3810 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3811
3812 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3813
3814 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3815
3816 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3817
3818 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3819
3820 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3821
3822 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3823 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3824
3825 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3826 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3827
3828 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3829
3830 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3831
3832 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3833
3834 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3835
3836 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3837
3838 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3839 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3840 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3841 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3842
3843 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3844 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3845 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3846 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3847 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3848 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3849 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3850 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3851 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3852 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3853 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3854 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3855 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3856 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3857 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3858 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3859 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3860 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3861 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3862 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3863 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3864 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3865 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3866 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3867 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3868 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3869 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3870 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3871 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3872 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3873 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3874 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3875 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3876 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3877 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3878
3879 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3880 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3881
3882 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3883 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3884 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3885 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3886
3887 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3888 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3889
3890 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3891 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3892 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3893 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3894
3895 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3896 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3897 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3898 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3899 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3900 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3901 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3902 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3903 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3904 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3905 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3906 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3907 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3908 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3909 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3910 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3911 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3912 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3913 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3914 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3915 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3916 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3917 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3918 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3919 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3920 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3921 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3922 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3923 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3924 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3925 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3926 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3927 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3928 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3929 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3930 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3931 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3932 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3933 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3934 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3935 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3936 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3937 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
3938 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3939 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3940 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3941 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3942 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3943 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3944 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3945 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3946 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3947 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3948 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3949 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3950 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3951 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3952 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3953 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3954 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3955 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3956 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3957 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3958 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3959 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3960 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3961 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3962 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3963 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3964 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3965 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3966 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3967 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3968 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3969 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3970 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3971 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3972 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3973 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3974 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3975 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3976 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3977 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3978 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3979 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
3980 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
3981 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
3982 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
3983 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
3984 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
3985 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
3986 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
3987 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
3988 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
3989 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
3990 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
3991 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
3992 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
3993 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
3994 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
3995 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
3996 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
3997 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
3998 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
3999 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4000 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4001 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4002 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4003 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4004 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4005 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4006 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4007 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
4008 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
4009 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
4010 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
4011 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
4012 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
4013 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
4014 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
4015 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
4016 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
4017 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
4018 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
4019 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4020 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
4021 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4022 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
4023 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4024 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4025 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4026 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
4027 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
4028 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
4029 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
4030 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
4031 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
4032 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
4033 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
4034 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4035 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
4036 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
4037 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4038 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
4039 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4040 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
4041 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4042 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
4043 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4044 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
4045 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4046
4047 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4048
4049 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4050 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4051
4052 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4053
4054 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4055
4056 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4057
4058 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4059
4060 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4061 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4062 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4063 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4064 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4065 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4066
4067 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4068 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4069 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4070 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4071
4072 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4073 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4074
4075 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4076 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4077 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4078 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4079
4080 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4081
4082 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4083
4084 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4085
4086 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4087
4088 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4089
4090 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4091 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4092
4093 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4094
4095 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
4096 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4097
4098 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
4099 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4100
4101 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
4102
4103 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4104 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4105 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4106 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4107
4108 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4109 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4110
4111 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4112 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4113
4114 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4115 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4116
4117 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
4118
4119 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4120
4121 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4122 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4123
4124 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4125
4126 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4127
4128 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4129
4130 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
4131 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
4132
4133 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4134 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4135 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4136 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4137 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4138
4139 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
4140
4141 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4142
4143 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4144
4145 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4146
4147 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4148
4149 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4150
4151 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4152
4153 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
4154 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
4155
4156 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
4157 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
4158
4159 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
4160
4161 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4162 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4163
4164 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4165 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4166
4167 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
4168
4169 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4170
4171 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4172
4173 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4174 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4175
4176 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4177
4178 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
4179 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
4180
4181 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
4182
4183 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4184 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4185
4186 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4187 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4188
4189 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4190
4191 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4192
4193 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4194
4195 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4196 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4197
4198 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4199
4200 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4201
4202 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4203 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4204
4205 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
4206
4207 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4208 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4209 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4210 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4211
4212 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4213 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4214
4215 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
4216
4217 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
4218 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
4219
4220 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4221
4222 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4223 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4224
4225 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4226 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4227 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4228 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4229
4230 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4231
4232 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4233 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4234
4235 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
4236 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
4237 { "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
4238 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
4239 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4240 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4241
4242 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4243
4244 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
4245
4246 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4247 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4248
4249 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4250 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4251
4252 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4253 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4254 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4255 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4256
4257 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
4258
4259 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
4260
4261 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4262 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4263 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
4264 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RS, RA, SH } },
4265
4266 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4267 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4268
4269 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4270 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4271
4272 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4273
4274 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4275
4276 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4277 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4278 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAO, SHO } },
4279 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4280
4281 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4282
4283 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
4284
4285 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4286 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4287
4288 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4289
4290 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4291 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4292
4293 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4294
4295 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4296 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4297
4298 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4299
4300 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4301 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4302 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4303 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4304 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4305 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4306 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4307 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4308 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4309 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4310 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4311 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4312
4313 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
4314 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4315
4316 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4317 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4318
4319 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
4320
4321 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4322
4323 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4324 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4325
4326 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4327 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4328
4329 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
4330
4331 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4332
4333 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
4334
4335 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4336
4337 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
4338
4339 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4340
4341 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
4342
4343 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4344
4345 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4346 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4347
4348 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4349 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4350
4351 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
4352
4353 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4354
4355 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
4356
4357 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4358
4359 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
4360
4361 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4362
4363 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
4364
4365 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4366
4367 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4368
4369 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
4370
4371 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
4372
4373 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4374 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4375 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4376 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4377 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4378 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4379 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4380 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4381 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
4382 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4383 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4384 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4385 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4386 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4387
4388 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
4389
4390 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4391
4392 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
4393
4394 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4395 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4396
4397 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4398 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4399
4400 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4401 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4402
4403 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4404 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4405
4406 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4407 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4408
4409 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4410 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4411
4412 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4413 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4414
4415 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4416 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4417
4418 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4419 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4420
4421 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4422 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4423
4424 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4425
4426 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4427
4428 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4429 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4430 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4431 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4432 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4433 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4434 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
4435 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4436 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4437 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4438 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4439 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4440
4441 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
4442
4443 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4444
4445 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA } },
4446
4447 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4448
4449 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4450 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4451
4452 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4453 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4454 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4455 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4456
4457 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4458 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4459 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4460 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4461
4462 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4463 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4464 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4465 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4466
4467 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4468 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4469 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4470 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4471
4472 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4473 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4474 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4475 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4476
4477 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4478 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4479
4480 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4481 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4482
4483 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4484 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4485 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4486 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4487
4488 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4489 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4490
4491 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4492 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4493 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4494 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4495
4496 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4497 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4498 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4499 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4500
4501 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4502 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4503 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4504 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4505
4506 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4507 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4508 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4509 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4510
4511 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4512
4513 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4514 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4515
4516 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4517 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4518
4519 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4520
4521 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4522 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4523
4524 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4525 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4526
4527 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4528 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4529
4530 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4531 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4532
4533 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4534 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4535
4536 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4537 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4538
4539 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4540 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4541
4542 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4543 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4544
4545 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4546 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4547
4548 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4549 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4550
4551 };
4552
4553 const int powerpc_num_opcodes =
4554   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4555 \f
4556 /* The macro table.  This is only used by the assembler.  */
4557
4558 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4559    when x=0; 32-x when x is between 1 and 31; are negative if x is
4560    negative; and are 32 or more otherwise.  This is what you want
4561    when, for instance, you are emulating a right shift by a
4562    rotate-left-and-mask, because the underlying instructions support
4563    shifts of size 0 but not shifts of size 32.  By comparison, when
4564    extracting x bits from some word you want to use just 32-x, because
4565    the underlying instructions don't support extracting 0 bits but do
4566    support extracting the whole word (32 bits in this case).  */
4567
4568 const struct powerpc_macro powerpc_macros[] = {
4569 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4570 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4571 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4572 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4573 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4574 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4575 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4576 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4577 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4578 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4579 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4580 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4581 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4582 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4583 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4584 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4585
4586 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4587 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4588 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4589 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4590 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4591 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4592 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4593 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4594 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4595 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4596 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4597 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4598 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4599 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4600 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4601 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4602 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4603 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4604 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4605 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4606 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4607 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4608 };
4609
4610 const int powerpc_num_macros =
4611   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);