opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bd (unsigned long, long, int, const char **);
  46 static long extract_bd (unsigned long, int, int *);
  47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  48 static long extract_bdm (unsigned long, int, int *);
  49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  50 static long extract_bdp (unsigned long, int, int *);
  51 static unsigned long insert_bo (unsigned long, long, int, const char **);
  52 static long extract_bo (unsigned long, int, int *);
  53 static unsigned long insert_boe (unsigned long, long, int, const char **);
  54 static long extract_boe (unsigned long, int, int *);
  55 static unsigned long insert_dq (unsigned long, long, int, const char **);
  56 static long extract_dq (unsigned long, int, int *);
  57 static unsigned long insert_ds (unsigned long, long, int, const char **);
  58 static long extract_ds (unsigned long, int, int *);
  59 static unsigned long insert_de (unsigned long, long, int, const char **);
  60 static long extract_de (unsigned long, int, int *);
  61 static unsigned long insert_des (unsigned long, long, int, const char **);
  62 static long extract_des (unsigned long, int, int *);
  63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  64 static long extract_fxm (unsigned long, int, int *);
  65 static unsigned long insert_li (unsigned long, long, int, const char **);
  66 static long extract_li (unsigned long, int, int *);
  67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  68 static long extract_mbe (unsigned long, int, int *);
  69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  70 static long extract_mb6 (unsigned long, int, int *);
  71 static unsigned long insert_nb (unsigned long, long, int, const char **);
  72 static long extract_nb (unsigned long, int, int *);
  73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  74 static long extract_nsi (unsigned long, int, int *);
  75 static unsigned long insert_ral (unsigned long, long, int, const char **);
  76 static unsigned long insert_ram (unsigned long, long, int, const char **);
  77 static unsigned long insert_raq (unsigned long, long, int, const char **);
  78 static unsigned long insert_ras (unsigned long, long, int, const char **);
  79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  80 static long extract_rbs (unsigned long, int, int *);
  81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
  82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
  83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  84 static long extract_sh6 (unsigned long, int, int *);
  85 static unsigned long insert_spr (unsigned long, long, int, const char **);
  86 static long extract_spr (unsigned long, int, int *);
  87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  88 static long extract_tbr (unsigned long, int, int *);
  89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
  90 static long extract_ev2 (unsigned long, int, int *);
  91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
  92 static long extract_ev4 (unsigned long, int, int *);
  93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
  94 static long extract_ev8 (unsigned long, int, int *);
  95 \f
  96 /* The operands table.
  97
  98    The fields are bits, shift, insert, extract, flags.
  99
 100    We used to put parens around the various additions, like the one
 101    for BA just below.  However, that caused trouble with feeble
 102    compilers with a limit on depth of a parenthesized expression, like
 103    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 104    omit the parens, since the macros are never used in a context where
 105    the addition will be ambiguous.  */
 106
 107 const struct powerpc_operand powerpc_operands[] =
 108 {
 109   /* The zero index is used to indicate the end of the list of
 110      operands.  */
 111 #define UNUSED 0
 112   { 0, 0, 0, 0, 0 },
 113
 114   /* The BA field in an XL form instruction.  */
 115 #define BA UNUSED + 1
 116 #define BA_MASK (0x1f << 16)
 117   { 5, 16, 0, 0, PPC_OPERAND_CR },
 118
 119   /* The BA field in an XL form instruction when it must be the same
 120      as the BT field in the same instruction.  */
 121 #define BAT BA + 1
 122   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 123
 124   /* The BB field in an XL form instruction.  */
 125 #define BB BAT + 1
 126 #define BB_MASK (0x1f << 11)
 127   { 5, 11, 0, 0, PPC_OPERAND_CR },
 128
 129   /* The BB field in an XL form instruction when it must be the same
 130      as the BA field in the same instruction.  */
 131 #define BBA BB + 1
 132   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 133
 134   /* The BD field in a B form instruction.  The lower two bits are
 135      forced to zero.  */
 136 #define BD BBA + 1
 137   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when absolute addressing is
 140      used.  */
 141 #define BDA BD + 1
 142   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the - modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDM BDA + 1
 147   { 16, 0, insert_bdm, extract_bdm,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the - modifier is used
 151      and absolute address is used.  */
 152 #define BDMA BDM + 1
 153   { 16, 0, insert_bdm, extract_bdm,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BD field in a B form instruction when the + modifier is used.
 157      This sets the y bit of the BO field appropriately.  */
 158 #define BDP BDMA + 1
 159   { 16, 0, insert_bdp, extract_bdp,
 160       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 161
 162   /* The BD field in a B form instruction when the + modifier is used
 163      and absolute addressing is used.  */
 164 #define BDPA BDP + 1
 165   { 16, 0, insert_bdp, extract_bdp,
 166       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 167
 168   /* The BF field in an X or XL form instruction.  */
 169 #define BF BDPA + 1
 170   { 3, 23, 0, 0, PPC_OPERAND_CR },
 171
 172   /* An optional BF field.  This is used for comparison instructions,
 173      in which an omitted BF field is taken as zero.  */
 174 #define OBF BF + 1
 175   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 176
 177   /* The BFA field in an X or XL form instruction.  */
 178 #define BFA OBF + 1
 179   { 3, 18, 0, 0, PPC_OPERAND_CR },
 180
 181   /* The BI field in a B form or XL form instruction.  */
 182 #define BI BFA + 1
 183 #define BI_MASK (0x1f << 16)
 184   { 5, 16, 0, 0, PPC_OPERAND_CR },
 185
 186   /* The BO field in a B form instruction.  Certain values are
 187      illegal.  */
 188 #define BO BI + 1
 189 #define BO_MASK (0x1f << 21)
 190   { 5, 21, insert_bo, extract_bo, 0 },
 191
 192   /* The BO field in a B form instruction when the + or - modifier is
 193      used.  This is like the BO field, but it must be even.  */
 194 #define BOE BO + 1
 195   { 5, 21, insert_boe, extract_boe, 0 },
 196
 197   /* The BT field in an X or XL form instruction.  */
 198 #define BT BOE + 1
 199   { 5, 21, 0, 0, PPC_OPERAND_CR },
 200
 201   /* The condition register number portion of the BI field in a B form
 202      or XL form instruction.  This is used for the extended
 203      conditional branch mnemonics, which set the lower two bits of the
 204      BI field.  This field is optional.  */
 205 #define CR BT + 1
 206   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 207
 208   /* The CRB field in an X form instruction.  */
 209 #define CRB CR + 1
 210   { 5, 6, 0, 0, 0 },
 211
 212   /* The CRFD field in an X form instruction.  */
 213 #define CRFD CRB + 1
 214   { 3, 23, 0, 0, PPC_OPERAND_CR },
 215
 216   /* The CRFS field in an X form instruction.  */
 217 #define CRFS CRFD + 1
 218   { 3, 0, 0, 0, PPC_OPERAND_CR },
 219
 220   /* The CT field in an X form instruction.  */
 221 #define CT CRFS + 1
 222   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 223
 224   /* The D field in a D form instruction.  This is a displacement off
 225      a register, and implies that the next operand is a register in
 226      parentheses.  */
 227 #define D CT + 1
 228   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 229
 230   /* The DE field in a DE form instruction.  This is like D, but is 12
 231      bits only.  */
 232 #define DE D + 1
 233   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 234
 235   /* The DES field in a DES form instruction.  This is like DS, but is 14
 236      bits only (12 stored.)  */
 237 #define DES DE + 1
 238   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 239
 240   /* The DQ field in a DQ form instruction.  This is like D, but the
 241      lower four bits are forced to zero. */
 242 #define DQ DES + 1
 243   { 16, 0, insert_dq, extract_dq,
 244       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 245
 246   /* The DS field in a DS form instruction.  This is like D, but the
 247      lower two bits are forced to zero.  */
 248 #define DS DQ + 1
 249   { 16, 0, insert_ds, extract_ds,
 250       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 251
 252   /* The E field in a wrteei instruction.  */
 253 #define E DS + 1
 254   { 1, 15, 0, 0, 0 },
 255
 256   /* The FL1 field in a POWER SC form instruction.  */
 257 #define FL1 E + 1
 258   { 4, 12, 0, 0, 0 },
 259
 260   /* The FL2 field in a POWER SC form instruction.  */
 261 #define FL2 FL1 + 1
 262   { 3, 2, 0, 0, 0 },
 263
 264   /* The FLM field in an XFL form instruction.  */
 265 #define FLM FL2 + 1
 266   { 8, 17, 0, 0, 0 },
 267
 268   /* The FRA field in an X or A form instruction.  */
 269 #define FRA FLM + 1
 270 #define FRA_MASK (0x1f << 16)
 271   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 272
 273   /* The FRB field in an X or A form instruction.  */
 274 #define FRB FRA + 1
 275 #define FRB_MASK (0x1f << 11)
 276   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 277
 278   /* The FRC field in an A form instruction.  */
 279 #define FRC FRB + 1
 280 #define FRC_MASK (0x1f << 6)
 281   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 282
 283   /* The FRS field in an X form instruction or the FRT field in a D, X
 284      or A form instruction.  */
 285 #define FRS FRC + 1
 286 #define FRT FRS
 287   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 288
 289   /* The FXM field in an XFX instruction.  */
 290 #define FXM FRS + 1
 291 #define FXM_MASK (0xff << 12)
 292   { 8, 12, insert_fxm, extract_fxm, 0 },
 293
 294   /* Power4 version for mfcr.  */
 295 #define FXM4 FXM + 1
 296   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 297
 298   /* The L field in a D or X form instruction.  */
 299 #define L FXM4 + 1
 300   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 301
 302   /* The LEV field in a POWER SC form instruction.  */
 303 #define LEV L + 1
 304   { 7, 5, 0, 0, 0 },
 305
 306   /* The LI field in an I form instruction.  The lower two bits are
 307      forced to zero.  */
 308 #define LI LEV + 1
 309   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 310
 311   /* The LI field in an I form instruction when used as an absolute
 312      address.  */
 313 #define LIA LI + 1
 314   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 315
 316   /* The LS field in an X (sync) form instruction.  */
 317 #define LS LIA + 1
 318   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 319
 320   /* The MB field in an M form instruction.  */
 321 #define MB LS + 1
 322 #define MB_MASK (0x1f << 6)
 323   { 5, 6, 0, 0, 0 },
 324
 325   /* The ME field in an M form instruction.  */
 326 #define ME MB + 1
 327 #define ME_MASK (0x1f << 1)
 328   { 5, 1, 0, 0, 0 },
 329
 330   /* The MB and ME fields in an M form instruction expressed a single
 331      operand which is a bitmask indicating which bits to select.  This
 332      is a two operand form using PPC_OPERAND_NEXT.  See the
 333      description in opcode/ppc.h for what this means.  */
 334 #define MBE ME + 1
 335   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 336   { 32, 0, insert_mbe, extract_mbe, 0 },
 337
 338   /* The MB or ME field in an MD or MDS form instruction.  The high
 339      bit is wrapped to the low end.  */
 340 #define MB6 MBE + 2
 341 #define ME6 MB6
 342 #define MB6_MASK (0x3f << 5)
 343   { 6, 5, insert_mb6, extract_mb6, 0 },
 344
 345   /* The MO field in an mbar instruction.  */
 346 #define MO MB6 + 1
 347   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 348
 349   /* The NB field in an X form instruction.  The value 32 is stored as
 350      0.  */
 351 #define NB MO + 1
 352   { 6, 11, insert_nb, extract_nb, 0 },
 353
 354   /* The NSI field in a D form instruction.  This is the same as the
 355      SI field, only negated.  */
 356 #define NSI NB + 1
 357   { 16, 0, insert_nsi, extract_nsi,
 358       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 359
 360   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 361 #define RA NSI + 1
 362 #define RA_MASK (0x1f << 16)
 363   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 364
 365   /* As above, but 0 in the RA field means zero, not r0.  */
 366 #define RA0 RA + 1
 367   { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
 368
 369   /* The RA field in the DQ form lq instruction, which has special
 370      value restrictions.  */
 371 #define RAQ RA0 + 1
 372   { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
 373
 374   /* The RA field in a D or X form instruction which is an updating
 375      load, which means that the RA field may not be zero and may not
 376      equal the RT field.  */
 377 #define RAL RAQ + 1
 378   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
 379
 380   /* The RA field in an lmw instruction, which has special value
 381      restrictions.  */
 382 #define RAM RAL + 1
 383   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
 384
 385   /* The RA field in a D or X form instruction which is an updating
 386      store or an updating floating point load, which means that the RA
 387      field may not be zero.  */
 388 #define RAS RAM + 1
 389   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
 390
 391   /* The RA field of the tlbwe instruction, which is optional.  */
 392 #define RAOPT RAS + 1
 393   { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 394
 395   /* The RB field in an X, XO, M, or MDS form instruction.  */
 396 #define RB RAOPT + 1
 397 #define RB_MASK (0x1f << 11)
 398   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 399
 400   /* The RB field in an X form instruction when it must be the same as
 401      the RS field in the instruction.  This is used for extended
 402      mnemonics like mr.  */
 403 #define RBS RB + 1
 404   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 405
 406   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 407      instruction or the RT field in a D, DS, X, XFX or XO form
 408      instruction.  */
 409 #define RS RBS + 1
 410 #define RT RS
 411 #define RT_MASK (0x1f << 21)
 412   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 413
 414   /* The RS field of the DS form stq instruction, which has special
 415      value restrictions.  */
 416 #define RSQ RS + 1
 417   { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
 418
 419   /* The RT field of the DQ form lq instruction, which has special
 420      value restrictions.  */
 421 #define RTQ RSQ + 1
 422   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
 423
 424   /* The RS field of the tlbwe instruction, which is optional.  */
 425 #define RSO RTQ + 1
 426   { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 427
 428   /* The SH field in an X or M form instruction.  */
 429 #define SH RSO + 1
 430 #define SH_MASK (0x1f << 11)
 431   { 5, 11, 0, 0, 0 },
 432
 433   /* The SH field in an MD form instruction.  This is split.  */
 434 #define SH6 SH + 1
 435 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 436   { 6, 1, insert_sh6, extract_sh6, 0 },
 437
 438   /* The SH field of the tlbwe instruction, which is optional.  */
 439 #define SHO SH6 + 1
 440   { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
 441
 442   /* The SI field in a D form instruction.  */
 443 #define SI SHO + 1
 444   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 445
 446   /* The SI field in a D form instruction when we accept a wide range
 447      of positive values.  */
 448 #define SISIGNOPT SI + 1
 449   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 450
 451   /* The SPR field in an XFX form instruction.  This is flipped--the
 452      lower 5 bits are stored in the upper 5 and vice- versa.  */
 453 #define SPR SISIGNOPT + 1
 454 #define PMR SPR
 455 #define SPR_MASK (0x3ff << 11)
 456   { 10, 11, insert_spr, extract_spr, 0 },
 457
 458   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 459 #define SPRBAT SPR + 1
 460 #define SPRBAT_MASK (0x3 << 17)
 461   { 2, 17, 0, 0, 0 },
 462
 463   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 464 #define SPRG SPRBAT + 1
 465 #define SPRG_MASK (0x3 << 16)
 466   { 2, 16, 0, 0, 0 },
 467
 468   /* The SR field in an X form instruction.  */
 469 #define SR SPRG + 1
 470   { 4, 16, 0, 0, 0 },
 471
 472   /* The STRM field in an X AltiVec form instruction.  */
 473 #define STRM SR + 1
 474 #define STRM_MASK (0x3 << 21)
 475   { 2, 21, 0, 0, 0 },
 476
 477   /* The SV field in a POWER SC form instruction.  */
 478 #define SV STRM + 1
 479   { 14, 2, 0, 0, 0 },
 480
 481   /* The TBR field in an XFX form instruction.  This is like the SPR
 482      field, but it is optional.  */
 483 #define TBR SV + 1
 484   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 485
 486   /* The TO field in a D or X form instruction.  */
 487 #define TO TBR + 1
 488 #define TO_MASK (0x1f << 21)
 489   { 5, 21, 0, 0, 0 },
 490
 491   /* The U field in an X form instruction.  */
 492 #define U TO + 1
 493   { 4, 12, 0, 0, 0 },
 494
 495   /* The UI field in a D form instruction.  */
 496 #define UI U + 1
 497   { 16, 0, 0, 0, 0 },
 498
 499   /* The VA field in a VA, VX or VXR form instruction.  */
 500 #define VA UI + 1
 501 #define VA_MASK (0x1f << 16)
 502   { 5, 16, 0, 0, PPC_OPERAND_VR },
 503
 504   /* The VB field in a VA, VX or VXR form instruction.  */
 505 #define VB VA + 1
 506 #define VB_MASK (0x1f << 11)
 507   { 5, 11, 0, 0, PPC_OPERAND_VR },
 508
 509   /* The VC field in a VA form instruction.  */
 510 #define VC VB + 1
 511 #define VC_MASK (0x1f << 6)
 512   { 5, 6, 0, 0, PPC_OPERAND_VR },
 513
 514   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 515 #define VD VC + 1
 516 #define VS VD
 517 #define VD_MASK (0x1f << 21)
 518   { 5, 21, 0, 0, PPC_OPERAND_VR },
 519
 520   /* The SIMM field in a VX form instruction.  */
 521 #define SIMM VD + 1
 522   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 523
 524   /* The UIMM field in a VX form instruction.  */
 525 #define UIMM SIMM + 1
 526   { 5, 16, 0, 0, 0 },
 527
 528   /* The SHB field in a VA form instruction.  */
 529 #define SHB UIMM + 1
 530   { 4, 6, 0, 0, 0 },
 531
 532   /* The other UIMM field in a EVX form instruction.  */
 533 #define EVUIMM SHB + 1
 534   { 5, 11, 0, 0, 0 },
 535
 536   /* The other UIMM field in a half word EVX form instruction.  */
 537 #define EVUIMM_2 EVUIMM + 1
 538   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 539
 540   /* The other UIMM field in a word EVX form instruction.  */
 541 #define EVUIMM_4 EVUIMM_2 + 1
 542   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 543
 544   /* The other UIMM field in a double EVX form instruction.  */
 545 #define EVUIMM_8 EVUIMM_4 + 1
 546   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 547
 548   /* The WS field.  */
 549 #define WS EVUIMM_8 + 1
 550 #define WS_MASK (0x7 << 11)
 551   { 3, 11, 0, 0, 0 },
 552
 553   /* The L field in an mtmsrd instruction */
 554 #define MTMSRD_L WS + 1
 555   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 556
 557 };
 558
 559 /* The functions used to insert and extract complicated operands.  */
 560
 561 /* The BA field in an XL form instruction when it must be the same as
 562    the BT field in the same instruction.  This operand is marked FAKE.
 563    The insertion function just copies the BT field into the BA field,
 564    and the extraction function just checks that the fields are the
 565    same.  */
 566
 567 static unsigned long
 568 insert_bat (unsigned long insn,
 569             long value ATTRIBUTE_UNUSED,
 570             int dialect ATTRIBUTE_UNUSED,
 571             const char **errmsg ATTRIBUTE_UNUSED)
 572 {
 573   return insn | (((insn >> 21) & 0x1f) << 16);
 574 }
 575
 576 static long
 577 extract_bat (unsigned long insn,
 578              int dialect ATTRIBUTE_UNUSED,
 579              int *invalid)
 580 {
 581   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 582     *invalid = 1;
 583   return 0;
 584 }
 585
 586 /* The BB field in an XL form instruction when it must be the same as
 587    the BA field in the same instruction.  This operand is marked FAKE.
 588    The insertion function just copies the BA field into the BB field,
 589    and the extraction function just checks that the fields are the
 590    same.  */
 591
 592 static unsigned long
 593 insert_bba (unsigned long insn,
 594             long value ATTRIBUTE_UNUSED,
 595             int dialect ATTRIBUTE_UNUSED,
 596             const char **errmsg ATTRIBUTE_UNUSED)
 597 {
 598   return insn | (((insn >> 16) & 0x1f) << 11);
 599 }
 600
 601 static long
 602 extract_bba (unsigned long insn,
 603              int dialect ATTRIBUTE_UNUSED,
 604              int *invalid)
 605 {
 606   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 607     *invalid = 1;
 608   return 0;
 609 }
 610
 611 /* The BD field in a B form instruction.  The lower two bits are
 612    forced to zero.  */
 613
 614 static unsigned long
 615 insert_bd (unsigned long insn,
 616            long value,
 617            int dialect ATTRIBUTE_UNUSED,
 618            const char **errmsg ATTRIBUTE_UNUSED)
 619 {
 620   return insn | (value & 0xfffc);
 621 }
 622
 623 static long
 624 extract_bd (unsigned long insn,
 625             int dialect ATTRIBUTE_UNUSED,
 626             int *invalid ATTRIBUTE_UNUSED)
 627 {
 628   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 629 }
 630
 631 /* The BD field in a B form instruction when the - modifier is used.
 632    This modifier means that the branch is not expected to be taken.
 633    For chips built to versions of the architecture prior to version 2
 634    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 635    if the offset is negative.  When extracting, we require that the y
 636    bit be 1 and that the offset be positive, since if the y bit is 0
 637    we just want to print the normal form of the instruction.
 638    Power4 compatible targets use two bits, "a", and "t", instead of
 639    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 640    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 641    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 642    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 643
 644 static unsigned long
 645 insert_bdm (unsigned long insn,
 646             long value,
 647             int dialect,
 648             const char **errmsg ATTRIBUTE_UNUSED)
 649 {
 650   if ((dialect & PPC_OPCODE_POWER4) == 0)
 651     {
 652       if ((value & 0x8000) != 0)
 653         insn |= 1 << 21;
 654     }
 655   else
 656     {
 657       if ((insn & (0x14 << 21)) == (0x04 << 21))
 658         insn |= 0x02 << 21;
 659       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 660         insn |= 0x08 << 21;
 661     }
 662   return insn | (value & 0xfffc);
 663 }
 664
 665 static long
 666 extract_bdm (unsigned long insn,
 667              int dialect,
 668              int *invalid)
 669 {
 670   if ((dialect & PPC_OPCODE_POWER4) == 0)
 671     {
 672       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 673         *invalid = 1;
 674     }
 675   else
 676     {
 677       if ((insn & (0x17 << 21)) != (0x06 << 21)
 678           && (insn & (0x1d << 21)) != (0x18 << 21))
 679         *invalid = 1;
 680     }
 681
 682   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 683 }
 684
 685 /* The BD field in a B form instruction when the + modifier is used.
 686    This is like BDM, above, except that the branch is expected to be
 687    taken.  */
 688
 689 static unsigned long
 690 insert_bdp (unsigned long insn,
 691             long value,
 692             int dialect,
 693             const char **errmsg ATTRIBUTE_UNUSED)
 694 {
 695   if ((dialect & PPC_OPCODE_POWER4) == 0)
 696     {
 697       if ((value & 0x8000) == 0)
 698         insn |= 1 << 21;
 699     }
 700   else
 701     {
 702       if ((insn & (0x14 << 21)) == (0x04 << 21))
 703         insn |= 0x03 << 21;
 704       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 705         insn |= 0x09 << 21;
 706     }
 707   return insn | (value & 0xfffc);
 708 }
 709
 710 static long
 711 extract_bdp (unsigned long insn,
 712              int dialect,
 713              int *invalid)
 714 {
 715   if ((dialect & PPC_OPCODE_POWER4) == 0)
 716     {
 717       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 718         *invalid = 1;
 719     }
 720   else
 721     {
 722       if ((insn & (0x17 << 21)) != (0x07 << 21)
 723           && (insn & (0x1d << 21)) != (0x19 << 21))
 724         *invalid = 1;
 725     }
 726
 727   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 728 }
 729
 730 /* Check for legal values of a BO field.  */
 731
 732 static int
 733 valid_bo (long value, int dialect)
 734 {
 735   if ((dialect & PPC_OPCODE_POWER4) == 0)
 736     {
 737       /* Certain encodings have bits that are required to be zero.
 738          These are (z must be zero, y may be anything):
 739              001zy
 740              011zy
 741              1z00y
 742              1z01y
 743              1z1zz
 744       */
 745       switch (value & 0x14)
 746         {
 747         default:
 748         case 0:
 749           return 1;
 750         case 0x4:
 751           return (value & 0x2) == 0;
 752         case 0x10:
 753           return (value & 0x8) == 0;
 754         case 0x14:
 755           return value == 0x14;
 756         }
 757     }
 758   else
 759     {
 760       /* Certain encodings have bits that are required to be zero.
 761          These are (z must be zero, a & t may be anything):
 762              0000z
 763              0001z
 764              0100z
 765              0101z
 766              001at
 767              011at
 768              1a00t
 769              1a01t
 770              1z1zz
 771       */
 772       if ((value & 0x14) == 0)
 773         return (value & 0x1) == 0;
 774       else if ((value & 0x14) == 0x14)
 775         return value == 0x14;
 776       else
 777         return 1;
 778     }
 779 }
 780
 781 /* The BO field in a B form instruction.  Warn about attempts to set
 782    the field to an illegal value.  */
 783
 784 static unsigned long
 785 insert_bo (unsigned long insn,
 786            long value,
 787            int dialect,
 788            const char **errmsg)
 789 {
 790   if (!valid_bo (value, dialect))
 791     *errmsg = _("invalid conditional option");
 792   return insn | ((value & 0x1f) << 21);
 793 }
 794
 795 static long
 796 extract_bo (unsigned long insn,
 797             int dialect,
 798             int *invalid)
 799 {
 800   long value;
 801
 802   value = (insn >> 21) & 0x1f;
 803   if (!valid_bo (value, dialect))
 804     *invalid = 1;
 805   return value;
 806 }
 807
 808 /* The BO field in a B form instruction when the + or - modifier is
 809    used.  This is like the BO field, but it must be even.  When
 810    extracting it, we force it to be even.  */
 811
 812 static unsigned long
 813 insert_boe (unsigned long insn,
 814             long value,
 815             int dialect,
 816             const char **errmsg)
 817 {
 818   if (!valid_bo (value, dialect))
 819     *errmsg = _("invalid conditional option");
 820   else if ((value & 1) != 0)
 821     *errmsg = _("attempt to set y bit when using + or - modifier");
 822
 823   return insn | ((value & 0x1f) << 21);
 824 }
 825
 826 static long
 827 extract_boe (unsigned long insn,
 828              int dialect,
 829              int *invalid)
 830 {
 831   long value;
 832
 833   value = (insn >> 21) & 0x1f;
 834   if (!valid_bo (value, dialect))
 835     *invalid = 1;
 836   return value & 0x1e;
 837 }
 838
 839 /* The DQ field in a DQ form instruction.  This is like D, but the
 840    lower four bits are forced to zero. */
 841
 842 static unsigned long
 843 insert_dq (unsigned long insn,
 844            long value,
 845            int dialect ATTRIBUTE_UNUSED,
 846            const char **errmsg)
 847 {
 848   if ((value & 0xf) != 0)
 849     *errmsg = _("offset not a multiple of 16");
 850   return insn | (value & 0xfff0);
 851 }
 852
 853 static long
 854 extract_dq (unsigned long insn,
 855             int dialect ATTRIBUTE_UNUSED,
 856             int *invalid ATTRIBUTE_UNUSED)
 857 {
 858   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
 859 }
 860
 861 static unsigned long
 862 insert_ev2 (unsigned long insn,
 863             long value,
 864             int dialect ATTRIBUTE_UNUSED,
 865             const char **errmsg)
 866 {
 867   if ((value & 1) != 0)
 868     *errmsg = _("offset not a multiple of 2");
 869   if ((value > 62) != 0)
 870     *errmsg = _("offset greater than 62");
 871   return insn | ((value & 0x3e) << 10);
 872 }
 873
 874 static long
 875 extract_ev2 (unsigned long insn,
 876              int dialect ATTRIBUTE_UNUSED,
 877              int *invalid ATTRIBUTE_UNUSED)
 878 {
 879   return (insn >> 10) & 0x3e;
 880 }
 881
 882 static unsigned long
 883 insert_ev4 (unsigned long insn,
 884             long value,
 885             int dialect ATTRIBUTE_UNUSED,
 886             const char **errmsg)
 887 {
 888   if ((value & 3) != 0)
 889     *errmsg = _("offset not a multiple of 4");
 890   if ((value > 124) != 0)
 891     *errmsg = _("offset greater than 124");
 892   return insn | ((value & 0x7c) << 9);
 893 }
 894
 895 static long
 896 extract_ev4 (unsigned long insn,
 897              int dialect ATTRIBUTE_UNUSED,
 898              int *invalid ATTRIBUTE_UNUSED)
 899 {
 900   return (insn >> 9) & 0x7c;
 901 }
 902
 903 static unsigned long
 904 insert_ev8 (unsigned long insn,
 905             long value,
 906             int dialect ATTRIBUTE_UNUSED,
 907             const char **errmsg)
 908 {
 909   if ((value & 7) != 0)
 910     *errmsg = _("offset not a multiple of 8");
 911   if ((value > 248) != 0)
 912     *errmsg = _("offset greater than 248");
 913   return insn | ((value & 0xf8) << 8);
 914 }
 915
 916 static long
 917 extract_ev8 (unsigned long insn,
 918              int dialect ATTRIBUTE_UNUSED,
 919              int *invalid ATTRIBUTE_UNUSED)
 920 {
 921   return (insn >> 8) & 0xf8;
 922 }
 923
 924 /* The DS field in a DS form instruction.  This is like D, but the
 925    lower two bits are forced to zero.  */
 926
 927 static unsigned long
 928 insert_ds (unsigned long insn,
 929            long value,
 930            int dialect ATTRIBUTE_UNUSED,
 931            const char **errmsg)
 932 {
 933   if ((value & 3) != 0)
 934     *errmsg = _("offset not a multiple of 4");
 935   return insn | (value & 0xfffc);
 936 }
 937
 938 static long
 939 extract_ds (unsigned long insn,
 940             int dialect ATTRIBUTE_UNUSED,
 941             int *invalid ATTRIBUTE_UNUSED)
 942 {
 943   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 944 }
 945
 946 /* The DE field in a DE form instruction.  */
 947
 948 static unsigned long
 949 insert_de (unsigned long insn,
 950            long value,
 951            int dialect ATTRIBUTE_UNUSED,
 952            const char **errmsg)
 953 {
 954   if (value > 2047 || value < -2048)
 955     *errmsg = _("offset not between -2048 and 2047");
 956   return insn | ((value << 4) & 0xfff0);
 957 }
 958
 959 static long
 960 extract_de (unsigned long insn,
 961             int dialect ATTRIBUTE_UNUSED,
 962             int *invalid ATTRIBUTE_UNUSED)
 963 {
 964   return (insn & 0xfff0) >> 4;
 965 }
 966
 967 /* The DES field in a DES form instruction.  */
 968
 969 static unsigned long
 970 insert_des (unsigned long insn,
 971             long value,
 972             int dialect ATTRIBUTE_UNUSED,
 973             const char **errmsg)
 974 {
 975   if (value > 8191 || value < -8192)
 976     *errmsg = _("offset not between -8192 and 8191");
 977   else if ((value & 3) != 0)
 978     *errmsg = _("offset not a multiple of 4");
 979   return insn | ((value << 2) & 0xfff0);
 980 }
 981
 982 static long
 983 extract_des (unsigned long insn,
 984              int dialect ATTRIBUTE_UNUSED,
 985              int *invalid ATTRIBUTE_UNUSED)
 986 {
 987   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 988 }
 989
 990 /* FXM mask in mfcr and mtcrf instructions.  */
 991
 992 static unsigned long
 993 insert_fxm (unsigned long insn,
 994             long value,
 995             int dialect,
 996             const char **errmsg)
 997 {
 998   /* If the optional field on mfcr is missing that means we want to use
 999      the old form of the instruction that moves the whole cr.  In that
1000      case we'll have VALUE zero.  There doesn't seem to be a way to
1001      distinguish this from the case where someone writes mfcr %r3,0.  */
1002   if (value == 0)
1003     ;
1004
1005   /* If only one bit of the FXM field is set, we can use the new form
1006      of the instruction, which is faster.  Unlike the Power4 branch hint
1007      encoding, this is not backward compatible.  */
1008   else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1009     insn |= 1 << 20;
1010
1011   /* Any other value on mfcr is an error.  */
1012   else if ((insn & (0x3ff << 1)) == 19 << 1)
1013     {
1014       *errmsg = _("ignoring invalid mfcr mask");
1015       value = 0;
1016     }
1017
1018   return insn | ((value & 0xff) << 12);
1019 }
1020
1021 static long
1022 extract_fxm (unsigned long insn,
1023              int dialect,
1024              int *invalid)
1025 {
1026   long mask = (insn >> 12) & 0xff;
1027
1028   /* Is this a Power4 insn?  */
1029   if ((insn & (1 << 20)) != 0)
1030     {
1031       if ((dialect & PPC_OPCODE_POWER4) == 0)
1032         *invalid = 1;
1033       else
1034         {
1035           /* Exactly one bit of MASK should be set.  */
1036           if (mask == 0 || (mask & -mask) != mask)
1037             *invalid = 1;
1038         }
1039     }
1040
1041   /* Check that non-power4 form of mfcr has a zero MASK.  */
1042   else if ((insn & (0x3ff << 1)) == 19 << 1)
1043     {
1044       if (mask != 0)
1045         *invalid = 1;
1046     }
1047
1048   return mask;
1049 }
1050
1051 /* The LI field in an I form instruction.  The lower two bits are
1052    forced to zero.  */
1053
1054 static unsigned long
1055 insert_li (unsigned long insn,
1056            long value,
1057            int dialect ATTRIBUTE_UNUSED,
1058            const char **errmsg)
1059 {
1060   if ((value & 3) != 0)
1061     *errmsg = _("ignoring least significant bits in branch offset");
1062   return insn | (value & 0x3fffffc);
1063 }
1064
1065 static long
1066 extract_li (unsigned long insn,
1067             int dialect ATTRIBUTE_UNUSED,
1068             int *invalid ATTRIBUTE_UNUSED)
1069 {
1070   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1071 }
1072
1073 /* The MB and ME fields in an M form instruction expressed as a single
1074    operand which is itself a bitmask.  The extraction function always
1075    marks it as invalid, since we never want to recognize an
1076    instruction which uses a field of this type.  */
1077
1078 static unsigned long
1079 insert_mbe (unsigned long insn,
1080             long value,
1081             int dialect ATTRIBUTE_UNUSED,
1082             const char **errmsg)
1083 {
1084   unsigned long uval, mask;
1085   int mb, me, mx, count, last;
1086
1087   uval = value;
1088
1089   if (uval == 0)
1090     {
1091       *errmsg = _("illegal bitmask");
1092       return insn;
1093     }
1094
1095   mb = 0;
1096   me = 32;
1097   if ((uval & 1) != 0)
1098     last = 1;
1099   else
1100     last = 0;
1101   count = 0;
1102
1103   /* mb: location of last 0->1 transition */
1104   /* me: location of last 1->0 transition */
1105   /* count: # transitions */
1106
1107   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1108     {
1109       if ((uval & mask) && !last)
1110         {
1111           ++count;
1112           mb = mx;
1113           last = 1;
1114         }
1115       else if (!(uval & mask) && last)
1116         {
1117           ++count;
1118           me = mx;
1119           last = 0;
1120         }
1121     }
1122   if (me == 0)
1123     me = 32;
1124
1125   if (count != 2 && (count != 0 || ! last))
1126     *errmsg = _("illegal bitmask");
1127
1128   return insn | (mb << 6) | ((me - 1) << 1);
1129 }
1130
1131 static long
1132 extract_mbe (unsigned long insn,
1133              int dialect ATTRIBUTE_UNUSED,
1134              int *invalid)
1135 {
1136   long ret;
1137   int mb, me;
1138   int i;
1139
1140   *invalid = 1;
1141
1142   mb = (insn >> 6) & 0x1f;
1143   me = (insn >> 1) & 0x1f;
1144   if (mb < me + 1)
1145     {
1146       ret = 0;
1147       for (i = mb; i <= me; i++)
1148         ret |= 1L << (31 - i);
1149     }
1150   else if (mb == me + 1)
1151     ret = ~0;
1152   else /* (mb > me + 1) */
1153     {
1154       ret = ~0;
1155       for (i = me + 1; i < mb; i++)
1156         ret &= ~(1L << (31 - i));
1157     }
1158   return ret;
1159 }
1160
1161 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1162    is wrapped to the low end.  */
1163
1164 static unsigned long
1165 insert_mb6 (unsigned long insn,
1166             long value,
1167             int dialect ATTRIBUTE_UNUSED,
1168             const char **errmsg ATTRIBUTE_UNUSED)
1169 {
1170   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1171 }
1172
1173 static long
1174 extract_mb6 (unsigned long insn,
1175              int dialect ATTRIBUTE_UNUSED,
1176              int *invalid ATTRIBUTE_UNUSED)
1177 {
1178   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1179 }
1180
1181 /* The NB field in an X form instruction.  The value 32 is stored as
1182    0.  */
1183
1184 static unsigned long
1185 insert_nb (unsigned long insn,
1186            long value,
1187            int dialect ATTRIBUTE_UNUSED,
1188            const char **errmsg)
1189 {
1190   if (value < 0 || value > 32)
1191     *errmsg = _("value out of range");
1192   if (value == 32)
1193     value = 0;
1194   return insn | ((value & 0x1f) << 11);
1195 }
1196
1197 static long
1198 extract_nb (unsigned long insn,
1199             int dialect ATTRIBUTE_UNUSED,
1200             int *invalid ATTRIBUTE_UNUSED)
1201 {
1202   long ret;
1203
1204   ret = (insn >> 11) & 0x1f;
1205   if (ret == 0)
1206     ret = 32;
1207   return ret;
1208 }
1209
1210 /* The NSI field in a D form instruction.  This is the same as the SI
1211    field, only negated.  The extraction function always marks it as
1212    invalid, since we never want to recognize an instruction which uses
1213    a field of this type.  */
1214
1215 static unsigned long
1216 insert_nsi (unsigned long insn,
1217             long value,
1218             int dialect ATTRIBUTE_UNUSED,
1219             const char **errmsg ATTRIBUTE_UNUSED)
1220 {
1221   return insn | (-value & 0xffff);
1222 }
1223
1224 static long
1225 extract_nsi (unsigned long insn,
1226              int dialect ATTRIBUTE_UNUSED,
1227              int *invalid)
1228 {
1229   *invalid = 1;
1230   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1231 }
1232
1233 /* The RA field in a D or X form instruction which is an updating
1234    load, which means that the RA field may not be zero and may not
1235    equal the RT field.  */
1236
1237 static unsigned long
1238 insert_ral (unsigned long insn,
1239             long value,
1240             int dialect ATTRIBUTE_UNUSED,
1241             const char **errmsg)
1242 {
1243   if (value == 0
1244       || (unsigned long) value == ((insn >> 21) & 0x1f))
1245     *errmsg = "invalid register operand when updating";
1246   return insn | ((value & 0x1f) << 16);
1247 }
1248
1249 /* The RA field in an lmw instruction, which has special value
1250    restrictions.  */
1251
1252 static unsigned long
1253 insert_ram (unsigned long insn,
1254             long value,
1255             int dialect ATTRIBUTE_UNUSED,
1256             const char **errmsg)
1257 {
1258   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1259     *errmsg = _("index register in load range");
1260   return insn | ((value & 0x1f) << 16);
1261 }
1262
1263 /* The RA field in the DQ form lq instruction, which has special
1264    value restrictions.  */
1265
1266 static unsigned long
1267 insert_raq (unsigned long insn,
1268             long value,
1269             int dialect ATTRIBUTE_UNUSED,
1270             const char **errmsg)
1271 {
1272   long rtvalue = (insn & RT_MASK) >> 21;
1273
1274   if (value == rtvalue)
1275     *errmsg = _("source and target register operands must be different");
1276   return insn | ((value & 0x1f) << 16);
1277 }
1278
1279 /* The RA field in a D or X form instruction which is an updating
1280    store or an updating floating point load, which means that the RA
1281    field may not be zero.  */
1282
1283 static unsigned long
1284 insert_ras (unsigned long insn,
1285             long value,
1286             int dialect ATTRIBUTE_UNUSED,
1287             const char **errmsg)
1288 {
1289   if (value == 0)
1290     *errmsg = _("invalid register operand when updating");
1291   return insn | ((value & 0x1f) << 16);
1292 }
1293
1294 /* The RB field in an X form instruction when it must be the same as
1295    the RS field in the instruction.  This is used for extended
1296    mnemonics like mr.  This operand is marked FAKE.  The insertion
1297    function just copies the BT field into the BA field, and the
1298    extraction function just checks that the fields are the same.  */
1299
1300 static unsigned long
1301 insert_rbs (unsigned long insn,
1302             long value ATTRIBUTE_UNUSED,
1303             int dialect ATTRIBUTE_UNUSED,
1304             const char **errmsg ATTRIBUTE_UNUSED)
1305 {
1306   return insn | (((insn >> 21) & 0x1f) << 11);
1307 }
1308
1309 static long
1310 extract_rbs (unsigned long insn,
1311              int dialect ATTRIBUTE_UNUSED,
1312              int *invalid)
1313 {
1314   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1315     *invalid = 1;
1316   return 0;
1317 }
1318
1319 /* The RT field of the DQ form lq instruction, which has special
1320    value restrictions.  */
1321
1322 static unsigned long
1323 insert_rtq (unsigned long insn,
1324             long value,
1325             int dialect ATTRIBUTE_UNUSED,
1326             const char **errmsg)
1327 {
1328   if ((value & 1) != 0)
1329     *errmsg = _("target register operand must be even");
1330   return insn | ((value & 0x1f) << 21);
1331 }
1332
1333 /* The RS field of the DS form stq instruction, which has special
1334    value restrictions.  */
1335
1336 static unsigned long
1337 insert_rsq (unsigned long insn,
1338             long value ATTRIBUTE_UNUSED,
1339             int dialect ATTRIBUTE_UNUSED,
1340             const char **errmsg)
1341 {
1342   if ((value & 1) != 0)
1343     *errmsg = _("source register operand must be even");
1344   return insn | ((value & 0x1f) << 21);
1345 }
1346
1347 /* The SH field in an MD form instruction.  This is split.  */
1348
1349 static unsigned long
1350 insert_sh6 (unsigned long insn,
1351             long value,
1352             int dialect ATTRIBUTE_UNUSED,
1353             const char **errmsg ATTRIBUTE_UNUSED)
1354 {
1355   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1356 }
1357
1358 static long
1359 extract_sh6 (unsigned long insn,
1360              int dialect ATTRIBUTE_UNUSED,
1361              int *invalid ATTRIBUTE_UNUSED)
1362 {
1363   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1364 }
1365
1366 /* The SPR field in an XFX form instruction.  This is flipped--the
1367    lower 5 bits are stored in the upper 5 and vice- versa.  */
1368
1369 static unsigned long
1370 insert_spr (unsigned long insn,
1371             long value,
1372             int dialect ATTRIBUTE_UNUSED,
1373             const char **errmsg ATTRIBUTE_UNUSED)
1374 {
1375   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1376 }
1377
1378 static long
1379 extract_spr (unsigned long insn,
1380              int dialect ATTRIBUTE_UNUSED,
1381              int *invalid ATTRIBUTE_UNUSED)
1382 {
1383   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1384 }
1385
1386 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1387    is optional.  When TBR is omitted, it must be inserted as 268 (the
1388    magic number of the TB register).  These functions treat 0
1389    (indicating an omitted optional operand) as 268.  This means that
1390    ``mftb 4,0'' is not handled correctly.  This does not matter very
1391    much, since the architecture manual does not define mftb as
1392    accepting any values other than 268 or 269.  */
1393
1394 #define TB (268)
1395
1396 static unsigned long
1397 insert_tbr (unsigned long insn,
1398             long value,
1399             int dialect ATTRIBUTE_UNUSED,
1400             const char **errmsg ATTRIBUTE_UNUSED)
1401 {
1402   if (value == 0)
1403     value = TB;
1404   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1405 }
1406
1407 static long
1408 extract_tbr (unsigned long insn,
1409              int dialect ATTRIBUTE_UNUSED,
1410              int *invalid ATTRIBUTE_UNUSED)
1411 {
1412   long ret;
1413
1414   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1415   if (ret == TB)
1416     ret = 0;
1417   return ret;
1418 }
1419 \f
1420 /* Macros used to form opcodes.  */
1421
1422 /* The main opcode.  */
1423 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1424 #define OP_MASK OP (0x3f)
1425
1426 /* The main opcode combined with a trap code in the TO field of a D
1427    form instruction.  Used for extended mnemonics for the trap
1428    instructions.  */
1429 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1430 #define OPTO_MASK (OP_MASK | TO_MASK)
1431
1432 /* The main opcode combined with a comparison size bit in the L field
1433    of a D form or X form instruction.  Used for extended mnemonics for
1434    the comparison instructions.  */
1435 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1436 #define OPL_MASK OPL (0x3f,1)
1437
1438 /* An A form instruction.  */
1439 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1440 #define A_MASK A (0x3f, 0x1f, 1)
1441
1442 /* An A_MASK with the FRB field fixed.  */
1443 #define AFRB_MASK (A_MASK | FRB_MASK)
1444
1445 /* An A_MASK with the FRC field fixed.  */
1446 #define AFRC_MASK (A_MASK | FRC_MASK)
1447
1448 /* An A_MASK with the FRA and FRC fields fixed.  */
1449 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1450
1451 /* A B form instruction.  */
1452 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1453 #define B_MASK B (0x3f, 1, 1)
1454
1455 /* A B form instruction setting the BO field.  */
1456 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1457 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1458
1459 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1460    matching a conditional branch regardless of the setting of the y
1461    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1462 #define Y_MASK   (((unsigned long) 1) << 21)
1463 #define AT1_MASK (((unsigned long) 3) << 21)
1464 #define AT2_MASK (((unsigned long) 9) << 21)
1465 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1466 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1467
1468 /* A B form instruction setting the BO field and the condition bits of
1469    the BI field.  */
1470 #define BBOCB(op, bo, cb, aa, lk) \
1471   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1472 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1473
1474 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1475 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1476 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1477 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1478
1479 /* A BBOYCB_MASK in which the BI field is fixed.  */
1480 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1481 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1482
1483 /* An Context form instruction.  */
1484 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1485 #define CTX_MASK CTX(0x3f, 0x7)
1486
1487 /* An User Context form instruction.  */
1488 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1489 #define UCTX_MASK UCTX(0x3f, 0x1f)
1490
1491 /* The main opcode mask with the RA field clear.  */
1492 #define DRA_MASK (OP_MASK | RA_MASK)
1493
1494 /* A DS form instruction.  */
1495 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1496 #define DS_MASK DSO (0x3f, 3)
1497
1498 /* A DE form instruction.  */
1499 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1500 #define DE_MASK DEO (0x3e, 0xf)
1501
1502 /* An EVSEL form instruction.  */
1503 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1504 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1505
1506 /* An M form instruction.  */
1507 #define M(op, rc) (OP (op) | ((rc) & 1))
1508 #define M_MASK M (0x3f, 1)
1509
1510 /* An M form instruction with the ME field specified.  */
1511 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1512
1513 /* An M_MASK with the MB and ME fields fixed.  */
1514 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1515
1516 /* An M_MASK with the SH and ME fields fixed.  */
1517 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1518
1519 /* An MD form instruction.  */
1520 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1521 #define MD_MASK MD (0x3f, 0x7, 1)
1522
1523 /* An MD_MASK with the MB field fixed.  */
1524 #define MDMB_MASK (MD_MASK | MB6_MASK)
1525
1526 /* An MD_MASK with the SH field fixed.  */
1527 #define MDSH_MASK (MD_MASK | SH6_MASK)
1528
1529 /* An MDS form instruction.  */
1530 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1531 #define MDS_MASK MDS (0x3f, 0xf, 1)
1532
1533 /* An MDS_MASK with the MB field fixed.  */
1534 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1535
1536 /* An SC form instruction.  */
1537 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1538 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1539
1540 /* An VX form instruction.  */
1541 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1542
1543 /* The mask for an VX form instruction.  */
1544 #define VX_MASK VX(0x3f, 0x7ff)
1545
1546 /* An VA form instruction.  */
1547 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1548
1549 /* The mask for an VA form instruction.  */
1550 #define VXA_MASK VXA(0x3f, 0x3f)
1551
1552 /* An VXR form instruction.  */
1553 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1554
1555 /* The mask for a VXR form instruction.  */
1556 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1557
1558 /* An X form instruction.  */
1559 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1560
1561 /* An X form instruction with the RC bit specified.  */
1562 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1563
1564 /* The mask for an X form instruction.  */
1565 #define X_MASK XRC (0x3f, 0x3ff, 1)
1566
1567 /* An X_MASK with the RA field fixed.  */
1568 #define XRA_MASK (X_MASK | RA_MASK)
1569
1570 /* An X_MASK with the RB field fixed.  */
1571 #define XRB_MASK (X_MASK | RB_MASK)
1572
1573 /* An X_MASK with the RT field fixed.  */
1574 #define XRT_MASK (X_MASK | RT_MASK)
1575
1576 /* An X_MASK with the RA and RB fields fixed.  */
1577 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1578
1579 /* An XRARB_MASK, but with the L bit clear.  */
1580 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1581
1582 /* An X_MASK with the RT and RA fields fixed.  */
1583 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1584
1585 /* An XRTRA_MASK, but with L bit clear.  */
1586 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1587
1588 /* An X form instruction with the L bit specified.  */
1589 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1590
1591 /* The mask for an X form comparison instruction.  */
1592 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1593
1594 /* The mask for an X form instruction with the L field fixed.  */
1595 #define XOPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1596
1597 /* An X form trap instruction with the TO field specified.  */
1598 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1599 #define XTO_MASK (X_MASK | TO_MASK)
1600
1601 /* An X form tlb instruction with the SH field specified.  */
1602 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1603 #define XTLB_MASK (X_MASK | SH_MASK)
1604
1605 /* An X form sync instruction.  */
1606 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1607
1608 /* An X form sync instruction with everything filled in except the LS field.  */
1609 #define XSYNC_MASK (0xff9fffff)
1610
1611 /* An X form AltiVec dss instruction.  */
1612 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1613 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1614
1615 /* An XFL form instruction.  */
1616 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1617 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1618
1619 /* An X form isel instruction.  */
1620 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1621 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1622
1623 /* An XL form instruction with the LK field set to 0.  */
1624 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1625
1626 /* An XL form instruction which uses the LK field.  */
1627 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1628
1629 /* The mask for an XL form instruction.  */
1630 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1631
1632 /* An XL form instruction which explicitly sets the BO field.  */
1633 #define XLO(op, bo, xop, lk) \
1634   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1635 #define XLO_MASK (XL_MASK | BO_MASK)
1636
1637 /* An XL form instruction which explicitly sets the y bit of the BO
1638    field.  */
1639 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1640 #define XLYLK_MASK (XL_MASK | Y_MASK)
1641
1642 /* An XL form instruction which sets the BO field and the condition
1643    bits of the BI field.  */
1644 #define XLOCB(op, bo, cb, xop, lk) \
1645   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1646 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1647
1648 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1649 #define XLBB_MASK (XL_MASK | BB_MASK)
1650 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1651 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1652
1653 /* An XL_MASK with the BO and BB fields fixed.  */
1654 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1655
1656 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1657 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1658
1659 /* An XO form instruction.  */
1660 #define XO(op, xop, oe, rc) \
1661   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1662 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1663
1664 /* An XO_MASK with the RB field fixed.  */
1665 #define XORB_MASK (XO_MASK | RB_MASK)
1666
1667 /* An XS form instruction.  */
1668 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1669 #define XS_MASK XS (0x3f, 0x1ff, 1)
1670
1671 /* A mask for the FXM version of an XFX form instruction.  */
1672 #define XFXFXM_MASK (X_MASK | (1 << 11))
1673
1674 /* An XFX form instruction with the FXM field filled in.  */
1675 #define XFXM(op, xop, fxm) \
1676   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1677
1678 /* An XFX form instruction with the SPR field filled in.  */
1679 #define XSPR(op, xop, spr) \
1680   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1681 #define XSPR_MASK (X_MASK | SPR_MASK)
1682
1683 /* An XFX form instruction with the SPR field filled in except for the
1684    SPRBAT field.  */
1685 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1686
1687 /* An XFX form instruction with the SPR field filled in except for the
1688    SPRG field.  */
1689 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1690
1691 /* An X form instruction with everything filled in except the E field.  */
1692 #define XE_MASK (0xffff7fff)
1693
1694 /* An X form user context instruction.  */
1695 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1696 #define XUC_MASK      XUC(0x3f, 0x1f)
1697
1698 /* The BO encodings used in extended conditional branch mnemonics.  */
1699 #define BODNZF  (0x0)
1700 #define BODNZFP (0x1)
1701 #define BODZF   (0x2)
1702 #define BODZFP  (0x3)
1703 #define BODNZT  (0x8)
1704 #define BODNZTP (0x9)
1705 #define BODZT   (0xa)
1706 #define BODZTP  (0xb)
1707
1708 #define BOF     (0x4)
1709 #define BOFP    (0x5)
1710 #define BOFM4   (0x6)
1711 #define BOFP4   (0x7)
1712 #define BOT     (0xc)
1713 #define BOTP    (0xd)
1714 #define BOTM4   (0xe)
1715 #define BOTP4   (0xf)
1716
1717 #define BODNZ   (0x10)
1718 #define BODNZP  (0x11)
1719 #define BODZ    (0x12)
1720 #define BODZP   (0x13)
1721 #define BODNZM4 (0x18)
1722 #define BODNZP4 (0x19)
1723 #define BODZM4  (0x1a)
1724 #define BODZP4  (0x1b)
1725
1726 #define BOU     (0x14)
1727
1728 /* The BI condition bit encodings used in extended conditional branch
1729    mnemonics.  */
1730 #define CBLT    (0)
1731 #define CBGT    (1)
1732 #define CBEQ    (2)
1733 #define CBSO    (3)
1734
1735 /* The TO encodings used in extended trap mnemonics.  */
1736 #define TOLGT   (0x1)
1737 #define TOLLT   (0x2)
1738 #define TOEQ    (0x4)
1739 #define TOLGE   (0x5)
1740 #define TOLNL   (0x5)
1741 #define TOLLE   (0x6)
1742 #define TOLNG   (0x6)
1743 #define TOGT    (0x8)
1744 #define TOGE    (0xc)
1745 #define TONL    (0xc)
1746 #define TOLT    (0x10)
1747 #define TOLE    (0x14)
1748 #define TONG    (0x14)
1749 #define TONE    (0x18)
1750 #define TOU     (0x1f)
1751 \f
1752 /* Smaller names for the flags so each entry in the opcodes table will
1753    fit on a single line.  */
1754 #undef  PPC
1755 #define PPC     PPC_OPCODE_PPC
1756 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1757 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1758 #define POWER4  PPC_OPCODE_POWER4
1759 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1760 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1761 #define PPC403  PPC_OPCODE_403
1762 #define PPC405  PPC403
1763 #define PPC440  PPC_OPCODE_440
1764 #define PPC750  PPC
1765 #define PPC860  PPC
1766 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1767 #define POWER   PPC_OPCODE_POWER
1768 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1769 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1770 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1771 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1772 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1773 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1774 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1775 #define MFDEC1  PPC_OPCODE_POWER
1776 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1777 #define BOOKE   PPC_OPCODE_BOOKE
1778 #define BOOKE64 PPC_OPCODE_BOOKE64
1779 #define CLASSIC PPC_OPCODE_CLASSIC
1780 #define PPCSPE  PPC_OPCODE_SPE
1781 #define PPCISEL PPC_OPCODE_ISEL
1782 #define PPCEFS  PPC_OPCODE_EFS
1783 #define PPCBRLK PPC_OPCODE_BRLOCK
1784 #define PPCPMR  PPC_OPCODE_PMR
1785 #define PPCCHLK PPC_OPCODE_CACHELCK
1786 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1787 #define PPCRFMCI        PPC_OPCODE_RFMCI
1788 \f
1789 /* The opcode table.
1790
1791    The format of the opcode table is:
1792
1793    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1794
1795    NAME is the name of the instruction.
1796    OPCODE is the instruction opcode.
1797    MASK is the opcode mask; this is used to tell the disassembler
1798      which bits in the actual opcode must match OPCODE.
1799    FLAGS are flags indicated what processors support the instruction.
1800    OPERANDS is the list of operands.
1801
1802    The disassembler reads the table in order and prints the first
1803    instruction which matches, so this table is sorted to put more
1804    specific instructions before more general instructions.  It is also
1805    sorted by major opcode.  */
1806
1807 const struct powerpc_opcode powerpc_opcodes[] = {
1808 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1809 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1810 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1811 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1812 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1813 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1814 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1815 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1816 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1817 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1818 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1819 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1820 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1821 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1822 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1823 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1824
1825 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1826 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1827 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1828 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1829 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1830 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1831 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1832 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1833 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1834 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1835 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1836 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1837 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1838 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1839 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1840 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1841 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1842 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1843 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1844 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1845 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1846 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1847 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1848 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1849 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1850 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1851 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1852 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1853 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1854 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1855
1856 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1857 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1858 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1859 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1860 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1861 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1862 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1863 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1864 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1865 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1866 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1867 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1868 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1869 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1870 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1871 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1872 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1873 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1874 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1875 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1876 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1877 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1878 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1879 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1880 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1881 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1882 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1883 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1884 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1885 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1886 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1887 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1888 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1889 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1890 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1891 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1892 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1893 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1894 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1895 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1896 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1897 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1898 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1899 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1900 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1901 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1902 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1903 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1904 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1905 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1906 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1907 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1908 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1909 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1910 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1911 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1912 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1913 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1914 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1915 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1916 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1917 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1918 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1919 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1920 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1921 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1922 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1923 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1924 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1925 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1926 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1927 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1928 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1929 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1930 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1931 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1932 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1933 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1934 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1935 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1936 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1937 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1938 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1939 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1940 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1941 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1942 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1943 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1944 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1945 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1946 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1947 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1948 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1949 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1950 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1951 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1952 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1953 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1954 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1955 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1956 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1957 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1958 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1959 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1960 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1961 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1962 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1963 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1964 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1965 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1966 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1967 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1968 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1969 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1970 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1971 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1972 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1973 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1974 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1975 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1976 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1977 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1978 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1979 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1980 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1981 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1982 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1983 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1984 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1985 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1986 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1987 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1988 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1989 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1990 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1991 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1992 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1993 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1994 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1995 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1996 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1997 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1998 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1999 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2000 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2001 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2002 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2003 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2004 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2005 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2006 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2007 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2008 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2010 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2011 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2012 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2013 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2014 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2015 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2016 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2017 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2018 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2019 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2020 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2021 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2022 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2023 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2024 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2025 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2026 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2027 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2028 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2029 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2030 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2031 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2032 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2033 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2034 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2035 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2036 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2037 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2038 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2039 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2040 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2041 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2042 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2043 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2044 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2045 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2046 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2047 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2048 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2049 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2050 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2051 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2052 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2053 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2054 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2055 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2056 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2057 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2058 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2059 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2060 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2061 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2062 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2063 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2064 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2065 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2066 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2067 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2068 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2069 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2070 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2071 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2072 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2073 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2074 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2075 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2076 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2077 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2078 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2079 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2080 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2081 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2082 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2083 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2084 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2085 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2086 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2087 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2088 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2089 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2090 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2091 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2092 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2093 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2094 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2095 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2096 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2097
2098 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2099 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2100 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2101 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2102 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2103 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2104 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2105 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2106 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2107 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2108 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2109 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2110 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2111
2112 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2113
2114 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2115 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2116 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2117 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2118 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2119 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2120 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2121 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2122 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2123 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2124
2125 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2126 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2127 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2128 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2129 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2130 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2131 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2132 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2133 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2134 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2135 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2136 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2137 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2138 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2139
2140 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2141 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2142 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2143 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2144 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2145 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2146
2147 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2148 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2149 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2150 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2151 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2152 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2153 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2154 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2155 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2156 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2157 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2158 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2159 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2160 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2161 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2162 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2163 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2164 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2165 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2166 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2167 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2168 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2169
2170 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2171 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2172 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2173 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2174 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2175 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2176 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2177 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2178 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2179 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2180 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2181 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2182 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2183 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2184
2185 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2186 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2187 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2188 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2189 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2190 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2191 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2192 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2193 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2194 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2195 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2196 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2197 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2198 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2199 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2200 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2201 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2202 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2203 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2204 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2205 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2206 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2207 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2208
2209 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2210 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2211 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2212 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2213 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2214 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2215 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2216 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2217 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2218 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2219 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2220 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2221 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2222 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2223 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2224 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2225 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2226 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2227 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2228 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2229 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2230 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2231 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2232
2233 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2234 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2235 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2236 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2237 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2238 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2239 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2240 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2241 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2242 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2243 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2244 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2245 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2246 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2247 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2248 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2249
2250 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2251 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2252 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2253 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2254 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2255 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2256 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2257 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2258 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2259 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2260 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2261 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2262
2263 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2264 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2265 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2266 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2267 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2268 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2269 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2270 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2271 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2272 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2273 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2274 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2275
2276 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2277 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2278 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2279 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2280 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2281 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2282
2283 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2284 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2285 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2286 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2287 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2288 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2289
2290 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2291 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2292 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2293 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2294 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2295 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2296 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2297 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2298
2299 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2300 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2301
2302 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2303 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2304 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2305 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2306
2307 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2308 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2309 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2310 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2311
2312 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2313 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2314 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2315 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2316 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2317 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2318 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2319 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2320
2321 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2322 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2323 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2324 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2325
2326 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2327 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2328 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2329 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2330
2331 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2332 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2333 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2334 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2335
2336 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2337 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2338 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2339 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2340
2341 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2342
2343 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2344 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2345
2346 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2347 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2348
2349 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2350 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2351
2352 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2353
2354 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2355 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2356 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2357 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2358
2359 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2360 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2361 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2362 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2363
2364 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2365 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2366 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2367 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2368
2369 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2370 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2371 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2372
2373 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2374 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2375 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2376
2377 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2378 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2379 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
2380 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
2381 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2382 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
2383
2384 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2385 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2386 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
2387 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
2388 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2389
2390 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2391 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2392 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2393 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2394 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2395 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2396 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2397 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2398 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2399 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2400 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2401 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2402 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2403 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2404 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2405 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2406 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2407 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2408 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2409 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2410 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2411 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2412 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2413 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2414 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2415 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2416 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2417 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2418 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2419 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2420 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2421 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2422 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2423 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2424 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2425 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2426 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2427 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2428 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2429 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2430 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2431 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2432 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2433 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2434 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2435 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2436 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2437 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2438 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2439 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2440 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2441 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2442 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2443 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2444 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2445 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2446 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2447 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2448 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2449 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2450 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2451 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2452 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2453 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2454 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2455 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2456 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2457 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2458 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2459 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2460 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2461 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2462 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2463 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2464 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2465 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2466 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2467 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2468 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2469 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2470 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2471 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2472 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2473 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2474 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2475 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2476 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2477 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2478 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2479 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2480 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2481 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2482 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2483 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2484 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2485 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2486 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2487 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2488 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2489 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2490 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2491 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2492 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2493 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2494 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2495 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2496 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2497 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2498 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2499 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2500 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2501 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2502 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2503 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2504 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2505 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2506 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2507 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2508 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2509 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2510 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2511 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2512 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2513 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2514 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2515 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2516 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2517 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2518 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2519 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2520 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2521 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2522 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2523 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2524 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2525 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2526 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2527 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2528 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2529 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2530 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2531 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2532 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2533 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2534 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2535 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2536 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2537 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2538 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2539 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2540 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2541 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2542 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2543 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2544 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2545 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2546 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2547 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2548 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2549 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2550 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2551 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2552 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2553 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2554 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2555 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2556 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2557 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2558 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2559 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2560 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2561 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2562 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2563 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2564 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2565 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2566 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2567 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2568 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2569 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2570 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2571 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2572 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2573 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2574 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2575 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2576 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2577 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2578 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2579 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2580 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2581 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2582 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2583 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2584 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2585 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2586 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2587 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2588 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2589 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2590 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2591 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2592 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2593 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2594 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2595 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2596 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2597 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2598 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2599 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2600 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2601 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2602 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2603 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2604 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2605 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2606 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2607 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2608 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2609 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2610 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2611 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2612 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2613 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2614 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2615 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2616 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2617 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2618 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2619 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2620 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2621 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2622 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2623 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2624 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2625 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2626 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2627 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2628 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2629 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2630 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2631 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2632 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2633 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2634 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2635 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2636 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2637 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2638 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2639 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2640 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2641 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2642 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2643 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2644 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2645 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2646 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2647 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2648 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2649 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2650 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2651 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2652 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2653 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2654
2655 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2656 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2657 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2658 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2659 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2660
2661 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2662 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2663 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2664 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2665
2666 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2667
2668 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2669 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2670 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2671 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2672 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2673 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2674 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2675 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2676 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2677 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2678 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2679 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2680 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2681 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2682 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2683 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2684 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2685 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2686 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2687 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2688 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2689 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2690 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2691 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2692 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2693 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2694 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2695 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2696 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2697 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2698 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2699 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2700 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2701 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2702 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2703 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2704 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2705 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2706 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2707 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2708 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2709 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2710 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2711 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2713 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2715 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2716 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2717 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2718 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2719 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2721 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2722 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2723 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2725 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2728 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2729 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2730 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2731 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2733 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2734 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2735 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2736 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2737 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2739 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2740 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2741 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2742 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2743 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2746 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2747 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2748 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2751 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2752 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2753 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2754 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2755 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2756 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2757 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2758 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2759 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2760 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2761 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2762 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2763 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2765 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2767 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2769 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2771 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2772 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2773 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2775 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2777 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2778 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2779 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2781 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2783 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2785 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2787 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2789 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2791 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2793 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2795 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2801 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2807 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2813 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2816 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2817 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2822 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2823 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2824 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2825 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2828 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2829 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2830 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2832 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2833 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2834 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2835 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2836 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2837 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2838 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2839 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2840 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2841 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2842 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2843 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2844 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2845 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2846 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2847 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2848 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2849 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2850 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2851 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2852 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2853 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2854 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2855 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2856 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2857 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2858 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2860 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2861 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2862 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2863 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2864 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2866 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2867 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2868 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2869 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2870 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2872 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2875 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2876 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2878 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2879 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2881 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2882 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2883 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2884 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2885 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2886 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2887 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2888 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2889 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2890
2891 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2892
2893 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2894 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2895 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2896
2897 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2898 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2899
2900 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2901
2902 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2903
2904 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2905 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2906
2907 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2908 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2909
2910 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2911
2912 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2913
2914 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2915 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2916
2917 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2918
2919 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2920 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2921
2922 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2923 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2924 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2925 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2926 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2927 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2930 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2931 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2932 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2933 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2934 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2935 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2936 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2937 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2940 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2941 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2942 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2944 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2945 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2946 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2947 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2950 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2951 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2952 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2954 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2955 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2956 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2957 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2960 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2961 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2962 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2964 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2965 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2966 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2967 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2970 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2971 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2972 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2974 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2975 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2980 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2985 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2990 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2995 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2996 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2997 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3000 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3001 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3002 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3005 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3010 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3011 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3012 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3015 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3020 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3021 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3022 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3025 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3026 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3027 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3030 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3031 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3032 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3035 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3036 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3037 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3040 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3041 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3042 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3045 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3046 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3047 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3048 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3049 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3050 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3051 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3052 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3053 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3054 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3055 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3056 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3057 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3058 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3059 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3060 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3061 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3062 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3063 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3064 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3065 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3066 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3067 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3068 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3069 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3070 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3071 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3072 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3073 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3074
3075 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3076 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3077
3078 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3079 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3080
3081 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3082 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3083 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3084 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3085 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3086 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3087 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3088 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3089
3090 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3091 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3092
3093 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3094 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3095 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3096 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3097
3098 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3099 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3100 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3101 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3102 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3103 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3104
3105 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3106 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3107 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3108
3109 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3110 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3111
3112 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3113 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3114
3115 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3116 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3117
3118 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3119 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3120
3121 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3122 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3123
3124 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3125 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3126 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3127 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3128 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3129 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3130
3131 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3132 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3133
3134 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3135 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3136
3137 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3138 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3139
3140 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3141 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3142 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3143 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3144
3145 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3146 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3147
3148 { "cmpw",    XOPL(31,0,0), XOPL_MASK, PPCCOM,           { OBF, RA, RB } },
3149 { "cmpd",    XOPL(31,0,1), XOPL_MASK, PPC64,            { OBF, RA, RB } },
3150 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3151 { "cmp",     X(31,0),   XOPL_MASK,      PWRCOM,         { BF, RA, RB } },
3152
3153 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3154 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3155 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3156 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3157 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3158 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3159 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3160 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3161 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3162 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3163 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3164 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3165 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3166 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3167 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3168 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3169 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3170 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3171 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3172 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3173 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3174 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3175 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3176 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3177 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3178 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3179 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3180 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3181 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3182 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3183 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3184
3185 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3186 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3187 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3188 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3189 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3190 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3191 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3192 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3193 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3194 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3195 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3196 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3197
3198 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3199 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3200
3201 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3202 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3203 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3204 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3205 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3206 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3207 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3208 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3209
3210 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3211 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3212
3213 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3214 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3215 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3216 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3217
3218 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
3219 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3220
3221 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA0, RB } },
3222
3223 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA0, RB } },
3224
3225 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3226 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3227
3228 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA0, RB } },
3229 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3230
3231 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3232 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3233 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3234 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3235
3236 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3237 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3238 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3239 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3240
3241 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3242 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3243
3244 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3245 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3246
3247 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3248 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3249
3250 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3251
3252 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3253
3254 { "cmplw",   XOPL(31,32,0), XOPL_MASK, PPCCOM,  { OBF, RA, RB } },
3255 { "cmpld",   XOPL(31,32,1), XOPL_MASK, PPC64,           { OBF, RA, RB } },
3256 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3257 { "cmpl",    X(31,32),  XOPL_MASK,       PWRCOM,        { BF, RA, RB } },
3258
3259 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3260 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3261 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3262 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3263 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3264 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3265 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3266 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3267
3268 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3269
3270 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3271
3272 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3273 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3274
3275 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3276
3277 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3278
3279 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3280 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3281
3282 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3283 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3284
3285 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3286 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3287 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3288 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3289 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3290 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3291 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3292 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3293 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3294 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3295 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3296 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3297 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3298 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3299 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3300
3301 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3302 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3303
3304 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3305 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3306
3307 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3308 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3309
3310 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3311
3312 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3313
3314 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA0, RB } },
3315
3316 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3317
3318 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA0, RB } },
3319
3320 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3321
3322 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3323
3324 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3325 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3326 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3327 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3328
3329 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3330 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3331 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3332 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3333
3334 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3335
3336 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3337
3338 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3339
3340 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3341 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3342 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3343 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3344
3345 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3346
3347 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3348
3349 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3350
3351 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3352
3353 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3354 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3355 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3356 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3357 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3358 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3359 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3360 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3361
3362 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3363 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3364 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3365 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3366 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3367 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3368 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3369 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3370
3371 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3372
3373 { "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,        { RS }},
3374 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3375
3376 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3377
3378 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA0, RB } },
3379
3380 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA0, RB } },
3381
3382 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA0, RB } },
3383 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3384
3385 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA0, RB } },
3386
3387 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3388
3389 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3390 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3391
3392 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3393 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3394
3395 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3396
3397 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3398 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3399
3400 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3401
3402 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3403
3404 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3405 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA0, RB } },
3406
3407 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3408 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3409
3410 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3411
3412 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3413 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3414 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3415 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3416 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3417 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3418 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3419 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3420
3421 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3422 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3423 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3424 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3425 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3426 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3427 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3428 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3429
3430 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3431
3432 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA0, RB } },
3433
3434 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA0, RB } },
3435
3436 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3437 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3438
3439 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3440 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3441
3442 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3443
3444 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3445
3446 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3447 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3448 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3449 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3450 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3451 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3452 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3453 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3454
3455 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3456 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3457 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3458 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3459
3460 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3461 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3462 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3463 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3464 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3465 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3466 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3467 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3468
3469 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3470 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3471 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3472 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3473 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3474 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3475 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3476 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3477
3478 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3479 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3480 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3481
3482 { "dcbtst",  X(31,246), X_MASK, PPC,                    { CT, RA, RB } },
3483
3484 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3485
3486 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3487 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3488
3489 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3490
3491 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3492
3493 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3494
3495 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3496 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3497 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3498 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3499
3500 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3501 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3502 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3503 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3504 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3505 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3506 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3507 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3508
3509 { "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
3510
3511 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3512
3513 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3514 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3515
3516 { "dcbt",    X(31,278), X_MASK, PPC,                    { CT, RA, RB } },
3517
3518 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA0, RB } },
3519
3520 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3521 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3522
3523 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3524
3525 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3526
3527 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3528 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA0, RB } },
3529
3530 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3531
3532 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3533
3534 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3535 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3536
3537 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3538
3539 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3540 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3541 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3542 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3543 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3544 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3545 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3546 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3547 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3548 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3549 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3550 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3551 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3552 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3553 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3554 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3555 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3556 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3557 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3558 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3559 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3560 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3561 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3562 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3563 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3564 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3565 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3566 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3567 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3568 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3569 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3570 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3571 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3572 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3573 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3574
3575 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3576 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3577 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3578 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3579
3580 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3581
3582 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3583 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3584 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3585 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3586 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3587 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3588 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3589 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3590 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3591 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3592 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3593 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3594 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3595 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3596 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3597 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3598 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3599 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3600 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3601 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3602 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3603 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3604 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3605 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3606 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3607 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3608 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3609 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3610 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3611 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3612 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3613 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3614 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3615 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3616 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3617 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3618 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3619 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3620 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3621 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3622 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3623 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3624 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
3625 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, BOOKE,    { RT } },
3626 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
3627 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, BOOKE,    { RT } },
3628 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
3629 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, BOOKE,    { RT } },
3630 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
3631 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, BOOKE,    { RT } },
3632 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3633 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3634 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3635 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3636 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3637 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3638 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
3639 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3640 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3641 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3642 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3643 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3644 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3645 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3646 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3647 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3648 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3649 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3650 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3651 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3652 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3653 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3654 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3655 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3656 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3657 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3658 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3659 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3660 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3661 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3662 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3663 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3664 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3665 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3666 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3667 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3668 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3669 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3670 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3671 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3672 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3673 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3674 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3675 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3676 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3677 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3678 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3679 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3680 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3681 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3682 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3683 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3684 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3685 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3686 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3687 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3688 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3689 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3690 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3691 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3692 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3693 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3694 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3695 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3696 { "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,   { RT } },
3697 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3698 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3699 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3700 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3701 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3702 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3703 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3704 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3705 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3706 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3707 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3708 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3709 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3710 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3711 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3712 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3713 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3714 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3715 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3716 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3717 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3718 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3719 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3720 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3721 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3722 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3723 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3724 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3725 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3726 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3727 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3728 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3729 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3730 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3731 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3732 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3733 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3734 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3735 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3736 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3737 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3738 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3739 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3740 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3741 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3742 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3743 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3744 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3745 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3746 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3747 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3748 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3749 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3750 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3751 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3752 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3753 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3754 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3755 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3756 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3757 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3758 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3759 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3760 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3761 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3762 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3763 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3764 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3765 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3766 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3767 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3768 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3769 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3770 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3771 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3772 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3773
3774 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA0, RB } },
3775
3776 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3777 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3778
3779 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA0, RB } },
3780
3781 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3782
3783 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3784 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3785
3786 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3787
3788 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3789 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3790 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3791 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3792
3793 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3794 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3795 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3796 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3797
3798 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3799
3800 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3801
3802 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3803
3804 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3805
3806 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3807
3808 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3809
3810 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3811 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3812
3813 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3814 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3815
3816 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3817
3818 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3819
3820 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA0, RB } },
3821
3822 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3823
3824 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3825
3826 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3827
3828 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3829
3830 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3831 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3832
3833 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3834 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3835
3836 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3837
3838 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3839
3840 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3841
3842 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3843
3844 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3845
3846 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3847 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3848 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3849 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3850
3851 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3852 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3853 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3854 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3855 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3856 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3857 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3858 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3859 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3860 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3861 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3862 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3863 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3864 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3865 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3866 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3867 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3868 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3869 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3870 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3871 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3872 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3873 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3874 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3875 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3876 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3877 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3878 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3879 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3880 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3881 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3882 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3883 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3884 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3885 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3886
3887 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3888 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3889
3890 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3891 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3892 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3893 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3894
3895 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3896 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3897
3898 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3899 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3900 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3901 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3902
3903 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3904 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3905 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3906 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3907 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3908 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3909 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3910 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3911 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3912 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3913 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3914 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3915 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3916 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3917 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3918 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3919 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3920 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3921 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3922 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3923 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3924 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3925 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3926 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3927 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3928 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3929 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3930 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3931 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3932 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3933 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3934 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3935 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3936 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3937 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3938 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3939 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3940 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3941 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3942 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3943 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3944 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3945 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
3946 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3947 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3948 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3949 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3950 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3951 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3952 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3953 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3954 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3955 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3956 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3957 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3958 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3959 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3960 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3961 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3962 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3963 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3964 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3965 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3966 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3967 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3968 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3969 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3970 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3971 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3972 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3973 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3974 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3975 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3976 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3977 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3978 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3979 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3980 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3981 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3982 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3983 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3984 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3985 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3986 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3987 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
3988 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
3989 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
3990 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
3991 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
3992 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
3993 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
3994 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
3995 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
3996 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
3997 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
3998 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
3999 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4000 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4001 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
4002 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4003 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
4004 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
4005 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
4006 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
4007 { "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,    { RS } },
4008 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4009 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4010 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4011 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4012 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4013 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4014 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4015 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4016 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
4017 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
4018 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
4019 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
4020 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
4021 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
4022 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
4023 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
4024 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
4025 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
4026 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
4027 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
4028 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4029 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
4030 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4031 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
4032 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4033 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4034 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4035 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
4036 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
4037 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
4038 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
4039 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
4040 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
4041 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
4042 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
4043 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4044 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
4045 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
4046 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4047 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
4048 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4049 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
4050 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4051 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
4052 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4053 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
4054 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4055
4056 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4057
4058 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4059 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4060
4061 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4062
4063 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4064
4065 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4066
4067 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4068
4069 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4070 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4071 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4072 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4073 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4074 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4075
4076 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4077 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4078 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4079 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4080
4081 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4082 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4083
4084 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4085 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4086 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4087 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4088
4089 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4090
4091 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4092
4093 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4094
4095 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4096
4097 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4098
4099 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4100 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4101
4102 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4103
4104 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4105 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4106
4107 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4108 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4109
4110 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA0, RB } },
4111
4112 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4113 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4114 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4115 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4116
4117 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4118 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4119
4120 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4121 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4122
4123 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4124 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4125
4126 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4127
4128 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4129
4130 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4131
4132 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4133
4134 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4135
4136 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4137
4138 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4139
4140 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA0, NB } },
4141 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA0, NB } },
4142
4143 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4144 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4145 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4146 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4147 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4148
4149 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA0, RB } },
4150
4151 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4152
4153 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4154
4155 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4156
4157 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4158
4159 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4160
4161 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4162
4163 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4164 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4165
4166 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4167 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4168
4169 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA0, RB } },
4170
4171 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4172 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4173
4174 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4175 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4176
4177 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4178
4179 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4180
4181 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4182
4183 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4184 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4185
4186 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4187
4188 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA0, NB } },
4189 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA0, NB } },
4190
4191 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA0, RB } },
4192
4193 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4194 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4195
4196 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4197 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4198
4199 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4200
4201 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4202
4203 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4204
4205 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4206 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4207
4208 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4209
4210 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4211
4212 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4213 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4214
4215 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA0, RB } },
4216
4217 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4218 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4219 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4220 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4221
4222 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4223 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4224
4225 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4226
4227 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4228 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4229
4230 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4231
4232 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4233 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4234
4235 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4236 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4237 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4238 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4239
4240 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4241
4242 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4243 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4244
4245 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
4246 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
4247 { "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
4248 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
4249 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4250 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4251
4252 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4253
4254 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA0, RB } },
4255
4256 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4257 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4258
4259 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4260 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4261
4262 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4263 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4264 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4265 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4266
4267 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4268
4269 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4270
4271 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4272 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4273 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
4274 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RS, RA, SH } },
4275
4276 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4277 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4278
4279 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4280 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4281
4282 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4283
4284 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4285
4286 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4287 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4288 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4289 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4290
4291 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4292
4293 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA0, RB } },
4294
4295 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4296 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4297
4298 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4299
4300 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4301 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4302
4303 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4304
4305 { "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4306 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4307 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4308
4309 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4310
4311 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4312 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4313 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4314 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4315 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4316 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4317 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4318 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4319 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4320 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4321 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4322 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4323
4324 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
4325 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4326
4327 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4328 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4329
4330 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA0 } },
4331
4332 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4333
4334 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4335 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4336
4337 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4338 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4339
4340 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA0 } },
4341
4342 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4343
4344 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA0 } },
4345
4346 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4347
4348 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA0 } },
4349
4350 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4351
4352 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA0 } },
4353
4354 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4355
4356 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4357 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4358
4359 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4360 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4361
4362 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA0 } },
4363
4364 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4365
4366 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA0 } },
4367
4368 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4369
4370 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA0 } },
4371
4372 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4373
4374 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA0 } },
4375
4376 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4377
4378 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4379
4380 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4381
4382 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4383
4384 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4385 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4386 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4387 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4388 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4389 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4390 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4391 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4392 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA0 } },
4393 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4394 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4395 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4396 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4397 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4398
4399 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4400
4401 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4402
4403 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4404
4405 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4406 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4407
4408 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4409 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4410
4411 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4412 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4413
4414 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4415 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4416
4417 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4418 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4419
4420 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4421 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4422
4423 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4424 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4425
4426 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4427 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4428
4429 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4430 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4431
4432 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4433 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4434
4435 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4436
4437 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4438
4439 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4440 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4441 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4442 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4443 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4444 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4445 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA0 } },
4446 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4447 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4448 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4449 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4450 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4451
4452 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA0 } },
4453
4454 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4455
4456 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
4457
4458 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4459
4460 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4461 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4462
4463 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4464 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4465 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4466 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4467
4468 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4469 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4470 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4471 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4472
4473 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4474 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4475 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4476 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4477
4478 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4479 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4480 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4481 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4482
4483 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4484 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4485 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4486 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4487
4488 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4489 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4490
4491 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4492 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4493
4494 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4495 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4496 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4497 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4498
4499 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4500 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4501
4502 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4503 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4504 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4505 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4506
4507 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4508 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4509 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4510 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4511
4512 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4513 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4514 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4515 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4516
4517 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4518 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4519 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4520 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4521
4522 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4523
4524 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4525 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4526
4527 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4528 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4529
4530 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4531
4532 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4533 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4534
4535 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4536 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4537
4538 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4539 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4540
4541 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4542 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4543
4544 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4545 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4546
4547 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4548 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4549
4550 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4551 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4552
4553 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4554 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4555
4556 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4557 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4558
4559 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4560 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4561
4562 };
4563
4564 const int powerpc_num_opcodes =
4565   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4566 \f
4567 /* The macro table.  This is only used by the assembler.  */
4568
4569 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4570    when x=0; 32-x when x is between 1 and 31; are negative if x is
4571    negative; and are 32 or more otherwise.  This is what you want
4572    when, for instance, you are emulating a right shift by a
4573    rotate-left-and-mask, because the underlying instructions support
4574    shifts of size 0 but not shifts of size 32.  By comparison, when
4575    extracting x bits from some word you want to use just 32-x, because
4576    the underlying instructions don't support extracting 0 bits but do
4577    support extracting the whole word (32 bits in this case).  */
4578
4579 const struct powerpc_macro powerpc_macros[] = {
4580 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4581 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4582 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4583 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4584 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4585 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4586 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4587 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4588 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4589 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4590 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4591 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4592 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4593 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4594 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4595 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4596
4597 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4598 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4599 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4600 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4601 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4602 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4603 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4604 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4605 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4606 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4607 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4608 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4609 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4610 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4611 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4614 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4615 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4616 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4617 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4618 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4619 };
4620
4621 const int powerpc_num_macros =
4622   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);