2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "opcode/riscv.h"
27 /* Register names used by gas and objdump. */
29 const char * const riscv_gpr_names_numeric
[NGPR
] =
31 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
32 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
33 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
34 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
37 const char * const riscv_gpr_names_abi
[NGPR
] = {
38 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
39 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
40 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
41 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
44 const char * const riscv_fpr_names_numeric
[NFPR
] =
46 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
47 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
48 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
49 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
52 const char * const riscv_fpr_names_abi
[NFPR
] = {
53 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
54 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
55 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
56 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
59 /* The order of overloaded instructions matters. Label arguments and
60 register arguments look the same. Instructions that can have either
61 for arguments must apear in the correct order in this table for the
62 assembler to pick the right one. In other words, entries with
63 immediate operands must apear after the same instruction with
66 Because of the lookup algorithm used, entries with the same opcode
67 name must be contiguous. */
69 #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
70 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
71 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
72 #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
73 #define MASK_IMM ENCODE_ITYPE_IMM (-1U)
74 #define MASK_RVC_IMM ENCODE_RVC_IMM (-1U)
75 #define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
76 #define MASK_RM (OP_MASK_RM << OP_SH_RM)
77 #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
78 #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
79 #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
80 #define MASK_RL (OP_MASK_RL << OP_SH_RL)
81 #define MASK_AQRL (MASK_AQ | MASK_RL)
82 #define MASK_RVB_IMM (OP_MASK_SHAMT << OP_SH_SHAMT)
85 match_opcode (const struct riscv_opcode
*op
, insn_t insn
)
87 return ((insn
^ op
->match
) & op
->mask
) == 0;
91 match_never (const struct riscv_opcode
*op ATTRIBUTE_UNUSED
,
92 insn_t insn ATTRIBUTE_UNUSED
)
98 match_rs1_eq_rs2 (const struct riscv_opcode
*op
, insn_t insn
)
100 int rs1
= (insn
& MASK_RS1
) >> OP_SH_RS1
;
101 int rs2
= (insn
& MASK_RS2
) >> OP_SH_RS2
;
102 return match_opcode (op
, insn
) && rs1
== rs2
;
106 match_rd_nonzero (const struct riscv_opcode
*op
, insn_t insn
)
108 return match_opcode (op
, insn
) && ((insn
& MASK_RD
) != 0);
112 match_c_add (const struct riscv_opcode
*op
, insn_t insn
)
114 return match_rd_nonzero (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
117 /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
118 matching function for this. */
121 match_c_add_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
123 return match_opcode (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
127 match_c_nop (const struct riscv_opcode
*op
, insn_t insn
)
129 return (match_opcode (op
, insn
)
130 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 0));
134 match_c_addi16sp (const struct riscv_opcode
*op
, insn_t insn
)
136 return (match_opcode (op
, insn
)
137 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 2)
138 && EXTRACT_RVC_ADDI16SP_IMM (insn
) != 0);
142 match_c_lui (const struct riscv_opcode
*op
, insn_t insn
)
144 return (match_rd_nonzero (op
, insn
)
145 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
146 && EXTRACT_RVC_LUI_IMM (insn
) != 0);
149 /* We don't allow lui zero,X to become a c.lui hint, so we need a separate
150 matching function for this. */
153 match_c_lui_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
155 return (match_opcode (op
, insn
)
156 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
157 && EXTRACT_RVC_LUI_IMM (insn
) != 0);
161 match_c_addi4spn (const struct riscv_opcode
*op
, insn_t insn
)
163 return match_opcode (op
, insn
) && EXTRACT_RVC_ADDI4SPN_IMM (insn
) != 0;
166 /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
169 match_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
171 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
174 /* This requires a non-zero rd, and a non-zero shift. */
177 match_slli_as_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
179 return match_rd_nonzero (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
182 /* This requires a zero shift. A zero rd is a hint, so is allowed. */
185 match_c_slli64 (const struct riscv_opcode
*op
, insn_t insn
)
187 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) == 0;
190 /* This is used for both srli and srai. This requires a non-zero shift.
191 A zero rd is not possible. */
194 match_srxi_as_c_srxi (const struct riscv_opcode
*op
, insn_t insn
)
196 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
199 const struct riscv_opcode riscv_opcodes
[] =
201 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
202 {"unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, INSN_ALIAS
},
203 {"unimp", 0, INSN_CLASS_I
, "", MATCH_CSRRW
| (CSR_CYCLE
<< OP_SH_CSR
), 0xffffffffU
, match_opcode
, 0 }, /* csrw cycle, x0 */
204 {"ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
205 {"ebreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, 0 },
206 {"sbreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
207 {"sbreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, INSN_ALIAS
},
208 {"ret", 0, INSN_CLASS_C
, "", MATCH_C_JR
| (X_RA
<< OP_SH_RD
), MASK_C_JR
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
209 {"ret", 0, INSN_CLASS_I
, "", MATCH_JALR
| (X_RA
<< OP_SH_RS1
), MASK_JALR
| MASK_RD
| MASK_RS1
| MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
210 {"jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_ALIAS
|INSN_BRANCH
},
211 {"jr", 0, INSN_CLASS_I
, "s", MATCH_JALR
, MASK_JALR
| MASK_RD
| MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
212 {"jr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
, MASK_JALR
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
213 {"jr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
, MASK_JALR
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
214 {"jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_ALIAS
|INSN_JSR
},
215 {"jalr", 0, INSN_CLASS_I
, "s", MATCH_JALR
| (X_RA
<< OP_SH_RD
), MASK_JALR
| MASK_RD
| MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
216 {"jalr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
| (X_RA
<< OP_SH_RD
), MASK_JALR
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
217 {"jalr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
| (X_RA
<< OP_SH_RD
), MASK_JALR
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
218 {"jalr", 0, INSN_CLASS_I
, "d,s", MATCH_JALR
, MASK_JALR
| MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
219 {"jalr", 0, INSN_CLASS_I
, "d,o(s)", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
220 {"jalr", 0, INSN_CLASS_I
, "d,s,j", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
221 {"j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
222 {"j", 0, INSN_CLASS_I
, "a", MATCH_JAL
, MASK_JAL
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
223 {"jal", 0, INSN_CLASS_I
, "d,a", MATCH_JAL
, MASK_JAL
, match_opcode
, INSN_JSR
},
224 {"jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
225 {"jal", 0, INSN_CLASS_I
, "a", MATCH_JAL
| (X_RA
<< OP_SH_RD
), MASK_JAL
| MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
226 {"call", 0, INSN_CLASS_I
, "d,c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
227 {"call", 0, INSN_CLASS_I
, "c", (X_RA
<< OP_SH_RS1
) | (X_RA
<< OP_SH_RD
), (int) M_CALL
, match_never
, INSN_MACRO
},
228 {"tail", 0, INSN_CLASS_I
, "c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
229 {"jump", 0, INSN_CLASS_I
, "c,s", 0, (int) M_CALL
, match_never
, INSN_MACRO
},
230 {"nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
231 {"nop", 0, INSN_CLASS_I
, "", MATCH_ADDI
, MASK_ADDI
| MASK_RD
| MASK_RS1
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
232 {"lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
233 {"lui", 0, INSN_CLASS_I
, "d,u", MATCH_LUI
, MASK_LUI
, match_opcode
, 0 },
234 {"li", 0, INSN_CLASS_C
, "d,Cv", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
235 {"li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
236 {"li", 0, INSN_CLASS_I
, "d,j", MATCH_ADDI
, MASK_ADDI
| MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* addi */
237 {"li", 0, INSN_CLASS_I
, "d,I", 0, (int) M_LI
, match_never
, INSN_MACRO
},
238 {"mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
239 {"mv", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
240 {"move", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
241 {"move", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
242 {"zext.b", 0, INSN_CLASS_I
, "d,s", MATCH_ANDI
| ENCODE_ITYPE_IMM (255), MASK_ANDI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
243 {"andi", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
244 {"andi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, 0 },
245 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
246 {"and", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
247 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
248 {"and", 0, INSN_CLASS_I
, "d,s,t", MATCH_AND
, MASK_AND
, match_opcode
, 0 },
249 {"and", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, INSN_ALIAS
},
250 {"beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
251 {"beqz", 0, INSN_CLASS_I
, "s,p", MATCH_BEQ
, MASK_BEQ
| MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
252 {"beq", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
253 {"beq", 0, INSN_CLASS_I
, "s,t,p", MATCH_BEQ
, MASK_BEQ
, match_opcode
, INSN_CONDBRANCH
},
254 {"blez", 0, INSN_CLASS_I
, "t,p", MATCH_BGE
, MASK_BGE
| MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
255 {"bgez", 0, INSN_CLASS_I
, "s,p", MATCH_BGE
, MASK_BGE
| MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
256 {"bge", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_CONDBRANCH
},
257 {"bgeu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_CONDBRANCH
},
258 {"ble", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
259 {"bleu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
260 {"bltz", 0, INSN_CLASS_I
, "s,p", MATCH_BLT
, MASK_BLT
| MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
261 {"bgtz", 0, INSN_CLASS_I
, "t,p", MATCH_BLT
, MASK_BLT
| MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
262 {"blt", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_CONDBRANCH
},
263 {"bltu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_CONDBRANCH
},
264 {"bgt", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
265 {"bgtu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
266 {"bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
267 {"bnez", 0, INSN_CLASS_I
, "s,p", MATCH_BNE
, MASK_BNE
| MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
268 {"bne", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
269 {"bne", 0, INSN_CLASS_I
, "s,t,p", MATCH_BNE
, MASK_BNE
, match_opcode
, INSN_CONDBRANCH
},
270 {"addi", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
271 {"addi", 0, INSN_CLASS_C
, "d,CU,Cj", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
272 {"addi", 0, INSN_CLASS_C
, "d,CU,z", MATCH_C_NOP
, MASK_C_ADDI
| MASK_RVC_IMM
, match_c_nop
, INSN_ALIAS
},
273 {"addi", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
274 {"addi", 0, INSN_CLASS_C
, "d,Cz,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
275 {"addi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, 0 },
276 {"add", 0, INSN_CLASS_C
, "d,CU,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
277 {"add", 0, INSN_CLASS_C
, "d,CV,CU", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
278 {"add", 0, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
279 {"add", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
280 {"add", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
281 {"add", 0, INSN_CLASS_C
, "d,Cz,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
282 {"add", 0, INSN_CLASS_I
, "d,s,t", MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
283 {"add", 0, INSN_CLASS_I
, "d,s,t,1",MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
284 {"add", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, INSN_ALIAS
},
285 {"la", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LA
, match_never
, INSN_MACRO
},
286 {"lla", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LLA
, match_never
, INSN_MACRO
},
287 {"la.tls.gd", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_GD
, match_never
, INSN_MACRO
},
288 {"la.tls.ie", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_IE
, match_never
, INSN_MACRO
},
289 {"neg", 0, INSN_CLASS_I
, "d,t", MATCH_SUB
, MASK_SUB
| MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
290 {"slli", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
291 {"slli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, 0 },
292 {"sll", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
293 {"sll", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLL
, MASK_SLL
, match_opcode
, 0 },
294 {"sll", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, INSN_ALIAS
},
295 {"srli", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
296 {"srli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, 0 },
297 {"srl", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
298 {"srl", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRL
, MASK_SRL
, match_opcode
, 0 },
299 {"srl", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, INSN_ALIAS
},
300 {"srai", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
301 {"srai", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, 0 },
302 {"sra", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
303 {"sra", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRA
, MASK_SRA
, match_opcode
, 0 },
304 {"sra", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, INSN_ALIAS
},
305 {"sub", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, INSN_ALIAS
},
306 {"sub", 0, INSN_CLASS_I
, "d,s,t", MATCH_SUB
, MASK_SUB
, match_opcode
, 0 },
307 {"lb", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LB
, MASK_LB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
308 {"lb", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LB
, match_never
, INSN_MACRO
},
309 {"lbu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LBU
, MASK_LBU
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
310 {"lbu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LBU
, match_never
, INSN_MACRO
},
311 {"lh", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LH
, MASK_LH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
312 {"lh", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LH
, match_never
, INSN_MACRO
},
313 {"lhu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LHU
, MASK_LHU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
314 {"lhu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LHU
, match_never
, INSN_MACRO
},
315 {"lw", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
316 {"lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
317 {"lw", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LW
, MASK_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
318 {"lw", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LW
, match_never
, INSN_MACRO
},
319 {"not", 0, INSN_CLASS_I
, "d,s", MATCH_XORI
| MASK_IMM
, MASK_XORI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
320 {"ori", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, 0 },
321 {"or", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
322 {"or", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
323 {"or", 0, INSN_CLASS_I
, "d,s,t", MATCH_OR
, MASK_OR
, match_opcode
, 0 },
324 {"or", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, INSN_ALIAS
},
325 {"auipc", 0, INSN_CLASS_I
, "d,u", MATCH_AUIPC
, MASK_AUIPC
, match_opcode
, 0 },
326 {"seqz", 0, INSN_CLASS_I
, "d,s", MATCH_SLTIU
| ENCODE_ITYPE_IMM (1), MASK_SLTIU
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
327 {"snez", 0, INSN_CLASS_I
, "d,t", MATCH_SLTU
, MASK_SLTU
| MASK_RS1
, match_opcode
, INSN_ALIAS
},
328 {"sltz", 0, INSN_CLASS_I
, "d,s", MATCH_SLT
, MASK_SLT
| MASK_RS2
, match_opcode
, INSN_ALIAS
},
329 {"sgtz", 0, INSN_CLASS_I
, "d,t", MATCH_SLT
, MASK_SLT
| MASK_RS1
, match_opcode
, INSN_ALIAS
},
330 {"slti", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, 0 },
331 {"slt", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLT
, MASK_SLT
, match_opcode
, 0 },
332 {"slt", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, INSN_ALIAS
},
333 {"sltiu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, 0 },
334 {"sltu", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLTU
, MASK_SLTU
, match_opcode
, 0 },
335 {"sltu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, INSN_ALIAS
},
336 {"sgt", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLT
, MASK_SLT
, match_opcode
, INSN_ALIAS
},
337 {"sgtu", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLTU
, MASK_SLTU
, match_opcode
, INSN_ALIAS
},
338 {"sb", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SB
, MASK_SB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
339 {"sb", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SB
, match_never
, INSN_MACRO
},
340 {"sh", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SH
, MASK_SH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
341 {"sh", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SH
, match_never
, INSN_MACRO
},
342 {"sw", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
343 {"sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
344 {"sw", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SW
, MASK_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
345 {"sw", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SW
, match_never
, INSN_MACRO
},
346 {"pause", 0, INSN_CLASS_ZIHINTPAUSE
, "", MATCH_PAUSE
, MASK_PAUSE
, match_opcode
, 0 },
347 {"fence", 0, INSN_CLASS_I
, "", MATCH_FENCE
| MASK_PRED
| MASK_SUCC
, MASK_FENCE
| MASK_RD
| MASK_RS1
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
348 {"fence", 0, INSN_CLASS_I
, "P,Q", MATCH_FENCE
, MASK_FENCE
| MASK_RD
| MASK_RS1
| (MASK_IMM
& ~MASK_PRED
& ~MASK_SUCC
), match_opcode
, 0 },
349 {"fence.i", 0, INSN_CLASS_ZIFENCEI
, "", MATCH_FENCE_I
, MASK_FENCE
| MASK_RD
| MASK_RS1
| MASK_IMM
, match_opcode
, 0 },
350 {"fence.tso", 0, INSN_CLASS_I
, "", MATCH_FENCE_TSO
, MASK_FENCE_TSO
| MASK_RD
| MASK_RS1
, match_opcode
, INSN_ALIAS
},
351 {"rdcycle", 0, INSN_CLASS_I
, "d", MATCH_RDCYCLE
, MASK_RDCYCLE
, match_opcode
, INSN_ALIAS
},
352 {"rdinstret", 0, INSN_CLASS_I
, "d", MATCH_RDINSTRET
, MASK_RDINSTRET
, match_opcode
, INSN_ALIAS
},
353 {"rdtime", 0, INSN_CLASS_I
, "d", MATCH_RDTIME
, MASK_RDTIME
, match_opcode
, INSN_ALIAS
},
354 {"rdcycleh", 32, INSN_CLASS_I
, "d", MATCH_RDCYCLEH
, MASK_RDCYCLEH
, match_opcode
, INSN_ALIAS
},
355 {"rdinstreth", 32, INSN_CLASS_I
, "d", MATCH_RDINSTRETH
, MASK_RDINSTRETH
, match_opcode
, INSN_ALIAS
},
356 {"rdtimeh", 32, INSN_CLASS_I
, "d", MATCH_RDTIMEH
, MASK_RDTIMEH
, match_opcode
, INSN_ALIAS
},
357 {"ecall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
358 {"scall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
359 {"xori", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, 0 },
360 {"xor", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
361 {"xor", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
362 {"xor", 0, INSN_CLASS_I
, "d,s,t", MATCH_XOR
, MASK_XOR
, match_opcode
, 0 },
363 {"xor", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, INSN_ALIAS
},
364 {"lwu", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LWU
, MASK_LWU
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
365 {"lwu", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LWU
, match_never
, INSN_MACRO
},
366 {"ld", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
367 {"ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
368 {"ld", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LD
, MASK_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
369 {"ld", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LD
, match_never
, INSN_MACRO
},
370 {"sd", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
371 {"sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
372 {"sd", 64, INSN_CLASS_I
, "t,q(s)", MATCH_SD
, MASK_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
373 {"sd", 64, INSN_CLASS_I
, "t,A,s", 0, (int) M_SD
, match_never
, INSN_MACRO
},
374 {"sext.w", 64, INSN_CLASS_C
, "d,CU", MATCH_C_ADDIW
, MASK_C_ADDIW
| MASK_RVC_IMM
, match_rd_nonzero
, INSN_ALIAS
},
375 {"sext.w", 64, INSN_CLASS_I
, "d,s", MATCH_ADDIW
, MASK_ADDIW
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
376 {"addiw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
377 {"addiw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, 0 },
378 {"addw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
379 {"addw", 64, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
380 {"addw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
381 {"addw", 64, INSN_CLASS_I
, "d,s,t", MATCH_ADDW
, MASK_ADDW
, match_opcode
, 0 },
382 {"addw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, INSN_ALIAS
},
383 {"negw", 64, INSN_CLASS_I
, "d,t", MATCH_SUBW
, MASK_SUBW
| MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
384 {"slliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, 0 },
385 {"sllw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SLLW
, MASK_SLLW
, match_opcode
, 0 },
386 {"sllw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, INSN_ALIAS
},
387 {"srliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, 0 },
388 {"srlw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRLW
, MASK_SRLW
, match_opcode
, 0 },
389 {"srlw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, INSN_ALIAS
},
390 {"sraiw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, 0 },
391 {"sraw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRAW
, MASK_SRAW
, match_opcode
, 0 },
392 {"sraw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, INSN_ALIAS
},
393 {"subw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, INSN_ALIAS
},
394 {"subw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SUBW
, MASK_SUBW
, match_opcode
, 0 },
396 /* Atomic memory operation instruction subset. */
397 {"lr.w", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
, MASK_LR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
398 {"sc.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
, MASK_SC_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
399 {"amoadd.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
, MASK_AMOADD_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
400 {"amoswap.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
401 {"amoand.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
, MASK_AMOAND_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
402 {"amoor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
, MASK_AMOOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
403 {"amoxor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
, MASK_AMOXOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
404 {"amomax.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
, MASK_AMOMAX_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
405 {"amomaxu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
406 {"amomin.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
, MASK_AMOMIN_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
407 {"amominu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
, MASK_AMOMINU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
408 {"lr.w.aq", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
| MASK_AQ
, MASK_LR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
409 {"sc.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
| MASK_AQ
, MASK_SC_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
410 {"amoadd.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
| MASK_AQ
, MASK_AMOADD_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
411 {"amoswap.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
| MASK_AQ
, MASK_AMOSWAP_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
412 {"amoand.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
| MASK_AQ
, MASK_AMOAND_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
413 {"amoor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
| MASK_AQ
, MASK_AMOOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
414 {"amoxor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
| MASK_AQ
, MASK_AMOXOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
415 {"amomax.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
| MASK_AQ
, MASK_AMOMAX_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
416 {"amomaxu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
| MASK_AQ
, MASK_AMOMAXU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
417 {"amomin.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
| MASK_AQ
, MASK_AMOMIN_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
418 {"amominu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
| MASK_AQ
, MASK_AMOMINU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
419 {"lr.w.rl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
| MASK_RL
, MASK_LR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
420 {"sc.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
| MASK_RL
, MASK_SC_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
421 {"amoadd.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
| MASK_RL
, MASK_AMOADD_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
422 {"amoswap.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
| MASK_RL
, MASK_AMOSWAP_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
423 {"amoand.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
| MASK_RL
, MASK_AMOAND_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
424 {"amoor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
| MASK_RL
, MASK_AMOOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
425 {"amoxor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
| MASK_RL
, MASK_AMOXOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
426 {"amomax.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
| MASK_RL
, MASK_AMOMAX_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
427 {"amomaxu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
| MASK_RL
, MASK_AMOMAXU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
428 {"amomin.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
| MASK_RL
, MASK_AMOMIN_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
429 {"amominu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
| MASK_RL
, MASK_AMOMINU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
430 {"lr.w.aqrl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
| MASK_AQRL
, MASK_LR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
431 {"sc.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
| MASK_AQRL
, MASK_SC_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
432 {"amoadd.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
| MASK_AQRL
, MASK_AMOADD_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
433 {"amoswap.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
| MASK_AQRL
, MASK_AMOSWAP_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
434 {"amoand.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
| MASK_AQRL
, MASK_AMOAND_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
435 {"amoor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
| MASK_AQRL
, MASK_AMOOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
436 {"amoxor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
| MASK_AQRL
, MASK_AMOXOR_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
437 {"amomax.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
| MASK_AQRL
, MASK_AMOMAX_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
438 {"amomaxu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
| MASK_AQRL
, MASK_AMOMAXU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
439 {"amomin.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
| MASK_AQRL
, MASK_AMOMIN_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
440 {"amominu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
| MASK_AQRL
, MASK_AMOMINU_W
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
441 {"lr.d", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
, MASK_LR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
442 {"sc.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
, MASK_SC_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
443 {"amoadd.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
, MASK_AMOADD_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
444 {"amoswap.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
445 {"amoand.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
, MASK_AMOAND_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
446 {"amoor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
, MASK_AMOOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
447 {"amoxor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
, MASK_AMOXOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
448 {"amomax.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
, MASK_AMOMAX_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
449 {"amomaxu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
450 {"amomin.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
, MASK_AMOMIN_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
451 {"amominu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
, MASK_AMOMINU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
452 {"lr.d.aq", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
| MASK_AQ
, MASK_LR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
453 {"sc.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
| MASK_AQ
, MASK_SC_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
454 {"amoadd.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
| MASK_AQ
, MASK_AMOADD_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
455 {"amoswap.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
| MASK_AQ
, MASK_AMOSWAP_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
456 {"amoand.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
| MASK_AQ
, MASK_AMOAND_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
457 {"amoor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
| MASK_AQ
, MASK_AMOOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
458 {"amoxor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
| MASK_AQ
, MASK_AMOXOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
459 {"amomax.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
| MASK_AQ
, MASK_AMOMAX_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
460 {"amomaxu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
| MASK_AQ
, MASK_AMOMAXU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
461 {"amomin.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
| MASK_AQ
, MASK_AMOMIN_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
462 {"amominu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
| MASK_AQ
, MASK_AMOMINU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
463 {"lr.d.rl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
| MASK_RL
, MASK_LR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
464 {"sc.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
| MASK_RL
, MASK_SC_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
465 {"amoadd.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
| MASK_RL
, MASK_AMOADD_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
466 {"amoswap.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
| MASK_RL
, MASK_AMOSWAP_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
467 {"amoand.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
| MASK_RL
, MASK_AMOAND_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
468 {"amoor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
| MASK_RL
, MASK_AMOOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
469 {"amoxor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
| MASK_RL
, MASK_AMOXOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
470 {"amomax.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
| MASK_RL
, MASK_AMOMAX_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
471 {"amomaxu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
| MASK_RL
, MASK_AMOMAXU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
472 {"amomin.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
| MASK_RL
, MASK_AMOMIN_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
473 {"amominu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
| MASK_RL
, MASK_AMOMINU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
474 {"lr.d.aqrl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
| MASK_AQRL
, MASK_LR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
475 {"sc.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
| MASK_AQRL
, MASK_SC_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
476 {"amoadd.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
| MASK_AQRL
, MASK_AMOADD_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
477 {"amoswap.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
| MASK_AQRL
, MASK_AMOSWAP_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
478 {"amoand.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
| MASK_AQRL
, MASK_AMOAND_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
479 {"amoor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
| MASK_AQRL
, MASK_AMOOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
480 {"amoxor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
| MASK_AQRL
, MASK_AMOXOR_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
481 {"amomax.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
| MASK_AQRL
, MASK_AMOMAX_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
482 {"amomaxu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
| MASK_AQRL
, MASK_AMOMAXU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
483 {"amomin.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
| MASK_AQRL
, MASK_AMOMIN_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
484 {"amominu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
| MASK_AQRL
, MASK_AMOMINU_D
| MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
486 /* Multiply/Divide instruction subset. */
487 {"mul", 0, INSN_CLASS_M
, "d,s,t", MATCH_MUL
, MASK_MUL
, match_opcode
, 0 },
488 {"mulh", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULH
, MASK_MULH
, match_opcode
, 0 },
489 {"mulhu", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULHU
, MASK_MULHU
, match_opcode
, 0 },
490 {"mulhsu", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULHSU
, MASK_MULHSU
, match_opcode
, 0 },
491 {"div", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIV
, MASK_DIV
, match_opcode
, 0 },
492 {"divu", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIVU
, MASK_DIVU
, match_opcode
, 0 },
493 {"rem", 0, INSN_CLASS_M
, "d,s,t", MATCH_REM
, MASK_REM
, match_opcode
, 0 },
494 {"remu", 0, INSN_CLASS_M
, "d,s,t", MATCH_REMU
, MASK_REMU
, match_opcode
, 0 },
495 {"mulw", 64, INSN_CLASS_M
, "d,s,t", MATCH_MULW
, MASK_MULW
, match_opcode
, 0 },
496 {"divw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVW
, MASK_DIVW
, match_opcode
, 0 },
497 {"divuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVUW
, MASK_DIVUW
, match_opcode
, 0 },
498 {"remw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMW
, MASK_REMW
, match_opcode
, 0 },
499 {"remuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMUW
, MASK_REMUW
, match_opcode
, 0 },
501 /* Bitmanip instruction subset - ZBA/ZBB/ZBC. */
502 {"sh1add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH1ADD
, MASK_SH1ADD
, match_opcode
, 0 },
503 {"sh2add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH2ADD
, MASK_SH2ADD
, match_opcode
, 0 },
504 {"sh3add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH3ADD
, MASK_SH3ADD
, match_opcode
, 0 },
505 {"sh1add.uw",64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH1ADD_UW
, MASK_SH1ADD_UW
, match_opcode
, 0 },
506 {"sh2add.uw",64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH2ADD_UW
, MASK_SH2ADD_UW
, match_opcode
, 0 },
507 {"sh3add.uw",64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH3ADD_UW
, MASK_SH3ADD_UW
, match_opcode
, 0 },
508 {"zext.w", 64, INSN_CLASS_ZBA_OR_ZBB
, "d,s", MATCH_ADD_UW
, MASK_ADD_UW
| MASK_RS2
, match_opcode
, INSN_ALIAS
},
509 {"zext.w", 64, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTW
, match_never
, INSN_MACRO
},
510 {"add.uw", 64, INSN_CLASS_ZBA
, "d,s,t", MATCH_ADD_UW
, MASK_ADD_UW
, match_opcode
, 0 },
511 {"slli.uw", 64, INSN_CLASS_ZBA
, "d,s,>", MATCH_SLLI_UW
, MASK_SLLI_UW
, match_opcode
, 0 },
513 {"clz", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CLZ
, MASK_CLZ
, match_opcode
, 0 },
514 {"ctz", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CTZ
, MASK_CTZ
, match_opcode
, 0 },
515 {"cpop", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CPOP
, MASK_CPOP
, match_opcode
, 0 },
516 {"min", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MIN
, MASK_MIN
, match_opcode
, 0 },
517 {"max", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MAX
, MASK_MAX
, match_opcode
, 0 },
518 {"minu", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MINU
, MASK_MINU
, match_opcode
, 0 },
519 {"maxu", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MAXU
, MASK_MAXU
, match_opcode
, 0 },
520 {"sext.b", 0, INSN_CLASS_ZBB
, "d,s", MATCH_SEXT_B
, MASK_SEXT_B
, match_opcode
, 0 },
521 {"sext.b", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTB
, match_never
, INSN_MACRO
},
522 {"sext.h", 0, INSN_CLASS_ZBB
, "d,s", MATCH_SEXT_H
, MASK_SEXT_H
, match_opcode
, 0 },
523 {"sext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTH
, match_never
, INSN_MACRO
},
524 {"zext.h", 32, INSN_CLASS_ZBB
, "d,s", MATCH_PACK
, MASK_PACK
| MASK_RS2
, match_opcode
, 0 },
525 {"zext.h", 64, INSN_CLASS_ZBB
, "d,s", MATCH_PACKW
, MASK_PACKW
| MASK_RS2
, match_opcode
, 0 },
526 {"zext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTH
, match_never
, INSN_MACRO
},
527 {"andn", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_ANDN
, MASK_ANDN
, match_opcode
, 0 },
528 {"orn", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_ORN
, MASK_ORN
, match_opcode
, 0 },
529 {"xnor", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_XNOR
, MASK_XNOR
, match_opcode
, 0 },
530 {"rori", 0, INSN_CLASS_ZBB
, "d,s,>", MATCH_RORI
, MASK_RORI
, match_opcode
, 0 },
531 {"ror", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_ROR
, MASK_ROR
, match_opcode
, 0 },
532 {"ror", 0, INSN_CLASS_ZBB
, "d,s,>", MATCH_RORI
, MASK_RORI
, match_opcode
, INSN_ALIAS
},
533 {"rol", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_ROL
, MASK_ROL
, match_opcode
, 0 },
534 {"clzw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CLZW
, MASK_CLZW
, match_opcode
, 0 },
535 {"ctzw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CTZW
, MASK_CTZW
, match_opcode
, 0 },
536 {"cpopw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CPOPW
, MASK_CPOPW
, match_opcode
, 0 },
537 {"roriw", 64, INSN_CLASS_ZBB
, "d,s,<", MATCH_RORIW
, MASK_RORIW
, match_opcode
, 0 },
538 {"rorw", 64, INSN_CLASS_ZBB
, "d,s,t", MATCH_RORW
, MASK_RORW
, match_opcode
, 0 },
539 {"rorw", 64, INSN_CLASS_ZBB
, "d,s,<", MATCH_RORIW
, MASK_RORIW
, match_opcode
, INSN_ALIAS
},
540 {"rolw", 64, INSN_CLASS_ZBB
, "d,s,t", MATCH_ROLW
, MASK_ROLW
, match_opcode
, 0 },
541 {"rev8", 32, INSN_CLASS_ZBB
, "d,s", MATCH_GREVI
| ENCODE_ITYPE_IMM (0x18), MASK_GREVI
| MASK_RVB_IMM
, match_opcode
, 0 },
542 {"rev8", 64, INSN_CLASS_ZBB
, "d,s", MATCH_GREVI
| ENCODE_ITYPE_IMM (0x38), MASK_GREVI
| MASK_RVB_IMM
, match_opcode
, 0 },
543 {"orc.b", 0, INSN_CLASS_ZBB
, "d,s", MATCH_GORCI
| ENCODE_ITYPE_IMM (0x7), MASK_GORCI
| MASK_RVB_IMM
, match_opcode
, 0 },
545 {"clmul", 0, INSN_CLASS_ZBC
, "d,s,t", MATCH_CLMUL
, MASK_CLMUL
, match_opcode
, 0 },
546 {"clmulh", 0, INSN_CLASS_ZBC
, "d,s,t", MATCH_CLMULH
, MASK_CLMULH
, match_opcode
, 0 },
547 {"clmulr", 0, INSN_CLASS_ZBC
, "d,s,t", MATCH_CLMULR
, MASK_CLMULR
, match_opcode
, 0 },
549 /* Single-precision floating-point instruction subset. */
550 {"frcsr", 0, INSN_CLASS_F
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
551 {"frsr", 0, INSN_CLASS_F
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
552 {"fscsr", 0, INSN_CLASS_F
, "s", MATCH_FSCSR
, MASK_FSCSR
| MASK_RD
, match_opcode
, INSN_ALIAS
},
553 {"fscsr", 0, INSN_CLASS_F
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
554 {"fssr", 0, INSN_CLASS_F
, "s", MATCH_FSCSR
, MASK_FSCSR
| MASK_RD
, match_opcode
, INSN_ALIAS
},
555 {"fssr", 0, INSN_CLASS_F
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
556 {"frrm", 0, INSN_CLASS_F
, "d", MATCH_FRRM
, MASK_FRRM
, match_opcode
, INSN_ALIAS
},
557 {"fsrm", 0, INSN_CLASS_F
, "s", MATCH_FSRM
, MASK_FSRM
| MASK_RD
, match_opcode
, INSN_ALIAS
},
558 {"fsrm", 0, INSN_CLASS_F
, "d,s", MATCH_FSRM
, MASK_FSRM
, match_opcode
, INSN_ALIAS
},
559 {"fsrmi", 0, INSN_CLASS_F
, "d,Z", MATCH_FSRMI
, MASK_FSRMI
, match_opcode
, INSN_ALIAS
},
560 {"fsrmi", 0, INSN_CLASS_F
, "Z", MATCH_FSRMI
, MASK_FSRMI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
561 {"frflags", 0, INSN_CLASS_F
, "d", MATCH_FRFLAGS
, MASK_FRFLAGS
, match_opcode
, INSN_ALIAS
},
562 {"fsflags", 0, INSN_CLASS_F
, "s", MATCH_FSFLAGS
, MASK_FSFLAGS
| MASK_RD
, match_opcode
, INSN_ALIAS
},
563 {"fsflags", 0, INSN_CLASS_F
, "d,s", MATCH_FSFLAGS
, MASK_FSFLAGS
, match_opcode
, INSN_ALIAS
},
564 {"fsflagsi", 0, INSN_CLASS_F
, "d,Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
, match_opcode
, INSN_ALIAS
},
565 {"fsflagsi", 0, INSN_CLASS_F
, "Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
566 {"flw", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
567 {"flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
568 {"flw", 0, INSN_CLASS_F
, "D,o(s)", MATCH_FLW
, MASK_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
569 {"flw", 0, INSN_CLASS_F
, "D,A,s", 0, (int) M_FLW
, match_never
, INSN_MACRO
},
570 {"fsw", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
571 {"fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
572 {"fsw", 0, INSN_CLASS_F
, "T,q(s)", MATCH_FSW
, MASK_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
573 {"fsw", 0, INSN_CLASS_F
, "T,A,s", 0, (int) M_FSW
, match_never
, INSN_MACRO
},
575 {"fmv.x.w", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
576 {"fmv.w.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
578 {"fmv.x.s", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
579 {"fmv.s.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
581 {"fmv.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
582 {"fneg.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
583 {"fabs.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
584 {"fsgnj.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_opcode
, 0 },
585 {"fsgnjn.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_opcode
, 0 },
586 {"fsgnjx.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_opcode
, 0 },
587 {"fadd.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FADD_S
| MASK_RM
, MASK_FADD_S
| MASK_RM
, match_opcode
, 0 },
588 {"fadd.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FADD_S
, MASK_FADD_S
, match_opcode
, 0 },
589 {"fsub.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSUB_S
| MASK_RM
, MASK_FSUB_S
| MASK_RM
, match_opcode
, 0 },
590 {"fsub.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FSUB_S
, MASK_FSUB_S
, match_opcode
, 0 },
591 {"fmul.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMUL_S
| MASK_RM
, MASK_FMUL_S
| MASK_RM
, match_opcode
, 0 },
592 {"fmul.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FMUL_S
, MASK_FMUL_S
, match_opcode
, 0 },
593 {"fdiv.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FDIV_S
| MASK_RM
, MASK_FDIV_S
| MASK_RM
, match_opcode
, 0 },
594 {"fdiv.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FDIV_S
, MASK_FDIV_S
, match_opcode
, 0 },
595 {"fsqrt.s", 0, INSN_CLASS_F
, "D,S", MATCH_FSQRT_S
| MASK_RM
, MASK_FSQRT_S
| MASK_RM
, match_opcode
, 0 },
596 {"fsqrt.s", 0, INSN_CLASS_F
, "D,S,m", MATCH_FSQRT_S
, MASK_FSQRT_S
, match_opcode
, 0 },
597 {"fmin.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMIN_S
, MASK_FMIN_S
, match_opcode
, 0 },
598 {"fmax.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMAX_S
, MASK_FMAX_S
, match_opcode
, 0 },
599 {"fmadd.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FMADD_S
| MASK_RM
, MASK_FMADD_S
| MASK_RM
, match_opcode
, 0 },
600 {"fmadd.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FMADD_S
, MASK_FMADD_S
, match_opcode
, 0 },
601 {"fnmadd.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FNMADD_S
| MASK_RM
, MASK_FNMADD_S
| MASK_RM
, match_opcode
, 0 },
602 {"fnmadd.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FNMADD_S
, MASK_FNMADD_S
, match_opcode
, 0 },
603 {"fmsub.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FMSUB_S
| MASK_RM
, MASK_FMSUB_S
| MASK_RM
, match_opcode
, 0 },
604 {"fmsub.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FMSUB_S
, MASK_FMSUB_S
, match_opcode
, 0 },
605 {"fnmsub.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FNMSUB_S
| MASK_RM
, MASK_FNMSUB_S
| MASK_RM
, match_opcode
, 0 },
606 {"fnmsub.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FNMSUB_S
, MASK_FNMSUB_S
, match_opcode
, 0 },
607 {"fcvt.w.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCVT_W_S
| MASK_RM
, MASK_FCVT_W_S
| MASK_RM
, match_opcode
, 0 },
608 {"fcvt.w.s", 0, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_W_S
, MASK_FCVT_W_S
, match_opcode
, 0 },
609 {"fcvt.wu.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCVT_WU_S
| MASK_RM
, MASK_FCVT_WU_S
| MASK_RM
, match_opcode
, 0 },
610 {"fcvt.wu.s", 0, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
, match_opcode
, 0 },
611 {"fcvt.s.w", 0, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_W
| MASK_RM
, MASK_FCVT_S_W
| MASK_RM
, match_opcode
, 0 },
612 {"fcvt.s.w", 0, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_W
, MASK_FCVT_S_W
, match_opcode
, 0 },
613 {"fcvt.s.wu", 0, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_WU
| MASK_RM
, MASK_FCVT_S_W
| MASK_RM
, match_opcode
, 0 },
614 {"fcvt.s.wu", 0, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
, match_opcode
, 0 },
615 {"fclass.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCLASS_S
, MASK_FCLASS_S
, match_opcode
, 0 },
616 {"feq.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FEQ_S
, MASK_FEQ_S
, match_opcode
, 0 },
617 {"flt.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
618 {"fle.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
619 {"fgt.s", 0, INSN_CLASS_F
, "d,T,S", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
620 {"fge.s", 0, INSN_CLASS_F
, "d,T,S", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
621 {"fcvt.l.s", 64, INSN_CLASS_F
, "d,S", MATCH_FCVT_L_S
| MASK_RM
, MASK_FCVT_L_S
| MASK_RM
, match_opcode
, 0 },
622 {"fcvt.l.s", 64, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_L_S
, MASK_FCVT_L_S
, match_opcode
, 0 },
623 {"fcvt.lu.s", 64, INSN_CLASS_F
, "d,S", MATCH_FCVT_LU_S
| MASK_RM
, MASK_FCVT_LU_S
| MASK_RM
, match_opcode
, 0 },
624 {"fcvt.lu.s", 64, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
, match_opcode
, 0 },
625 {"fcvt.s.l", 64, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_L
| MASK_RM
, MASK_FCVT_S_L
| MASK_RM
, match_opcode
, 0 },
626 {"fcvt.s.l", 64, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_L
, MASK_FCVT_S_L
, match_opcode
, 0 },
627 {"fcvt.s.lu", 64, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_LU
| MASK_RM
, MASK_FCVT_S_L
| MASK_RM
, match_opcode
, 0 },
628 {"fcvt.s.lu", 64, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
, match_opcode
, 0 },
630 /* Double-precision floating-point instruction subset. */
631 {"fld", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
632 {"fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
633 {"fld", 0, INSN_CLASS_D
, "D,o(s)", MATCH_FLD
, MASK_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
634 {"fld", 0, INSN_CLASS_D
, "D,A,s", 0, (int) M_FLD
, match_never
, INSN_MACRO
},
635 {"fsd", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
636 {"fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
637 {"fsd", 0, INSN_CLASS_D
, "T,q(s)", MATCH_FSD
, MASK_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
638 {"fsd", 0, INSN_CLASS_D
, "T,A,s", 0, (int) M_FSD
, match_never
, INSN_MACRO
},
639 {"fmv.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
640 {"fneg.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
641 {"fabs.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
642 {"fsgnj.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_opcode
, 0 },
643 {"fsgnjn.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_opcode
, 0 },
644 {"fsgnjx.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_opcode
, 0 },
645 {"fadd.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FADD_D
| MASK_RM
, MASK_FADD_D
| MASK_RM
, match_opcode
, 0 },
646 {"fadd.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FADD_D
, MASK_FADD_D
, match_opcode
, 0 },
647 {"fsub.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSUB_D
| MASK_RM
, MASK_FSUB_D
| MASK_RM
, match_opcode
, 0 },
648 {"fsub.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FSUB_D
, MASK_FSUB_D
, match_opcode
, 0 },
649 {"fmul.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMUL_D
| MASK_RM
, MASK_FMUL_D
| MASK_RM
, match_opcode
, 0 },
650 {"fmul.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FMUL_D
, MASK_FMUL_D
, match_opcode
, 0 },
651 {"fdiv.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FDIV_D
| MASK_RM
, MASK_FDIV_D
| MASK_RM
, match_opcode
, 0 },
652 {"fdiv.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FDIV_D
, MASK_FDIV_D
, match_opcode
, 0 },
653 {"fsqrt.d", 0, INSN_CLASS_D
, "D,S", MATCH_FSQRT_D
| MASK_RM
, MASK_FSQRT_D
| MASK_RM
, match_opcode
, 0 },
654 {"fsqrt.d", 0, INSN_CLASS_D
, "D,S,m", MATCH_FSQRT_D
, MASK_FSQRT_D
, match_opcode
, 0 },
655 {"fmin.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMIN_D
, MASK_FMIN_D
, match_opcode
, 0 },
656 {"fmax.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMAX_D
, MASK_FMAX_D
, match_opcode
, 0 },
657 {"fmadd.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FMADD_D
| MASK_RM
, MASK_FMADD_D
| MASK_RM
, match_opcode
, 0 },
658 {"fmadd.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FMADD_D
, MASK_FMADD_D
, match_opcode
, 0 },
659 {"fnmadd.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FNMADD_D
| MASK_RM
, MASK_FNMADD_D
| MASK_RM
, match_opcode
, 0 },
660 {"fnmadd.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FNMADD_D
, MASK_FNMADD_D
, match_opcode
, 0 },
661 {"fmsub.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FMSUB_D
| MASK_RM
, MASK_FMSUB_D
| MASK_RM
, match_opcode
, 0 },
662 {"fmsub.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FMSUB_D
, MASK_FMSUB_D
, match_opcode
, 0 },
663 {"fnmsub.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FNMSUB_D
| MASK_RM
, MASK_FNMSUB_D
| MASK_RM
, match_opcode
, 0 },
664 {"fnmsub.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FNMSUB_D
, MASK_FNMSUB_D
, match_opcode
, 0 },
665 {"fcvt.w.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCVT_W_D
| MASK_RM
, MASK_FCVT_W_D
| MASK_RM
, match_opcode
, 0 },
666 {"fcvt.w.d", 0, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_W_D
, MASK_FCVT_W_D
, match_opcode
, 0 },
667 {"fcvt.wu.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCVT_WU_D
| MASK_RM
, MASK_FCVT_WU_D
| MASK_RM
, match_opcode
, 0 },
668 {"fcvt.wu.d", 0, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
, match_opcode
, 0 },
669 {"fcvt.d.w", 0, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_W
, MASK_FCVT_D_W
| MASK_RM
, match_opcode
, 0 },
670 {"fcvt.d.wu", 0, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
| MASK_RM
, match_opcode
, 0 },
671 {"fcvt.d.s", 0, INSN_CLASS_D
, "D,S", MATCH_FCVT_D_S
, MASK_FCVT_D_S
| MASK_RM
, match_opcode
, 0 },
672 {"fcvt.s.d", 0, INSN_CLASS_D
, "D,S", MATCH_FCVT_S_D
| MASK_RM
, MASK_FCVT_S_D
| MASK_RM
, match_opcode
, 0 },
673 {"fcvt.s.d", 0, INSN_CLASS_D
, "D,S,m", MATCH_FCVT_S_D
, MASK_FCVT_S_D
, match_opcode
, 0 },
674 {"fclass.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCLASS_D
, MASK_FCLASS_D
, match_opcode
, 0 },
675 {"feq.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FEQ_D
, MASK_FEQ_D
, match_opcode
, 0 },
676 {"flt.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
677 {"fle.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
678 {"fgt.d", 0, INSN_CLASS_D
, "d,T,S", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
679 {"fge.d", 0, INSN_CLASS_D
, "d,T,S", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
680 {"fmv.x.d", 64, INSN_CLASS_D
, "d,S", MATCH_FMV_X_D
, MASK_FMV_X_D
, match_opcode
, 0 },
681 {"fmv.d.x", 64, INSN_CLASS_D
, "D,s", MATCH_FMV_D_X
, MASK_FMV_D_X
, match_opcode
, 0 },
682 {"fcvt.l.d", 64, INSN_CLASS_D
, "d,S", MATCH_FCVT_L_D
| MASK_RM
, MASK_FCVT_L_D
| MASK_RM
, match_opcode
, 0 },
683 {"fcvt.l.d", 64, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_L_D
, MASK_FCVT_L_D
, match_opcode
, 0 },
684 {"fcvt.lu.d", 64, INSN_CLASS_D
, "d,S", MATCH_FCVT_LU_D
| MASK_RM
, MASK_FCVT_LU_D
| MASK_RM
, match_opcode
, 0 },
685 {"fcvt.lu.d", 64, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
, match_opcode
, 0 },
686 {"fcvt.d.l", 64, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_L
| MASK_RM
, MASK_FCVT_D_L
| MASK_RM
, match_opcode
, 0 },
687 {"fcvt.d.l", 64, INSN_CLASS_D
, "D,s,m", MATCH_FCVT_D_L
, MASK_FCVT_D_L
, match_opcode
, 0 },
688 {"fcvt.d.lu", 64, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_LU
| MASK_RM
, MASK_FCVT_D_L
| MASK_RM
, match_opcode
, 0 },
689 {"fcvt.d.lu", 64, INSN_CLASS_D
, "D,s,m", MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
, match_opcode
, 0 },
691 /* Quad-precision floating-point instruction subset. */
692 {"flq", 0, INSN_CLASS_Q
, "D,o(s)", MATCH_FLQ
, MASK_FLQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
693 {"flq", 0, INSN_CLASS_Q
, "D,A,s", 0, (int) M_FLQ
, match_never
, INSN_MACRO
},
694 {"fsq", 0, INSN_CLASS_Q
, "T,q(s)", MATCH_FSQ
, MASK_FSQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
695 {"fsq", 0, INSN_CLASS_Q
, "T,A,s", 0, (int) M_FSQ
, match_never
, INSN_MACRO
},
696 {"fmv.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
697 {"fneg.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
698 {"fabs.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
699 {"fsgnj.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_opcode
, 0 },
700 {"fsgnjn.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_opcode
, 0 },
701 {"fsgnjx.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_opcode
, 0 },
702 {"fadd.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FADD_Q
| MASK_RM
, MASK_FADD_Q
| MASK_RM
, match_opcode
, 0 },
703 {"fadd.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FADD_Q
, MASK_FADD_Q
, match_opcode
, 0 },
704 {"fsub.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSUB_Q
| MASK_RM
, MASK_FSUB_Q
| MASK_RM
, match_opcode
, 0 },
705 {"fsub.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FSUB_Q
, MASK_FSUB_Q
, match_opcode
, 0 },
706 {"fmul.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMUL_Q
| MASK_RM
, MASK_FMUL_Q
| MASK_RM
, match_opcode
, 0 },
707 {"fmul.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FMUL_Q
, MASK_FMUL_Q
, match_opcode
, 0 },
708 {"fdiv.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FDIV_Q
| MASK_RM
, MASK_FDIV_Q
| MASK_RM
, match_opcode
, 0 },
709 {"fdiv.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FDIV_Q
, MASK_FDIV_Q
, match_opcode
, 0 },
710 {"fsqrt.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FSQRT_Q
| MASK_RM
, MASK_FSQRT_Q
| MASK_RM
, match_opcode
, 0 },
711 {"fsqrt.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FSQRT_Q
, MASK_FSQRT_Q
, match_opcode
, 0 },
712 {"fmin.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMIN_Q
, MASK_FMIN_Q
, match_opcode
, 0 },
713 {"fmax.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMAX_Q
, MASK_FMAX_Q
, match_opcode
, 0 },
714 {"fmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FMADD_Q
| MASK_RM
, MASK_FMADD_Q
| MASK_RM
, match_opcode
, 0 },
715 {"fmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FMADD_Q
, MASK_FMADD_Q
, match_opcode
, 0 },
716 {"fnmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FNMADD_Q
| MASK_RM
, MASK_FNMADD_Q
| MASK_RM
, match_opcode
, 0 },
717 {"fnmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FNMADD_Q
, MASK_FNMADD_Q
, match_opcode
, 0 },
718 {"fmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FMSUB_Q
| MASK_RM
, MASK_FMSUB_Q
| MASK_RM
, match_opcode
, 0 },
719 {"fmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FMSUB_Q
, MASK_FMSUB_Q
, match_opcode
, 0 },
720 {"fnmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FNMSUB_Q
| MASK_RM
, MASK_FNMSUB_Q
| MASK_RM
, match_opcode
, 0 },
721 {"fnmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FNMSUB_Q
, MASK_FNMSUB_Q
, match_opcode
, 0 },
722 {"fcvt.w.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCVT_W_Q
| MASK_RM
, MASK_FCVT_W_Q
| MASK_RM
, match_opcode
, 0 },
723 {"fcvt.w.q", 0, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_W_Q
, MASK_FCVT_W_Q
, match_opcode
, 0 },
724 {"fcvt.wu.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCVT_WU_Q
| MASK_RM
, MASK_FCVT_WU_Q
| MASK_RM
, match_opcode
, 0 },
725 {"fcvt.wu.q", 0, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_WU_Q
, MASK_FCVT_WU_Q
, match_opcode
, 0 },
726 {"fcvt.q.w", 0, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_W
, MASK_FCVT_Q_W
| MASK_RM
, match_opcode
, 0 },
727 {"fcvt.q.wu", 0, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_WU
, MASK_FCVT_Q_WU
| MASK_RM
, match_opcode
, 0 },
728 {"fcvt.q.s", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_Q_S
, MASK_FCVT_Q_S
| MASK_RM
, match_opcode
, 0 },
729 {"fcvt.q.d", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_Q_D
, MASK_FCVT_Q_D
| MASK_RM
, match_opcode
, 0 },
730 {"fcvt.s.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_S_Q
| MASK_RM
, MASK_FCVT_S_Q
| MASK_RM
, match_opcode
, 0 },
731 {"fcvt.s.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FCVT_S_Q
, MASK_FCVT_S_Q
, match_opcode
, 0 },
732 {"fcvt.d.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_D_Q
| MASK_RM
, MASK_FCVT_D_Q
| MASK_RM
, match_opcode
, 0 },
733 {"fcvt.d.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FCVT_D_Q
, MASK_FCVT_D_Q
, match_opcode
, 0 },
734 {"fclass.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCLASS_Q
, MASK_FCLASS_Q
, match_opcode
, 0 },
735 {"feq.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FEQ_Q
, MASK_FEQ_Q
, match_opcode
, 0 },
736 {"flt.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
737 {"fle.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
738 {"fgt.q", 0, INSN_CLASS_Q
, "d,T,S", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
739 {"fge.q", 0, INSN_CLASS_Q
, "d,T,S", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
740 {"fmv.x.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FMV_X_Q
, MASK_FMV_X_Q
, match_opcode
, 0 },
741 {"fmv.q.x", 64, INSN_CLASS_Q
, "D,s", MATCH_FMV_Q_X
, MASK_FMV_Q_X
, match_opcode
, 0 },
742 {"fcvt.l.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FCVT_L_Q
| MASK_RM
, MASK_FCVT_L_Q
| MASK_RM
, match_opcode
, 0 },
743 {"fcvt.l.q", 64, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_L_Q
, MASK_FCVT_L_Q
, match_opcode
, 0 },
744 {"fcvt.lu.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FCVT_LU_Q
| MASK_RM
, MASK_FCVT_LU_Q
| MASK_RM
, match_opcode
, 0 },
745 {"fcvt.lu.q", 64, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_LU_Q
, MASK_FCVT_LU_Q
, match_opcode
, 0 },
746 {"fcvt.q.l", 64, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_L
| MASK_RM
, MASK_FCVT_Q_L
| MASK_RM
, match_opcode
, 0 },
747 {"fcvt.q.l", 64, INSN_CLASS_Q
, "D,s,m", MATCH_FCVT_Q_L
, MASK_FCVT_Q_L
, match_opcode
, 0 },
748 {"fcvt.q.lu", 64, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_LU
| MASK_RM
, MASK_FCVT_Q_L
| MASK_RM
, match_opcode
, 0 },
749 {"fcvt.q.lu", 64, INSN_CLASS_Q
, "D,s,m", MATCH_FCVT_Q_LU
, MASK_FCVT_Q_LU
, match_opcode
, 0 },
751 /* Compressed instructions. */
752 {"c.unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, 0 },
753 {"c.ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, 0 },
754 {"c.jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_BRANCH
},
755 {"c.jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_JSR
},
756 {"c.j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_BRANCH
},
757 {"c.jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_JSR
},
758 {"c.beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_CONDBRANCH
},
759 {"c.bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_CONDBRANCH
},
760 {"c.lwsp", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, 0 },
761 {"c.lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
762 {"c.swsp", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
763 {"c.sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
764 {"c.nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
765 {"c.nop", 0, INSN_CLASS_C
, "Cj", MATCH_C_ADDI
, MASK_C_ADDI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
766 {"c.mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add_with_hint
, 0 },
767 {"c.lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui_with_hint
, 0 },
768 {"c.li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_opcode
, 0 },
769 {"c.addi4spn", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, 0 },
770 {"c.addi16sp", 0, INSN_CLASS_C
, "Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, 0 },
771 {"c.addi", 0, INSN_CLASS_C
, "d,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_opcode
, 0 },
772 {"c.add", 0, INSN_CLASS_C
, "d,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add_with_hint
, 0 },
773 {"c.sub", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, 0 },
774 {"c.and", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, 0 },
775 {"c.or", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, 0 },
776 {"c.xor", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, 0 },
777 {"c.slli", 0, INSN_CLASS_C
, "d,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_c_slli
, 0 },
778 {"c.srli", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_c_slli
, 0 },
779 {"c.srai", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_c_slli
, 0 },
780 {"c.slli64", 0, INSN_CLASS_C
, "d", MATCH_C_SLLI64
, MASK_C_SLLI64
, match_c_slli64
, 0 },
781 {"c.srli64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRLI64
, MASK_C_SRLI64
, match_c_slli64
, 0 },
782 {"c.srai64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRAI64
, MASK_C_SRAI64
, match_c_slli64
, 0 },
783 {"c.andi", 0, INSN_CLASS_C
, "Cs,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, 0 },
784 {"c.addiw", 64, INSN_CLASS_C
, "d,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, 0 },
785 {"c.addw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, 0 },
786 {"c.subw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, 0 },
787 {"c.ldsp", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_DREF
|INSN_8_BYTE
},
788 {"c.ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
789 {"c.sdsp", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
790 {"c.sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
791 {"c.fldsp", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
792 {"c.fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
793 {"c.fsdsp", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
794 {"c.fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
795 {"c.flwsp", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
796 {"c.flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
797 {"c.fswsp", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
798 {"c.fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
800 /* Supervisor instructions. */
801 {"csrr", 0, INSN_CLASS_ZICSR
, "d,E", MATCH_CSRRS
, MASK_CSRRS
| MASK_RS1
, match_opcode
, INSN_ALIAS
},
802 {"csrwi", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRWI
, MASK_CSRRWI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
803 {"csrsi", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRSI
, MASK_CSRRSI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
804 {"csrci", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRCI
, MASK_CSRRCI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
805 {"csrw", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRW
, MASK_CSRRW
| MASK_RD
, match_opcode
, INSN_ALIAS
},
806 {"csrw", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRWI
, MASK_CSRRWI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
807 {"csrs", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRS
, MASK_CSRRS
| MASK_RD
, match_opcode
, INSN_ALIAS
},
808 {"csrs", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRSI
, MASK_CSRRSI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
809 {"csrc", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRC
, MASK_CSRRC
| MASK_RD
, match_opcode
, INSN_ALIAS
},
810 {"csrc", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRCI
, MASK_CSRRCI
| MASK_RD
, match_opcode
, INSN_ALIAS
},
811 {"csrrwi", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, 0 },
812 {"csrrsi", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, 0 },
813 {"csrrci", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, 0 },
814 {"csrrw", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRW
, MASK_CSRRW
, match_opcode
, 0 },
815 {"csrrw", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, INSN_ALIAS
},
816 {"csrrs", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRS
, MASK_CSRRS
, match_opcode
, 0 },
817 {"csrrs", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, INSN_ALIAS
},
818 {"csrrc", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRC
, MASK_CSRRC
, match_opcode
, 0 },
819 {"csrrc", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, INSN_ALIAS
},
820 {"uret", 0, INSN_CLASS_I
, "", MATCH_URET
, MASK_URET
, match_opcode
, 0 },
821 {"sret", 0, INSN_CLASS_I
, "", MATCH_SRET
, MASK_SRET
, match_opcode
, 0 },
822 {"hret", 0, INSN_CLASS_I
, "", MATCH_HRET
, MASK_HRET
, match_opcode
, 0 },
823 {"mret", 0, INSN_CLASS_I
, "", MATCH_MRET
, MASK_MRET
, match_opcode
, 0 },
824 {"dret", 0, INSN_CLASS_I
, "", MATCH_DRET
, MASK_DRET
, match_opcode
, 0 },
825 {"sfence.vm", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VM
, MASK_SFENCE_VM
| MASK_RS1
, match_opcode
, 0 },
826 {"sfence.vm", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VM
, MASK_SFENCE_VM
, match_opcode
, 0 },
827 {"sfence.vma", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
| MASK_RS1
| MASK_RS2
, match_opcode
, INSN_ALIAS
},
828 {"sfence.vma", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
| MASK_RS2
, match_opcode
, INSN_ALIAS
},
829 {"sfence.vma", 0, INSN_CLASS_I
, "s,t", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
, match_opcode
, 0 },
830 {"wfi", 0, INSN_CLASS_I
, "", MATCH_WFI
, MASK_WFI
, match_opcode
, 0 },
832 /* Terminate the list. */
833 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}
836 /* Instruction format for .insn directive. */
837 const struct riscv_opcode riscv_insn_types
[] =
839 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
840 {"r", 0, INSN_CLASS_I
, "O4,F3,F7,d,s,t", 0, 0, match_opcode
, 0 },
841 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,t", 0, 0, match_opcode
, 0 },
842 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,t", 0, 0, match_opcode
, 0 },
843 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,t", 0, 0, match_opcode
, 0 },
844 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,s,T", 0, 0, match_opcode
, 0 },
845 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,T", 0, 0, match_opcode
, 0 },
846 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,T", 0, 0, match_opcode
, 0 },
847 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,T", 0, 0, match_opcode
, 0 },
849 {"r", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
850 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
851 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
852 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
853 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
854 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
855 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
856 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
857 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
858 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
859 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
860 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
861 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
862 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
863 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
864 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
866 {"r4", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
867 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
868 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
869 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
870 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
871 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
872 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
873 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
874 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
875 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
876 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
877 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
878 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
879 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
880 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
881 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
883 {"i", 0, INSN_CLASS_I
, "O4,F3,d,s,j", 0, 0, match_opcode
, 0 },
884 {"i", 0, INSN_CLASS_F
, "O4,F3,D,s,j", 0, 0, match_opcode
, 0 },
885 {"i", 0, INSN_CLASS_F
, "O4,F3,d,S,j", 0, 0, match_opcode
, 0 },
886 {"i", 0, INSN_CLASS_F
, "O4,F3,D,S,j", 0, 0, match_opcode
, 0 },
888 {"i", 0, INSN_CLASS_I
, "O4,F3,d,o(s)", 0, 0, match_opcode
, 0 },
889 {"i", 0, INSN_CLASS_F
, "O4,F3,D,o(s)", 0, 0, match_opcode
, 0 },
891 {"s", 0, INSN_CLASS_I
, "O4,F3,t,q(s)", 0, 0, match_opcode
, 0 },
892 {"s", 0, INSN_CLASS_F
, "O4,F3,T,q(s)", 0, 0, match_opcode
, 0 },
894 {"sb", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
895 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
896 {"sb", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
897 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
899 {"b", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
900 {"b", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
901 {"b", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
902 {"b", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
904 {"u", 0, INSN_CLASS_I
, "O4,d,u", 0, 0, match_opcode
, 0 },
905 {"u", 0, INSN_CLASS_F
, "O4,D,u", 0, 0, match_opcode
, 0 },
907 {"uj", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
908 {"uj", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
910 {"j", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
911 {"j", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
913 {"cr", 0, INSN_CLASS_C
, "O2,CF4,d,CV", 0, 0, match_opcode
, 0 },
914 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CV", 0, 0, match_opcode
, 0 },
915 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,d,CT", 0, 0, match_opcode
, 0 },
916 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CT", 0, 0, match_opcode
, 0 },
918 {"ci", 0, INSN_CLASS_C
, "O2,CF3,d,Co", 0, 0, match_opcode
, 0 },
919 {"ci", 0, INSN_CLASS_F_AND_C
, "O2,CF3,D,Co", 0, 0, match_opcode
, 0 },
921 {"ciw", 0, INSN_CLASS_C
, "O2,CF3,Ct,C8", 0, 0, match_opcode
, 0 },
922 {"ciw", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C8", 0, 0, match_opcode
, 0 },
924 {"ca", 0, INSN_CLASS_C
, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode
, 0 },
925 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode
, 0 },
926 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode
, 0 },
927 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode
, 0 },
929 {"cb", 0, INSN_CLASS_C
, "O2,CF3,Cs,Cp", 0, 0, match_opcode
, 0 },
930 {"cb", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CS,Cp", 0, 0, match_opcode
, 0 },
932 {"cj", 0, INSN_CLASS_C
, "O2,CF3,Ca", 0, 0, match_opcode
, 0 },
934 /* Terminate the list. */
935 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}
938 /* All standard extensions defined in all supported ISA spec. */
939 const struct riscv_ext_version riscv_ext_version_table
[] =
941 /* name, ISA spec, major version, minor version. */
942 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
943 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
944 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
946 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
947 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
948 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
950 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
951 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
952 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
954 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
955 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
956 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
958 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
959 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
960 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
962 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
963 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
964 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
966 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
967 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
968 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
970 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
971 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
972 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
974 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
975 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
977 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
978 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
980 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
982 {"zba", ISA_SPEC_CLASS_DRAFT
, 0, 93},
983 {"zbb", ISA_SPEC_CLASS_DRAFT
, 0, 93},
984 {"zbc", ISA_SPEC_CLASS_DRAFT
, 0, 93},
986 /* Terminate the list. */
993 enum riscv_isa_spec_class
class;
996 /* List for all supported ISA spec versions. */
997 static const struct isa_spec_t isa_specs
[] =
999 {"2.2", ISA_SPEC_CLASS_2P2
},
1000 {"20190608", ISA_SPEC_CLASS_20190608
},
1001 {"20191213", ISA_SPEC_CLASS_20191213
},
1003 /* Terminate the list. */
1007 /* Get the corresponding ISA spec class by giving a ISA spec string. */
1010 riscv_get_isa_spec_class (const char *s
,
1011 enum riscv_isa_spec_class
*class)
1013 const struct isa_spec_t
*version
;
1018 for (version
= &isa_specs
[0]; version
->name
!= NULL
; ++version
)
1019 if (strcmp (version
->name
, s
) == 0)
1021 *class = version
->class;
1025 /* Can not find the supported ISA spec. */