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Increase the accuracy of sparc instruction aliases.
[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c
1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2012
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <stdio.h>
25 #include "opcode/sparc.h"
26 #include "dis-asm.h"
27 #include "libiberty.h"
28 #include "opintl.h"
29
30 /* Bitmask of v9 architectures. */
31 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
32 | (1 << SPARC_OPCODE_ARCH_V9A) \
33 | (1 << SPARC_OPCODE_ARCH_V9B))
34 /* 1 if INSN is for v9 only. */
35 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
36 /* 1 if INSN is for v9. */
37 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
38
39 /* The sorted opcode table. */
40 static const sparc_opcode **sorted_opcodes;
41
42 /* For faster lookup, after insns are sorted they are hashed. */
43 /* ??? I think there is room for even more improvement. */
44
45 #define HASH_SIZE 256
46 /* It is important that we only look at insn code bits as that is how the
47 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
48 of the main types (0,1,2,3). */
49 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
50 #define HASH_INSN(INSN) \
51 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
52 typedef struct sparc_opcode_hash
53 {
54 struct sparc_opcode_hash *next;
55 const sparc_opcode *opcode;
56 } sparc_opcode_hash;
57
58 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
59
60 /* Sign-extend a value which is N bits long. */
61 #define SEX(value, bits) \
62 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
63 >> ((8 * sizeof (int)) - bits) )
64
65 static char *reg_names[] =
66 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
67 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
68 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
69 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
70 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
71 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
72 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
73 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
74 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
75 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
76 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
77 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
78 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
79 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
80 };
81
82 #define freg_names (&reg_names[4 * 8])
83
84 /* These are ordered according to there register number in
85 rdpr and wrpr insns. */
86 static char *v9_priv_reg_names[] =
87 {
88 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
89 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
90 "wstate", "fq", "gl"
91 /* "ver" - special cased */
92 };
93
94 /* These are ordered according to there register number in
95 rdhpr and wrhpr insns. */
96 static char *v9_hpriv_reg_names[] =
97 {
98 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
99 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
100 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
101 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
102 "resv28", "resv29", "resv30", "hstick_cmpr"
103 };
104
105 /* These are ordered according to there register number in
106 rd and wr insns (-16). */
107 static char *v9a_asr_reg_names[] =
108 {
109 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
110 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
111 "pause", "cps"
112 };
113
114 /* Macros used to extract instruction fields. Not all fields have
115 macros defined here, only those which are actually used. */
116
117 #define X_RD(i) (((i) >> 25) & 0x1f)
118 #define X_RS1(i) (((i) >> 14) & 0x1f)
119 #define X_LDST_I(i) (((i) >> 13) & 1)
120 #define X_ASI(i) (((i) >> 5) & 0xff)
121 #define X_RS2(i) (((i) >> 0) & 0x1f)
122 #define X_RS3(i) (((i) >> 9) & 0x1f)
123 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
124 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
125 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
126 #define X_IMM22(i) X_DISP22 (i)
127 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
128
129 /* These are for v9. */
130 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
131 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
132 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
133 #define X_MEMBAR(i) ((i) & 0x7f)
134
135 /* Here is the union which was used to extract instruction fields
136 before the shift and mask macros were written.
137
138 union sparc_insn
139 {
140 unsigned long int code;
141 struct
142 {
143 unsigned int anop:2;
144 #define op ldst.anop
145 unsigned int anrd:5;
146 #define rd ldst.anrd
147 unsigned int op3:6;
148 unsigned int anrs1:5;
149 #define rs1 ldst.anrs1
150 unsigned int i:1;
151 unsigned int anasi:8;
152 #define asi ldst.anasi
153 unsigned int anrs2:5;
154 #define rs2 ldst.anrs2
155 #define shcnt rs2
156 } ldst;
157 struct
158 {
159 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
160 unsigned int IMM13:13;
161 #define imm13 IMM13.IMM13
162 } IMM13;
163 struct
164 {
165 unsigned int anop:2;
166 unsigned int a:1;
167 unsigned int cond:4;
168 unsigned int op2:3;
169 unsigned int DISP22:22;
170 #define disp22 branch.DISP22
171 #define imm22 disp22
172 } branch;
173 struct
174 {
175 unsigned int anop:2;
176 unsigned int a:1;
177 unsigned int z:1;
178 unsigned int rcond:3;
179 unsigned int op2:3;
180 unsigned int DISP16HI:2;
181 unsigned int p:1;
182 unsigned int _rs1:5;
183 unsigned int DISP16LO:14;
184 } branch16;
185 struct
186 {
187 unsigned int anop:2;
188 unsigned int adisp30:30;
189 #define disp30 call.adisp30
190 } call;
191 }; */
192
193 /* Nonzero if INSN is the opcode for a delayed branch. */
194
195 static int
196 is_delayed_branch (unsigned long insn)
197 {
198 sparc_opcode_hash *op;
199
200 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
201 {
202 const sparc_opcode *opcode = op->opcode;
203
204 if ((opcode->match & insn) == opcode->match
205 && (opcode->lose & insn) == 0)
206 return opcode->flags & F_DELAYED;
207 }
208 return 0;
209 }
210
211 /* extern void qsort (); */
212
213 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
214 to compare_opcodes. */
215 static unsigned int current_arch_mask;
216
217 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
218
219 static int
220 compute_arch_mask (unsigned long mach)
221 {
222 switch (mach)
223 {
224 case 0 :
225 case bfd_mach_sparc :
226 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
227 case bfd_mach_sparc_sparclet :
228 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
229 case bfd_mach_sparc_sparclite :
230 case bfd_mach_sparc_sparclite_le :
231 /* sparclites insns are recognized by default (because that's how
232 they've always been treated, for better or worse). Kludge this by
233 indicating generic v8 is also selected. */
234 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
235 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
236 case bfd_mach_sparc_v8plus :
237 case bfd_mach_sparc_v9 :
238 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
239 case bfd_mach_sparc_v8plusa :
240 case bfd_mach_sparc_v9a :
241 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
242 case bfd_mach_sparc_v8plusb :
243 case bfd_mach_sparc_v9b :
244 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
245 }
246 abort ();
247 }
248
249 /* Compare opcodes A and B. */
250
251 static int
252 compare_opcodes (const void * a, const void * b)
253 {
254 sparc_opcode *op0 = * (sparc_opcode **) a;
255 sparc_opcode *op1 = * (sparc_opcode **) b;
256 unsigned long int match0 = op0->match, match1 = op1->match;
257 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
258 register unsigned int i;
259
260 /* If one (and only one) insn isn't supported by the current architecture,
261 prefer the one that is. If neither are supported, but they're both for
262 the same architecture, continue processing. Otherwise (both unsupported
263 and for different architectures), prefer lower numbered arch's (fudged
264 by comparing the bitmasks). */
265 if (op0->architecture & current_arch_mask)
266 {
267 if (! (op1->architecture & current_arch_mask))
268 return -1;
269 }
270 else
271 {
272 if (op1->architecture & current_arch_mask)
273 return 1;
274 else if (op0->architecture != op1->architecture)
275 return op0->architecture - op1->architecture;
276 }
277
278 /* If a bit is set in both match and lose, there is something
279 wrong with the opcode table. */
280 if (match0 & lose0)
281 {
282 fprintf
283 (stderr,
284 /* xgettext:c-format */
285 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
286 op0->name, match0, lose0);
287 op0->lose &= ~op0->match;
288 lose0 = op0->lose;
289 }
290
291 if (match1 & lose1)
292 {
293 fprintf
294 (stderr,
295 /* xgettext:c-format */
296 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
297 op1->name, match1, lose1);
298 op1->lose &= ~op1->match;
299 lose1 = op1->lose;
300 }
301
302 /* Because the bits that are variable in one opcode are constant in
303 another, it is important to order the opcodes in the right order. */
304 for (i = 0; i < 32; ++i)
305 {
306 unsigned long int x = 1 << i;
307 int x0 = (match0 & x) != 0;
308 int x1 = (match1 & x) != 0;
309
310 if (x0 != x1)
311 return x1 - x0;
312 }
313
314 for (i = 0; i < 32; ++i)
315 {
316 unsigned long int x = 1 << i;
317 int x0 = (lose0 & x) != 0;
318 int x1 = (lose1 & x) != 0;
319
320 if (x0 != x1)
321 return x1 - x0;
322 }
323
324 /* They are functionally equal. So as long as the opcode table is
325 valid, we can put whichever one first we want, on aesthetic grounds. */
326
327 /* Our first aesthetic ground is that aliases defer to real insns. */
328 {
329 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
330
331 if (alias_diff != 0)
332 /* Put the one that isn't an alias first. */
333 return alias_diff;
334 }
335
336 /* Except for aliases, two "identical" instructions had
337 better have the same opcode. This is a sanity check on the table. */
338 i = strcmp (op0->name, op1->name);
339 if (i)
340 {
341 if (op0->flags & F_ALIAS)
342 {
343 if (op0->flags & F_PREFERRED)
344 return -1;
345 if (op1->flags & F_PREFERRED)
346 return 1;
347
348 /* If they're both aliases, and neither is marked as preferred,
349 be arbitrary. */
350 return i;
351 }
352 else
353 fprintf (stderr,
354 /* xgettext:c-format */
355 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
356 op0->name, op1->name);
357 }
358
359 /* Fewer arguments are preferred. */
360 {
361 int length_diff = strlen (op0->args) - strlen (op1->args);
362
363 if (length_diff != 0)
364 /* Put the one with fewer arguments first. */
365 return length_diff;
366 }
367
368 /* Put 1+i before i+1. */
369 {
370 char *p0 = (char *) strchr (op0->args, '+');
371 char *p1 = (char *) strchr (op1->args, '+');
372
373 if (p0 && p1)
374 {
375 /* There is a plus in both operands. Note that a plus
376 sign cannot be the first character in args,
377 so the following [-1]'s are valid. */
378 if (p0[-1] == 'i' && p1[1] == 'i')
379 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
380 return 1;
381 if (p0[1] == 'i' && p1[-1] == 'i')
382 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
383 return -1;
384 }
385 }
386
387 /* Put 1,i before i,1. */
388 {
389 int i0 = strncmp (op0->args, "i,1", 3) == 0;
390 int i1 = strncmp (op1->args, "i,1", 3) == 0;
391
392 if (i0 ^ i1)
393 return i0 - i1;
394 }
395
396 /* They are, as far as we can tell, identical.
397 Since qsort may have rearranged the table partially, there is
398 no way to tell which one was first in the opcode table as
399 written, so just say there are equal. */
400 /* ??? This is no longer true now that we sort a vector of pointers,
401 not the table itself. */
402 return 0;
403 }
404
405 /* Build a hash table from the opcode table.
406 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
407
408 static void
409 build_hash_table (const sparc_opcode **opcode_table,
410 sparc_opcode_hash **hash_table,
411 int num_opcodes)
412 {
413 int i;
414 int hash_count[HASH_SIZE];
415 static sparc_opcode_hash *hash_buf = NULL;
416
417 /* Start at the end of the table and work backwards so that each
418 chain is sorted. */
419
420 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
421 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
422 if (hash_buf != NULL)
423 free (hash_buf);
424 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
425 for (i = num_opcodes - 1; i >= 0; --i)
426 {
427 int hash = HASH_INSN (opcode_table[i]->match);
428 sparc_opcode_hash *h = &hash_buf[i];
429
430 h->next = hash_table[hash];
431 h->opcode = opcode_table[i];
432 hash_table[hash] = h;
433 ++hash_count[hash];
434 }
435
436 #if 0 /* for debugging */
437 {
438 int min_count = num_opcodes, max_count = 0;
439 int total;
440
441 for (i = 0; i < HASH_SIZE; ++i)
442 {
443 if (hash_count[i] < min_count)
444 min_count = hash_count[i];
445 if (hash_count[i] > max_count)
446 max_count = hash_count[i];
447 total += hash_count[i];
448 }
449
450 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
451 min_count, max_count, (double) total / HASH_SIZE);
452 }
453 #endif
454 }
455
456 /* Print one instruction from MEMADDR on INFO->STREAM.
457
458 We suffix the instruction with a comment that gives the absolute
459 address involved, as well as its symbolic form, if the instruction
460 is preceded by a findable `sethi' and it either adds an immediate
461 displacement to that register, or it is an `add' or `or' instruction
462 on that register. */
463
464 int
465 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
466 {
467 FILE *stream = info->stream;
468 bfd_byte buffer[4];
469 unsigned long insn;
470 sparc_opcode_hash *op;
471 /* Nonzero of opcode table has been initialized. */
472 static int opcodes_initialized = 0;
473 /* bfd mach number of last call. */
474 static unsigned long current_mach = 0;
475 bfd_vma (*getword) (const void *);
476
477 if (!opcodes_initialized
478 || info->mach != current_mach)
479 {
480 int i;
481
482 current_arch_mask = compute_arch_mask (info->mach);
483
484 if (!opcodes_initialized)
485 sorted_opcodes =
486 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
487 /* Reset the sorted table so we can resort it. */
488 for (i = 0; i < sparc_num_opcodes; ++i)
489 sorted_opcodes[i] = &sparc_opcodes[i];
490 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
491 sizeof (sorted_opcodes[0]), compare_opcodes);
492
493 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
494 current_mach = info->mach;
495 opcodes_initialized = 1;
496 }
497
498 {
499 int status =
500 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
501
502 if (status != 0)
503 {
504 (*info->memory_error_func) (status, memaddr, info);
505 return -1;
506 }
507 }
508
509 /* On SPARClite variants such as DANlite (sparc86x), instructions
510 are always big-endian even when the machine is in little-endian mode. */
511 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
512 getword = bfd_getb32;
513 else
514 getword = bfd_getl32;
515
516 insn = getword (buffer);
517
518 info->insn_info_valid = 1; /* We do return this info. */
519 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
520 info->branch_delay_insns = 0; /* Assume no delay. */
521 info->target = 0; /* Assume no target known. */
522
523 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
524 {
525 const sparc_opcode *opcode = op->opcode;
526
527 /* If the insn isn't supported by the current architecture, skip it. */
528 if (! (opcode->architecture & current_arch_mask))
529 continue;
530
531 if ((opcode->match & insn) == opcode->match
532 && (opcode->lose & insn) == 0)
533 {
534 /* Nonzero means that we have found an instruction which has
535 the effect of adding or or'ing the imm13 field to rs1. */
536 int imm_added_to_rs1 = 0;
537 int imm_ored_to_rs1 = 0;
538
539 /* Nonzero means that we have found a plus sign in the args
540 field of the opcode table. */
541 int found_plus = 0;
542
543 /* Nonzero means we have an annulled branch. */
544 int is_annulled = 0;
545
546 /* Do we have an `add' or `or' instruction combining an
547 immediate with rs1? */
548 if (opcode->match == 0x80102000) /* or */
549 imm_ored_to_rs1 = 1;
550 if (opcode->match == 0x80002000) /* add */
551 imm_added_to_rs1 = 1;
552
553 if (X_RS1 (insn) != X_RD (insn)
554 && strchr (opcode->args, 'r') != 0)
555 /* Can't do simple format if source and dest are different. */
556 continue;
557 if (X_RS2 (insn) != X_RD (insn)
558 && strchr (opcode->args, 'O') != 0)
559 /* Can't do simple format if source and dest are different. */
560 continue;
561
562 (*info->fprintf_func) (stream, "%s", opcode->name);
563
564 {
565 const char *s;
566
567 if (opcode->args[0] != ',')
568 (*info->fprintf_func) (stream, " ");
569
570 for (s = opcode->args; *s != '\0'; ++s)
571 {
572 while (*s == ',')
573 {
574 (*info->fprintf_func) (stream, ",");
575 ++s;
576 switch (*s)
577 {
578 case 'a':
579 (*info->fprintf_func) (stream, "a");
580 is_annulled = 1;
581 ++s;
582 continue;
583 case 'N':
584 (*info->fprintf_func) (stream, "pn");
585 ++s;
586 continue;
587
588 case 'T':
589 (*info->fprintf_func) (stream, "pt");
590 ++s;
591 continue;
592
593 default:
594 break;
595 }
596 }
597
598 (*info->fprintf_func) (stream, " ");
599
600 switch (*s)
601 {
602 case '+':
603 found_plus = 1;
604 /* Fall through. */
605
606 default:
607 (*info->fprintf_func) (stream, "%c", *s);
608 break;
609
610 case '#':
611 (*info->fprintf_func) (stream, "0");
612 break;
613
614 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
615 case '1':
616 case 'r':
617 reg (X_RS1 (insn));
618 break;
619
620 case '2':
621 case 'O':
622 reg (X_RS2 (insn));
623 break;
624
625 case 'd':
626 reg (X_RD (insn));
627 break;
628 #undef reg
629
630 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
631 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
632 case 'e':
633 freg (X_RS1 (insn));
634 break;
635 case 'v': /* Double/even. */
636 case 'V': /* Quad/multiple of 4. */
637 fregx (X_RS1 (insn));
638 break;
639
640 case 'f':
641 freg (X_RS2 (insn));
642 break;
643 case 'B': /* Double/even. */
644 case 'R': /* Quad/multiple of 4. */
645 fregx (X_RS2 (insn));
646 break;
647
648 case '4':
649 freg (X_RS3 (insn));
650 break;
651 case '5': /* Double/even. */
652 fregx (X_RS3 (insn));
653 break;
654
655 case 'g':
656 freg (X_RD (insn));
657 break;
658 case 'H': /* Double/even. */
659 case 'J': /* Quad/multiple of 4. */
660 fregx (X_RD (insn));
661 break;
662 #undef freg
663 #undef fregx
664
665 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
666 case 'b':
667 creg (X_RS1 (insn));
668 break;
669
670 case 'c':
671 creg (X_RS2 (insn));
672 break;
673
674 case 'D':
675 creg (X_RD (insn));
676 break;
677 #undef creg
678
679 case 'h':
680 (*info->fprintf_func) (stream, "%%hi(%#x)",
681 ((unsigned) 0xFFFFFFFF
682 & ((int) X_IMM22 (insn) << 10)));
683 break;
684
685 case 'i': /* 13 bit immediate. */
686 case 'I': /* 11 bit immediate. */
687 case 'j': /* 10 bit immediate. */
688 {
689 int imm;
690
691 if (*s == 'i')
692 imm = X_SIMM (insn, 13);
693 else if (*s == 'I')
694 imm = X_SIMM (insn, 11);
695 else
696 imm = X_SIMM (insn, 10);
697
698 /* Check to see whether we have a 1+i, and take
699 note of that fact.
700
701 Note: because of the way we sort the table,
702 we will be matching 1+i rather than i+1,
703 so it is OK to assume that i is after +,
704 not before it. */
705 if (found_plus)
706 imm_added_to_rs1 = 1;
707
708 if (imm <= 9)
709 (*info->fprintf_func) (stream, "%d", imm);
710 else
711 (*info->fprintf_func) (stream, "%#x", imm);
712 }
713 break;
714
715 case ')': /* 5 bit unsigned immediate from RS3. */
716 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
717 break;
718
719 case 'X': /* 5 bit unsigned immediate. */
720 case 'Y': /* 6 bit unsigned immediate. */
721 {
722 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
723
724 if (imm <= 9)
725 (info->fprintf_func) (stream, "%d", imm);
726 else
727 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
728 }
729 break;
730
731 case '3':
732 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
733 break;
734
735 case 'K':
736 {
737 int mask = X_MEMBAR (insn);
738 int bit = 0x40, printed_one = 0;
739 const char *name;
740
741 if (mask == 0)
742 (info->fprintf_func) (stream, "0");
743 else
744 while (bit)
745 {
746 if (mask & bit)
747 {
748 if (printed_one)
749 (info->fprintf_func) (stream, "|");
750 name = sparc_decode_membar (bit);
751 (info->fprintf_func) (stream, "%s", name);
752 printed_one = 1;
753 }
754 bit >>= 1;
755 }
756 break;
757 }
758
759 case '=':
760 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
761 (*info->print_address_func) (info->target, info);
762 break;
763
764 case 'k':
765 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
766 (*info->print_address_func) (info->target, info);
767 break;
768
769 case 'G':
770 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
771 (*info->print_address_func) (info->target, info);
772 break;
773
774 case '6':
775 case '7':
776 case '8':
777 case '9':
778 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
779 break;
780
781 case 'z':
782 (*info->fprintf_func) (stream, "%%icc");
783 break;
784
785 case 'Z':
786 (*info->fprintf_func) (stream, "%%xcc");
787 break;
788
789 case 'E':
790 (*info->fprintf_func) (stream, "%%ccr");
791 break;
792
793 case 's':
794 (*info->fprintf_func) (stream, "%%fprs");
795 break;
796
797 case 'o':
798 (*info->fprintf_func) (stream, "%%asi");
799 break;
800
801 case 'W':
802 (*info->fprintf_func) (stream, "%%tick");
803 break;
804
805 case 'P':
806 (*info->fprintf_func) (stream, "%%pc");
807 break;
808
809 case '?':
810 if (X_RS1 (insn) == 31)
811 (*info->fprintf_func) (stream, "%%ver");
812 else if ((unsigned) X_RS1 (insn) < 17)
813 (*info->fprintf_func) (stream, "%%%s",
814 v9_priv_reg_names[X_RS1 (insn)]);
815 else
816 (*info->fprintf_func) (stream, "%%reserved");
817 break;
818
819 case '!':
820 if ((unsigned) X_RD (insn) < 17)
821 (*info->fprintf_func) (stream, "%%%s",
822 v9_priv_reg_names[X_RD (insn)]);
823 else
824 (*info->fprintf_func) (stream, "%%reserved");
825 break;
826
827 case '$':
828 if ((unsigned) X_RS1 (insn) < 32)
829 (*info->fprintf_func) (stream, "%%%s",
830 v9_hpriv_reg_names[X_RS1 (insn)]);
831 else
832 (*info->fprintf_func) (stream, "%%reserved");
833 break;
834
835 case '%':
836 if ((unsigned) X_RD (insn) < 32)
837 (*info->fprintf_func) (stream, "%%%s",
838 v9_hpriv_reg_names[X_RD (insn)]);
839 else
840 (*info->fprintf_func) (stream, "%%reserved");
841 break;
842
843 case '/':
844 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
845 (*info->fprintf_func) (stream, "%%reserved");
846 else
847 (*info->fprintf_func) (stream, "%%%s",
848 v9a_asr_reg_names[X_RS1 (insn)-16]);
849 break;
850
851 case '_':
852 if (X_RD (insn) < 16 || X_RD (insn) > 28)
853 (*info->fprintf_func) (stream, "%%reserved");
854 else
855 (*info->fprintf_func) (stream, "%%%s",
856 v9a_asr_reg_names[X_RD (insn)-16]);
857 break;
858
859 case '*':
860 {
861 const char *name = sparc_decode_prefetch (X_RD (insn));
862
863 if (name)
864 (*info->fprintf_func) (stream, "%s", name);
865 else
866 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
867 break;
868 }
869
870 case 'M':
871 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
872 break;
873
874 case 'm':
875 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
876 break;
877
878 case 'L':
879 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
880 (*info->print_address_func) (info->target, info);
881 break;
882
883 case 'n':
884 (*info->fprintf_func)
885 (stream, "%#x", SEX (X_DISP22 (insn), 22));
886 break;
887
888 case 'l':
889 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
890 (*info->print_address_func) (info->target, info);
891 break;
892
893 case 'A':
894 {
895 const char *name = sparc_decode_asi (X_ASI (insn));
896
897 if (name)
898 (*info->fprintf_func) (stream, "%s", name);
899 else
900 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
901 break;
902 }
903
904 case 'C':
905 (*info->fprintf_func) (stream, "%%csr");
906 break;
907
908 case 'F':
909 (*info->fprintf_func) (stream, "%%fsr");
910 break;
911
912 case '(':
913 (*info->fprintf_func) (stream, "%%efsr");
914 break;
915
916 case 'p':
917 (*info->fprintf_func) (stream, "%%psr");
918 break;
919
920 case 'q':
921 (*info->fprintf_func) (stream, "%%fq");
922 break;
923
924 case 'Q':
925 (*info->fprintf_func) (stream, "%%cq");
926 break;
927
928 case 't':
929 (*info->fprintf_func) (stream, "%%tbr");
930 break;
931
932 case 'w':
933 (*info->fprintf_func) (stream, "%%wim");
934 break;
935
936 case 'x':
937 (*info->fprintf_func) (stream, "%ld",
938 ((X_LDST_I (insn) << 8)
939 + X_ASI (insn)));
940 break;
941
942 case 'y':
943 (*info->fprintf_func) (stream, "%%y");
944 break;
945
946 case 'u':
947 case 'U':
948 {
949 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
950 const char *name = sparc_decode_sparclet_cpreg (val);
951
952 if (name)
953 (*info->fprintf_func) (stream, "%s", name);
954 else
955 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
956 break;
957 }
958 }
959 }
960 }
961
962 /* If we are adding or or'ing something to rs1, then
963 check to see whether the previous instruction was
964 a sethi to the same register as in the sethi.
965 If so, attempt to print the result of the add or
966 or (in this context add and or do the same thing)
967 and its symbolic value. */
968 if (imm_ored_to_rs1 || imm_added_to_rs1)
969 {
970 unsigned long prev_insn;
971 int errcode;
972
973 if (memaddr >= 4)
974 errcode =
975 (*info->read_memory_func)
976 (memaddr - 4, buffer, sizeof (buffer), info);
977 else
978 errcode = 1;
979
980 prev_insn = getword (buffer);
981
982 if (errcode == 0)
983 {
984 /* If it is a delayed branch, we need to look at the
985 instruction before the delayed branch. This handles
986 sequences such as:
987
988 sethi %o1, %hi(_foo), %o1
989 call _printf
990 or %o1, %lo(_foo), %o1 */
991
992 if (is_delayed_branch (prev_insn))
993 {
994 if (memaddr >= 8)
995 errcode = (*info->read_memory_func)
996 (memaddr - 8, buffer, sizeof (buffer), info);
997 else
998 errcode = 1;
999
1000 prev_insn = getword (buffer);
1001 }
1002 }
1003
1004 /* If there was a problem reading memory, then assume
1005 the previous instruction was not sethi. */
1006 if (errcode == 0)
1007 {
1008 /* Is it sethi to the same register? */
1009 if ((prev_insn & 0xc1c00000) == 0x01000000
1010 && X_RD (prev_insn) == X_RS1 (insn))
1011 {
1012 (*info->fprintf_func) (stream, "\t! ");
1013 info->target =
1014 ((unsigned) 0xFFFFFFFF
1015 & ((int) X_IMM22 (prev_insn) << 10));
1016 if (imm_added_to_rs1)
1017 info->target += X_SIMM (insn, 13);
1018 else
1019 info->target |= X_SIMM (insn, 13);
1020 (*info->print_address_func) (info->target, info);
1021 info->insn_type = dis_dref;
1022 info->data_size = 4; /* FIXME!!! */
1023 }
1024 }
1025 }
1026
1027 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1028 {
1029 /* FIXME -- check is_annulled flag. */
1030 (void) is_annulled;
1031 if (opcode->flags & F_UNBR)
1032 info->insn_type = dis_branch;
1033 if (opcode->flags & F_CONDBR)
1034 info->insn_type = dis_condbranch;
1035 if (opcode->flags & F_JSR)
1036 info->insn_type = dis_jsr;
1037 if (opcode->flags & F_DELAYED)
1038 info->branch_delay_insns = 1;
1039 }
1040
1041 return sizeof (buffer);
1042 }
1043 }
1044
1045 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1046 (*info->fprintf_func) (stream, _("unknown"));
1047 return sizeof (buffer);
1048 }
GDB Binutils - Deliverables
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