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Add support for sparc pause instruction.
[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c
1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include <stdio.h>
24
25 #include "sysdep.h"
26 #include "opcode/sparc.h"
27 #include "dis-asm.h"
28 #include "libiberty.h"
29 #include "opintl.h"
30
31 /* Bitmask of v9 architectures. */
32 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
33 | (1 << SPARC_OPCODE_ARCH_V9A) \
34 | (1 << SPARC_OPCODE_ARCH_V9B))
35 /* 1 if INSN is for v9 only. */
36 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
37 /* 1 if INSN is for v9. */
38 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
39
40 /* The sorted opcode table. */
41 static const sparc_opcode **sorted_opcodes;
42
43 /* For faster lookup, after insns are sorted they are hashed. */
44 /* ??? I think there is room for even more improvement. */
45
46 #define HASH_SIZE 256
47 /* It is important that we only look at insn code bits as that is how the
48 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
49 of the main types (0,1,2,3). */
50 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
51 #define HASH_INSN(INSN) \
52 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
53 typedef struct sparc_opcode_hash
54 {
55 struct sparc_opcode_hash *next;
56 const sparc_opcode *opcode;
57 } sparc_opcode_hash;
58
59 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
60
61 /* Sign-extend a value which is N bits long. */
62 #define SEX(value, bits) \
63 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
64 >> ((8 * sizeof (int)) - bits) )
65
66 static char *reg_names[] =
67 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
68 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
69 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
70 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
71 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
72 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
73 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
74 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
75 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
76 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
77 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
78 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
79 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
80 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
81 };
82
83 #define freg_names (&reg_names[4 * 8])
84
85 /* These are ordered according to there register number in
86 rdpr and wrpr insns. */
87 static char *v9_priv_reg_names[] =
88 {
89 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
90 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
91 "wstate", "fq", "gl"
92 /* "ver" - special cased */
93 };
94
95 /* These are ordered according to there register number in
96 rdhpr and wrhpr insns. */
97 static char *v9_hpriv_reg_names[] =
98 {
99 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
100 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
101 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
102 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
103 "resv28", "resv29", "resv30", "hstick_cmpr"
104 };
105
106 /* These are ordered according to there register number in
107 rd and wr insns (-16). */
108 static char *v9a_asr_reg_names[] =
109 {
110 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
111 "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
112 "pause", "cps"
113 };
114
115 /* Macros used to extract instruction fields. Not all fields have
116 macros defined here, only those which are actually used. */
117
118 #define X_RD(i) (((i) >> 25) & 0x1f)
119 #define X_RS1(i) (((i) >> 14) & 0x1f)
120 #define X_LDST_I(i) (((i) >> 13) & 1)
121 #define X_ASI(i) (((i) >> 5) & 0xff)
122 #define X_RS2(i) (((i) >> 0) & 0x1f)
123 #define X_RS3(i) (((i) >> 9) & 0x1f)
124 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
125 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
126 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
127 #define X_IMM22(i) X_DISP22 (i)
128 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
129
130 /* These are for v9. */
131 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
132 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
133 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
134 #define X_MEMBAR(i) ((i) & 0x7f)
135
136 /* Here is the union which was used to extract instruction fields
137 before the shift and mask macros were written.
138
139 union sparc_insn
140 {
141 unsigned long int code;
142 struct
143 {
144 unsigned int anop:2;
145 #define op ldst.anop
146 unsigned int anrd:5;
147 #define rd ldst.anrd
148 unsigned int op3:6;
149 unsigned int anrs1:5;
150 #define rs1 ldst.anrs1
151 unsigned int i:1;
152 unsigned int anasi:8;
153 #define asi ldst.anasi
154 unsigned int anrs2:5;
155 #define rs2 ldst.anrs2
156 #define shcnt rs2
157 } ldst;
158 struct
159 {
160 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
161 unsigned int IMM13:13;
162 #define imm13 IMM13.IMM13
163 } IMM13;
164 struct
165 {
166 unsigned int anop:2;
167 unsigned int a:1;
168 unsigned int cond:4;
169 unsigned int op2:3;
170 unsigned int DISP22:22;
171 #define disp22 branch.DISP22
172 #define imm22 disp22
173 } branch;
174 struct
175 {
176 unsigned int anop:2;
177 unsigned int a:1;
178 unsigned int z:1;
179 unsigned int rcond:3;
180 unsigned int op2:3;
181 unsigned int DISP16HI:2;
182 unsigned int p:1;
183 unsigned int _rs1:5;
184 unsigned int DISP16LO:14;
185 } branch16;
186 struct
187 {
188 unsigned int anop:2;
189 unsigned int adisp30:30;
190 #define disp30 call.adisp30
191 } call;
192 }; */
193
194 /* Nonzero if INSN is the opcode for a delayed branch. */
195
196 static int
197 is_delayed_branch (unsigned long insn)
198 {
199 sparc_opcode_hash *op;
200
201 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
202 {
203 const sparc_opcode *opcode = op->opcode;
204
205 if ((opcode->match & insn) == opcode->match
206 && (opcode->lose & insn) == 0)
207 return opcode->flags & F_DELAYED;
208 }
209 return 0;
210 }
211
212 /* extern void qsort (); */
213
214 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
215 to compare_opcodes. */
216 static unsigned int current_arch_mask;
217
218 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
219
220 static int
221 compute_arch_mask (unsigned long mach)
222 {
223 switch (mach)
224 {
225 case 0 :
226 case bfd_mach_sparc :
227 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
228 case bfd_mach_sparc_sparclet :
229 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
230 case bfd_mach_sparc_sparclite :
231 case bfd_mach_sparc_sparclite_le :
232 /* sparclites insns are recognized by default (because that's how
233 they've always been treated, for better or worse). Kludge this by
234 indicating generic v8 is also selected. */
235 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
236 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
237 case bfd_mach_sparc_v8plus :
238 case bfd_mach_sparc_v9 :
239 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
240 case bfd_mach_sparc_v8plusa :
241 case bfd_mach_sparc_v9a :
242 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
243 case bfd_mach_sparc_v8plusb :
244 case bfd_mach_sparc_v9b :
245 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
246 }
247 abort ();
248 }
249
250 /* Compare opcodes A and B. */
251
252 static int
253 compare_opcodes (const void * a, const void * b)
254 {
255 sparc_opcode *op0 = * (sparc_opcode **) a;
256 sparc_opcode *op1 = * (sparc_opcode **) b;
257 unsigned long int match0 = op0->match, match1 = op1->match;
258 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
259 register unsigned int i;
260
261 /* If one (and only one) insn isn't supported by the current architecture,
262 prefer the one that is. If neither are supported, but they're both for
263 the same architecture, continue processing. Otherwise (both unsupported
264 and for different architectures), prefer lower numbered arch's (fudged
265 by comparing the bitmasks). */
266 if (op0->architecture & current_arch_mask)
267 {
268 if (! (op1->architecture & current_arch_mask))
269 return -1;
270 }
271 else
272 {
273 if (op1->architecture & current_arch_mask)
274 return 1;
275 else if (op0->architecture != op1->architecture)
276 return op0->architecture - op1->architecture;
277 }
278
279 /* If a bit is set in both match and lose, there is something
280 wrong with the opcode table. */
281 if (match0 & lose0)
282 {
283 fprintf
284 (stderr,
285 /* xgettext:c-format */
286 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
287 op0->name, match0, lose0);
288 op0->lose &= ~op0->match;
289 lose0 = op0->lose;
290 }
291
292 if (match1 & lose1)
293 {
294 fprintf
295 (stderr,
296 /* xgettext:c-format */
297 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
298 op1->name, match1, lose1);
299 op1->lose &= ~op1->match;
300 lose1 = op1->lose;
301 }
302
303 /* Because the bits that are variable in one opcode are constant in
304 another, it is important to order the opcodes in the right order. */
305 for (i = 0; i < 32; ++i)
306 {
307 unsigned long int x = 1 << i;
308 int x0 = (match0 & x) != 0;
309 int x1 = (match1 & x) != 0;
310
311 if (x0 != x1)
312 return x1 - x0;
313 }
314
315 for (i = 0; i < 32; ++i)
316 {
317 unsigned long int x = 1 << i;
318 int x0 = (lose0 & x) != 0;
319 int x1 = (lose1 & x) != 0;
320
321 if (x0 != x1)
322 return x1 - x0;
323 }
324
325 /* They are functionally equal. So as long as the opcode table is
326 valid, we can put whichever one first we want, on aesthetic grounds. */
327
328 /* Our first aesthetic ground is that aliases defer to real insns. */
329 {
330 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
331
332 if (alias_diff != 0)
333 /* Put the one that isn't an alias first. */
334 return alias_diff;
335 }
336
337 /* Except for aliases, two "identical" instructions had
338 better have the same opcode. This is a sanity check on the table. */
339 i = strcmp (op0->name, op1->name);
340 if (i)
341 {
342 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
343 return i;
344 else
345 fprintf (stderr,
346 /* xgettext:c-format */
347 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
348 op0->name, op1->name);
349 }
350
351 /* Fewer arguments are preferred. */
352 {
353 int length_diff = strlen (op0->args) - strlen (op1->args);
354
355 if (length_diff != 0)
356 /* Put the one with fewer arguments first. */
357 return length_diff;
358 }
359
360 /* Put 1+i before i+1. */
361 {
362 char *p0 = (char *) strchr (op0->args, '+');
363 char *p1 = (char *) strchr (op1->args, '+');
364
365 if (p0 && p1)
366 {
367 /* There is a plus in both operands. Note that a plus
368 sign cannot be the first character in args,
369 so the following [-1]'s are valid. */
370 if (p0[-1] == 'i' && p1[1] == 'i')
371 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
372 return 1;
373 if (p0[1] == 'i' && p1[-1] == 'i')
374 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
375 return -1;
376 }
377 }
378
379 /* Put 1,i before i,1. */
380 {
381 int i0 = strncmp (op0->args, "i,1", 3) == 0;
382 int i1 = strncmp (op1->args, "i,1", 3) == 0;
383
384 if (i0 ^ i1)
385 return i0 - i1;
386 }
387
388 /* They are, as far as we can tell, identical.
389 Since qsort may have rearranged the table partially, there is
390 no way to tell which one was first in the opcode table as
391 written, so just say there are equal. */
392 /* ??? This is no longer true now that we sort a vector of pointers,
393 not the table itself. */
394 return 0;
395 }
396
397 /* Build a hash table from the opcode table.
398 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
399
400 static void
401 build_hash_table (const sparc_opcode **opcode_table,
402 sparc_opcode_hash **hash_table,
403 int num_opcodes)
404 {
405 int i;
406 int hash_count[HASH_SIZE];
407 static sparc_opcode_hash *hash_buf = NULL;
408
409 /* Start at the end of the table and work backwards so that each
410 chain is sorted. */
411
412 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
413 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
414 if (hash_buf != NULL)
415 free (hash_buf);
416 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
417 for (i = num_opcodes - 1; i >= 0; --i)
418 {
419 int hash = HASH_INSN (opcode_table[i]->match);
420 sparc_opcode_hash *h = &hash_buf[i];
421
422 h->next = hash_table[hash];
423 h->opcode = opcode_table[i];
424 hash_table[hash] = h;
425 ++hash_count[hash];
426 }
427
428 #if 0 /* for debugging */
429 {
430 int min_count = num_opcodes, max_count = 0;
431 int total;
432
433 for (i = 0; i < HASH_SIZE; ++i)
434 {
435 if (hash_count[i] < min_count)
436 min_count = hash_count[i];
437 if (hash_count[i] > max_count)
438 max_count = hash_count[i];
439 total += hash_count[i];
440 }
441
442 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
443 min_count, max_count, (double) total / HASH_SIZE);
444 }
445 #endif
446 }
447
448 /* Print one instruction from MEMADDR on INFO->STREAM.
449
450 We suffix the instruction with a comment that gives the absolute
451 address involved, as well as its symbolic form, if the instruction
452 is preceded by a findable `sethi' and it either adds an immediate
453 displacement to that register, or it is an `add' or `or' instruction
454 on that register. */
455
456 int
457 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
458 {
459 FILE *stream = info->stream;
460 bfd_byte buffer[4];
461 unsigned long insn;
462 sparc_opcode_hash *op;
463 /* Nonzero of opcode table has been initialized. */
464 static int opcodes_initialized = 0;
465 /* bfd mach number of last call. */
466 static unsigned long current_mach = 0;
467 bfd_vma (*getword) (const void *);
468
469 if (!opcodes_initialized
470 || info->mach != current_mach)
471 {
472 int i;
473
474 current_arch_mask = compute_arch_mask (info->mach);
475
476 if (!opcodes_initialized)
477 sorted_opcodes =
478 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
479 /* Reset the sorted table so we can resort it. */
480 for (i = 0; i < sparc_num_opcodes; ++i)
481 sorted_opcodes[i] = &sparc_opcodes[i];
482 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
483 sizeof (sorted_opcodes[0]), compare_opcodes);
484
485 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
486 current_mach = info->mach;
487 opcodes_initialized = 1;
488 }
489
490 {
491 int status =
492 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
493
494 if (status != 0)
495 {
496 (*info->memory_error_func) (status, memaddr, info);
497 return -1;
498 }
499 }
500
501 /* On SPARClite variants such as DANlite (sparc86x), instructions
502 are always big-endian even when the machine is in little-endian mode. */
503 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
504 getword = bfd_getb32;
505 else
506 getword = bfd_getl32;
507
508 insn = getword (buffer);
509
510 info->insn_info_valid = 1; /* We do return this info. */
511 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
512 info->branch_delay_insns = 0; /* Assume no delay. */
513 info->target = 0; /* Assume no target known. */
514
515 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
516 {
517 const sparc_opcode *opcode = op->opcode;
518
519 /* If the insn isn't supported by the current architecture, skip it. */
520 if (! (opcode->architecture & current_arch_mask))
521 continue;
522
523 if ((opcode->match & insn) == opcode->match
524 && (opcode->lose & insn) == 0)
525 {
526 /* Nonzero means that we have found an instruction which has
527 the effect of adding or or'ing the imm13 field to rs1. */
528 int imm_added_to_rs1 = 0;
529 int imm_ored_to_rs1 = 0;
530
531 /* Nonzero means that we have found a plus sign in the args
532 field of the opcode table. */
533 int found_plus = 0;
534
535 /* Nonzero means we have an annulled branch. */
536 int is_annulled = 0;
537
538 /* Do we have an `add' or `or' instruction combining an
539 immediate with rs1? */
540 if (opcode->match == 0x80102000) /* or */
541 imm_ored_to_rs1 = 1;
542 if (opcode->match == 0x80002000) /* add */
543 imm_added_to_rs1 = 1;
544
545 if (X_RS1 (insn) != X_RD (insn)
546 && strchr (opcode->args, 'r') != 0)
547 /* Can't do simple format if source and dest are different. */
548 continue;
549 if (X_RS2 (insn) != X_RD (insn)
550 && strchr (opcode->args, 'O') != 0)
551 /* Can't do simple format if source and dest are different. */
552 continue;
553
554 (*info->fprintf_func) (stream, opcode->name);
555
556 {
557 const char *s;
558
559 if (opcode->args[0] != ',')
560 (*info->fprintf_func) (stream, " ");
561
562 for (s = opcode->args; *s != '\0'; ++s)
563 {
564 while (*s == ',')
565 {
566 (*info->fprintf_func) (stream, ",");
567 ++s;
568 switch (*s)
569 {
570 case 'a':
571 (*info->fprintf_func) (stream, "a");
572 is_annulled = 1;
573 ++s;
574 continue;
575 case 'N':
576 (*info->fprintf_func) (stream, "pn");
577 ++s;
578 continue;
579
580 case 'T':
581 (*info->fprintf_func) (stream, "pt");
582 ++s;
583 continue;
584
585 default:
586 break;
587 }
588 }
589
590 (*info->fprintf_func) (stream, " ");
591
592 switch (*s)
593 {
594 case '+':
595 found_plus = 1;
596 /* Fall through. */
597
598 default:
599 (*info->fprintf_func) (stream, "%c", *s);
600 break;
601
602 case '#':
603 (*info->fprintf_func) (stream, "0");
604 break;
605
606 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
607 case '1':
608 case 'r':
609 reg (X_RS1 (insn));
610 break;
611
612 case '2':
613 case 'O':
614 reg (X_RS2 (insn));
615 break;
616
617 case 'd':
618 reg (X_RD (insn));
619 break;
620 #undef reg
621
622 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
623 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
624 case 'e':
625 freg (X_RS1 (insn));
626 break;
627 case 'v': /* Double/even. */
628 case 'V': /* Quad/multiple of 4. */
629 fregx (X_RS1 (insn));
630 break;
631
632 case 'f':
633 freg (X_RS2 (insn));
634 break;
635 case 'B': /* Double/even. */
636 case 'R': /* Quad/multiple of 4. */
637 fregx (X_RS2 (insn));
638 break;
639
640 case '4':
641 freg (X_RS3 (insn));
642 break;
643 case '5': /* Double/even. */
644 fregx (X_RS3 (insn));
645 break;
646
647 case 'g':
648 freg (X_RD (insn));
649 break;
650 case 'H': /* Double/even. */
651 case 'J': /* Quad/multiple of 4. */
652 fregx (X_RD (insn));
653 break;
654 #undef freg
655 #undef fregx
656
657 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
658 case 'b':
659 creg (X_RS1 (insn));
660 break;
661
662 case 'c':
663 creg (X_RS2 (insn));
664 break;
665
666 case 'D':
667 creg (X_RD (insn));
668 break;
669 #undef creg
670
671 case 'h':
672 (*info->fprintf_func) (stream, "%%hi(%#x)",
673 ((unsigned) 0xFFFFFFFF
674 & ((int) X_IMM22 (insn) << 10)));
675 break;
676
677 case 'i': /* 13 bit immediate. */
678 case 'I': /* 11 bit immediate. */
679 case 'j': /* 10 bit immediate. */
680 {
681 int imm;
682
683 if (*s == 'i')
684 imm = X_SIMM (insn, 13);
685 else if (*s == 'I')
686 imm = X_SIMM (insn, 11);
687 else
688 imm = X_SIMM (insn, 10);
689
690 /* Check to see whether we have a 1+i, and take
691 note of that fact.
692
693 Note: because of the way we sort the table,
694 we will be matching 1+i rather than i+1,
695 so it is OK to assume that i is after +,
696 not before it. */
697 if (found_plus)
698 imm_added_to_rs1 = 1;
699
700 if (imm <= 9)
701 (*info->fprintf_func) (stream, "%d", imm);
702 else
703 (*info->fprintf_func) (stream, "%#x", imm);
704 }
705 break;
706
707 case ')': /* 5 bit unsigned immediate from RS3. */
708 (info->fprintf_func) (stream, "%#x", X_RS3 (insn));
709 break;
710
711 case 'X': /* 5 bit unsigned immediate. */
712 case 'Y': /* 6 bit unsigned immediate. */
713 {
714 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
715
716 if (imm <= 9)
717 (info->fprintf_func) (stream, "%d", imm);
718 else
719 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
720 }
721 break;
722
723 case '3':
724 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
725 break;
726
727 case 'K':
728 {
729 int mask = X_MEMBAR (insn);
730 int bit = 0x40, printed_one = 0;
731 const char *name;
732
733 if (mask == 0)
734 (info->fprintf_func) (stream, "0");
735 else
736 while (bit)
737 {
738 if (mask & bit)
739 {
740 if (printed_one)
741 (info->fprintf_func) (stream, "|");
742 name = sparc_decode_membar (bit);
743 (info->fprintf_func) (stream, "%s", name);
744 printed_one = 1;
745 }
746 bit >>= 1;
747 }
748 break;
749 }
750
751 case '=':
752 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
753 (*info->print_address_func) (info->target, info);
754 break;
755
756 case 'k':
757 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
758 (*info->print_address_func) (info->target, info);
759 break;
760
761 case 'G':
762 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
763 (*info->print_address_func) (info->target, info);
764 break;
765
766 case '6':
767 case '7':
768 case '8':
769 case '9':
770 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
771 break;
772
773 case 'z':
774 (*info->fprintf_func) (stream, "%%icc");
775 break;
776
777 case 'Z':
778 (*info->fprintf_func) (stream, "%%xcc");
779 break;
780
781 case 'E':
782 (*info->fprintf_func) (stream, "%%ccr");
783 break;
784
785 case 's':
786 (*info->fprintf_func) (stream, "%%fprs");
787 break;
788
789 case 'o':
790 (*info->fprintf_func) (stream, "%%asi");
791 break;
792
793 case 'W':
794 (*info->fprintf_func) (stream, "%%tick");
795 break;
796
797 case 'P':
798 (*info->fprintf_func) (stream, "%%pc");
799 break;
800
801 case '?':
802 if (X_RS1 (insn) == 31)
803 (*info->fprintf_func) (stream, "%%ver");
804 else if ((unsigned) X_RS1 (insn) < 17)
805 (*info->fprintf_func) (stream, "%%%s",
806 v9_priv_reg_names[X_RS1 (insn)]);
807 else
808 (*info->fprintf_func) (stream, "%%reserved");
809 break;
810
811 case '!':
812 if ((unsigned) X_RD (insn) < 17)
813 (*info->fprintf_func) (stream, "%%%s",
814 v9_priv_reg_names[X_RD (insn)]);
815 else
816 (*info->fprintf_func) (stream, "%%reserved");
817 break;
818
819 case '$':
820 if ((unsigned) X_RS1 (insn) < 32)
821 (*info->fprintf_func) (stream, "%%%s",
822 v9_hpriv_reg_names[X_RS1 (insn)]);
823 else
824 (*info->fprintf_func) (stream, "%%reserved");
825 break;
826
827 case '%':
828 if ((unsigned) X_RD (insn) < 32)
829 (*info->fprintf_func) (stream, "%%%s",
830 v9_hpriv_reg_names[X_RD (insn)]);
831 else
832 (*info->fprintf_func) (stream, "%%reserved");
833 break;
834
835 case '/':
836 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
837 (*info->fprintf_func) (stream, "%%reserved");
838 else
839 (*info->fprintf_func) (stream, "%%%s",
840 v9a_asr_reg_names[X_RS1 (insn)-16]);
841 break;
842
843 case '_':
844 if (X_RD (insn) < 16 || X_RD (insn) > 28)
845 (*info->fprintf_func) (stream, "%%reserved");
846 else
847 (*info->fprintf_func) (stream, "%%%s",
848 v9a_asr_reg_names[X_RD (insn)-16]);
849 break;
850
851 case '*':
852 {
853 const char *name = sparc_decode_prefetch (X_RD (insn));
854
855 if (name)
856 (*info->fprintf_func) (stream, "%s", name);
857 else
858 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
859 break;
860 }
861
862 case 'M':
863 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
864 break;
865
866 case 'm':
867 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
868 break;
869
870 case 'L':
871 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
872 (*info->print_address_func) (info->target, info);
873 break;
874
875 case 'n':
876 (*info->fprintf_func)
877 (stream, "%#x", SEX (X_DISP22 (insn), 22));
878 break;
879
880 case 'l':
881 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
882 (*info->print_address_func) (info->target, info);
883 break;
884
885 case 'A':
886 {
887 const char *name = sparc_decode_asi (X_ASI (insn));
888
889 if (name)
890 (*info->fprintf_func) (stream, "%s", name);
891 else
892 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
893 break;
894 }
895
896 case 'C':
897 (*info->fprintf_func) (stream, "%%csr");
898 break;
899
900 case 'F':
901 (*info->fprintf_func) (stream, "%%fsr");
902 break;
903
904 case '(':
905 (*info->fprintf_func) (stream, "%%efsr");
906 break;
907
908 case 'p':
909 (*info->fprintf_func) (stream, "%%psr");
910 break;
911
912 case 'q':
913 (*info->fprintf_func) (stream, "%%fq");
914 break;
915
916 case 'Q':
917 (*info->fprintf_func) (stream, "%%cq");
918 break;
919
920 case 't':
921 (*info->fprintf_func) (stream, "%%tbr");
922 break;
923
924 case 'w':
925 (*info->fprintf_func) (stream, "%%wim");
926 break;
927
928 case 'x':
929 (*info->fprintf_func) (stream, "%ld",
930 ((X_LDST_I (insn) << 8)
931 + X_ASI (insn)));
932 break;
933
934 case 'y':
935 (*info->fprintf_func) (stream, "%%y");
936 break;
937
938 case 'u':
939 case 'U':
940 {
941 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
942 const char *name = sparc_decode_sparclet_cpreg (val);
943
944 if (name)
945 (*info->fprintf_func) (stream, "%s", name);
946 else
947 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
948 break;
949 }
950 }
951 }
952 }
953
954 /* If we are adding or or'ing something to rs1, then
955 check to see whether the previous instruction was
956 a sethi to the same register as in the sethi.
957 If so, attempt to print the result of the add or
958 or (in this context add and or do the same thing)
959 and its symbolic value. */
960 if (imm_ored_to_rs1 || imm_added_to_rs1)
961 {
962 unsigned long prev_insn;
963 int errcode;
964
965 if (memaddr >= 4)
966 errcode =
967 (*info->read_memory_func)
968 (memaddr - 4, buffer, sizeof (buffer), info);
969 else
970 errcode = 1;
971
972 prev_insn = getword (buffer);
973
974 if (errcode == 0)
975 {
976 /* If it is a delayed branch, we need to look at the
977 instruction before the delayed branch. This handles
978 sequences such as:
979
980 sethi %o1, %hi(_foo), %o1
981 call _printf
982 or %o1, %lo(_foo), %o1 */
983
984 if (is_delayed_branch (prev_insn))
985 {
986 if (memaddr >= 8)
987 errcode = (*info->read_memory_func)
988 (memaddr - 8, buffer, sizeof (buffer), info);
989 else
990 errcode = 1;
991
992 prev_insn = getword (buffer);
993 }
994 }
995
996 /* If there was a problem reading memory, then assume
997 the previous instruction was not sethi. */
998 if (errcode == 0)
999 {
1000 /* Is it sethi to the same register? */
1001 if ((prev_insn & 0xc1c00000) == 0x01000000
1002 && X_RD (prev_insn) == X_RS1 (insn))
1003 {
1004 (*info->fprintf_func) (stream, "\t! ");
1005 info->target =
1006 ((unsigned) 0xFFFFFFFF
1007 & ((int) X_IMM22 (prev_insn) << 10));
1008 if (imm_added_to_rs1)
1009 info->target += X_SIMM (insn, 13);
1010 else
1011 info->target |= X_SIMM (insn, 13);
1012 (*info->print_address_func) (info->target, info);
1013 info->insn_type = dis_dref;
1014 info->data_size = 4; /* FIXME!!! */
1015 }
1016 }
1017 }
1018
1019 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1020 {
1021 /* FIXME -- check is_annulled flag. */
1022 (void) is_annulled;
1023 if (opcode->flags & F_UNBR)
1024 info->insn_type = dis_branch;
1025 if (opcode->flags & F_CONDBR)
1026 info->insn_type = dis_condbranch;
1027 if (opcode->flags & F_JSR)
1028 info->insn_type = dis_jsr;
1029 if (opcode->flags & F_DELAYED)
1030 info->branch_delay_insns = 1;
1031 }
1032
1033 return sizeof (buffer);
1034 }
1035 }
1036
1037 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1038 (*info->fprintf_func) (stream, _("unknown"));
1039 return sizeof (buffer);
1040 }
GDB Binutils - Deliverables
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