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This patch adds support for the hyperprivileged registers %hstick_offset
[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c
1 /* Print SPARC instructions.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <stdio.h>
23 #include "opcode/sparc.h"
24 #include "dis-asm.h"
25 #include "libiberty.h"
26 #include "opintl.h"
27
28 /* Bitmask of v9 architectures. */
29 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
30 | (1 << SPARC_OPCODE_ARCH_V9A) \
31 | (1 << SPARC_OPCODE_ARCH_V9B))
32 /* 1 if INSN is for v9 only. */
33 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
34 /* 1 if INSN is for v9. */
35 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
36
37 /* The sorted opcode table. */
38 static const sparc_opcode **sorted_opcodes;
39
40 /* For faster lookup, after insns are sorted they are hashed. */
41 /* ??? I think there is room for even more improvement. */
42
43 #define HASH_SIZE 256
44 /* It is important that we only look at insn code bits as that is how the
45 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
46 of the main types (0,1,2,3). */
47 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
48 #define HASH_INSN(INSN) \
49 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
50 typedef struct sparc_opcode_hash
51 {
52 struct sparc_opcode_hash *next;
53 const sparc_opcode *opcode;
54 } sparc_opcode_hash;
55
56 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
57
58 /* Sign-extend a value which is N bits long. */
59 #define SEX(value, bits) \
60 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
61 >> ((8 * sizeof (int)) - bits) )
62
63 static char *reg_names[] =
64 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
65 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
66 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
67 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
68 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
69 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
70 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
71 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
72 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
73 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
74 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
75 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
76 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
77 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
78 };
79
80 #define freg_names (&reg_names[4 * 8])
81
82 /* These are ordered according to there register number in
83 rdpr and wrpr insns. */
84 static char *v9_priv_reg_names[] =
85 {
86 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
87 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
88 "wstate", "fq", "gl"
89 /* "ver" - special cased */
90 };
91
92 /* These are ordered according to there register number in
93 rdhpr and wrhpr insns. */
94 static char *v9_hpriv_reg_names[] =
95 {
96 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
97 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
98 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
99 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
100 "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
101 };
102
103 /* These are ordered according to there register number in
104 rd and wr insns (-16). */
105 static char *v9a_asr_reg_names[] =
106 {
107 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
108 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
109 "pause", "cps"
110 };
111
112 /* Macros used to extract instruction fields. Not all fields have
113 macros defined here, only those which are actually used. */
114
115 #define X_RD(i) (((i) >> 25) & 0x1f)
116 #define X_RS1(i) (((i) >> 14) & 0x1f)
117 #define X_LDST_I(i) (((i) >> 13) & 1)
118 #define X_ASI(i) (((i) >> 5) & 0xff)
119 #define X_RS2(i) (((i) >> 0) & 0x1f)
120 #define X_RS3(i) (((i) >> 9) & 0x1f)
121 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
122 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
123 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
124 #define X_IMM22(i) X_DISP22 (i)
125 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
126
127 /* These are for v9. */
128 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
129 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
130 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
131 #define X_MEMBAR(i) ((i) & 0x7f)
132
133 /* Here is the union which was used to extract instruction fields
134 before the shift and mask macros were written.
135
136 union sparc_insn
137 {
138 unsigned long int code;
139 struct
140 {
141 unsigned int anop:2;
142 #define op ldst.anop
143 unsigned int anrd:5;
144 #define rd ldst.anrd
145 unsigned int op3:6;
146 unsigned int anrs1:5;
147 #define rs1 ldst.anrs1
148 unsigned int i:1;
149 unsigned int anasi:8;
150 #define asi ldst.anasi
151 unsigned int anrs2:5;
152 #define rs2 ldst.anrs2
153 #define shcnt rs2
154 } ldst;
155 struct
156 {
157 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
158 unsigned int IMM13:13;
159 #define imm13 IMM13.IMM13
160 } IMM13;
161 struct
162 {
163 unsigned int anop:2;
164 unsigned int a:1;
165 unsigned int cond:4;
166 unsigned int op2:3;
167 unsigned int DISP22:22;
168 #define disp22 branch.DISP22
169 #define imm22 disp22
170 } branch;
171 struct
172 {
173 unsigned int anop:2;
174 unsigned int a:1;
175 unsigned int z:1;
176 unsigned int rcond:3;
177 unsigned int op2:3;
178 unsigned int DISP16HI:2;
179 unsigned int p:1;
180 unsigned int _rs1:5;
181 unsigned int DISP16LO:14;
182 } branch16;
183 struct
184 {
185 unsigned int anop:2;
186 unsigned int adisp30:30;
187 #define disp30 call.adisp30
188 } call;
189 }; */
190
191 /* Nonzero if INSN is the opcode for a delayed branch. */
192
193 static int
194 is_delayed_branch (unsigned long insn)
195 {
196 sparc_opcode_hash *op;
197
198 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
199 {
200 const sparc_opcode *opcode = op->opcode;
201
202 if ((opcode->match & insn) == opcode->match
203 && (opcode->lose & insn) == 0)
204 return opcode->flags & F_DELAYED;
205 }
206 return 0;
207 }
208
209 /* extern void qsort (); */
210
211 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
212 to compare_opcodes. */
213 static unsigned int current_arch_mask;
214
215 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
216
217 static int
218 compute_arch_mask (unsigned long mach)
219 {
220 switch (mach)
221 {
222 case 0 :
223 case bfd_mach_sparc :
224 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
225 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
226 case bfd_mach_sparc_sparclet :
227 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
228 case bfd_mach_sparc_sparclite :
229 case bfd_mach_sparc_sparclite_le :
230 /* sparclites insns are recognized by default (because that's how
231 they've always been treated, for better or worse). Kludge this by
232 indicating generic v8 is also selected. */
233 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
234 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
235 case bfd_mach_sparc_v8plus :
236 case bfd_mach_sparc_v9 :
237 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
238 case bfd_mach_sparc_v8plusa :
239 case bfd_mach_sparc_v9a :
240 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
241 case bfd_mach_sparc_v8plusb :
242 case bfd_mach_sparc_v9b :
243 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
244 }
245 abort ();
246 }
247
248 /* Compare opcodes A and B. */
249
250 static int
251 compare_opcodes (const void * a, const void * b)
252 {
253 sparc_opcode *op0 = * (sparc_opcode **) a;
254 sparc_opcode *op1 = * (sparc_opcode **) b;
255 unsigned long int match0 = op0->match, match1 = op1->match;
256 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
257 register unsigned int i;
258
259 /* If one (and only one) insn isn't supported by the current architecture,
260 prefer the one that is. If neither are supported, but they're both for
261 the same architecture, continue processing. Otherwise (both unsupported
262 and for different architectures), prefer lower numbered arch's (fudged
263 by comparing the bitmasks). */
264 if (op0->architecture & current_arch_mask)
265 {
266 if (! (op1->architecture & current_arch_mask))
267 return -1;
268 }
269 else
270 {
271 if (op1->architecture & current_arch_mask)
272 return 1;
273 else if (op0->architecture != op1->architecture)
274 return op0->architecture - op1->architecture;
275 }
276
277 /* If a bit is set in both match and lose, there is something
278 wrong with the opcode table. */
279 if (match0 & lose0)
280 {
281 fprintf
282 (stderr,
283 /* xgettext:c-format */
284 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
285 op0->name, match0, lose0);
286 op0->lose &= ~op0->match;
287 lose0 = op0->lose;
288 }
289
290 if (match1 & lose1)
291 {
292 fprintf
293 (stderr,
294 /* xgettext:c-format */
295 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
296 op1->name, match1, lose1);
297 op1->lose &= ~op1->match;
298 lose1 = op1->lose;
299 }
300
301 /* Because the bits that are variable in one opcode are constant in
302 another, it is important to order the opcodes in the right order. */
303 for (i = 0; i < 32; ++i)
304 {
305 unsigned long int x = 1 << i;
306 int x0 = (match0 & x) != 0;
307 int x1 = (match1 & x) != 0;
308
309 if (x0 != x1)
310 return x1 - x0;
311 }
312
313 for (i = 0; i < 32; ++i)
314 {
315 unsigned long int x = 1 << i;
316 int x0 = (lose0 & x) != 0;
317 int x1 = (lose1 & x) != 0;
318
319 if (x0 != x1)
320 return x1 - x0;
321 }
322
323 /* They are functionally equal. So as long as the opcode table is
324 valid, we can put whichever one first we want, on aesthetic grounds. */
325
326 /* Our first aesthetic ground is that aliases defer to real insns. */
327 {
328 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
329
330 if (alias_diff != 0)
331 /* Put the one that isn't an alias first. */
332 return alias_diff;
333 }
334
335 /* Except for aliases, two "identical" instructions had
336 better have the same opcode. This is a sanity check on the table. */
337 i = strcmp (op0->name, op1->name);
338 if (i)
339 {
340 if (op0->flags & F_ALIAS)
341 {
342 if (op0->flags & F_PREFERRED)
343 return -1;
344 if (op1->flags & F_PREFERRED)
345 return 1;
346
347 /* If they're both aliases, and neither is marked as preferred,
348 be arbitrary. */
349 return i;
350 }
351 else
352 fprintf (stderr,
353 /* xgettext:c-format */
354 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
355 op0->name, op1->name);
356 }
357
358 /* Fewer arguments are preferred. */
359 {
360 int length_diff = strlen (op0->args) - strlen (op1->args);
361
362 if (length_diff != 0)
363 /* Put the one with fewer arguments first. */
364 return length_diff;
365 }
366
367 /* Put 1+i before i+1. */
368 {
369 char *p0 = (char *) strchr (op0->args, '+');
370 char *p1 = (char *) strchr (op1->args, '+');
371
372 if (p0 && p1)
373 {
374 /* There is a plus in both operands. Note that a plus
375 sign cannot be the first character in args,
376 so the following [-1]'s are valid. */
377 if (p0[-1] == 'i' && p1[1] == 'i')
378 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
379 return 1;
380 if (p0[1] == 'i' && p1[-1] == 'i')
381 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
382 return -1;
383 }
384 }
385
386 /* Put 1,i before i,1. */
387 {
388 int i0 = strncmp (op0->args, "i,1", 3) == 0;
389 int i1 = strncmp (op1->args, "i,1", 3) == 0;
390
391 if (i0 ^ i1)
392 return i0 - i1;
393 }
394
395 /* They are, as far as we can tell, identical.
396 Since qsort may have rearranged the table partially, there is
397 no way to tell which one was first in the opcode table as
398 written, so just say there are equal. */
399 /* ??? This is no longer true now that we sort a vector of pointers,
400 not the table itself. */
401 return 0;
402 }
403
404 /* Build a hash table from the opcode table.
405 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
406
407 static void
408 build_hash_table (const sparc_opcode **opcode_table,
409 sparc_opcode_hash **hash_table,
410 int num_opcodes)
411 {
412 int i;
413 int hash_count[HASH_SIZE];
414 static sparc_opcode_hash *hash_buf = NULL;
415
416 /* Start at the end of the table and work backwards so that each
417 chain is sorted. */
418
419 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
420 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
421 if (hash_buf != NULL)
422 free (hash_buf);
423 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
424 for (i = num_opcodes - 1; i >= 0; --i)
425 {
426 int hash = HASH_INSN (opcode_table[i]->match);
427 sparc_opcode_hash *h = &hash_buf[i];
428
429 h->next = hash_table[hash];
430 h->opcode = opcode_table[i];
431 hash_table[hash] = h;
432 ++hash_count[hash];
433 }
434
435 #if 0 /* for debugging */
436 {
437 int min_count = num_opcodes, max_count = 0;
438 int total;
439
440 for (i = 0; i < HASH_SIZE; ++i)
441 {
442 if (hash_count[i] < min_count)
443 min_count = hash_count[i];
444 if (hash_count[i] > max_count)
445 max_count = hash_count[i];
446 total += hash_count[i];
447 }
448
449 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
450 min_count, max_count, (double) total / HASH_SIZE);
451 }
452 #endif
453 }
454
455 /* Print one instruction from MEMADDR on INFO->STREAM.
456
457 We suffix the instruction with a comment that gives the absolute
458 address involved, as well as its symbolic form, if the instruction
459 is preceded by a findable `sethi' and it either adds an immediate
460 displacement to that register, or it is an `add' or `or' instruction
461 on that register. */
462
463 int
464 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
465 {
466 FILE *stream = info->stream;
467 bfd_byte buffer[4];
468 unsigned long insn;
469 sparc_opcode_hash *op;
470 /* Nonzero of opcode table has been initialized. */
471 static int opcodes_initialized = 0;
472 /* bfd mach number of last call. */
473 static unsigned long current_mach = 0;
474 bfd_vma (*getword) (const void *);
475
476 if (!opcodes_initialized
477 || info->mach != current_mach)
478 {
479 int i;
480
481 current_arch_mask = compute_arch_mask (info->mach);
482
483 if (!opcodes_initialized)
484 sorted_opcodes =
485 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
486 /* Reset the sorted table so we can resort it. */
487 for (i = 0; i < sparc_num_opcodes; ++i)
488 sorted_opcodes[i] = &sparc_opcodes[i];
489 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
490 sizeof (sorted_opcodes[0]), compare_opcodes);
491
492 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
493 current_mach = info->mach;
494 opcodes_initialized = 1;
495 }
496
497 {
498 int status =
499 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
500
501 if (status != 0)
502 {
503 (*info->memory_error_func) (status, memaddr, info);
504 return -1;
505 }
506 }
507
508 /* On SPARClite variants such as DANlite (sparc86x), instructions
509 are always big-endian even when the machine is in little-endian mode. */
510 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
511 getword = bfd_getb32;
512 else
513 getword = bfd_getl32;
514
515 insn = getword (buffer);
516
517 info->insn_info_valid = 1; /* We do return this info. */
518 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
519 info->branch_delay_insns = 0; /* Assume no delay. */
520 info->target = 0; /* Assume no target known. */
521
522 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
523 {
524 const sparc_opcode *opcode = op->opcode;
525
526 /* If the insn isn't supported by the current architecture, skip it. */
527 if (! (opcode->architecture & current_arch_mask))
528 continue;
529
530 if ((opcode->match & insn) == opcode->match
531 && (opcode->lose & insn) == 0)
532 {
533 /* Nonzero means that we have found an instruction which has
534 the effect of adding or or'ing the imm13 field to rs1. */
535 int imm_added_to_rs1 = 0;
536 int imm_ored_to_rs1 = 0;
537
538 /* Nonzero means that we have found a plus sign in the args
539 field of the opcode table. */
540 int found_plus = 0;
541
542 /* Nonzero means we have an annulled branch. */
543 int is_annulled = 0;
544
545 /* Do we have an `add' or `or' instruction combining an
546 immediate with rs1? */
547 if (opcode->match == 0x80102000) /* or */
548 imm_ored_to_rs1 = 1;
549 if (opcode->match == 0x80002000) /* add */
550 imm_added_to_rs1 = 1;
551
552 if (X_RS1 (insn) != X_RD (insn)
553 && strchr (opcode->args, 'r') != 0)
554 /* Can't do simple format if source and dest are different. */
555 continue;
556 if (X_RS2 (insn) != X_RD (insn)
557 && strchr (opcode->args, 'O') != 0)
558 /* Can't do simple format if source and dest are different. */
559 continue;
560
561 (*info->fprintf_func) (stream, "%s", opcode->name);
562
563 {
564 const char *s;
565
566 if (opcode->args[0] != ',')
567 (*info->fprintf_func) (stream, " ");
568
569 for (s = opcode->args; *s != '\0'; ++s)
570 {
571 while (*s == ',')
572 {
573 (*info->fprintf_func) (stream, ",");
574 ++s;
575 switch (*s)
576 {
577 case 'a':
578 (*info->fprintf_func) (stream, "a");
579 is_annulled = 1;
580 ++s;
581 continue;
582 case 'N':
583 (*info->fprintf_func) (stream, "pn");
584 ++s;
585 continue;
586
587 case 'T':
588 (*info->fprintf_func) (stream, "pt");
589 ++s;
590 continue;
591
592 default:
593 break;
594 }
595 }
596
597 (*info->fprintf_func) (stream, " ");
598
599 switch (*s)
600 {
601 case '+':
602 found_plus = 1;
603 /* Fall through. */
604
605 default:
606 (*info->fprintf_func) (stream, "%c", *s);
607 break;
608
609 case '#':
610 (*info->fprintf_func) (stream, "0");
611 break;
612
613 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
614 case '1':
615 case 'r':
616 reg (X_RS1 (insn));
617 break;
618
619 case '2':
620 case 'O':
621 reg (X_RS2 (insn));
622 break;
623
624 case 'd':
625 reg (X_RD (insn));
626 break;
627 #undef reg
628
629 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
630 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
631 case 'e':
632 freg (X_RS1 (insn));
633 break;
634 case 'v': /* Double/even. */
635 case 'V': /* Quad/multiple of 4. */
636 fregx (X_RS1 (insn));
637 break;
638
639 case 'f':
640 freg (X_RS2 (insn));
641 break;
642 case 'B': /* Double/even. */
643 case 'R': /* Quad/multiple of 4. */
644 fregx (X_RS2 (insn));
645 break;
646
647 case '4':
648 freg (X_RS3 (insn));
649 break;
650 case '5': /* Double/even. */
651 fregx (X_RS3 (insn));
652 break;
653
654 case 'g':
655 freg (X_RD (insn));
656 break;
657 case 'H': /* Double/even. */
658 case 'J': /* Quad/multiple of 4. */
659 fregx (X_RD (insn));
660 break;
661 #undef freg
662 #undef fregx
663
664 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
665 case 'b':
666 creg (X_RS1 (insn));
667 break;
668
669 case 'c':
670 creg (X_RS2 (insn));
671 break;
672
673 case 'D':
674 creg (X_RD (insn));
675 break;
676 #undef creg
677
678 case 'h':
679 (*info->fprintf_func) (stream, "%%hi(%#x)",
680 ((unsigned) 0xFFFFFFFF
681 & ((int) X_IMM22 (insn) << 10)));
682 break;
683
684 case 'i': /* 13 bit immediate. */
685 case 'I': /* 11 bit immediate. */
686 case 'j': /* 10 bit immediate. */
687 {
688 int imm;
689
690 if (*s == 'i')
691 imm = X_SIMM (insn, 13);
692 else if (*s == 'I')
693 imm = X_SIMM (insn, 11);
694 else
695 imm = X_SIMM (insn, 10);
696
697 /* Check to see whether we have a 1+i, and take
698 note of that fact.
699
700 Note: because of the way we sort the table,
701 we will be matching 1+i rather than i+1,
702 so it is OK to assume that i is after +,
703 not before it. */
704 if (found_plus)
705 imm_added_to_rs1 = 1;
706
707 if (imm <= 9)
708 (*info->fprintf_func) (stream, "%d", imm);
709 else
710 (*info->fprintf_func) (stream, "%#x", imm);
711 }
712 break;
713
714 case ')': /* 5 bit unsigned immediate from RS3. */
715 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
716 break;
717
718 case 'X': /* 5 bit unsigned immediate. */
719 case 'Y': /* 6 bit unsigned immediate. */
720 {
721 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
722
723 if (imm <= 9)
724 (info->fprintf_func) (stream, "%d", imm);
725 else
726 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
727 }
728 break;
729
730 case '3':
731 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
732 break;
733
734 case 'K':
735 {
736 int mask = X_MEMBAR (insn);
737 int bit = 0x40, printed_one = 0;
738 const char *name;
739
740 if (mask == 0)
741 (info->fprintf_func) (stream, "0");
742 else
743 while (bit)
744 {
745 if (mask & bit)
746 {
747 if (printed_one)
748 (info->fprintf_func) (stream, "|");
749 name = sparc_decode_membar (bit);
750 (info->fprintf_func) (stream, "%s", name);
751 printed_one = 1;
752 }
753 bit >>= 1;
754 }
755 break;
756 }
757
758 case '=':
759 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
760 (*info->print_address_func) (info->target, info);
761 break;
762
763 case 'k':
764 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
765 (*info->print_address_func) (info->target, info);
766 break;
767
768 case 'G':
769 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
770 (*info->print_address_func) (info->target, info);
771 break;
772
773 case '6':
774 case '7':
775 case '8':
776 case '9':
777 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
778 break;
779
780 case 'z':
781 (*info->fprintf_func) (stream, "%%icc");
782 break;
783
784 case 'Z':
785 (*info->fprintf_func) (stream, "%%xcc");
786 break;
787
788 case 'E':
789 (*info->fprintf_func) (stream, "%%ccr");
790 break;
791
792 case 's':
793 (*info->fprintf_func) (stream, "%%fprs");
794 break;
795
796 case 'o':
797 (*info->fprintf_func) (stream, "%%asi");
798 break;
799
800 case 'W':
801 (*info->fprintf_func) (stream, "%%tick");
802 break;
803
804 case 'P':
805 (*info->fprintf_func) (stream, "%%pc");
806 break;
807
808 case '?':
809 if (X_RS1 (insn) == 31)
810 (*info->fprintf_func) (stream, "%%ver");
811 else if ((unsigned) X_RS1 (insn) < 17)
812 (*info->fprintf_func) (stream, "%%%s",
813 v9_priv_reg_names[X_RS1 (insn)]);
814 else
815 (*info->fprintf_func) (stream, "%%reserved");
816 break;
817
818 case '!':
819 if ((unsigned) X_RD (insn) < 17)
820 (*info->fprintf_func) (stream, "%%%s",
821 v9_priv_reg_names[X_RD (insn)]);
822 else
823 (*info->fprintf_func) (stream, "%%reserved");
824 break;
825
826 case '$':
827 if ((unsigned) X_RS1 (insn) < 32)
828 (*info->fprintf_func) (stream, "%%%s",
829 v9_hpriv_reg_names[X_RS1 (insn)]);
830 else
831 (*info->fprintf_func) (stream, "%%reserved");
832 break;
833
834 case '%':
835 if ((unsigned) X_RD (insn) < 32)
836 (*info->fprintf_func) (stream, "%%%s",
837 v9_hpriv_reg_names[X_RD (insn)]);
838 else
839 (*info->fprintf_func) (stream, "%%reserved");
840 break;
841
842 case '/':
843 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
844 (*info->fprintf_func) (stream, "%%reserved");
845 else
846 (*info->fprintf_func) (stream, "%%%s",
847 v9a_asr_reg_names[X_RS1 (insn)-16]);
848 break;
849
850 case '_':
851 if (X_RD (insn) < 16 || X_RD (insn) > 28)
852 (*info->fprintf_func) (stream, "%%reserved");
853 else
854 (*info->fprintf_func) (stream, "%%%s",
855 v9a_asr_reg_names[X_RD (insn)-16]);
856 break;
857
858 case '*':
859 {
860 const char *name = sparc_decode_prefetch (X_RD (insn));
861
862 if (name)
863 (*info->fprintf_func) (stream, "%s", name);
864 else
865 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
866 break;
867 }
868
869 case 'M':
870 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
871 break;
872
873 case 'm':
874 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
875 break;
876
877 case 'L':
878 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
879 (*info->print_address_func) (info->target, info);
880 break;
881
882 case 'n':
883 (*info->fprintf_func)
884 (stream, "%#x", SEX (X_DISP22 (insn), 22));
885 break;
886
887 case 'l':
888 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
889 (*info->print_address_func) (info->target, info);
890 break;
891
892 case 'A':
893 {
894 const char *name = sparc_decode_asi (X_ASI (insn));
895
896 if (name)
897 (*info->fprintf_func) (stream, "%s", name);
898 else
899 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
900 break;
901 }
902
903 case 'C':
904 (*info->fprintf_func) (stream, "%%csr");
905 break;
906
907 case 'F':
908 (*info->fprintf_func) (stream, "%%fsr");
909 break;
910
911 case '(':
912 (*info->fprintf_func) (stream, "%%efsr");
913 break;
914
915 case 'p':
916 (*info->fprintf_func) (stream, "%%psr");
917 break;
918
919 case 'q':
920 (*info->fprintf_func) (stream, "%%fq");
921 break;
922
923 case 'Q':
924 (*info->fprintf_func) (stream, "%%cq");
925 break;
926
927 case 't':
928 (*info->fprintf_func) (stream, "%%tbr");
929 break;
930
931 case 'w':
932 (*info->fprintf_func) (stream, "%%wim");
933 break;
934
935 case 'x':
936 (*info->fprintf_func) (stream, "%ld",
937 ((X_LDST_I (insn) << 8)
938 + X_ASI (insn)));
939 break;
940
941 case 'y':
942 (*info->fprintf_func) (stream, "%%y");
943 break;
944
945 case 'u':
946 case 'U':
947 {
948 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
949 const char *name = sparc_decode_sparclet_cpreg (val);
950
951 if (name)
952 (*info->fprintf_func) (stream, "%s", name);
953 else
954 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
955 break;
956 }
957 }
958 }
959 }
960
961 /* If we are adding or or'ing something to rs1, then
962 check to see whether the previous instruction was
963 a sethi to the same register as in the sethi.
964 If so, attempt to print the result of the add or
965 or (in this context add and or do the same thing)
966 and its symbolic value. */
967 if (imm_ored_to_rs1 || imm_added_to_rs1)
968 {
969 unsigned long prev_insn;
970 int errcode;
971
972 if (memaddr >= 4)
973 errcode =
974 (*info->read_memory_func)
975 (memaddr - 4, buffer, sizeof (buffer), info);
976 else
977 errcode = 1;
978
979 prev_insn = getword (buffer);
980
981 if (errcode == 0)
982 {
983 /* If it is a delayed branch, we need to look at the
984 instruction before the delayed branch. This handles
985 sequences such as:
986
987 sethi %o1, %hi(_foo), %o1
988 call _printf
989 or %o1, %lo(_foo), %o1 */
990
991 if (is_delayed_branch (prev_insn))
992 {
993 if (memaddr >= 8)
994 errcode = (*info->read_memory_func)
995 (memaddr - 8, buffer, sizeof (buffer), info);
996 else
997 errcode = 1;
998
999 prev_insn = getword (buffer);
1000 }
1001 }
1002
1003 /* If there was a problem reading memory, then assume
1004 the previous instruction was not sethi. */
1005 if (errcode == 0)
1006 {
1007 /* Is it sethi to the same register? */
1008 if ((prev_insn & 0xc1c00000) == 0x01000000
1009 && X_RD (prev_insn) == X_RS1 (insn))
1010 {
1011 (*info->fprintf_func) (stream, "\t! ");
1012 info->target =
1013 ((unsigned) 0xFFFFFFFF
1014 & ((int) X_IMM22 (prev_insn) << 10));
1015 if (imm_added_to_rs1)
1016 info->target += X_SIMM (insn, 13);
1017 else
1018 info->target |= X_SIMM (insn, 13);
1019 (*info->print_address_func) (info->target, info);
1020 info->insn_type = dis_dref;
1021 info->data_size = 4; /* FIXME!!! */
1022 }
1023 }
1024 }
1025
1026 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1027 {
1028 /* FIXME -- check is_annulled flag. */
1029 (void) is_annulled;
1030 if (opcode->flags & F_UNBR)
1031 info->insn_type = dis_branch;
1032 if (opcode->flags & F_CONDBR)
1033 info->insn_type = dis_condbranch;
1034 if (opcode->flags & F_JSR)
1035 info->insn_type = dis_jsr;
1036 if (opcode->flags & F_DELAYED)
1037 info->branch_delay_insns = 1;
1038 }
1039
1040 return sizeof (buffer);
1041 }
1042 }
1043
1044 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1045 (*info->fprintf_func) (stream, _("unknown"));
1046 return sizeof (buffer);
1047 }
GDB Binutils - Deliverables
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