1 /* Disassembly routines for TMS320C30 architecture
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/tic30.h"
28 #define PARALLEL_INSN 2
30 /* Gets the type of instruction based on the top 2 or 3 bits of the
32 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
34 /* Instruction types. */
35 #define TWO_OPERAND_1 0x00000000
36 #define TWO_OPERAND_2 0x40000000
37 #define THREE_OPERAND 0x20000000
38 #define PAR_STORE 0xC0000000
39 #define MUL_ADDS 0x80000000
40 #define BRANCHES 0x60000000
42 /* Specific instruction id bits. */
43 #define NORMAL_IDEN 0x1F800000
44 #define PAR_STORE_IDEN 0x3E000000
45 #define MUL_ADD_IDEN 0x2C000000
46 #define BR_IMM_IDEN 0x1F000000
47 #define BR_COND_IDEN 0x1C3F0000
49 /* Addressing modes. */
50 #define AM_REGISTER 0x00000000
51 #define AM_DIRECT 0x00200000
52 #define AM_INDIRECT 0x00400000
53 #define AM_IMM 0x00600000
55 #define P_FIELD 0x03000000
58 #define LDP_INSN 0x08700000
60 /* TMS320C30 program counter for current instruction. */
61 static unsigned int _pc
;
70 int get_tic30_instruction
PARAMS ((unsigned long, struct instruction
*));
72 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
73 int print_three_operand
74 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
76 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
78 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
79 int get_indirect_operand
PARAMS ((unsigned short, int, char *));
80 int get_register_operand
PARAMS ((unsigned char, char *));
81 int cnvt_tmsfloat_ieee
PARAMS ((unsigned long, int, float *));
84 print_insn_tic30 (pc
, info
)
86 disassemble_info
*info
;
88 unsigned long insn_word
;
89 struct instruction insn
=
91 bfd_vma bufaddr
= pc
- info
->buffer_vma
;
92 /* Obtain the current instruction word from the buffer. */
93 insn_word
= (*(info
->buffer
+ bufaddr
) << 24) | (*(info
->buffer
+ bufaddr
+ 1) << 16) |
94 (*(info
->buffer
+ bufaddr
+ 2) << 8) | *(info
->buffer
+ bufaddr
+ 3);
96 /* Get the instruction refered to by the current instruction word
97 and print it out based on its type. */
98 if (!get_tic30_instruction (insn_word
, &insn
))
100 switch (GET_TYPE (insn_word
))
104 if (!print_two_operand (info
, insn_word
, &insn
))
108 if (!print_three_operand (info
, insn_word
, &insn
))
113 if (!print_par_insn (info
, insn_word
, &insn
))
117 if (!print_branch (info
, insn_word
, &insn
))
125 get_tic30_instruction (insn_word
, insn
)
126 unsigned long insn_word
;
127 struct instruction
*insn
;
129 switch (GET_TYPE (insn_word
))
134 insn
->type
= NORMAL_INSN
;
136 template *current_optab
= (template *) tic30_optab
;
137 for (; current_optab
< tic30_optab_end
; current_optab
++)
139 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
141 if (current_optab
->operands
== 0)
143 if (current_optab
->base_opcode
== insn_word
)
145 insn
->tm
= current_optab
;
149 else if ((current_optab
->base_opcode
& NORMAL_IDEN
) == (insn_word
& NORMAL_IDEN
))
151 insn
->tm
= current_optab
;
159 insn
->type
= PARALLEL_INSN
;
161 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
162 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
164 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
166 if ((current_optab
->base_opcode
& PAR_STORE_IDEN
) == (insn_word
& PAR_STORE_IDEN
))
168 insn
->ptm
= current_optab
;
176 insn
->type
= PARALLEL_INSN
;
178 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
179 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
181 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
183 if ((current_optab
->base_opcode
& MUL_ADD_IDEN
) == (insn_word
& MUL_ADD_IDEN
))
185 insn
->ptm
= current_optab
;
193 insn
->type
= NORMAL_INSN
;
195 template *current_optab
= (template *) tic30_optab
;
196 for (; current_optab
< tic30_optab_end
; current_optab
++)
198 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
200 if (current_optab
->operand_types
[0] & Imm24
)
202 if ((current_optab
->base_opcode
& BR_IMM_IDEN
) == (insn_word
& BR_IMM_IDEN
))
204 insn
->tm
= current_optab
;
208 else if (current_optab
->operands
> 0)
210 if ((current_optab
->base_opcode
& BR_COND_IDEN
) == (insn_word
& BR_COND_IDEN
))
212 insn
->tm
= current_optab
;
218 if ((current_optab
->base_opcode
& (BR_COND_IDEN
| 0x00800000)) == (insn_word
& (BR_COND_IDEN
| 0x00800000)))
220 insn
->tm
= current_optab
;
235 print_two_operand (info
, insn_word
, insn
)
236 disassemble_info
*info
;
237 unsigned long insn_word
;
238 struct instruction
*insn
;
241 char operand
[2][13] =
247 if (insn
->tm
== NULL
)
249 strcpy (name
, insn
->tm
->name
);
250 if (insn
->tm
->opcode_modifier
== AddressMode
)
253 /* Determine whether instruction is a store or a normal instruction. */
254 if ((insn
->tm
->operand_types
[1] & (Direct
| Indirect
)) == (Direct
| Indirect
))
264 /* Get the destination register. */
265 if (insn
->tm
->operands
== 2)
266 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[dest_op
]);
267 /* Get the source operand based on addressing mode. */
268 switch (insn_word
& AddressMode
)
271 /* Check for the NOP instruction before getting the operand. */
272 if ((insn
->tm
->operand_types
[0] & NotReq
) == 0)
273 get_register_operand ((insn_word
& 0x0000001F), operand
[src_op
]);
276 sprintf (operand
[src_op
], "@0x%lX", (insn_word
& 0x0000FFFF));
279 get_indirect_operand ((insn_word
& 0x0000FFFF), 2, operand
[src_op
]);
282 /* Get the value of the immediate operand based on variable type. */
283 switch (insn
->tm
->imm_arg_type
)
286 cnvt_tmsfloat_ieee ((insn_word
& 0x0000FFFF), 2, &f_number
);
287 sprintf (operand
[src_op
], "%2.2f", f_number
);
290 sprintf (operand
[src_op
], "%d", (short) (insn_word
& 0x0000FFFF));
293 sprintf (operand
[src_op
], "%lu", (insn_word
& 0x0000FFFF));
298 /* Handle special case for LDP instruction. */
299 if ((insn_word
& 0xFFFFFF00) == LDP_INSN
)
301 strcpy (name
, "ldp");
302 sprintf (operand
[0], "0x%06lX", (insn_word
& 0x000000FF) << 16);
303 operand
[1][0] = '\0';
307 /* Handle case for stack and rotate instructions. */
308 else if (insn
->tm
->operands
== 1)
310 if (insn
->tm
->opcode_modifier
== StackOp
)
312 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[0]);
315 /* Output instruction to stream. */
316 info
->fprintf_func (info
->stream
, " %s %s%c%s", name
,
317 operand
[0][0] ? operand
[0] : "",
318 operand
[1][0] ? ',' : ' ',
319 operand
[1][0] ? operand
[1] : "");
324 print_three_operand (info
, insn_word
, insn
)
325 disassemble_info
*info
;
326 unsigned long insn_word
;
327 struct instruction
*insn
;
329 char operand
[3][13] =
335 if (insn
->tm
== NULL
)
337 switch (insn_word
& AddressMode
)
340 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
341 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
344 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
345 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
348 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
349 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
352 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
353 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
358 if (insn
->tm
->operands
== 3)
359 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[2]);
360 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", insn
->tm
->name
,
361 operand
[0], operand
[1],
362 operand
[2][0] ? ',' : ' ',
363 operand
[2][0] ? operand
[2] : "");
368 print_par_insn (info
, insn_word
, insn
)
369 disassemble_info
*info
;
370 unsigned long insn_word
;
371 struct instruction
*insn
;
375 char operand
[2][3][13] =
386 if (insn
->ptm
== NULL
)
388 /* Parse out the names of each of the parallel instructions from the
389 q_insn1_insn2 format. */
390 name1
= (char *) strdup (insn
->ptm
->name
+ 2);
392 len
= strlen (name1
);
393 for (i
= 0; i
< len
; i
++)
397 name2
= &name1
[i
+ 1];
402 /* Get the operands of the instruction based on the operand order. */
403 switch (insn
->ptm
->oporder
)
406 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
407 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
408 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
409 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
412 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
413 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
414 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][1]);
415 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
418 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
419 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
420 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
421 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][0]);
424 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
425 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
426 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
427 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
428 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
431 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
432 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
433 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
434 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
435 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
438 if (insn_word
& 0x00800000)
439 get_register_operand (0x01, operand
[0][2]);
441 get_register_operand (0x00, operand
[0][2]);
442 if (insn_word
& 0x00400000)
443 get_register_operand (0x03, operand
[1][2]);
445 get_register_operand (0x02, operand
[1][2]);
446 switch (insn_word
& P_FIELD
)
449 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
450 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
451 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
452 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][0]);
455 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][0]);
456 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
457 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
458 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
461 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
462 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
463 get_register_operand ((insn_word
>> 16) & 0x07, operand
[0][1]);
464 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
467 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
468 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
469 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
470 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
477 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", name1
,
478 operand
[0][0], operand
[0][1],
479 operand
[0][2][0] ? ',' : ' ',
480 operand
[0][2][0] ? operand
[0][2] : "");
481 info
->fprintf_func (info
->stream
, "\n\t\t\t|| %s %s,%s%c%s", name2
,
482 operand
[1][0], operand
[1][1],
483 operand
[1][2][0] ? ',' : ' ',
484 operand
[1][2][0] ? operand
[1][2] : "");
490 print_branch (info
, insn_word
, insn
)
491 disassemble_info
*info
;
492 unsigned long insn_word
;
493 struct instruction
*insn
;
495 char operand
[2][13] =
499 unsigned long address
;
502 if (insn
->tm
== NULL
)
504 /* Get the operands for 24-bit immediate jumps. */
505 if (insn
->tm
->operand_types
[0] & Imm24
)
507 address
= insn_word
& 0x00FFFFFF;
508 sprintf (operand
[0], "0x%lX", address
);
511 /* Get the operand for the trap instruction. */
512 else if (insn
->tm
->operand_types
[0] & IVector
)
514 address
= insn_word
& 0x0000001F;
515 sprintf (operand
[0], "0x%lX", address
);
519 address
= insn_word
& 0x0000FFFF;
520 /* Get the operands for the DB instructions. */
521 if (insn
->tm
->operands
== 2)
523 get_register_operand (((insn_word
& 0x01C00000) >> 22) + REG_AR0
, operand
[0]);
524 if (insn_word
& PCRel
)
526 sprintf (operand
[1], "%d", (short) address
);
530 get_register_operand (insn_word
& 0x0000001F, operand
[1]);
532 /* Get the operands for the standard branches. */
533 else if (insn
->tm
->operands
== 1)
535 if (insn_word
& PCRel
)
537 address
= (short) address
;
538 sprintf (operand
[0], "%ld", address
);
542 get_register_operand (insn_word
& 0x0000001F, operand
[0]);
545 info
->fprintf_func (info
->stream
, " %s %s%c%s", insn
->tm
->name
,
546 operand
[0][0] ? operand
[0] : "",
547 operand
[1][0] ? ',' : ' ',
548 operand
[1][0] ? operand
[1] : "");
549 /* Print destination of branch in relation to current symbol. */
550 if (print_label
&& info
->symbols
)
552 asymbol
*sym
= *info
->symbols
;
554 if ((insn
->tm
->opcode_modifier
== PCRel
) && (insn_word
& PCRel
))
556 address
= (_pc
+ 1 + (short) address
) - ((sym
->section
->vma
+ sym
->value
) / 4);
557 /* Check for delayed instruction, if so adjust destination. */
558 if (insn_word
& 0x00200000)
563 address
-= ((sym
->section
->vma
+ sym
->value
) / 4);
566 info
->fprintf_func (info
->stream
, " <%s>", sym
->name
);
568 info
->fprintf_func (info
->stream
, " <%s %c %d>", sym
->name
,
569 ((short) address
< 0) ? '-' : '+',
576 get_indirect_operand (fragment
, size
, buffer
)
577 unsigned short fragment
;
587 /* Determine which bits identify the sections of the indirect operand based on the
592 mod
= (fragment
& 0x00F8) >> 3;
593 arnum
= (fragment
& 0x0007);
597 mod
= (fragment
& 0xF800) >> 11;
598 arnum
= (fragment
& 0x0700) >> 8;
599 disp
= (fragment
& 0x00FF);
605 const ind_addr_type
*current_ind
= tic30_indaddr_tab
;
606 for (; current_ind
< tic30_indaddrtab_end
; current_ind
++)
608 if (current_ind
->modfield
== mod
)
610 if (current_ind
->displacement
== IMPLIED_DISP
&& size
== 2)
619 len
= strlen (current_ind
->syntax
);
620 for (i
= 0, bufcnt
= 0; i
< len
; i
++, bufcnt
++)
622 buffer
[bufcnt
] = current_ind
->syntax
[i
];
623 if (buffer
[bufcnt
- 1] == 'a' && buffer
[bufcnt
] == 'r')
624 buffer
[++bufcnt
] = arnum
+ '0';
625 if (buffer
[bufcnt
] == '(' && current_ind
->displacement
== DISP_REQUIRED
)
627 sprintf (&buffer
[bufcnt
+ 1], "%u", disp
);
628 bufcnt
+= strlen (&buffer
[bufcnt
+ 1]);
631 buffer
[bufcnt
+ 1] = '\0';
641 get_register_operand (fragment
, buffer
)
642 unsigned char fragment
;
645 const reg
*current_reg
= tic30_regtab
;
649 for (; current_reg
< tic30_regtab_end
; current_reg
++)
651 if ((fragment
& 0x1F) == current_reg
->opcode
)
653 strcpy (buffer
, current_reg
->name
);
661 cnvt_tmsfloat_ieee (tmsfloat
, size
, ieeefloat
)
662 unsigned long tmsfloat
;
666 unsigned long exp
, sign
, mant
;
670 if ((tmsfloat
& 0x0000F000) == 0x00008000)
671 tmsfloat
= 0x80000000;
675 tmsfloat
= (long) tmsfloat
>> 4;
678 exp
= tmsfloat
& 0xFF000000;
679 if (exp
== 0x80000000)
685 sign
= (tmsfloat
& 0x00800000) << 8;
686 mant
= tmsfloat
& 0x007FFFFF;
687 if (exp
== 0xFF000000)
692 *ieeefloat
= 1.0 / 0.0;
694 *ieeefloat
= -1.0 / 0.0;
700 mant
= (~mant
) & 0x007FFFFF;
702 exp
+= mant
& 0x00800000;
706 if (tmsfloat
== 0x80000000)
707 sign
= mant
= exp
= 0;
708 tmsfloat
= sign
| exp
| mant
;
709 *ieeefloat
= *((float *) &tmsfloat
);
This page took 0.045 seconds and 5 git commands to generate.