opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* regular opcode */
   5 #define OP(x)           ((x & 0x3f) << 5)
   6 #define OP_MASK         OP(0x3f)
   7
   8 /* conditional branch opcode */
   9 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  10 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  11
  12 /* one-word opcodes */
  13 #define one(x)          ((unsigned int) (x))
  14
  15 /* two-word opcodes */
  16 #define two(x,y)        ((unsigned int) (y) | ((unsigned int) (x) << 16))
  17
  18
  19 \f
  20 const struct v850_operand v850_operands[] = {
  21 #define UNUSED  0
  22   { 0, 0, 0 },
  23
  24 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  25 #define R1      (UNUSED+1)
  26   { 5, 0, OPERAND_REG },
  27
  28 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  29 #define R2      (R1+1)
  30   { 5, 11, OPERAND_REG },
  31
  32 /* The IMM5 field in a format 2 insn. */
  33 #define I5      (R2+1)
  34   { 5, 0, OPERAND_NUM },
  35
  36 #define IMM16 field in a format 6 insn. */
  37 #define I16     (I5+1)
  38   { 16, 0, OPERAND_NUM },
  39
  40 /* The DISP6 field in a format 4 insn. */
  41 #define D6      (I16+1)
  42   { 6, 1, OPERAND_NUM },
  43
  44 /* The DISP8 field in a format 3 insn. */
  45 #define D8      (D6+1)
  46   { 9, 0, OPERAND_NUM },
  47
  48 /* The DISP16 field in a format 6 insn. */
  49 #define D16     (D8+1)
  50   { 16, 0, OPERAND_NUM },
  51
  52 /* The DISP22 field in a format 4 insn. */
  53 #define D22     (D16+1)
  54   { 16, 0, OPERAND_NUM },
  55
  56 #define B3      (D22+1)
  57 /* The 3 bit immediate field in format 8 insn.  */
  58   { 3, 27, OPERAND_NUM }
  59 } ;
  60
  61 \f
  62 /* reg-reg instruction format (Format I) */
  63 #define IF1     {R1, R2}
  64
  65 /* imm-reg instruction format (Format II) */
  66 #define IF2     {I5, R2}
  67
  68 /* conditional branch instruction format (Format III) */
  69 #define IF3     {D8}
  70
  71 /* 16-bit load/store instruction (Format IV) */
  72 #define IF4     {D6}
  73
  74 /* Jump instruction (Format V) */
  75 #define IF5     {D22}
  76
  77 /* 3 operand instruction (Format VI) */
  78 #define IF6     {R1, R2, I16}
  79
  80 /* 32-bit load/store instruction (Format VII) */
  81 #define IF7     {R1, R2, D16}
  82
  83 /* Bit manipulation function.  */
  84
  85
  86 \f
  87 /* The opcode table.
  88
  89    The format of the opcode table is:
  90
  91    NAME         OPCODE          MASK            { OPERANDS }
  92
  93    NAME is the name of the instruction.
  94    OPCODE is the instruction opcode.
  95    MASK is the opcode mask; this is used to tell the disassembler
  96      which bits in the actual opcode must match OPCODE.
  97    OPERANDS is the list of operands.
  98
  99    The disassembler reads the table in order and prints the first
 100    instruction which matches, so this table is sorted to put more
 101    specific instructions before more general instructions.  It is also
 102    sorted by major opcode.  */
 103
 104 const struct v850_opcode v850_opcodes[] = {
 105 /* load/store instructions */
 106 /* XXX */
 107
 108 /* arithmetic operation instructions */
 109 { "mov",        OP(0x00),               OP_MASK,        IF1 },
 110 { "mov",        OP(0x08),               OP_MASK,        IF2 },
 111 { "movea",      OP(0x31),               OP_MASK,        IF6 },
 112 { "movhi",      OP(0x31),               OP_MASK,        IF6 },
 113 { "add",        OP(0x0e),               OP_MASK,        IF1 },
 114 { "add",        OP(0x12),               OP_MASK,        IF2 },
 115 { "addi",       OP(0x30),               OP_MASK,        IF6 },
 116 { "sub",        OP(0x0d),               OP_MASK,        IF1 },
 117 { "subr",       OP(0x0c),               OP_MASK,        IF1 },
 118 { "mulh",       OP(0x07),               OP_MASK,        IF1 },
 119 { "mulh",       OP(0x17),               OP_MASK,        IF2 },
 120 { "mulhi",      OP(0x37),               OP_MASK,        IF6 },
 121 { "divh",       OP(0x02),               OP_MASK,        IF1 },
 122 { "cmp",        OP(0x0f),               OP_MASK,        IF1 },
 123 { "cmp",        OP(0x13),               OP_MASK,        IF2 },
 124 /* XXX missing setf */
 125
 126 /* saturated operation instructions */
 127 { "satadd",     OP(0x06),               OP_MASK,        IF1 },
 128 { "satadd",     OP(0x11),               OP_MASK,        IF2 },
 129 { "satsub",     OP(0x05),               OP_MASK,        IF1 },
 130 { "satsubi",    OP(0x33),               OP_MASK,        IF6 },
 131 { "satsubr",    OP(0x04),               OP_MASK,        IF1 },
 132
 133 /* logical operation instructions */
 134 { "tst",        OP(0x0b),               OP_MASK,        IF1 },
 135 { "or",         OP(0x08),               OP_MASK,        IF1 },
 136 { "ori",        OP(0x34),               OP_MASK,        IF6 },
 137 { "and",        OP(0x0a),               OP_MASK,        IF1 },
 138 { "andi",       OP(0x36),               OP_MASK,        IF6 },
 139 { "xor",        OP(0x09),               OP_MASK,        IF1 },
 140 { "xori",       OP(0x35),               OP_MASK,        IF6 },
 141 { "not",        OP(0x01),               OP_MASK,        IF1 },
 142 { "sar",        OP(0x15),               OP_MASK,        IF2 },
 143 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2} },
 144 { "shl",        OP(0x16),               OP_MASK,                IF2 },
 145 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2} },
 146 { "shr",        OP(0x14),               OP_MASK,                IF2 },
 147 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2} },
 148
 149 /* branch instructions */
 150         /* signed integer */
 151 { "bgt",        BOP(0xf),               BOP_MASK,       IF3 },
 152 { "bge",        BOP(0xe),               BOP_MASK,       IF3 },
 153 { "blt",        BOP(0x6),               BOP_MASK,       IF3 },
 154 { "ble",        BOP(0x7),               BOP_MASK,       IF3 },
 155         /* unsigned integer */
 156 { "bh",         BOP(0xb),               BOP_MASK,       IF3 },
 157 { "bnh",        BOP(0x3),               BOP_MASK,       IF3 },
 158 { "bl",         BOP(0x1),               BOP_MASK,       IF3 },
 159 { "bnl",        BOP(0x9),               BOP_MASK,       IF3 },
 160         /* common */
 161 { "be",         BOP(0x2),               BOP_MASK,       IF3 },
 162 { "bne",        BOP(0xa),               BOP_MASK,       IF3 },
 163         /* others */
 164 { "bv",         BOP(0x0),               BOP_MASK,       IF3 },
 165 { "bnv",        BOP(0x8),               BOP_MASK,       IF3 },
 166 { "bn",         BOP(0x4),               BOP_MASK,       IF3 },
 167 { "bp",         BOP(0xc),               BOP_MASK,       IF3 },
 168 { "bc",         BOP(0x1),               BOP_MASK,       IF3 },
 169 { "bnc",        BOP(0x9),               BOP_MASK,       IF3 },
 170 { "bz",         BOP(0x2),               BOP_MASK,       IF3 },
 171 { "bnz",        BOP(0xa),               BOP_MASK,       IF3 },
 172 { "br",         BOP(0x5),               BOP_MASK,       IF3 },
 173 { "bsa",        BOP(0xd),               BOP_MASK,       IF3 },
 174
 175 { "jmp",        one(0x0060),            one(0xffe0),    R1 },
 176 { "jarl",       one(0x0780),            one(0xf83f),    { R2,D22 } },
 177 { "jr",         one(0x0780),            one(0xffe0),    { D22 } },
 178
 179 /* bit manipulation instructions */
 180 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, R1, D16} },
 181 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, R1, D16} },
 182 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, R1, D16} },
 183 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, R1, D16} },
 184
 185 /* special instructions */
 186 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0} },
 187 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0} },
 188 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0} },
 189 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0} },
 190 #if 0
 191 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5} },
 192 #endif
 193 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {0} },
 194 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {0} },
 195 { "nop",        one(0x00),              one(0xff),              {0} },
 196
 197 } ;
 198
 199 const int v850_num_opcodes =
 200   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 201