opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* Local insertion and extraction functions.  */
   5 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
   6 static long extract_d9 PARAMS ((unsigned long, int *));
   7
   8 /* regular opcode */
   9 #define OP(x)           ((x & 0x3f) << 5)
  10 #define OP_MASK         OP(0x3f)
  11
  12 /* conditional branch opcode */
  13 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  14 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  15
  16 /* one-word opcodes */
  17 #define one(x)          ((unsigned int) (x))
  18
  19 /* two-word opcodes */
  20 #define two(x,y)        ((unsigned int) (y) | ((unsigned int) (x) << 16))
  21
  22
  23 \f
  24 const struct v850_operand v850_operands[] = {
  25 #define UNUSED  0
  26   { 0, 0, 0, 0, 0 },
  27
  28 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  29 #define R1      (UNUSED+1)
  30   { 5, 0, 0, 0, V850_OPERAND_REG },
  31
  32 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  33 #define R2      (R1+1)
  34   { 5, 11, 0, 0, V850_OPERAND_REG },
  35
  36 /* The IMM5 field in a format 2 insn. */
  37 #define I5      (R2+1)
  38   { 5, 0, 0, 0, 0 },
  39
  40 /* The IMM16 field in a format 6 insn. */
  41 #define I16     (I5+1)
  42   { 16, 0, 0, 0, 0 },
  43
  44 /* The DISP6 field in a format 4 insn. */
  45 #define D6      (I16+1)
  46   { 6, 1, 0, 0, 0 },
  47
  48 /* The DISP9 field in a format 3 insn. */
  49 #define D9      (D6+1)
  50   { 0, 0, insert_d9, extract_d9, 0 },
  51
  52 /* The DISP16 field in a format 6 insn. */
  53 #define D16     (D9+1)
  54   { 16, 0, 0, 0, 0 },
  55
  56 /* The DISP22 field in a format 4 insn. */
  57 #define D22     (D16+1)
  58   { 16, 0, 0, 0, 0 },
  59
  60 #define B3      (D22+1)
  61 /* The 3 bit immediate field in format 8 insn.  */
  62   { 3, 11, 0, 0, 0 },
  63
  64 #define CCCC    (B3+1)
  65 /* The 4 bit condition code in a setf instruction */
  66   { 4, 0, 0, 0, V850_OPERAND_CC }
  67 } ;
  68
  69 \f
  70 /* reg-reg instruction format (Format I) */
  71 #define IF1     {R1, R2}
  72
  73 /* imm-reg instruction format (Format II) */
  74 #define IF2     {I5, R2}
  75
  76 /* conditional branch instruction format (Format III) */
  77 #define IF3     {D9}
  78
  79 /* 16-bit load/store instruction (Format IV) */
  80 #define IF4A    {D6, R2}
  81 #define IF4B    {R2, D6}
  82
  83 /* Jump instruction (Format V) */
  84 #define IF5     {D22}
  85
  86 /* 3 operand instruction (Format VI) */
  87 #define IF6     {I16, R1, R2}
  88
  89 /* 32-bit load/store instruction (Format VII) */
  90 #define IF7A    {D16, R1, R2}
  91 #define IF7B    {R2, D16, R1}
  92
  93 /* Bit manipulation function.  */
  94
  95
  96 \f
  97 /* The opcode table.
  98
  99    The format of the opcode table is:
 100
 101    NAME         OPCODE          MASK            { OPERANDS }
 102
 103    NAME is the name of the instruction.
 104    OPCODE is the instruction opcode.
 105    MASK is the opcode mask; this is used to tell the disassembler
 106      which bits in the actual opcode must match OPCODE.
 107    OPERANDS is the list of operands.
 108
 109    The disassembler reads the table in order and prints the first
 110    instruction which matches, so this table is sorted to put more
 111    specific instructions before more general instructions.  It is also
 112    sorted by major opcode.  */
 113
 114 const struct v850_opcode v850_opcodes[] = {
 115 /* load/store instructions */
 116 { "sld.b",      OP(0x00),               OP_MASK,        IF4A },
 117 { "sld.h",      OP(0x00),               OP_MASK,        IF4A },
 118 { "sld.w",      OP(0x00),               OP_MASK,        IF4A },
 119 { "sst.b",      OP(0x00),               OP_MASK,        IF4B },
 120 { "sst.h",      OP(0x00),               OP_MASK,        IF4B },
 121 { "sst.w",      OP(0x00),               OP_MASK,        IF4B },
 122
 123 { "ld.b",       OP(0x00),               OP_MASK,        IF7A },
 124 { "ld.h",       OP(0x00),               OP_MASK,        IF7A },
 125 { "ld.w",       OP(0x00),               OP_MASK,        IF7A },
 126 { "st.b",       OP(0x00),               OP_MASK,        IF7B },
 127 { "st.h",       OP(0x00),               OP_MASK,        IF7B },
 128 { "st.w",       OP(0x00),               OP_MASK,        IF7B },
 129
 130 /* arithmetic operation instructions */
 131 { "mov",        OP(0x00),               OP_MASK,        IF1 },
 132 { "mov",        OP(0x08),               OP_MASK,        IF2 },
 133 { "movea",      OP(0x31),               OP_MASK,        IF6 },
 134 { "movhi",      OP(0x31),               OP_MASK,        IF6 },
 135 { "add",        OP(0x0e),               OP_MASK,        IF1 },
 136 { "add",        OP(0x12),               OP_MASK,        IF2 },
 137 { "addi",       OP(0x30),               OP_MASK,        IF6 },
 138 { "sub",        OP(0x0d),               OP_MASK,        IF1 },
 139 { "subr",       OP(0x0c),               OP_MASK,        IF1 },
 140 { "mulh",       OP(0x07),               OP_MASK,        IF1 },
 141 { "mulh",       OP(0x17),               OP_MASK,        IF2 },
 142 { "mulhi",      OP(0x37),               OP_MASK,        IF6 },
 143 { "divh",       OP(0x02),               OP_MASK,        IF1 },
 144 { "cmp",        OP(0x0f),               OP_MASK,        IF1 },
 145 { "cmp",        OP(0x13),               OP_MASK,        IF2 },
 146 { "setf",       two(0x0000,0x0000),     two(0x0000,0xffff), {CCCC,R2} },
 147
 148 /* saturated operation instructions */
 149 { "satadd",     OP(0x06),               OP_MASK,        IF1 },
 150 { "satadd",     OP(0x11),               OP_MASK,        IF2 },
 151 { "satsub",     OP(0x05),               OP_MASK,        IF1 },
 152 { "satsubi",    OP(0x33),               OP_MASK,        IF6 },
 153 { "satsubr",    OP(0x04),               OP_MASK,        IF1 },
 154
 155 /* logical operation instructions */
 156 { "tst",        OP(0x0b),               OP_MASK,        IF1 },
 157 { "or",         OP(0x08),               OP_MASK,        IF1 },
 158 { "ori",        OP(0x34),               OP_MASK,        IF6 },
 159 { "and",        OP(0x0a),               OP_MASK,        IF1 },
 160 { "andi",       OP(0x36),               OP_MASK,        IF6 },
 161 { "xor",        OP(0x09),               OP_MASK,        IF1 },
 162 { "xori",       OP(0x35),               OP_MASK,        IF6 },
 163 { "not",        OP(0x01),               OP_MASK,        IF1 },
 164 { "sar",        OP(0x15),               OP_MASK,        IF2 },
 165 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2} },
 166 { "shl",        OP(0x16),               OP_MASK,                IF2 },
 167 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2} },
 168 { "shr",        OP(0x14),               OP_MASK,                IF2 },
 169 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2} },
 170
 171 /* branch instructions */
 172         /* signed integer */
 173 { "bgt",        BOP(0xf),               BOP_MASK,       IF3 },
 174 { "bge",        BOP(0xe),               BOP_MASK,       IF3 },
 175 { "blt",        BOP(0x6),               BOP_MASK,       IF3 },
 176 { "ble",        BOP(0x7),               BOP_MASK,       IF3 },
 177         /* unsigned integer */
 178 { "bh",         BOP(0xb),               BOP_MASK,       IF3 },
 179 { "bnh",        BOP(0x3),               BOP_MASK,       IF3 },
 180 { "bl",         BOP(0x1),               BOP_MASK,       IF3 },
 181 { "bnl",        BOP(0x9),               BOP_MASK,       IF3 },
 182         /* common */
 183 { "be",         BOP(0x2),               BOP_MASK,       IF3 },
 184 { "bne",        BOP(0xa),               BOP_MASK,       IF3 },
 185         /* others */
 186 { "bv",         BOP(0x0),               BOP_MASK,       IF3 },
 187 { "bnv",        BOP(0x8),               BOP_MASK,       IF3 },
 188 { "bn",         BOP(0x4),               BOP_MASK,       IF3 },
 189 { "bp",         BOP(0xc),               BOP_MASK,       IF3 },
 190 { "bc",         BOP(0x1),               BOP_MASK,       IF3 },
 191 { "bnc",        BOP(0x9),               BOP_MASK,       IF3 },
 192 { "bz",         BOP(0x2),               BOP_MASK,       IF3 },
 193 { "bnz",        BOP(0xa),               BOP_MASK,       IF3 },
 194 { "br",         BOP(0x5),               BOP_MASK,       IF3 },
 195 { "bsa",        BOP(0xd),               BOP_MASK,       IF3 },
 196
 197 { "jmp",        one(0x0060),            one(0xffe0),    R1 },
 198 { "jarl",       one(0x0780),            one(0xf83f),    { D22, R2 } },
 199 { "jr",         one(0x0780),            one(0xffe0),    { D22 } },
 200
 201 /* bit manipulation instructions */
 202 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1} },
 203 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1} },
 204 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1} },
 205 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1} },
 206
 207 /* special instructions */
 208 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0} },
 209 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0} },
 210 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0} },
 211 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0} },
 212 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5} },
 213 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {0} },
 214 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {0} },
 215 { "nop",        one(0x00),              one(0xff),              {0} },
 216
 217 } ;
 218
 219 const int v850_num_opcodes =
 220   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 221
 222 \f
 223 /* The functions used to insert and extract complicated operands.  */
 224
 225 static unsigned long
 226 insert_d9 (insn, value, errmsg)
 227      unsigned long insn;
 228      long value;
 229      const char **errmsg;
 230 {
 231   if (value > 511 || value <= -512)
 232     *errmsg = "value out of range";
 233
 234   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 235 }
 236
 237 static long
 238 extract_d9 (insn, invalid)
 239      unsigned long insn;
 240      int *invalid;
 241 {
 242   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 243
 244   if ((insn & 0x8000) != 0)
 245     ret -= 0x0200;
 246
 247   return ret;
 248 }