opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* Local insertion and extraction functions.  */
   5 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
   6 static long extract_d9 PARAMS ((unsigned long, int *));
   7
   8 /* regular opcode */
   9 #define OP(x)           ((x & 0x3f) << 5)
  10 #define OP_MASK         OP(0x3f)
  11
  12 /* conditional branch opcode */
  13 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  14 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  15
  16 /* one-word opcodes */
  17 #define one(x)          ((unsigned int) (x))
  18
  19 /* two-word opcodes */
  20 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  21
  22
  23 \f
  24 const struct v850_operand v850_operands[] = {
  25 #define UNUSED  0
  26   { 0, 0, 0, 0, 0 },
  27
  28 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  29 #define R1      (UNUSED+1)
  30   { 5, 0, 0, 0, V850_OPERAND_REG },
  31
  32 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  33 #define R2      (R1+1)
  34   { 5, 11, 0, 0, V850_OPERAND_REG },
  35
  36 /* The IMM5 field in a format 2 insn. */
  37 #define I5      (R2+1)
  38   { 5, 0, 0, 0, V850_OPERAND_SIGNED },
  39
  40 #define I5U     (I5+1)
  41   { 5, 0, 0, 0, 0 },
  42
  43 /* The IMM16 field in a format 6 insn. */
  44 #define I16     (I5U+1)
  45   { 16, 16, 0, 0, 0 },
  46
  47 /* The signed DISP7 field in a format 4 insn. */
  48 #define D7S     (I16+1)
  49   { 7, 0, 0, 0, V850_OPERAND_SIGNED },
  50
  51 /* The DISP9 field in a format 3 insn. */
  52 #define D9      (D7S+1)
  53   { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
  54
  55 /* The DISP16 field in a format 6 insn. */
  56 #define D16     (D9+1)
  57   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  58
  59 /* The DISP22 field in a format 4 insn. */
  60 #define D22     (D16+1)
  61   { 16, 0, 0, 0, 0 },
  62
  63 #define B3      (D22+1)
  64 /* The 3 bit immediate field in format 8 insn.  */
  65   { 3, 11, 0, 0, 0 },
  66
  67 #define CCCC    (B3+1)
  68 /* The 4 bit condition code in a setf instruction */
  69   { 4, 0, 0, 0, V850_OPERAND_CC },
  70
  71 /* The unsigned DISP8 field in a format 4 insn. */
  72 #define D8      (CCCC+1)
  73   { 8, 0, 0, 0, 0 },
  74
  75 /* System register operands.  */
  76 #define SR1     (D8+1)
  77   { 5, 0, 0, 0, V850_OPERAND_SRG },
  78
  79 /* EP Register.  */
  80 #define EP      (SR1+1)
  81   { 0, 0, 0, 0, V850_OPERAND_EP }
  82 } ;
  83
  84 \f
  85 /* reg-reg instruction format (Format I) */
  86 #define IF1     {R1, R2}
  87
  88 /* imm-reg instruction format (Format II) */
  89 #define IF2     {I5, R2}
  90
  91 /* conditional branch instruction format (Format III) */
  92 #define IF3     {D9}
  93
  94 /* 16-bit load/store instruction (Format IV) */
  95 #define IF4A    {D7S, EP, R2}
  96 #define IF4B    {R2, D7S, EP}
  97 #define IF4C    {D8, EP, R2}
  98 #define IF4D    {R2, D8, EP}
  99
 100 /* Jump instruction (Format V) */
 101 #define IF5     {D22}
 102
 103 /* 3 operand instruction (Format VI) */
 104 #define IF6     {I16, R1, R2}
 105
 106 /* 32-bit load/store instruction (Format VII) */
 107 #define IF7A    {D16, R1, R2}
 108 #define IF7B    {R2, D16, R1}
 109
 110 /* Bit manipulation function.  */
 111
 112
 113 \f
 114 /* The opcode table.
 115
 116    The format of the opcode table is:
 117
 118    NAME         OPCODE          MASK            { OPERANDS }
 119
 120    NAME is the name of the instruction.
 121    OPCODE is the instruction opcode.
 122    MASK is the opcode mask; this is used to tell the disassembler
 123      which bits in the actual opcode must match OPCODE.
 124    OPERANDS is the list of operands.
 125
 126    The disassembler reads the table in order and prints the first
 127    instruction which matches, so this table is sorted to put more
 128    specific instructions before more general instructions.  It is also
 129    sorted by major opcode.  */
 130
 131 const struct v850_opcode v850_opcodes[] = {
 132 /* load/store instructions */
 133 { "sld.b",      one(0x0300),            one(0x0780),    IF4A, 2 },
 134 { "sld.h",      one(0x0400),            one(0x0780),    IF4A, 2 },
 135 { "sld.w",      one(0x0500),            one(0x0780),    IF4A, 2 },
 136 { "sst.b",      OP(0x00),               OP_MASK,        IF4B, 2 },
 137 { "sst.h",      OP(0x00),               OP_MASK,        IF4D, 2 },
 138 { "sst.w",      OP(0x00),               OP_MASK,        IF4D, 2 },
 139
 140 { "ld.b",       two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7A, 4 },
 141 { "ld.h",       two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 4 },
 142 { "ld.w",       two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 4 },
 143 { "st.b",       two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7B, 4 },
 144 { "st.h",       two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 4 },
 145 { "st.w",       two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 4 },
 146
 147 /* arithmetic operation instructions */
 148 { "mov",        OP(0x00),               OP_MASK,        IF1, 2 },
 149 { "mov",        OP(0x10),               OP_MASK,        IF2, 2 },
 150 { "movea",      OP(0x31),               OP_MASK,        IF6, 4 },
 151 { "movhi",      OP(0x32),               OP_MASK,        IF6, 4 },
 152 { "add",        OP(0x0e),               OP_MASK,        IF1, 2 },
 153 { "add",        OP(0x12),               OP_MASK,        IF2, 2 },
 154 { "addi",       OP(0x30),               OP_MASK,        IF6, 4 },
 155 { "sub",        OP(0x0d),               OP_MASK,        IF1, 2 },
 156 { "subr",       OP(0x0c),               OP_MASK,        IF1, 2 },
 157 { "mulh",       OP(0x07),               OP_MASK,        IF1, 2 },
 158 { "mulh",       OP(0x17),               OP_MASK,        IF2, 2 },
 159 { "mulhi",      OP(0x37),               OP_MASK,        IF6, 4 },
 160 { "divh",       OP(0x02),               OP_MASK,        IF1, 2 },
 161 { "cmp",        OP(0x0f),               OP_MASK,        IF1, 2 },
 162 { "cmp",        OP(0x13),               OP_MASK,        IF2, 2 },
 163 { "setf",       two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 4 },
 164
 165 /* saturated operation instructions */
 166 { "satadd",     OP(0x06),               OP_MASK,        IF1, 2 },
 167 { "satadd",     OP(0x11),               OP_MASK,        IF2, 2 },
 168 { "satsub",     OP(0x05),               OP_MASK,        IF1, 2 },
 169 { "satsubi",    OP(0x33),               OP_MASK,        IF6, 4 },
 170 { "satsubr",    OP(0x04),               OP_MASK,        IF1, 2 },
 171
 172 /* logical operation instructions */
 173 { "tst",        OP(0x0b),               OP_MASK,        IF1, 2 },
 174 { "or",         OP(0x08),               OP_MASK,        IF1, 2 },
 175 { "ori",        OP(0x34),               OP_MASK,        IF6, 4 },
 176 { "and",        OP(0x0a),               OP_MASK,        IF1, 2 },
 177 { "andi",       OP(0x36),               OP_MASK,        IF6, 4 },
 178 { "xor",        OP(0x09),               OP_MASK,        IF1, 2 },
 179 { "xori",       OP(0x35),               OP_MASK,        IF6, 4 },
 180 { "not",        OP(0x01),               OP_MASK,        IF1, 2 },
 181 { "sar",        OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 182 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 183 { "shl",        OP(0x16),               OP_MASK,                {I5U, R2}, 2 },
 184 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 185 { "shr",        OP(0x14),               OP_MASK,                {I5U, R2}, 2 },
 186 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 187
 188 /* branch instructions */
 189         /* signed integer */
 190 { "bgt",        BOP(0xf),               BOP_MASK,       IF3, 2 },
 191 { "bge",        BOP(0xe),               BOP_MASK,       IF3, 2 },
 192 { "blt",        BOP(0x6),               BOP_MASK,       IF3, 2 },
 193 { "ble",        BOP(0x7),               BOP_MASK,       IF3, 2 },
 194         /* unsigned integer */
 195 { "bh",         BOP(0xb),               BOP_MASK,       IF3, 2 },
 196 { "bnh",        BOP(0x3),               BOP_MASK,       IF3, 2 },
 197 { "bl",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 198 { "bnl",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 199         /* common */
 200 { "be",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 201 { "bne",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 202         /* others */
 203 { "bv",         BOP(0x0),               BOP_MASK,       IF3, 2 },
 204 { "bnv",        BOP(0x8),               BOP_MASK,       IF3, 2 },
 205 { "bn",         BOP(0x4),               BOP_MASK,       IF3, 2 },
 206 { "bp",         BOP(0xc),               BOP_MASK,       IF3, 2 },
 207 { "bc",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 208 { "bnc",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 209 { "bz",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 210 { "bnz",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 211 { "br",         BOP(0x5),               BOP_MASK,       IF3, 2 },
 212 { "bsa",        BOP(0xd),               BOP_MASK,       IF3, 2 },
 213
 214 { "jmp",        one(0x0060),            one(0xffe0),    { R1}, 2 },
 215 { "jarl",       one(0x0780),            one(0xf83f),    { D22, R2 }, 4 },
 216 { "jr",         one(0x0780),            one(0xffe0),    { D22 }, 4 },
 217
 218 /* bit manipulation instructions */
 219 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 220 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 221 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 222 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 223
 224 /* special instructions */
 225 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 226 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 227 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 228 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
 229 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
 230 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R2,SR1}, 4 },
 231 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 232 { "nop",        one(0x00),              one(0xff),              {0}, 2 },
 233
 234 } ;
 235
 236 const int v850_num_opcodes =
 237   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 238
 239 \f
 240 /* The functions used to insert and extract complicated operands.  */
 241
 242 static unsigned long
 243 insert_d9 (insn, value, errmsg)
 244      unsigned long insn;
 245      long value;
 246      const char **errmsg;
 247 {
 248   if (value > 511 || value <= -512)
 249     *errmsg = "value out of range";
 250
 251   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 252 }
 253
 254 static long
 255 extract_d9 (insn, invalid)
 256      unsigned long insn;
 257      int *invalid;
 258 {
 259   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 260
 261   if ((insn & 0x8000) != 0)
 262     ret -= 0x0200;
 263
 264   return ret;
 265 }