opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* Local insertion and extraction functions.  */
   5 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
   6 static long extract_d9 PARAMS ((unsigned long, int *));
   7
   8 /* regular opcode */
   9 #define OP(x)           ((x & 0x3f) << 5)
  10 #define OP_MASK         OP(0x3f)
  11
  12 /* conditional branch opcode */
  13 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  14 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  15
  16 /* one-word opcodes */
  17 #define one(x)          ((unsigned int) (x))
  18
  19 /* two-word opcodes */
  20 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  21
  22
  23 \f
  24 const struct v850_operand v850_operands[] = {
  25 #define UNUSED  0
  26   { 0, 0, 0, 0, 0 },
  27
  28 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  29 #define R1      (UNUSED+1)
  30   { 5, 0, 0, 0, V850_OPERAND_REG },
  31
  32 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  33 #define R2      (R1+1)
  34   { 5, 11, 0, 0, V850_OPERAND_REG },
  35
  36 /* The IMM5 field in a format 2 insn. */
  37 #define I5      (R2+1)
  38   { 5, 0, 0, 0, V850_OPERAND_SIGNED },
  39
  40 #define I5U     (I5+1)
  41   { 5, 0, 0, 0, 0 },
  42
  43 /* The IMM16 field in a format 6 insn. */
  44 #define I16     (I5U+1)
  45   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  46
  47 /* The signed DISP7 field in a format 4 insn. */
  48 #define D7S     (I16+1)
  49   { 7, 0, 0, 0, V850_OPERAND_SIGNED },
  50
  51 /* The DISP9 field in a format 3 insn. */
  52 #define D9      (D7S+1)
  53   { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
  54
  55 /* The DISP16 field in a format 6 insn. */
  56 #define D16     (D9+1)
  57   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  58
  59 /* The DISP22 field in a format 4 insn. */
  60 #define D22     (D16+1)
  61   { 16, 0, 0, 0, 0 },
  62
  63 #define B3      (D22+1)
  64 /* The 3 bit immediate field in format 8 insn.  */
  65   { 3, 11, 0, 0, 0 },
  66
  67 #define CCCC    (B3+1)
  68 /* The 4 bit condition code in a setf instruction */
  69   { 4, 0, 0, 0, V850_OPERAND_CC },
  70
  71 /* The unsigned DISP8 field in a format 4 insn. */
  72 #define D8      (CCCC+1)
  73   { 8, 0, 0, 0, 0 },
  74
  75 /* System register operands.  */
  76 #define SR1     (D8+1)
  77   { 5, 0, 0, 0, V850_OPERAND_SRG },
  78
  79 /* EP Register.  */
  80 #define EP      (SR1+1)
  81   { 0, 0, 0, 0, V850_OPERAND_EP },
  82
  83 /* The IMM16 field (unsigned0 in a format 6 insn. */
  84 #define I16U    (EP+1)
  85   { 16, 16, 0, 0, 0},
  86 } ;
  87
  88 \f
  89 /* reg-reg instruction format (Format I) */
  90 #define IF1     {R1, R2}
  91
  92 /* imm-reg instruction format (Format II) */
  93 #define IF2     {I5, R2}
  94
  95 /* conditional branch instruction format (Format III) */
  96 #define IF3     {D9}
  97
  98 /* 16-bit load/store instruction (Format IV) */
  99 #define IF4A    {D7S, EP, R2}
 100 #define IF4B    {R2, D7S, EP}
 101 #define IF4C    {D8, EP, R2}
 102 #define IF4D    {R2, D8, EP}
 103
 104 /* Jump instruction (Format V) */
 105 #define IF5     {D22}
 106
 107 /* 3 operand instruction (Format VI) */
 108 #define IF6     {I16, R1, R2}
 109
 110 /* 3 operand instruction (Format VI) */
 111 #define IF6U    {I16U, R1, R2}
 112
 113 /* 32-bit load/store instruction (Format VII) */
 114 #define IF7A    {D16, R1, R2}
 115 #define IF7B    {R2, D16, R1}
 116
 117 /* Bit manipulation function.  */
 118
 119
 120 \f
 121 /* The opcode table.
 122
 123    The format of the opcode table is:
 124
 125    NAME         OPCODE          MASK            { OPERANDS }
 126
 127    NAME is the name of the instruction.
 128    OPCODE is the instruction opcode.
 129    MASK is the opcode mask; this is used to tell the disassembler
 130      which bits in the actual opcode must match OPCODE.
 131    OPERANDS is the list of operands.
 132
 133    The disassembler reads the table in order and prints the first
 134    instruction which matches, so this table is sorted to put more
 135    specific instructions before more general instructions.  It is also
 136    sorted by major opcode.  */
 137
 138 const struct v850_opcode v850_opcodes[] = {
 139 /* load/store instructions */
 140 { "sld.b",      one(0x0300),            one(0x0780),    IF4A, 2 },
 141 { "sld.h",      one(0x0400),            one(0x0780),    IF4A, 2 },
 142 { "sld.w",      one(0x0500),            one(0x0781),    IF4A, 2 },
 143 { "sst.b",      one(0x0380),            one(0x0780),    IF4B, 2 },
 144 { "sst.h",      one(0x0480),            one(0x0780),    IF4D, 2 },
 145 { "sst.w",      one(0x0501),            one(0x0781),    IF4D, 2 },
 146
 147 { "ld.b",       two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7A, 4 },
 148 { "ld.h",       two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 4 },
 149 { "ld.w",       two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 4 },
 150 { "st.b",       two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7B, 4 },
 151 { "st.h",       two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 4 },
 152 { "st.w",       two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 4 },
 153
 154 /* arithmetic operation instructions */
 155 { "mov",        OP(0x00),               OP_MASK,        IF1, 2 },
 156 { "mov",        OP(0x10),               OP_MASK,        IF2, 2 },
 157 { "movea",      OP(0x31),               OP_MASK,        IF6, 4 },
 158 { "movhi",      OP(0x32),               OP_MASK,        IF6, 4 },
 159 { "add",        OP(0x0e),               OP_MASK,        IF1, 2 },
 160 { "add",        OP(0x12),               OP_MASK,        IF2, 2 },
 161 { "addi",       OP(0x30),               OP_MASK,        IF6, 4 },
 162 { "sub",        OP(0x0d),               OP_MASK,        IF1, 2 },
 163 { "subr",       OP(0x0c),               OP_MASK,        IF1, 2 },
 164 { "mulh",       OP(0x07),               OP_MASK,        IF1, 2 },
 165 { "mulh",       OP(0x17),               OP_MASK,        IF2, 2 },
 166 { "mulhi",      OP(0x37),               OP_MASK,        IF6, 4 },
 167 { "divh",       OP(0x02),               OP_MASK,        IF1, 2 },
 168 { "cmp",        OP(0x0f),               OP_MASK,        IF1, 2 },
 169 { "cmp",        OP(0x13),               OP_MASK,        IF2, 2 },
 170 { "setf",       two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 4 },
 171
 172 /* saturated operation instructions */
 173 { "satadd",     OP(0x06),               OP_MASK,        IF1, 2 },
 174 { "satadd",     OP(0x11),               OP_MASK,        IF2, 2 },
 175 { "satsub",     OP(0x05),               OP_MASK,        IF1, 2 },
 176 { "satsubi",    OP(0x33),               OP_MASK,        IF6, 4 },
 177 { "satsubr",    OP(0x04),               OP_MASK,        IF1, 2 },
 178
 179 /* logical operation instructions */
 180 { "tst",        OP(0x0b),               OP_MASK,        IF1, 2 },
 181 { "or",         OP(0x08),               OP_MASK,        IF1, 2 },
 182 { "ori",        OP(0x34),               OP_MASK,        IF6U, 4 },
 183 { "and",        OP(0x0a),               OP_MASK,        IF1, 2 },
 184 { "andi",       OP(0x36),               OP_MASK,        IF6U, 4 },
 185 { "xor",        OP(0x09),               OP_MASK,        IF1, 2 },
 186 { "xori",       OP(0x35),               OP_MASK,        IF6U, 4 },
 187 { "not",        OP(0x01),               OP_MASK,        IF1, 2 },
 188 { "sar",        OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 189 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 190 { "shl",        OP(0x16),               OP_MASK,                {I5U, R2}, 2 },
 191 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 192 { "shr",        OP(0x14),               OP_MASK,                {I5U, R2}, 2 },
 193 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 194
 195 /* branch instructions */
 196         /* signed integer */
 197 { "bgt",        BOP(0xf),               BOP_MASK,       IF3, 2 },
 198 { "bge",        BOP(0xe),               BOP_MASK,       IF3, 2 },
 199 { "blt",        BOP(0x6),               BOP_MASK,       IF3, 2 },
 200 { "ble",        BOP(0x7),               BOP_MASK,       IF3, 2 },
 201         /* unsigned integer */
 202 { "bh",         BOP(0xb),               BOP_MASK,       IF3, 2 },
 203 { "bnh",        BOP(0x3),               BOP_MASK,       IF3, 2 },
 204 { "bl",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 205 { "bnl",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 206         /* common */
 207 { "be",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 208 { "bne",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 209         /* others */
 210 { "bv",         BOP(0x0),               BOP_MASK,       IF3, 2 },
 211 { "bnv",        BOP(0x8),               BOP_MASK,       IF3, 2 },
 212 { "bn",         BOP(0x4),               BOP_MASK,       IF3, 2 },
 213 { "bp",         BOP(0xc),               BOP_MASK,       IF3, 2 },
 214 { "bc",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 215 { "bnc",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 216 { "bz",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 217 { "bnz",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 218 { "br",         BOP(0x5),               BOP_MASK,       IF3, 2 },
 219 { "bsa",        BOP(0xd),               BOP_MASK,       IF3, 2 },
 220
 221 { "jmp",        one(0x0060),            one(0xffe0),    { R1}, 2 },
 222 { "jarl",       one(0x0780),            one(0xf83f),    { D22, R2 }, 4 },
 223 { "jr",         one(0x0780),            one(0xffe0),    { D22 }, 4 },
 224
 225 /* bit manipulation instructions */
 226 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 227 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 228 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 229 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 230
 231 /* special instructions */
 232 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 233 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 234 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 235 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
 236 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
 237 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R2,SR1}, 4 },
 238 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 239 { "nop",        one(0x00),              one(0xffff),            {0}, 2 },
 240 { 0, 0, 0, {0}, 0 },
 241
 242 } ;
 243
 244 const int v850_num_opcodes =
 245   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 246
 247 \f
 248 /* The functions used to insert and extract complicated operands.  */
 249
 250 static unsigned long
 251 insert_d9 (insn, value, errmsg)
 252      unsigned long insn;
 253      long value;
 254      const char **errmsg;
 255 {
 256   if (value > 511 || value <= -512)
 257     *errmsg = "value out of range";
 258
 259   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 260 }
 261
 262 static long
 263 extract_d9 (insn, invalid)
 264      unsigned long insn;
 265      int *invalid;
 266 {
 267   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 268
 269   if ((insn & 0x8000) != 0)
 270     ret -= 0x0200;
 271
 272   return ret;
 273 }