sim/aarch64/ChangeLog

   1 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
   2
   3         PR sim/25318
   4         * simulator.c (blr): Read destination register before calling
   5         aarch64_save_LR.
   6
   7 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
   8
   9         * cpustate.c: Add 'libiberty.h' include.
  10         * interp.c: Add 'sim-assert.h' include.
  11
  12 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  13
  14         * configure: Regenerate.
  15
  16 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
  17
  18         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
  19         registers based on structure size.
  20         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  21         (LD1_1): Replace with call to vec_load.
  22         (vec_store): Add new M argument.  Rewrite to iterate over registers
  23         based on structure size.
  24         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  25         (ST1_1): Replace with call to vec_store.
  26
  27 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  28
  29         * simulator.c (do_vec_FCVTL): New.
  30         (do_vec_op1): Call do_vec_FCVTL.
  31
  32         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  33         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  34         (do_scalar_vec): Add calls to new functions.
  35
  36 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  37
  38         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  39         flag check.
  40
  41 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  42
  43         * simulator.c (mul64hi): Shift carry left by 32.
  44         (smulh): Change signum to negate.  If negate, invert result, and add
  45         carry bit if low part of multiply result is zero.
  46
  47 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  48
  49         * simulator.c (do_vec_SMOV_into_scalar): New.
  50         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  51         Rewritten.
  52         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  53         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  54         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  55         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  56
  57         * simulator.c (popcount): New.
  58         (do_vec_CNT): New.
  59         (do_vec_op1): Add do_vec_CNT call.
  60
  61 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  62
  63         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  64         with type set to input type size.
  65         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  66
  67 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  68
  69         * simulator.c (do_vec_MLA): Rewrite switch body.
  70
  71         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  72         2.  Move test_false if inside loop.  Fix logic for computing result
  73         stored to vd.
  74
  75         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  76         (do_vec_LDn_single, do_vec_STn_single): New.
  77         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  78         loop over nregs using new var n.  Add n times size to address in loop.
  79         Add n to vd in loop.
  80         (do_vec_load_store): Add comment for instruction bit 24.  New var
  81         single to hold instruction bit 24.  Add new code to use single.  Move
  82         ldnr support inside single if statements.  Fix ldnr register counts
  83         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  84
  85 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  86
  87         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  88
  89 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  90
  91         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  92         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  93         case 3, call HALT_UNALLOC unconditionally.
  94         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  95         i + 2.  Delete if on bias, change index to i + bias * X.
  96
  97 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  98
  99         * simulator.c (do_vec_UZP): Rewrite.
 100
 101 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 102
 103         * cpustate.c: Include math.h.
 104         (aarch64_set_FP_float): Use signbit to check for signed zero.
 105         (aarch64_set_FP_double): Likewise.
 106         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 107         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 108         args same size as third arg.
 109         (fmaxnm): Use isnan instead of fpclassify.
 110         (fminnm, dmaxnm, dminnm): Likewise.
 111         (do_vec_MLS): Reverse order of subtraction operands.
 112         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 113         aarch64_get_FP_float to get source register contents.
 114         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 115         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 116         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 117         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 118         raise_exception calls.
 119
 120 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 121
 122         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 123         Add comment to document NaN issue.
 124         (set_flags_for_double_compare): Likewise.
 125
 126 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 127
 128         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 129         (set_flags_for_add64): Replace with a modified copy of
 130         set_flags_for_sub64.
 131
 132 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 133
 134         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 135         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 136
 137 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 138
 139         * simulator.c (fsturs): Switch use of rn and st variables.
 140         (fsturd, fsturq): Likewise
 141
 142 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 143
 144         * interp.c: Include bfd.h.
 145         (symcount, symtab, aarch64_get_sym_value): Delete.
 146         (remove_useless_symbols): Change count type to long.
 147         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 148         and symtab local variables.
 149         (sim_create_inferior): Delete storage.  Replace symbol code
 150         with a call to trace_load_symbols.
 151         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 152         includes.
 153         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 154         trace_sym_value.
 155         * memory.h: Delete bfd.h include.
 156         (mem_add_blk): Delete unused prototype.
 157         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 158         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 159         (aarch64_get_sym_value): Delete.
 160
 161 2016-08-12  Nick Clifton  <nickc@redhat.com>
 162
 163         * simulator.c (aarch64_step): Revert pervious delta.
 164         (aarch64_run): Call sim_events_tick after each
 165         instruction is simulated, and if necessary call
 166         sim_events_process.
 167         * simulator.h: Revert previous delta.
 168
 169 2016-08-11  Nick Clifton  <nickc@redhat.com>
 170
 171         * interp.c (sim_create_inferior): Allow for being called with a
 172         NULL abfd parameter.  If a bfd is provided, initialise the sim
 173         with that start address.
 174         * simulator.c (HALT_NYI): Just print out the numeric value of the
 175         instruction when not tracing.
 176         (aarch64_step): Change from static to global.
 177         * simulator.h: Add a prototype for aarch64_step().
 178
 179 2016-07-27  Alan Modra  <amodra@gmail.com>
 180
 181         * memory.c: Don't include libbfd.h.
 182
 183 2016-07-21  Nick Clifton  <nickc@redhat.com>
 184
 185         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 186
 187 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 188
 189         * cpustate.h: Include config.h.
 190         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 191         use anonymous structs to align members.
 192         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 193         endian_le2h_4 to read instruction from pc.
 194
 195 2016-05-06  Nick Clifton  <nickc@redhat.com>
 196
 197         * simulator.c (do_FMLA_by_element): New function.
 198         (do_vec_op2): Call it.
 199
 200 2016-04-27  Nick Clifton  <nickc@redhat.com>
 201
 202         * simulator.c: Add TRACE_DECODE statements to all emulation
 203         functions.
 204
 205 2016-03-30  Nick Clifton  <nickc@redhat.com>
 206
 207         * cpustate.c (aarch64_set_reg_s32): New function.
 208         (aarch64_set_reg_u32): New function.
 209         (aarch64_get_FP_half): Place half precision value into the correct
 210         slot of the union.
 211         (aarch64_set_FP_half): Likewise.
 212         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 213         aarch64_set_reg_u32.
 214         * memory.c (FETCH_FUNC): Cast the read value to the access type
 215         before converting it to the return type.  Rename to FETCH_FUNC64.
 216         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 217         accesses.  Use for 32-bit memory access functions.
 218         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 219         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 220         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 221         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 222         (ldrh32_abs): Store 32 bit value not 64-bits.
 223         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 224         (do_vec_MOV_immediate): Fix computation of val.
 225         (do_vec_MVNI): Likewise.
 226         (DO_VEC_WIDENING_MUL): New macro.
 227         (do_vec_mull): Use new macro.
 228         (do_vec_mul): Use new macro.
 229         (do_vec_MLA): Read values before writing.
 230         (do_vec_xtl): Likewise.
 231         (do_vec_SSHL): Select correct shift value.
 232         (do_vec_USHL): Likewise.
 233         (do_scalar_UCVTF): New function.
 234         (do_scalar_vec): Call new function.
 235         (store_pair_u64): Treat reads of SP as reads of XZR.
 236
 237 2016-03-29  Nick Clifton  <nickc@redhat.com>
 238
 239         * cpustate.c: Remove space after asterisk in function parameters.
 240         * decode.h (greg): Delete unused function.
 241         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 242         * simulator.c: Use INSTR macro in more places.
 243         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 244         Remove extraneous whitespace.
 245
 246 2016-03-23  Nick Clifton  <nickc@redhat.com>
 247
 248         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 249         register as a half precision floating point number.
 250         (aarch64_set_FP_half): New function.  Similar, but for setting
 251         a half precision register.
 252         (aarch64_get_thread_id): New function.  Returns the value of the
 253         CPU's TPIDR register.
 254         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 255         floating point control register.
 256         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 257         register.
 258         * cpustate.h: Add prototypes for new functions.
 259         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 260         * memory.c: Use unaligned core access functions for all memory
 261         reads and writes.
 262         * simulator.c (HALT_NYI): Generate an error message if tracing
 263         will not tell the user why the simulator is halting.
 264         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 265         (INSTR): New time-saver macro.
 266         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 267         offset.
 268         (fldrh_abs): New function.  Likewise for 16-bit values.
 269         (do_vec_SSHL): Allow for negative shift values.
 270         (do_vec_USHL): Likewise.
 271         (do_vec_SHL): Correct computation of shift amount.
 272         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 273         shifts and computation of shift value.
 274         (clz): New function.  Counts leading zero bits.
 275         (do_vec_CLZ): New function.  Implements CLZ (vector).
 276         (do_vec_MOV_element): Call do_vec_CLZ.
 277         (dexSimpleFPCondCompare): Implement.
 278         (do_FCVT_half_to_single): New function.  Implements one of the
 279         FCVT operations.
 280         (do_FCVT_half_to_double): New function.  Likewise.
 281         (do_FCVT_single_to_half): New function.  Likewise.
 282         (do_FCVT_double_to_half): New function.  Likewise.
 283         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 284         (do_scalar_SHL): Handle negative shifts.
 285         (do_scalar_shift): Handle SSHR.
 286         (do_scalar_USHL): New function.
 287         (do_double_add): Simplify to just performing a double precision
 288         add operation.  Move remaining code into...
 289         (do_scalar_vec): ... New function.
 290         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 291         functions.
 292         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 293         registers.
 294         (system_set): New function.
 295         (do_MSR_immediate): New function.  Stub for now.
 296         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 297         instruction.
 298         (do_SYS): New function.  Stub for now,
 299         (dexSystem): Call new functions.
 300
 301 2016-03-18  Nick Clifton  <nickc@redhat.com>
 302
 303         * cpustate.c: Remove spurious spaces from TRACE strings.
 304         Print hex equivalents of floats and doubles.
 305         Check element number against array size when accessing vector
 306         registers.
 307         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 308         element index.
 309         (SET_VEC_ELEMENT): Likewise.
 310         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 311
 312         * memory.c: Trace memory reads when --trace-memory is enabled.
 313         Remove float and double load and store functions.
 314         * memory.h (aarch64_get_mem_float): Delete prototype.
 315         (aarch64_get_mem_double): Likewise.
 316         (aarch64_set_mem_float): Likewise.
 317         (aarch64_set_mem_double): Likewise.
 318         * simulator (IS_SET): Always return either 0 or 1.
 319         (IS_CLEAR): Likewise.
 320         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 321         and doubles using 64-bit memory accesses.
 322         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 323         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 324         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 325         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 326         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 327         (do_vec_MUL_by_element): New function.
 328         (do_vec_op2): Call do_vec_MUL_by_element.
 329         (do_scalar_NEG): New function.
 330         (do_double_add): Call do_scalar_NEG.
 331
 332 2016-03-03  Nick Clifton  <nickc@redhat.com>
 333
 334         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 335         (CondCompare): Swap interpretation of bit 30.
 336         (DO_ADDP): Delete macro.
 337         (do_vec_ADDP): Copy source registers before starting to update
 338         destination register.
 339         (do_vec_FADDP): Likewise.
 340         (do_vec_load_store): Fix computation of sizeof_operation.
 341         (rbit64): Fix type of constant.
 342         (aarch64_step): When displaying insn value, display all 32 bits.
 343
 344 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 345
 346         * config.in, configure: Regenerate.
 347
 348 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 349
 350         * configure: Regenerate.
 351
 352 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 353
 354         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 355         * configure: Regenerate.
 356
 357 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 358
 359         * configure: Regenerate.
 360
 361 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 362
 363         * configure: Regenerate.
 364
 365 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 366
 367         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 368         * configure: Regenerate.
 369
 370 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 371
 372         * configure: Regenerate.
 373
 374 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 375
 376         * configure: Regenerate.
 377
 378 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 379
 380         * config.in, configure: Regenerate.
 381
 382 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 383
 384         * interp.c (sim_create_inferior): Mark argv and env const.
 385         (sim_open): Mark argv const.
 386
 387 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 388
 389         * interp.c: Delete dis-asm.h include.
 390         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 391         (sim_create_inferior): Delete disassemble init logic.
 392         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 393         (sim_open): Delete sim_add_option_table call.
 394         * memory.c (mem_error): Delete disas check.
 395         * simulator.c: Delete dis-asm.h include.
 396         (disas): Delete.
 397         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 398         (HALT_NYI): Likewise.
 399         (handle_halt): Delete disas call.
 400         (aarch64_step): Replace disas logic with TRACE_DISASM.
 401         * simulator.h: Delete dis-asm.h include.
 402         (aarch64_print_insn): Delete.
 403
 404 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 405
 406         * simulator.c (MAX, MIN): Delete.
 407         (do_vec_maxv): Change MAX to max and MIN to min.
 408         (do_vec_fminmaxV): Likewise.
 409
 410 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 411
 412         * simulator.c: Remove syscall.h include.
 413
 414 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 415
 416         * configure: Regenerate.
 417
 418 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 419
 420         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 421         * configure: Regenerate.
 422
 423 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 424
 425         * configure: Regenerate.
 426
 427 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 428
 429         * interp.c (sim_dis_read): Change private_data to application_data.
 430         (sim_create_inferior): Likewise.
 431
 432 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 433
 434         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 435
 436 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 437
 438         * config.in, configure: Regenerate.
 439
 440 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 441
 442         * interp.c (sim_create_inferior): Update comment and argv check.
 443
 444 2015-12-14  Nick Clifton  <nickc@redhat.com>
 445
 446         * simulator.c (system_get): New function.  Provides read
 447         access to the dczid system register.
 448         (do_mrs): New function - implements the MRS instruction.
 449         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 450         unimplemented system instructions.
 451
 452 2015-11-24  Nick Clifton  <nickc@redhat.com>
 453
 454         * configure.ac: New configure template.
 455         * aclocal.m4: Generate.
 456         * config.in: Generate.
 457         * configure: Generate.
 458         * cpustate.c: New file - functions for accessing AArch64 registers.
 459         * cpustate.h: New header.
 460         * decode.h: New header.
 461         * interp.c: New file - interface between GDB and simulator.
 462         * Makefile.in: New makefile template.
 463         * memory.c: New file - functions for simulating aarch64 memory
 464         accesses.
 465         * memory.h: New header.
 466         * sim-main.h: New header.
 467         * simulator.c: New file - aarch64 simulator functions.
 468         * simulator.h: New header.