sim/arm/wrapper.c

   1 /* run front end support for arm
   2    Copyright (C) 1995-2021 Free Software Foundation, Inc.
   3
   4    This file is part of ARM SIM.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 /* This file provides the interface between the simulator and
  20    run.c and gdb (when the simulator is linked with gdb).
  21    All simulator interaction should go through this file.  */
  22
  23 /* This must come before any other includes.  */
  24 #include "defs.h"
  25
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <bfd.h>
  31 #include <signal.h>
  32 #include "sim/callback.h"
  33 #include "sim/sim.h"
  34 #include "sim-main.h"
  35 #include "sim-options.h"
  36 #include "armemu.h"
  37 #include "dbg_rdi.h"
  38 #include "ansidecl.h"
  39 #include "gdb/sim-arm.h"
  40 #include "gdb/signals.h"
  41 #include "libiberty.h"
  42 #include "iwmmxt.h"
  43 #include "maverick.h"
  44
  45 /* TODO: This should get pulled from the SIM_DESC.  */
  46 host_callback *sim_callback;
  47
  48 /* TODO: This should get merged into sim_cpu.  */
  49 struct ARMul_State *state;
  50
  51 /* Memory size in bytes.  */
  52 /* TODO: Memory should be converted to the common memory module.  */
  53 static int mem_size = (1 << 21);
  54
  55 int stop_simulator;
  56
  57 #include "dis-asm.h"
  58
  59 /* TODO: Tracing should be converted to common tracing module.  */
  60 int trace = 0;
  61 int disas = 0;
  62 int trace_funcs = 0;
  63
  64 static struct disassemble_info  info;
  65 static char opbuf[1000];
  66
  67 static int ATTRIBUTE_PRINTF (2, 3)
  68 op_printf (char *buf, const char *fmt, ...)
  69 {
  70   int ret;
  71   va_list ap;
  72
  73   va_start (ap, fmt);
  74   ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
  75   va_end (ap);
  76   return ret;
  77 }
  78
  79 static int
  80 sim_dis_read (bfd_vma                     memaddr ATTRIBUTE_UNUSED,
  81               bfd_byte *                  ptr,
  82               unsigned int                length,
  83               struct disassemble_info *   info)
  84 {
  85   ARMword val = (ARMword) *((ARMword *) info->application_data);
  86
  87   while (length--)
  88     {
  89       * ptr ++ = val & 0xFF;
  90       val >>= 8;
  91     }
  92   return 0;
  93 }
  94
  95 void
  96 print_insn (ARMword instr)
  97 {
  98   int size;
  99   disassembler_ftype disassemble_fn;
 100
 101   opbuf[0] = 0;
 102   info.application_data = & instr;
 103   disassemble_fn = disassembler (bfd_arch_arm, 0, 0, NULL);
 104   size = disassemble_fn (0, & info);
 105   fprintf (stderr, " %*s\n", size, opbuf);
 106 }
 107
 108 static void
 109 init (void)
 110 {
 111   static int done;
 112
 113   if (!done)
 114     {
 115       ARMul_EmulateInit ();
 116       state = ARMul_NewState ();
 117       state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW);
 118       ARMul_MemoryInit (state, mem_size);
 119       ARMul_OSInit (state);
 120       state->verbose = 0;
 121       done = 1;
 122     }
 123 }
 124
 125 void
 126 ARMul_ConsolePrint (ARMul_State * state,
 127                     const char * format,
 128                     ...)
 129 {
 130   va_list ap;
 131
 132   if (state->verbose)
 133     {
 134       va_start (ap, format);
 135       vprintf (format, ap);
 136       va_end (ap);
 137     }
 138 }
 139
 140 int
 141 sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
 142            SIM_ADDR addr,
 143            const unsigned char * buffer,
 144            int size)
 145 {
 146   int i;
 147
 148   init ();
 149
 150   for (i = 0; i < size; i++)
 151     ARMul_SafeWriteByte (state, addr + i, buffer[i]);
 152
 153   return size;
 154 }
 155
 156 int
 157 sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
 158           SIM_ADDR addr,
 159           unsigned char * buffer,
 160           int size)
 161 {
 162   int i;
 163
 164   init ();
 165
 166   for (i = 0; i < size; i++)
 167     buffer[i] = ARMul_SafeReadByte (state, addr + i);
 168
 169   return size;
 170 }
 171
 172 int
 173 sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
 174 {
 175   state->Emulate = STOP;
 176   stop_simulator = 1;
 177   return 1;
 178 }
 179
 180 void
 181 sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
 182             int step,
 183             int siggnal ATTRIBUTE_UNUSED)
 184 {
 185   state->EndCondition = 0;
 186   stop_simulator = 0;
 187
 188   if (step)
 189     {
 190       state->Reg[15] = ARMul_DoInstr (state);
 191       if (state->EndCondition == 0)
 192         state->EndCondition = RDIError_BreakpointReached;
 193     }
 194   else
 195     {
 196       state->NextInstr = RESUME;        /* treat as PC change */
 197       state->Reg[15] = ARMul_DoProg (state);
 198     }
 199
 200   FLUSHPIPE;
 201 }
 202
 203 SIM_RC
 204 sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
 205                      struct bfd * abfd,
 206                      char * const *argv,
 207                      char * const *env)
 208 {
 209   int argvlen = 0;
 210   int mach;
 211   char * const *arg;
 212
 213   init ();
 214
 215   if (abfd != NULL)
 216     {
 217       ARMul_SetPC (state, bfd_get_start_address (abfd));
 218       mach = bfd_get_mach (abfd);
 219     }
 220   else
 221     {
 222       ARMul_SetPC (state, 0);   /* ??? */
 223       mach = 0;
 224     }
 225
 226 #ifdef MODET
 227   if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
 228     SETT;
 229 #endif
 230
 231   switch (mach)
 232     {
 233     default:
 234       (*sim_callback->printf_filtered)
 235         (sim_callback,
 236          "Unknown machine type '%d'; please update sim_create_inferior.\n",
 237          mach);
 238       /* fall through */
 239
 240     case 0:
 241       /* We wouldn't set the machine type with earlier toolchains, so we
 242          explicitly select a processor capable of supporting all ARMs in
 243          32bit mode.  */
 244       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
 245       break;
 246
 247 #if 1
 248     case bfd_mach_arm_6T2:
 249     case bfd_mach_arm_7:
 250     case bfd_mach_arm_7EM:
 251       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
 252       break;
 253 #endif
 254
 255     case bfd_mach_arm_XScale:
 256       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
 257       break;
 258
 259     case bfd_mach_arm_iWMMXt2:
 260     case bfd_mach_arm_iWMMXt:
 261       {
 262         extern int SWI_vector_installed;
 263         ARMword i;
 264
 265         if (! SWI_vector_installed)
 266           {
 267             /* Intialise the hardware vectors to zero.  */
 268             if (! SWI_vector_installed)
 269               for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
 270                 ARMul_WriteWord (state, i, 0);
 271
 272             /* ARM_WriteWord will have detected the write to the SWI vector,
 273                but we want SWI_vector_installed to remain at 0 so that thumb
 274                mode breakpoints will work.  */
 275             SWI_vector_installed = 0;
 276           }
 277       }
 278       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
 279       break;
 280
 281     case bfd_mach_arm_ep9312:
 282       ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
 283       break;
 284
 285     case bfd_mach_arm_5:
 286       if (bfd_family_coff (abfd))
 287         {
 288           /* This is a special case in order to support COFF based ARM toolchains.
 289              The COFF header does not have enough room to store all the different
 290              kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
 291              to v5.  (See coff_set_flags() in bdf/coffcode.h).  So if we see a v5
 292              machine type here, we assume it could be any of the above architectures
 293              and so select the most feature-full.  */
 294           ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
 295           break;
 296         }
 297       /* Otherwise drop through.  */
 298
 299     case bfd_mach_arm_5T:
 300       ARMul_SelectProcessor (state, ARM_v5_Prop);
 301       break;
 302
 303     case bfd_mach_arm_5TE:
 304       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
 305       break;
 306
 307     case bfd_mach_arm_4:
 308     case bfd_mach_arm_4T:
 309       ARMul_SelectProcessor (state, ARM_v4_Prop);
 310       break;
 311
 312     case bfd_mach_arm_3:
 313     case bfd_mach_arm_3M:
 314       ARMul_SelectProcessor (state, ARM_Lock_Prop);
 315       break;
 316
 317     case bfd_mach_arm_2:
 318     case bfd_mach_arm_2a:
 319       ARMul_SelectProcessor (state, ARM_Fix26_Prop);
 320       break;
 321     }
 322
 323   memset (& info, 0, sizeof (info));
 324   INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
 325   info.read_memory_func = sim_dis_read;
 326   info.arch = bfd_get_arch (abfd);
 327   info.mach = bfd_get_mach (abfd);
 328   info.endian_code = BFD_ENDIAN_LITTLE;
 329   if (info.mach == 0)
 330     info.arch = bfd_arch_arm;
 331   disassemble_init_for_target (& info);
 332
 333   if (argv != NULL)
 334     {
 335       /* Set up the command line by laboriously stringing together
 336          the environment carefully picked apart by our caller.  */
 337
 338       /* Free any old stuff.  */
 339       if (state->CommandLine != NULL)
 340         {
 341           free (state->CommandLine);
 342           state->CommandLine = NULL;
 343         }
 344
 345       /* See how much we need.  */
 346       for (arg = argv; *arg != NULL; arg++)
 347         argvlen += strlen (*arg) + 1;
 348
 349       /* Allocate it.  */
 350       state->CommandLine = malloc (argvlen + 1);
 351       if (state->CommandLine != NULL)
 352         {
 353           arg = argv;
 354           state->CommandLine[0] = '\0';
 355
 356           for (arg = argv; *arg != NULL; arg++)
 357             {
 358               strcat (state->CommandLine, *arg);
 359               strcat (state->CommandLine, " ");
 360             }
 361         }
 362     }
 363
 364   if (env != NULL)
 365     {
 366       /* Now see if there's a MEMSIZE spec in the environment.  */
 367       while (*env)
 368         {
 369           if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
 370             {
 371               char *end_of_num;
 372
 373               /* Set up memory limit.  */
 374               state->MemSize =
 375                 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
 376             }
 377           env++;
 378         }
 379     }
 380
 381   return SIM_RC_OK;
 382 }
 383
 384 static int
 385 frommem (struct ARMul_State *state, unsigned char *memory)
 386 {
 387   if (state->bigendSig == HIGH)
 388     return (memory[0] << 24) | (memory[1] << 16)
 389       | (memory[2] << 8) | (memory[3] << 0);
 390   else
 391     return (memory[3] << 24) | (memory[2] << 16)
 392       | (memory[1] << 8) | (memory[0] << 0);
 393 }
 394
 395 static void
 396 tomem (struct ARMul_State *state,
 397        unsigned char *memory,
 398        int val)
 399 {
 400   if (state->bigendSig == HIGH)
 401     {
 402       memory[0] = val >> 24;
 403       memory[1] = val >> 16;
 404       memory[2] = val >> 8;
 405       memory[3] = val >> 0;
 406     }
 407   else
 408     {
 409       memory[3] = val >> 24;
 410       memory[2] = val >> 16;
 411       memory[1] = val >> 8;
 412       memory[0] = val >> 0;
 413     }
 414 }
 415
 416 static int
 417 arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 418 {
 419   init ();
 420
 421   switch ((enum sim_arm_regs) rn)
 422     {
 423     case SIM_ARM_R0_REGNUM:
 424     case SIM_ARM_R1_REGNUM:
 425     case SIM_ARM_R2_REGNUM:
 426     case SIM_ARM_R3_REGNUM:
 427     case SIM_ARM_R4_REGNUM:
 428     case SIM_ARM_R5_REGNUM:
 429     case SIM_ARM_R6_REGNUM:
 430     case SIM_ARM_R7_REGNUM:
 431     case SIM_ARM_R8_REGNUM:
 432     case SIM_ARM_R9_REGNUM:
 433     case SIM_ARM_R10_REGNUM:
 434     case SIM_ARM_R11_REGNUM:
 435     case SIM_ARM_R12_REGNUM:
 436     case SIM_ARM_R13_REGNUM:
 437     case SIM_ARM_R14_REGNUM:
 438     case SIM_ARM_R15_REGNUM: /* PC */
 439     case SIM_ARM_FP0_REGNUM:
 440     case SIM_ARM_FP1_REGNUM:
 441     case SIM_ARM_FP2_REGNUM:
 442     case SIM_ARM_FP3_REGNUM:
 443     case SIM_ARM_FP4_REGNUM:
 444     case SIM_ARM_FP5_REGNUM:
 445     case SIM_ARM_FP6_REGNUM:
 446     case SIM_ARM_FP7_REGNUM:
 447     case SIM_ARM_FPS_REGNUM:
 448       ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
 449       break;
 450
 451     case SIM_ARM_PS_REGNUM:
 452       state->Cpsr = frommem (state, memory);
 453       ARMul_CPSRAltered (state);
 454       break;
 455
 456     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 457     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 458     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 459     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 460     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 461     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 462     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 463     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 464     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 465     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 466     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 467     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 468     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 469     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 470     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 471     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 472       memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 473               memory, sizeof (struct maverick_regs));
 474       return sizeof (struct maverick_regs);
 475
 476     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 477       memcpy (&DSPsc, memory, sizeof DSPsc);
 478       return sizeof DSPsc;
 479
 480     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 481     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 482     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 483     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 484     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 485     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 486     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 487     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 488     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 489     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 490     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 491     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 492     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 493     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 494     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 495     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 496     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 497     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 498     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 499     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 500     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 501     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 502     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 503     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 504     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 505     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 506     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 507     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 508     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 509     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 510     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 511     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 512       return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 513
 514     default:
 515       return 0;
 516     }
 517
 518   return length;
 519 }
 520
 521 static int
 522 arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 523 {
 524   ARMword regval;
 525   int len = length;
 526
 527   init ();
 528
 529   switch ((enum sim_arm_regs) rn)
 530     {
 531     case SIM_ARM_R0_REGNUM:
 532     case SIM_ARM_R1_REGNUM:
 533     case SIM_ARM_R2_REGNUM:
 534     case SIM_ARM_R3_REGNUM:
 535     case SIM_ARM_R4_REGNUM:
 536     case SIM_ARM_R5_REGNUM:
 537     case SIM_ARM_R6_REGNUM:
 538     case SIM_ARM_R7_REGNUM:
 539     case SIM_ARM_R8_REGNUM:
 540     case SIM_ARM_R9_REGNUM:
 541     case SIM_ARM_R10_REGNUM:
 542     case SIM_ARM_R11_REGNUM:
 543     case SIM_ARM_R12_REGNUM:
 544     case SIM_ARM_R13_REGNUM:
 545     case SIM_ARM_R14_REGNUM:
 546     case SIM_ARM_R15_REGNUM: /* PC */
 547       regval = ARMul_GetReg (state, state->Mode, rn);
 548       break;
 549
 550     case SIM_ARM_FP0_REGNUM:
 551     case SIM_ARM_FP1_REGNUM:
 552     case SIM_ARM_FP2_REGNUM:
 553     case SIM_ARM_FP3_REGNUM:
 554     case SIM_ARM_FP4_REGNUM:
 555     case SIM_ARM_FP5_REGNUM:
 556     case SIM_ARM_FP6_REGNUM:
 557     case SIM_ARM_FP7_REGNUM:
 558     case SIM_ARM_FPS_REGNUM:
 559       memset (memory, 0, length);
 560       return 0;
 561
 562     case SIM_ARM_PS_REGNUM:
 563       regval = ARMul_GetCPSR (state);
 564       break;
 565
 566     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 567     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 568     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 569     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 570     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 571     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 572     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 573     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 574     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 575     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 576     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 577     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 578     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 579     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 580     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 581     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 582       memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 583               sizeof (struct maverick_regs));
 584       return sizeof (struct maverick_regs);
 585
 586     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 587       memcpy (memory, & DSPsc, sizeof DSPsc);
 588       return sizeof DSPsc;
 589
 590     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 591     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 592     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 593     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 594     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 595     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 596     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 597     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 598     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 599     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 600     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 601     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 602     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 603     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 604     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 605     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 606     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 607     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 608     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 609     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 610     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 611     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 612     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 613     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 614     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 615     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 616     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 617     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 618     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 619     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 620     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 621     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 622       return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 623
 624     default:
 625       return 0;
 626     }
 627
 628   while (len)
 629     {
 630       tomem (state, memory, regval);
 631
 632       len -= 4;
 633       memory += 4;
 634       regval = 0;
 635     }
 636
 637   return length;
 638 }
 639
 640 typedef struct
 641 {
 642   char *        swi_option;
 643   unsigned int  swi_mask;
 644 } swi_options;
 645
 646 #define SWI_SWITCH      "--swi-support"
 647
 648 static swi_options options[] =
 649   {
 650     { "none",    0 },
 651     { "demon",   SWI_MASK_DEMON },
 652     { "angel",   SWI_MASK_ANGEL },
 653     { "redboot", SWI_MASK_REDBOOT },
 654     { "all",     -1 },
 655     { "NONE",    0 },
 656     { "DEMON",   SWI_MASK_DEMON },
 657     { "ANGEL",   SWI_MASK_ANGEL },
 658     { "REDBOOT", SWI_MASK_REDBOOT },
 659     { "ALL",     -1 }
 660   };
 661
 662
 663 static int
 664 sim_target_parse_command_line (int argc, char ** argv)
 665 {
 666   int i;
 667
 668   for (i = 1; i < argc; i++)
 669     {
 670       char * ptr = argv[i];
 671       int arg;
 672
 673       if ((ptr == NULL) || (* ptr != '-'))
 674         break;
 675
 676       if (strcmp (ptr, "-t") == 0)
 677         {
 678           trace = 1;
 679           continue;
 680         }
 681
 682       if (strcmp (ptr, "-z") == 0)
 683         {
 684           /* Remove this option from the argv array.  */
 685           for (arg = i; arg < argc; arg ++)
 686             {
 687               free (argv[arg]);
 688               argv[arg] = argv[arg + 1];
 689             }
 690           argc --;
 691           i --;
 692           trace_funcs = 1;
 693           continue;
 694         }
 695
 696       if (strcmp (ptr, "-d") == 0)
 697         {
 698           /* Remove this option from the argv array.  */
 699           for (arg = i; arg < argc; arg ++)
 700             {
 701               free (argv[arg]);
 702               argv[arg] = argv[arg + 1];
 703             }
 704           argc --;
 705           i --;
 706           disas = 1;
 707           continue;
 708         }
 709
 710       if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
 711         continue;
 712
 713       if (ptr[sizeof SWI_SWITCH - 1] == 0)
 714         {
 715           /* Remove this option from the argv array.  */
 716           for (arg = i; arg < argc; arg ++)
 717             {
 718               free (argv[arg]);
 719               argv[arg] = argv[arg + 1];
 720             }
 721           argc --;
 722
 723           ptr = argv[i];
 724         }
 725       else
 726         ptr += sizeof SWI_SWITCH;
 727
 728       swi_mask = 0;
 729
 730       while (* ptr)
 731         {
 732           int i;
 733
 734           for (i = ARRAY_SIZE (options); i--;)
 735             if (strncmp (ptr, options[i].swi_option,
 736                          strlen (options[i].swi_option)) == 0)
 737               {
 738                 swi_mask |= options[i].swi_mask;
 739                 ptr += strlen (options[i].swi_option);
 740
 741                 if (* ptr == ',')
 742                   ++ ptr;
 743
 744                 break;
 745               }
 746
 747           if (i < 0)
 748             break;
 749         }
 750
 751       if (* ptr != 0)
 752         fprintf (stderr, "Ignoring swi options: %s\n", ptr);
 753
 754       /* Remove this option from the argv array.  */
 755       for (arg = i; arg < argc; arg ++)
 756         {
 757           free (argv[arg]);
 758           argv[arg] = argv[arg + 1];
 759         }
 760       argc --;
 761       i --;
 762     }
 763   return argc;
 764 }
 765
 766 static void
 767 sim_target_parse_arg_array (char ** argv)
 768 {
 769   sim_target_parse_command_line (countargv (argv), argv);
 770 }
 771
 772 static sim_cia
 773 arm_pc_get (sim_cpu *cpu)
 774 {
 775   return PC;
 776 }
 777
 778 static void
 779 arm_pc_set (sim_cpu *cpu, sim_cia pc)
 780 {
 781   ARMul_SetPC (state, pc);
 782 }
 783
 784 static void
 785 free_state (SIM_DESC sd)
 786 {
 787   if (STATE_MODULES (sd) != NULL)
 788     sim_module_uninstall (sd);
 789   sim_cpu_free_all (sd);
 790   sim_state_free (sd);
 791 }
 792
 793 SIM_DESC
 794 sim_open (SIM_OPEN_KIND kind,
 795           host_callback *cb,
 796           struct bfd *abfd,
 797           char * const *argv)
 798 {
 799   int i;
 800   char **argv_copy;
 801   SIM_DESC sd = sim_state_alloc (kind, cb);
 802   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 803
 804   /* Set default options before parsing user options.  */
 805   current_alignment = STRICT_ALIGNMENT;
 806
 807   /* The cpu data is kept in a separately allocated chunk of memory.  */
 808   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
 809     {
 810       free_state (sd);
 811       return 0;
 812     }
 813
 814   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 815     {
 816       free_state (sd);
 817       return 0;
 818     }
 819
 820   /* The parser will print an error message for us, so we silently return.  */
 821   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 822     {
 823       free_state (sd);
 824       return 0;
 825     }
 826
 827   /* Check for/establish the a reference program image.  */
 828   if (sim_analyze_program (sd,
 829                            (STATE_PROG_ARGV (sd) != NULL
 830                             ? *STATE_PROG_ARGV (sd)
 831                             : NULL), abfd) != SIM_RC_OK)
 832     {
 833       free_state (sd);
 834       return 0;
 835     }
 836
 837   /* Configure/verify the target byte order and other runtime
 838      configuration options.  */
 839   if (sim_config (sd) != SIM_RC_OK)
 840     {
 841       sim_module_uninstall (sd);
 842       return 0;
 843     }
 844
 845   if (sim_post_argv_init (sd) != SIM_RC_OK)
 846     {
 847       /* Uninstall the modules to avoid memory leaks,
 848          file descriptor leaks, etc.  */
 849       sim_module_uninstall (sd);
 850       return 0;
 851     }
 852
 853   /* CPU specific initialization.  */
 854   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 855     {
 856       SIM_CPU *cpu = STATE_CPU (sd, i);
 857
 858       CPU_REG_FETCH (cpu) = arm_reg_fetch;
 859       CPU_REG_STORE (cpu) = arm_reg_store;
 860       CPU_PC_FETCH (cpu) = arm_pc_get;
 861       CPU_PC_STORE (cpu) = arm_pc_set;
 862     }
 863
 864   sim_callback = cb;
 865
 866   /* Copy over the argv contents so we can modify them.  */
 867   argv_copy = dupargv (argv);
 868
 869   sim_target_parse_arg_array (argv_copy);
 870
 871   if (argv_copy[1] != NULL)
 872     {
 873       int i;
 874
 875       /* Scan for memory-size switches.  */
 876       for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
 877         if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
 878           {
 879             if (argv_copy[i][2] != '\0')
 880               mem_size = atoi (&argv_copy[i][2]);
 881             else if (argv_copy[i + 1] != NULL)
 882               {
 883                 mem_size = atoi (argv_copy[i + 1]);
 884                 i++;
 885               }
 886             else
 887               {
 888                 sim_callback->printf_filtered (sim_callback,
 889                                                "Missing argument to -m option\n");
 890                 return NULL;
 891               }
 892           }
 893     }
 894
 895   freeargv (argv_copy);
 896
 897   return sd;
 898 }
 899
 900 void
 901 sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
 902                  enum sim_stop *reason,
 903                  int *sigrc)
 904 {
 905   if (stop_simulator)
 906     {
 907       *reason = sim_stopped;
 908       *sigrc = GDB_SIGNAL_INT;
 909     }
 910   else if (state->EndCondition == 0)
 911     {
 912       *reason = sim_exited;
 913       *sigrc = state->Reg[0] & 255;
 914     }
 915   else
 916     {
 917       *reason = sim_stopped;
 918       if (state->EndCondition == RDIError_BreakpointReached)
 919         *sigrc = GDB_SIGNAL_TRAP;
 920       else if (   state->EndCondition == RDIError_DataAbort
 921                || state->EndCondition == RDIError_AddressException)
 922         *sigrc = GDB_SIGNAL_BUS;
 923       else
 924         *sigrc = 0;
 925     }
 926 }