sim/bfin/devices.c

   1 /* Blackfin device support.
   2
   3    Copyright (C) 2010-2022 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "sim-hw.h"
  26 #include "hw-device.h"
  27 #include "devices.h"
  28 #include "dv-bfin_cec.h"
  29 #include "dv-bfin_mmu.h"
  30
  31 static void
  32 bfin_mmr_invalid (struct hw *me, address_word addr,
  33                   unsigned nr_bytes, bool write, bool missing)
  34 {
  35   SIM_CPU *cpu = hw_system_cpu (me);
  36   const char *rw = write ? "write" : "read";
  37   const char *reason =
  38     missing ? "no such register" :
  39               (addr & 3) ? "must be 32-bit aligned" : "invalid length";
  40
  41   /* Only throw a fit if the cpu is doing the access.  DMA/GDB simply
  42      go unnoticed.  Not exactly hardware behavior, but close enough.  */
  43   if (!cpu)
  44     {
  45       sim_io_eprintf (hw_system (me),
  46                       "%s: invalid MMR %s at %#x length %u: %s\n",
  47                       hw_path (me), rw, addr, nr_bytes, reason);
  48       return;
  49     }
  50
  51   HW_TRACE ((me, "invalid MMR %s at %#x length %u: %s",
  52              rw, addr, nr_bytes, reason));
  53
  54   /* XXX: is this what hardware does ?  What about priority of unaligned vs
  55      wrong length vs missing register ?  What about system-vs-core ?  */
  56   /* XXX: We should move this addr check to a model property so we get the
  57      same behavior regardless of where we map the model.  */
  58   if (addr >= BFIN_CORE_MMR_BASE)
  59     /* XXX: This should be setting up CPLB fault addrs ?  */
  60     mmu_process_fault (cpu, addr, write, false, false, true);
  61   else
  62     /* XXX: Newer parts set up an interrupt from EBIU and program
  63             EBIU_ERRADDR with the address.  */
  64     cec_hwerr (cpu, HWERR_SYSTEM_MMR);
  65 }
  66
  67 void
  68 dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes,
  69                      bool write)
  70 {
  71   bfin_mmr_invalid (me, addr, nr_bytes, write, true);
  72 }
  73
  74 bool
  75 dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes,
  76                      unsigned size, bool write)
  77 {
  78   if ((addr & 0x3) == 0 && nr_bytes == size)
  79     return true;
  80
  81   bfin_mmr_invalid (me, addr, nr_bytes, write, false);
  82   return false;
  83 }
  84
  85 /* For 32-bit memory mapped registers that allow 16-bit or 32-bit access.  */
  86 bool
  87 dv_bfin_mmr_require_16_32 (struct hw *me, address_word addr, unsigned nr_bytes,
  88                            bool write)
  89 {
  90   if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4))
  91     return true;
  92
  93   bfin_mmr_invalid (me, addr, nr_bytes, write, false);
  94   return false;
  95 }
  96
  97 unsigned int dv_get_bus_num (struct hw *me)
  98 {
  99   const hw_unit *unit = hw_unit_address (me);
 100   return unit->cells[unit->nr_cells - 1];
 101 }