sim/common/cgen-trace.c

   1 /* Tracing support for CGEN-based simulators.
   2    Copyright (C) 1996-2020 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include <errno.h>
  22 #include "dis-asm.h"
  23 #include "bfd.h"
  24 #include "sim-main.h"
  25 #include "sim-fpu.h"
  26
  27 #ifndef SIZE_INSTRUCTION
  28 #define SIZE_INSTRUCTION 16
  29 #endif
  30
  31 #ifndef SIZE_LOCATION
  32 #define SIZE_LOCATION 20
  33 #endif
  34
  35 #ifndef SIZE_PC
  36 #define SIZE_PC 6
  37 #endif
  38
  39 #ifndef SIZE_LINE_NUMBER
  40 #define SIZE_LINE_NUMBER 4
  41 #endif
  42
  43 #ifndef SIZE_CYCLE_COUNT
  44 #define SIZE_CYCLE_COUNT 2
  45 #endif
  46
  47 #ifndef SIZE_TOTAL_CYCLE_COUNT
  48 #define SIZE_TOTAL_CYCLE_COUNT 9
  49 #endif
  50
  51 #ifndef SIZE_TRACE_BUF
  52 #define SIZE_TRACE_BUF 1024
  53 #endif
  54
  55 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
  56    count first but that isn't known until after the insn has executed.
  57    This also handles the queueing of trace results, TRACE_RESULT may be
  58    called multiple times for one insn.  */
  59 static char trace_buf[SIZE_TRACE_BUF];
  60 /* If NULL, output to stdout directly.  */
  61 static char *bufptr;
  62
  63 /* Non-zero if this is the first insn in a set of parallel insns.  */
  64 static int first_insn_p;
  65
  66 /* For communication between cgen_trace_insn and cgen_trace_result.  */
  67 static int printed_result_p;
  68
  69 /* Insn and its extracted fields.
  70    Set by cgen_trace_insn, used by cgen_trace_insn_fini.
  71    ??? Move to SIM_CPU to support heterogeneous multi-cpu case.  */
  72 static const struct cgen_insn *current_insn;
  73 static const struct argbuf *current_abuf;
  74
  75 void
  76 cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
  77 {
  78   bufptr = trace_buf;
  79   *bufptr = 0;
  80   first_insn_p = first_p;
  81
  82   /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
  83      called.  */
  84   current_insn = NULL;
  85   current_abuf = NULL;
  86 }
  87
  88 void
  89 cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
  90 {
  91   SIM_DESC sd = CPU_STATE (cpu);
  92
  93   /* Was insn traced?  It might not be if trace ranges are in effect.  */
  94   if (current_insn == NULL)
  95     return;
  96
  97   /* The first thing printed is current and total cycle counts.  */
  98
  99   if (PROFILE_MODEL_P (cpu)
 100       && ARGBUF_PROFILE_P (current_abuf))
 101     {
 102       unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
 103       unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
 104
 105       if (last_p)
 106         {
 107           trace_printf (sd, cpu, "%-*ld %-*ld ",
 108                         SIZE_CYCLE_COUNT, this_insn,
 109                         SIZE_TOTAL_CYCLE_COUNT, total);
 110         }
 111       else
 112         {
 113           trace_printf (sd, cpu, "%-*ld %-*s ",
 114                         SIZE_CYCLE_COUNT, this_insn,
 115                         SIZE_TOTAL_CYCLE_COUNT, "---");
 116         }
 117     }
 118
 119   /* Print the disassembled insn.  */
 120
 121   trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
 122
 123 #if 0
 124   /* Print insn results.  */
 125   {
 126     const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
 127
 128     if (opinst)
 129       {
 130         int i;
 131         int indices[MAX_OPERAND_INSTANCES];
 132
 133         /* Fetch the operands used by the insn.  */
 134         /* FIXME: Add fn ptr to CGEN_CPU_DESC.  */
 135         CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
 136                                       0, CGEN_FIELDS_BITSIZE (&insn_fields),
 137                                       indices);
 138
 139         for (i = 0;
 140              CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
 141              ++i, ++opinst)
 142           {
 143             if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
 144               cgen_trace_result (cpu, current_insn, opinst, indices[i]);
 145           }
 146       }
 147   }
 148 #endif
 149
 150   /* Print anything else requested.  */
 151
 152   if (*trace_buf)
 153     trace_printf (sd, cpu, " %s\n", trace_buf);
 154   else
 155     trace_printf (sd, cpu, "\n");
 156 }
 157
 158 void
 159 cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
 160                  const struct argbuf *abuf, IADDR pc)
 161 {
 162   char disasm_buf[50];
 163
 164   printed_result_p = 0;
 165   current_insn = opcode;
 166   current_abuf = abuf;
 167
 168   if (CGEN_INSN_VIRTUAL_P (opcode))
 169     {
 170       trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
 171                     NULL, 0, CGEN_INSN_NAME (opcode));
 172       return;
 173     }
 174
 175   CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
 176   trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
 177                 NULL, 0,
 178                 "%s%-*s",
 179                 first_insn_p ? " " : "|",
 180                 SIZE_INSTRUCTION, disasm_buf);
 181 }
 182
 183 void
 184 cgen_trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
 185 {
 186   va_list args;
 187   int printed_one_p = 0;
 188   char *fmt;
 189
 190   va_start (args, name);
 191
 192   trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
 193                 SIZE_PC, (unsigned long) pc, name);
 194
 195   do {
 196     int type,ival;
 197
 198     fmt = va_arg (args, char *);
 199
 200     if (fmt)
 201       {
 202         if (printed_one_p)
 203           trace_printf (CPU_STATE (cpu), cpu, ", ");
 204         printed_one_p = 1;
 205         type = va_arg (args, int);
 206         switch (type)
 207           {
 208           case 'x' :
 209             ival = va_arg (args, int);
 210             trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
 211             break;
 212           default :
 213             abort ();
 214           }
 215       }
 216   } while (fmt);
 217
 218   va_end (args);
 219   trace_printf (CPU_STATE (cpu), cpu, "\n");
 220 }
 221
 222 void
 223 cgen_trace_result (SIM_CPU *cpu, char *name, int type, ...)
 224 {
 225   va_list args;
 226
 227   va_start (args, type);
 228   if (printed_result_p)
 229     cgen_trace_printf (cpu, ", ");
 230
 231   switch (type)
 232     {
 233     case 'x' :
 234     default :
 235       cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
 236       break;
 237     case 'f':
 238       {
 239         DI di;
 240         sim_fpu f;
 241
 242         /* this is separated from previous line for sunos cc */
 243         di = va_arg (args, DI);
 244         sim_fpu_64to (&f, di);
 245
 246         cgen_trace_printf (cpu, "%s <- ", name);
 247         sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
 248         break;
 249       }
 250     case 'D' :
 251       {
 252         DI di;
 253         /* this is separated from previous line for sunos cc */
 254         di = va_arg (args, DI);
 255         cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
 256                            GETHIDI(di), GETLODI (di));
 257         break;
 258       }
 259     }
 260
 261   printed_result_p = 1;
 262   va_end (args);
 263 }
 264
 265 /* Print trace output to BUFPTR if active, otherwise print normally.
 266    This is only for tracing semantic code.  */
 267
 268 void
 269 cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...)
 270 {
 271   va_list args;
 272
 273   va_start (args, fmt);
 274
 275   if (bufptr == NULL)
 276     {
 277       if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
 278         (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
 279           (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
 280       else
 281         vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
 282     }
 283   else
 284     {
 285       vsprintf (bufptr, fmt, args);
 286       bufptr += strlen (bufptr);
 287       /* ??? Need version of SIM_ASSERT that is always enabled.  */
 288       if (bufptr - trace_buf > SIZE_TRACE_BUF)
 289         abort ();
 290     }
 291
 292   va_end (args);
 293 }
 294 \f
 295 /* Disassembly support.  */
 296
 297 /* sprintf to a "stream" */
 298
 299 int
 300 sim_disasm_sprintf (SFILE *f, const char *format, ...)
 301 {
 302   int n;
 303   va_list args;
 304
 305   va_start (args, format);
 306   vsprintf (f->current, format, args);
 307   f->current += n = strlen (f->current);
 308   va_end (args);
 309   return n;
 310 }
 311
 312 /* Memory read support for an opcodes disassembler.  */
 313
 314 int
 315 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
 316                         struct disassemble_info *info)
 317 {
 318   SIM_CPU *cpu = (SIM_CPU *) info->application_data;
 319   SIM_DESC sd = CPU_STATE (cpu);
 320   unsigned length_read;
 321
 322   length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
 323                                       length);
 324   if (length_read != length)
 325     return EIO;
 326   return 0;
 327 }
 328
 329 /* Memory error support for an opcodes disassembler.  */
 330
 331 void
 332 sim_disasm_perror_memory (int status, bfd_vma memaddr,
 333                           struct disassemble_info *info)
 334 {
 335   if (status != EIO)
 336     /* Can't happen.  */
 337     info->fprintf_func (info->stream, "Unknown error %d.", status);
 338   else
 339     /* Actually, address between memaddr and memaddr + len was
 340        out of bounds.  */
 341     info->fprintf_func (info->stream,
 342                         "Address 0x%x is out of bounds.",
 343                         (int) memaddr);
 344 }
 345
 346 /* Disassemble using the CGEN opcode table.
 347    ??? While executing an instruction, the insn has been decoded and all its
 348    fields have been extracted.  It is certainly possible to do the disassembly
 349    with that data.  This seems simpler, but maybe in the future the already
 350    extracted fields will be used.  */
 351
 352 void
 353 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
 354                            const ARGBUF *abuf, IADDR pc, char *buf)
 355 {
 356   unsigned int length;
 357   unsigned int base_length;
 358   unsigned long insn_value;
 359   struct disassemble_info disasm_info;
 360   SFILE sfile;
 361   union {
 362     unsigned8 bytes[CGEN_MAX_INSN_SIZE];
 363     unsigned16 shorts[8];
 364     unsigned32 words[4];
 365   } insn_buf;
 366   SIM_DESC sd = CPU_STATE (cpu);
 367   CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
 368   CGEN_EXTRACT_INFO ex_info;
 369   CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
 370   int insn_bit_length = CGEN_INSN_BITSIZE (insn);
 371   int insn_length = insn_bit_length / 8;
 372
 373   sfile.buffer = sfile.current = buf;
 374   INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
 375                          (fprintf_ftype) sim_disasm_sprintf);
 376   disasm_info.endian =
 377     (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
 378      : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
 379      : BFD_ENDIAN_UNKNOWN);
 380
 381   length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
 382                                  insn_length);
 383
 384   if (length != insn_length)
 385   {
 386     sim_io_error (sd, "unable to read address %x", pc);
 387   }
 388
 389   /* If the entire insn will fit into an integer, then do it. Otherwise, just
 390      use the bits of the base_insn.  */
 391   if (insn_bit_length <= 32)
 392     base_length = insn_bit_length;
 393   else
 394     base_length = min (cd->base_insn_bitsize, insn_bit_length);
 395   switch (base_length)
 396     {
 397     case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
 398     case 8 : insn_value = insn_buf.bytes[0]; break;
 399     case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
 400     case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
 401     default: abort ();
 402     }
 403
 404   disasm_info.buffer_vma = pc;
 405   disasm_info.buffer = insn_buf.bytes;
 406   disasm_info.buffer_length = length;
 407
 408   ex_info.dis_info = (PTR) &disasm_info;
 409   ex_info.valid = (1 << length) - 1;
 410   ex_info.insn_bytes = insn_buf.bytes;
 411
 412   length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
 413   /* Result of extract fn is in bits.  */
 414   /* ??? This assumes that each instruction has a fixed length (and thus
 415      for insns with multiple versions of variable lengths they would each
 416      have their own table entry).  */
 417   if (length == insn_bit_length)
 418     {
 419       (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
 420     }
 421   else
 422     {
 423       /* This shouldn't happen, but aborting is too drastic.  */
 424       strcpy (buf, "***unknown***");
 425     }
 426 }