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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2020 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #ifdef HAVE_STRING_H
31 #include <string.h>
32 #endif
33 #ifdef HAVE_TIME_H
34 #include <time.h>
35 #endif
36 #ifdef HAVE_SYS_TIME_H
37 #include <sys/time.h>
38 #endif
39
40 #include "sim-main.h"
41 #include "simops.h"
42 #include "targ-vals.h"
43
44 #ifdef TARGET_SYS_utime
45 #include <utime.h>
46 #endif
47 #ifdef TARGET_SYS_wait
48 #include <sys/wait.h>
49 #endif
50
51 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
52
53 enum op_types {
54 OP_VOID,
55 OP_CONSTANT3,
56 OP_UCONSTANT3,
57 OP_CONSTANT4,
58 OP_CONSTANT4_1,
59 OP_CONSTANT5,
60 OP_CONSTANT6,
61 OP_CONSTANT16,
62 OP_UCONSTANT16,
63 OP_CONSTANT20,
64 OP_UCONSTANT20,
65 OP_CONSTANT32,
66 OP_UCONSTANT32,
67 OP_MEMREF,
68 OP_MEMREF2,
69 OP_MEMREF3,
70
71 OP_DISP5,
72 OP_DISP17,
73 OP_DISP25,
74 OP_DISPE9,
75 //OP_ABS20,
76 OP_ABS20_OUTPUT,
77 //OP_ABS24,
78 OP_ABS24_OUTPUT,
79
80 OP_R_BASE_DISPS16,
81 OP_R_BASE_DISP20,
82 OP_R_BASE_DISPS20,
83 OP_R_BASE_DISPE20,
84
85 OP_RP_BASE_DISPE0,
86 OP_RP_BASE_DISP4,
87 OP_RP_BASE_DISPE4,
88 OP_RP_BASE_DISP14,
89 OP_RP_BASE_DISP16,
90 OP_RP_BASE_DISP20,
91 OP_RP_BASE_DISPS20,
92 OP_RP_BASE_DISPE20,
93
94 OP_R_INDEX7_ABS20,
95 OP_R_INDEX8_ABS20,
96
97 OP_RP_INDEX_DISP0,
98 OP_RP_INDEX_DISP14,
99 OP_RP_INDEX_DISP20,
100 OP_RP_INDEX_DISPS20,
101
102 OP_REG,
103 OP_REGP,
104 OP_PROC_REG,
105 OP_PROC_REGP,
106 OP_COND,
107 OP_RA
108 };
109
110
111 enum {
112 PSR_MASK = (PSR_I_BIT
113 | PSR_P_BIT
114 | PSR_E_BIT
115 | PSR_N_BIT
116 | PSR_Z_BIT
117 | PSR_F_BIT
118 | PSR_U_BIT
119 | PSR_L_BIT
120 | PSR_T_BIT
121 | PSR_C_BIT),
122 /* The following bits in the PSR _can't_ be set by instructions such
123 as mvtc. */
124 PSR_HW_MASK = (PSR_MASK)
125 };
126
127 /* cond Code Condition True State
128 * EQ Equal Z flag is 1
129 * NE Not Equal Z flag is 0
130 * CS Carry Set C flag is 1
131 * CC Carry Clear C flag is 0
132 * HI Higher L flag is 1
133 * LS Lower or Same L flag is 0
134 * GT Greater Than N flag is 1
135 * LE Less Than or Equal To N flag is 0
136 * FS Flag Set F flag is 1
137 * FC Flag Clear F flag is 0
138 * LO Lower Z and L flags are 0
139 * HS Higher or Same Z or L flag is 1
140 * LT Less Than Z and N flags are 0
141 * GE Greater Than or Equal To Z or N flag is 1. */
142
143 static int cond_stat(int cc)
144 {
145 switch (cc)
146 {
147 case 0: return PSR_Z; break;
148 case 1: return !PSR_Z; break;
149 case 2: return PSR_C; break;
150 case 3: return !PSR_C; break;
151 case 4: return PSR_L; break;
152 case 5: return !PSR_L; break;
153 case 6: return PSR_N; break;
154 case 7: return !PSR_N; break;
155 case 8: return PSR_F; break;
156 case 9: return !PSR_F; break;
157 case 10: return !PSR_Z && !PSR_L; break;
158 case 11: return PSR_Z || PSR_L; break;
159 case 12: return !PSR_Z && !PSR_N; break;
160 case 13: return PSR_Z || PSR_N; break;
161 case 14: return 1; break; /*ALWAYS. */
162 default:
163 // case NEVER: return false; break;
164 //case NO_COND_CODE:
165 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
166 return 0; break;
167 }
168 return 0;
169 }
170
171
172 creg_t
173 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
174 {
175 /* A MASK bit is set when the corresponding bit in the CR should
176 be left alone. */
177 /* This assumes that (VAL & MASK) == 0. */
178 switch (cr)
179 {
180 case PSR_CR:
181 if (psw_hw_p)
182 val &= PSR_HW_MASK;
183 #if 0
184 else
185 val &= PSR_MASK;
186 sim_io_printf
187 (sd,
188 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
189 EXCEPTION (SIM_SIGILL);
190 #endif
191 /* keep an up-to-date psw around for tracing. */
192 State.trace.psw = (State.trace.psw & mask) | val;
193 break;
194 default:
195 break;
196 }
197 /* only issue an update if the register is being changed. */
198 if ((State.cregs[cr] & ~mask) != val)
199 SLOT_PEND_MASK (State.cregs[cr], mask, val);
200
201 return val;
202 }
203
204 #ifdef DEBUG
205 static void trace_input_func (SIM_DESC sd,
206 const char *name,
207 enum op_types in1,
208 enum op_types in2,
209 enum op_types in3);
210
211 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
212
213 #ifndef SIZE_INSTRUCTION
214 #define SIZE_INSTRUCTION 8
215 #endif
216
217 #ifndef SIZE_OPERANDS
218 #define SIZE_OPERANDS 18
219 #endif
220
221 #ifndef SIZE_VALUES
222 #define SIZE_VALUES 13
223 #endif
224
225 #ifndef SIZE_LOCATION
226 #define SIZE_LOCATION 20
227 #endif
228
229 #ifndef SIZE_PC
230 #define SIZE_PC 4
231 #endif
232
233 #ifndef SIZE_LINE_NUMBER
234 #define SIZE_LINE_NUMBER 2
235 #endif
236
237 static void
238 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
239 {
240 char *comma;
241 enum op_types in[3];
242 int i;
243 char buf[1024];
244 char *p;
245 long tmp;
246 char *type;
247 const char *filename;
248 const char *functionname;
249 unsigned int linenumber;
250 bfd_vma byte_pc;
251
252 if ((cr16_debug & DEBUG_TRACE) == 0)
253 return;
254
255 switch (State.ins_type)
256 {
257 default:
258 case INS_UNKNOWN: type = " ?"; break;
259 }
260
261 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
262 sim_io_printf (sd,
263 "0x%.*x %s: %-*s ",
264 SIZE_PC, (unsigned)PC,
265 type,
266 SIZE_INSTRUCTION, name);
267
268 else
269 {
270 buf[0] = '\0';
271 byte_pc = PC;
272 if (STATE_TEXT_SECTION (sd)
273 && byte_pc >= STATE_TEXT_START (sd)
274 && byte_pc < STATE_TEXT_END (sd))
275 {
276 filename = (const char *)0;
277 functionname = (const char *)0;
278 linenumber = 0;
279 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
280 STATE_TEXT_SECTION (sd),
281 (struct bfd_symbol **)0,
282 byte_pc - STATE_TEXT_START (sd),
283 &filename, &functionname, &linenumber))
284 {
285 p = buf;
286 if (linenumber)
287 {
288 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
289 p += strlen (p);
290 }
291 else
292 {
293 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
294 p += SIZE_LINE_NUMBER+2;
295 }
296
297 if (functionname)
298 {
299 sprintf (p, "%s ", functionname);
300 p += strlen (p);
301 }
302 else if (filename)
303 {
304 char *q = strrchr (filename, '/');
305 sprintf (p, "%s ", (q) ? q+1 : filename);
306 p += strlen (p);
307 }
308
309 if (*p == ' ')
310 *p = '\0';
311 }
312 }
313
314 sim_io_printf (sd,
315 "0x%.*x %s: %-*.*s %-*s ",
316 SIZE_PC, (unsigned)PC,
317 type,
318 SIZE_LOCATION, SIZE_LOCATION, buf,
319 SIZE_INSTRUCTION, name);
320 }
321
322 in[0] = in1;
323 in[1] = in2;
324 in[2] = in3;
325 comma = "";
326 p = buf;
327 for (i = 0; i < 3; i++)
328 {
329 switch (in[i])
330 {
331 case OP_VOID:
332 break;
333
334 case OP_REG:
335 case OP_REGP:
336 sprintf (p, "%sr%d", comma, OP[i]);
337 p += strlen (p);
338 comma = ",";
339 break;
340
341 case OP_PROC_REG:
342 sprintf (p, "%scr%d", comma, OP[i]);
343 p += strlen (p);
344 comma = ",";
345 break;
346
347 case OP_CONSTANT16:
348 sprintf (p, "%s%d", comma, OP[i]);
349 p += strlen (p);
350 comma = ",";
351 break;
352
353 case OP_CONSTANT4:
354 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
355 p += strlen (p);
356 comma = ",";
357 break;
358
359 case OP_CONSTANT3:
360 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
361 p += strlen (p);
362 comma = ",";
363 break;
364
365 case OP_MEMREF:
366 sprintf (p, "%s@r%d", comma, OP[i]);
367 p += strlen (p);
368 comma = ",";
369 break;
370
371 case OP_MEMREF2:
372 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
373 p += strlen (p);
374 comma = ",";
375 break;
376
377 case OP_MEMREF3:
378 sprintf (p, "%s@%d", comma, OP[i]);
379 p += strlen (p);
380 comma = ",";
381 break;
382 }
383 }
384
385 if ((cr16_debug & DEBUG_VALUES) == 0)
386 {
387 *p++ = '\n';
388 *p = '\0';
389 sim_io_printf (sd, "%s", buf);
390 }
391 else
392 {
393 *p = '\0';
394 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
395
396 p = buf;
397 for (i = 0; i < 3; i++)
398 {
399 buf[0] = '\0';
400 switch (in[i])
401 {
402 case OP_VOID:
403 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
404 break;
405
406 case OP_REG:
407 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
408 (uint16) GPR (OP[i]));
409 break;
410
411 case OP_REGP:
412 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
413 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
414 break;
415
416 case OP_PROC_REG:
417 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16) CREG (OP[i]));
419 break;
420
421 case OP_CONSTANT16:
422 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
423 (uint16)OP[i]);
424 break;
425
426 case OP_CONSTANT4:
427 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
428 (uint16)SEXT4(OP[i]));
429 break;
430
431 case OP_CONSTANT3:
432 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
433 (uint16)SEXT3(OP[i]));
434 break;
435
436 case OP_MEMREF2:
437 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
438 (uint16)OP[i]);
439 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)GPR (OP[i + 1]));
441 i++;
442 break;
443 }
444 }
445 }
446
447 sim_io_flush_stdout (sd);
448 }
449
450 static void
451 do_trace_output_flush (SIM_DESC sd)
452 {
453 sim_io_flush_stdout (sd);
454 }
455
456 static void
457 do_trace_output_finish (SIM_DESC sd)
458 {
459 sim_io_printf (sd,
460 " F0=%d F1=%d C=%d\n",
461 (State.trace.psw & PSR_F_BIT) != 0,
462 (State.trace.psw & PSR_F_BIT) != 0,
463 (State.trace.psw & PSR_C_BIT) != 0);
464 sim_io_flush_stdout (sd);
465 }
466
467 #if 0
468 static void
469 trace_output_40 (SIM_DESC sd, uint64 val)
470 {
471 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
472 {
473 sim_io_printf (sd,
474 " :: %*s0x%.2x%.8lx",
475 SIZE_VALUES - 12,
476 "",
477 ((int)(val >> 32) & 0xff),
478 ((unsigned long) val) & 0xffffffff);
479 do_trace_output_finish ();
480 }
481 }
482 #endif
483
484 static void
485 trace_output_32 (SIM_DESC sd, uint32 val)
486 {
487 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
488 {
489 sim_io_printf (sd,
490 " :: %*s0x%.8x",
491 SIZE_VALUES - 10,
492 "",
493 (int) val);
494 do_trace_output_finish (sd);
495 }
496 }
497
498 static void
499 trace_output_16 (SIM_DESC sd, uint16 val)
500 {
501 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
502 {
503 sim_io_printf (sd,
504 " :: %*s0x%.4x",
505 SIZE_VALUES - 6,
506 "",
507 (int) val);
508 do_trace_output_finish (sd);
509 }
510 }
511
512 static void
513 trace_output_void (SIM_DESC sd)
514 {
515 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
516 {
517 sim_io_printf (sd, "\n");
518 do_trace_output_flush (sd);
519 }
520 }
521
522 static void
523 trace_output_flag (SIM_DESC sd)
524 {
525 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
526 {
527 sim_io_printf (sd,
528 " :: %*s",
529 SIZE_VALUES,
530 "");
531 do_trace_output_finish (sd);
532 }
533 }
534
535
536
537
538 #else
539 #define trace_input(NAME, IN1, IN2, IN3)
540 #define trace_output(RESULT)
541 #endif
542
543 /* addub. */
544 void
545 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
546 {
547 uint8 tmp;
548 uint8 a = OP[0] & 0xff;
549 uint16 b = (GPR (OP[1])) & 0xff;
550 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
551 tmp = (a + b) & 0xff;
552 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
553 trace_output_16 (sd, tmp);
554 }
555
556 /* addub. */
557 void
558 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
559 {
560 uint16 tmp;
561 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
562 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
563 tmp = (a + b) & 0xff;
564 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
565 trace_output_16 (sd, tmp);
566 }
567
568 /* addub. */
569 void
570 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
571 {
572 uint8 a = (GPR (OP[0])) & 0xff;
573 uint8 b = (GPR (OP[1])) & 0xff;
574 uint16 tmp = (a + b) & 0xff;
575 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
576 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
577 trace_output_16 (sd, tmp);
578 }
579
580 /* adduw. */
581 void
582 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
583 {
584 uint16 a = OP[0];
585 uint16 b = GPR (OP[1]);
586 uint16 tmp = (a + b);
587 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
588 SET_GPR (OP[1], tmp);
589 trace_output_16 (sd, tmp);
590 }
591
592 /* adduw. */
593 void
594 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
595 {
596 uint16 a = OP[0];
597 uint16 b = GPR (OP[1]);
598 uint16 tmp = (a + b);
599 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
600 SET_GPR (OP[1], tmp);
601 trace_output_16 (sd, tmp);
602 }
603
604 /* adduw. */
605 void
606 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
607 {
608 uint16 a = GPR (OP[0]);
609 uint16 b = GPR (OP[1]);
610 uint16 tmp = (a + b);
611 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
612 SET_GPR (OP[1], tmp);
613 trace_output_16 (sd, tmp);
614 }
615
616 /* addb. */
617 void
618 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
619 {
620 uint8 a = OP[0];
621 uint8 b = (GPR (OP[1]) & 0xff);
622 uint16 tmp = (a + b) & 0xff;
623 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
624 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
625 SET_PSR_C (tmp > 0xFF);
626 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
627 trace_output_16 (sd, tmp);
628 }
629
630 /* addb. */
631 void
632 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
633 {
634 uint8 a = (OP[0]) & 0xff;
635 uint8 b = (GPR (OP[1]) & 0xff);
636 uint16 tmp = (a + b) & 0xff;
637 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
638 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
639 SET_PSR_C (tmp > 0xFF);
640 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
641 trace_output_16 (sd, tmp);
642 }
643
644 /* addb. */
645 void
646 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
647 {
648 uint8 a = (GPR (OP[0]) & 0xff);
649 uint8 b = (GPR (OP[1]) & 0xff);
650 uint16 tmp = (a + b) & 0xff;
651 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
652 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
653 SET_PSR_C (tmp > 0xFF);
654 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
655 trace_output_16 (sd, tmp);
656 }
657
658 /* addw. */
659 void
660 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
661 {
662 int16 a = OP[0];
663 uint16 tmp, b = GPR (OP[1]);
664 tmp = (a + b);
665 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
666 SET_GPR (OP[1], tmp);
667 SET_PSR_C (tmp > 0xFFFF);
668 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
669 trace_output_16 (sd, tmp);
670 }
671
672 /* addw. */
673 void
674 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
675 {
676 int16 a = OP[0];
677 uint16 tmp, b = GPR (OP[1]);
678 tmp = (a + b);
679 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
680 SET_GPR (OP[1], tmp);
681 SET_PSR_C (tmp > 0xFFFF);
682 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
683 trace_output_16 (sd, tmp);
684 }
685
686 /* addw. */
687 void
688 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
689 {
690 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
691 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
692 tmp = (a + b);
693 SET_GPR (OP[1], tmp);
694 SET_PSR_C (tmp > 0xFFFF);
695 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
696 trace_output_16 (sd, tmp);
697 }
698
699 /* addcb. */
700 void
701 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
702 {
703 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
704 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
705 tmp = (a + b + PSR_C) & 0xff;
706 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
707 SET_PSR_C (tmp > 0xFF);
708 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
709 trace_output_16 (sd, tmp);
710 }
711
712 /* addcb. */
713 void
714 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
715 {
716 int8 a = OP[0] & 0xff;
717 uint8 b = (GPR (OP[1])) & 0xff;
718 uint8 tmp = (a + b + PSR_C) & 0xff;
719 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
720 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
721 SET_PSR_C (tmp > 0xFF);
722 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
723 trace_output_16 (sd, tmp);
724 }
725
726 /* addcb. */
727 void
728 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
729 {
730 uint8 a = (GPR (OP[0])) & 0xff;
731 uint8 b = (GPR (OP[1])) & 0xff;
732 uint8 tmp = (a + b + PSR_C) & 0xff;
733 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
734 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
735 SET_PSR_C (tmp > 0xFF);
736 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
737 trace_output_16 (sd, tmp);
738 }
739
740 /* addcw. */
741 void
742 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
743 {
744 uint16 a = OP[0];
745 uint16 b = GPR (OP[1]);
746 uint16 tmp = (a + b + PSR_C);
747 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
748 SET_GPR (OP[1], tmp);
749 SET_PSR_C (tmp > 0xFFFF);
750 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
751 trace_output_16 (sd, tmp);
752 }
753
754 /* addcw. */
755 void
756 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
757 {
758 int16 a = OP[0];
759 uint16 b = GPR (OP[1]);
760 uint16 tmp = (a + b + PSR_C);
761 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
762 SET_GPR (OP[1], tmp);
763 SET_PSR_C (tmp > 0xFFFF);
764 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
765 trace_output_16 (sd, tmp);
766 }
767
768 /* addcw. */
769 void
770 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
771 {
772 uint16 a = GPR (OP[1]);
773 uint16 b = GPR (OP[1]);
774 uint16 tmp = (a + b + PSR_C);
775 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
776 SET_GPR (OP[1], tmp);
777 SET_PSR_C (tmp > 0xFFFF);
778 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
779 trace_output_16 (sd, tmp);
780 }
781
782 /* addd. */
783 void
784 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
785 {
786 int16 a = (OP[0]);
787 uint32 b = GPR32 (OP[1]);
788 uint32 tmp = (a + b);
789 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
790 SET_GPR32 (OP[1], tmp);
791 SET_PSR_C (tmp > 0xFFFFFFFF);
792 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
793 trace_output_32 (sd, tmp);
794 }
795
796 /* addd. */
797 void
798 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
799 {
800 int32 a = (SEXT16(OP[0]));
801 uint32 b = GPR32 (OP[1]);
802 uint32 tmp = (a + b);
803 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
804 SET_GPR32 (OP[1], tmp);
805 SET_PSR_C (tmp > 0xFFFFFFFF);
806 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
807 trace_output_32 (sd, tmp);
808 }
809
810 /* addd. */
811 void
812 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
813 {
814 uint32 a = GPR32 (OP[0]);
815 uint32 b = GPR32 (OP[1]);
816 uint32 tmp = (a + b);
817 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
818 SET_GPR32 (OP[1], tmp);
819 trace_output_32 (sd, tmp);
820 SET_PSR_C (tmp > 0xFFFFFFFF);
821 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
822 }
823
824 /* addd. */
825 void
826 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
827 {
828 uint32 a = OP[0];
829 uint32 b = GPR32 (OP[1]);
830 uint32 tmp;
831 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
832 tmp = (a + b);
833 SET_GPR32 (OP[1], tmp);
834 SET_PSR_C (tmp > 0xFFFFFFFF);
835 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
836 trace_output_32 (sd, tmp);
837 }
838
839 /* addd. */
840 void
841 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
842 {
843 int32 a = OP[0];
844 uint32 b = GPR32 (OP[1]);
845 uint32 tmp;
846 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
847 tmp = (a + b);
848 SET_GPR32 (OP[1], tmp);
849 SET_PSR_C (tmp > 0xFFFFFFFF);
850 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
851 trace_output_32 (sd, tmp);
852 }
853
854 /* andb. */
855 void
856 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
857 {
858 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
859 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
860 tmp = a & b;
861 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
862 trace_output_16 (sd, tmp);
863 }
864
865 /* andb. */
866 void
867 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
868 {
869 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
870 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
871 tmp = a & b;
872 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
873 trace_output_16 (sd, tmp);
874 }
875
876 /* andb. */
877 void
878 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
879 {
880 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
881 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
882 tmp = a & b;
883 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
884 trace_output_16 (sd, tmp);
885 }
886
887 /* andw. */
888 void
889 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
890 {
891 uint16 tmp, a = OP[0], b = GPR (OP[1]);
892 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
893 tmp = a & b;
894 SET_GPR (OP[1], tmp);
895 trace_output_16 (sd, tmp);
896 }
897
898 /* andw. */
899 void
900 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
901 {
902 uint16 tmp, a = OP[0], b = GPR (OP[1]);
903 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
904 tmp = a & b;
905 SET_GPR (OP[1], tmp);
906 trace_output_16 (sd, tmp);
907 }
908
909 /* andw. */
910 void
911 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
912 {
913 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
914 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
915 tmp = a & b;
916 SET_GPR (OP[1], tmp);
917 trace_output_16 (sd, tmp);
918 }
919
920 /* andd. */
921 void
922 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
923 {
924 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
925 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
926 tmp = a & b;
927 SET_GPR32 (OP[1], tmp);
928 trace_output_32 (sd, tmp);
929 }
930
931 /* andd. */
932 void
933 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
934 {
935 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
936 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
937 tmp = a & b;
938 SET_GPR32 (OP[1], tmp);
939 trace_output_32 (sd, tmp);
940 }
941
942 /* ord. */
943 void
944 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
945 {
946 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
947 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
948 tmp = a | b;
949 SET_GPR32 (OP[1], tmp);
950 trace_output_32 (sd, tmp);
951 }
952
953 /* ord. */
954 void
955 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
956 {
957 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
958 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
959 tmp = a | b;
960 SET_GPR32 (OP[1], tmp);
961 trace_output_32 (sd, tmp);
962 }
963
964 /* xord. */
965 void
966 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
967 {
968 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
969 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
970 tmp = a ^ b;
971 SET_GPR32 (OP[1], tmp);
972 trace_output_32 (sd, tmp);
973 }
974
975 /* xord. */
976 void
977 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
978 {
979 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
980 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
981 tmp = a ^ b;
982 SET_GPR32 (OP[1], tmp);
983 trace_output_32 (sd, tmp);
984 }
985
986
987 /* b. */
988 void
989 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
990 {
991 uint32 tmp = 0, cc = cond_stat (OP[0]);
992 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
993 if (cc)
994 {
995 if (sign_flag)
996 tmp = (PC - (OP[1]));
997 else
998 tmp = (PC + (OP[1]));
999 /* If the resulting PC value is less than 0x00_0000 or greater
1000 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1001
1002 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1003 {
1004 trace_output_void (sd);
1005 EXCEPTION (SIM_SIGBUS);
1006 }
1007 else
1008 JMP (tmp);
1009 }
1010 sign_flag = 0; /* Reset sign_flag. */
1011 trace_output_32 (sd, tmp);
1012 }
1013
1014 /* b. */
1015 void
1016 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
1017 {
1018 uint32 tmp = 0, cc = cond_stat (OP[0]);
1019 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1020 if (cc)
1021 {
1022 if (sign_flag)
1023 tmp = (PC - OP[1]);
1024 else
1025 tmp = (PC + OP[1]);
1026 /* If the resulting PC value is less than 0x00_0000 or greater
1027 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1028
1029 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1030 {
1031 trace_output_void (sd);
1032 EXCEPTION (SIM_SIGBUS);
1033 }
1034 else
1035 JMP (tmp);
1036 }
1037 sign_flag = 0; /* Reset sign_flag. */
1038 trace_output_32 (sd, tmp);
1039 }
1040
1041 /* b. */
1042 void
1043 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
1044 {
1045 uint32 tmp = 0, cc = cond_stat (OP[0]);
1046 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1047 if (cc)
1048 {
1049 if (sign_flag)
1050 tmp = (PC - (OP[1]));
1051 else
1052 tmp = (PC + (OP[1]));
1053 /* If the resulting PC value is less than 0x00_0000 or greater
1054 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1055
1056 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1057 {
1058 trace_output_void (sd);
1059 EXCEPTION (SIM_SIGBUS);
1060 }
1061 else
1062 JMP (tmp);
1063 }
1064 sign_flag = 0; /* Reset sign_flag. */
1065 trace_output_32 (sd, tmp);
1066 }
1067
1068 /* bal. */
1069 void
1070 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
1071 {
1072 uint32 tmp;
1073 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1074 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1075 SET_GPR32 (14, tmp);
1076 if (sign_flag)
1077 tmp = (PC - (OP[1]));
1078 else
1079 tmp = (PC + (OP[1]));
1080
1081 /* If the resulting PC value is less than 0x00_0000 or greater
1082 than 0xFF_FFFF, this instruction causes an IAD trap. */
1083
1084 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1085 {
1086 trace_output_void (sd);
1087 EXCEPTION (SIM_SIGBUS);
1088 }
1089 else
1090 JMP (tmp);
1091 sign_flag = 0; /* Reset sign_flag. */
1092 trace_output_32 (sd, tmp);
1093 }
1094
1095
1096 /* bal. */
1097 void
1098 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
1099 {
1100 uint32 tmp;
1101 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1102 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1103 SET_GPR32 (OP[0], tmp);
1104 if (sign_flag)
1105 tmp = ((PC) - (OP[1]));
1106 else
1107 tmp = ((PC) + (OP[1]));
1108 /* If the resulting PC value is less than 0x00_0000 or greater
1109 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1110
1111 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1112 {
1113 trace_output_void (sd);
1114 EXCEPTION (SIM_SIGBUS);
1115 }
1116 else
1117 JMP (tmp);
1118 sign_flag = 0; /* Reset sign_flag. */
1119 trace_output_32 (sd, tmp);
1120 }
1121
1122 /* jal. */
1123 void
1124 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
1125 {
1126 uint32 tmp;
1127 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1128 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1129 tmp = GPR32 (OP[1]);
1130 tmp = SEXT24(tmp << 1);
1131 /* If the resulting PC value is less than 0x00_0000 or greater
1132 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1133
1134 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1135 {
1136 trace_output_void (sd);
1137 EXCEPTION (SIM_SIGBUS);
1138 }
1139 else
1140 JMP (tmp);
1141
1142 trace_output_32 (sd, tmp);
1143 }
1144
1145
1146 /* jal. */
1147 void
1148 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
1149 {
1150 uint32 tmp;
1151 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1152 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1153 tmp = GPR32 (OP[0]);
1154 tmp = SEXT24(tmp << 1);
1155 /* If the resulting PC value is less than 0x00_0000 or greater
1156 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1157
1158 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1159 {
1160 trace_output_void (sd);
1161 EXCEPTION (SIM_SIGBUS);
1162 }
1163 else
1164 JMP (tmp);
1165
1166 trace_output_32 (sd, tmp);
1167 }
1168
1169
1170 /* beq0b. */
1171 void
1172 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
1173 {
1174 uint32 addr;
1175 uint8 a = (GPR (OP[0]) & 0xFF);
1176 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1177 addr = OP[1];
1178 if (a == 0)
1179 {
1180 if (sign_flag)
1181 addr = (PC - OP[1]);
1182 else
1183 addr = (PC + OP[1]);
1184
1185 JMP (addr);
1186 }
1187 sign_flag = 0; /* Reset sign_flag. */
1188 trace_output_void (sd);
1189 }
1190
1191 /* bne0b. */
1192 void
1193 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
1194 {
1195 uint32 addr;
1196 uint8 a = (GPR (OP[0]) & 0xFF);
1197 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1198 addr = OP[1];
1199 if (a != 0)
1200 {
1201 if (sign_flag)
1202 addr = (PC - OP[1]);
1203 else
1204 addr = (PC + OP[1]);
1205
1206 JMP (addr);
1207 }
1208 sign_flag = 0; /* Reset sign_flag. */
1209 trace_output_void (sd);
1210 }
1211
1212 /* beq0w. */
1213 void
1214 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
1215 {
1216 uint32 addr;
1217 uint16 a = GPR (OP[0]);
1218 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1219 addr = OP[1];
1220 if (a == 0)
1221 {
1222 if (sign_flag)
1223 addr = (PC - OP[1]);
1224 else
1225 addr = (PC + OP[1]);
1226
1227 JMP (addr);
1228 }
1229 sign_flag = 0; /* Reset sign_flag. */
1230 trace_output_void (sd);
1231 }
1232
1233 /* bne0w. */
1234 void
1235 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
1236 {
1237 uint32 addr;
1238 uint16 a = GPR (OP[0]);
1239 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1240 addr = OP[1];
1241 if (a != 0)
1242 {
1243 if (sign_flag)
1244 addr = (PC - OP[1]);
1245 else
1246 addr = (PC + OP[1]);
1247
1248 JMP (addr);
1249 }
1250 sign_flag = 0; /* Reset sign_flag. */
1251 trace_output_void (sd);
1252 }
1253
1254
1255 /* jeq. */
1256 void
1257 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
1258 {
1259 uint32 tmp = 0;
1260 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1261 if ((PSR_Z) == 1)
1262 {
1263 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1264 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1265 }
1266 trace_output_32 (sd, tmp);
1267 }
1268
1269 /* jne. */
1270 void
1271 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
1272 {
1273 uint32 tmp = 0;
1274 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1275 if ((PSR_Z) == 0)
1276 {
1277 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1278 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1279 }
1280 trace_output_32 (sd, tmp);
1281 }
1282
1283 /* jcs. */
1284 void
1285 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
1286 {
1287 uint32 tmp = 0;
1288 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1289 if ((PSR_C) == 1)
1290 {
1291 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1292 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1293 }
1294 trace_output_32 (sd, tmp);
1295 }
1296
1297 /* jcc. */
1298 void
1299 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
1300 {
1301 uint32 tmp = 0;
1302 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1303 if ((PSR_C) == 0)
1304 {
1305 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1306 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1307 }
1308 trace_output_32 (sd, tmp);
1309 }
1310
1311 /* jhi. */
1312 void
1313 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
1314 {
1315 uint32 tmp = 0;
1316 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1317 if ((PSR_L) == 1)
1318 {
1319 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1320 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1321 }
1322 trace_output_32 (sd, tmp);
1323 }
1324
1325 /* jls. */
1326 void
1327 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
1328 {
1329 uint32 tmp = 0;
1330 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1331 if ((PSR_L) == 0)
1332 {
1333 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1334 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1335 }
1336 trace_output_32 (sd, tmp);
1337 }
1338
1339 /* jgt. */
1340 void
1341 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
1342 {
1343 uint32 tmp = 0;
1344 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1345 if ((PSR_N) == 1)
1346 {
1347 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1348 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1349 }
1350 trace_output_32 (sd, tmp);
1351 }
1352
1353 /* jle. */
1354 void
1355 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
1356 {
1357 uint32 tmp = 0;
1358 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1359 if ((PSR_N) == 0)
1360 {
1361 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1362 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1363 }
1364 trace_output_32 (sd, tmp);
1365 }
1366
1367
1368 /* jfs. */
1369 void
1370 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
1371 {
1372 uint32 tmp = 0;
1373 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1374 if ((PSR_F) == 1)
1375 {
1376 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1377 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1378 }
1379 trace_output_32 (sd, tmp);
1380 }
1381
1382 /* jfc. */
1383 void
1384 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
1385 {
1386 uint32 tmp = 0;
1387 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1388 if ((PSR_F) == 0)
1389 {
1390 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1391 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1392 }
1393 trace_output_32 (sd, tmp);
1394 }
1395
1396 /* jlo. */
1397 void
1398 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
1399 {
1400 uint32 tmp = 0;
1401 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1402 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1403 {
1404 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1405 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1406 }
1407 trace_output_32 (sd, tmp);
1408 }
1409
1410 /* jhs. */
1411 void
1412 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
1413 {
1414 uint32 tmp = 0;
1415 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1416 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1417 {
1418 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1419 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1420 }
1421 trace_output_32 (sd, tmp);
1422 }
1423
1424 /* jlt. */
1425 void
1426 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
1427 {
1428 uint32 tmp = 0;
1429 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1430 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1431 {
1432 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1433 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1434 }
1435 trace_output_32 (sd, tmp);
1436 }
1437
1438 /* jge. */
1439 void
1440 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
1441 {
1442 uint32 tmp = 0;
1443 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1444 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1445 {
1446 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1447 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1448 }
1449 trace_output_32 (sd, tmp);
1450 }
1451
1452 /* jump. */
1453 void
1454 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
1455 {
1456 uint32 tmp;
1457 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1458 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1459 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1460 trace_output_32 (sd, tmp);
1461 }
1462
1463 /* jusr. */
1464 void
1465 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
1466 {
1467 uint32 tmp;
1468 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1469 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1470 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1471 SET_PSR_U(1);
1472 trace_output_32 (sd, tmp);
1473 }
1474
1475 /* seq. */
1476 void
1477 OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
1478 {
1479 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1480 if ((PSR_Z) == 1)
1481 SET_GPR (OP[0], 1);
1482 else
1483 SET_GPR (OP[0], 0);
1484 trace_output_void (sd);
1485 }
1486 /* sne. */
1487 void
1488 OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
1489 {
1490 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1491 if ((PSR_Z) == 0)
1492 SET_GPR (OP[0], 1);
1493 else
1494 SET_GPR (OP[0], 0);
1495 trace_output_void (sd);
1496 }
1497
1498 /* scs. */
1499 void
1500 OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
1501 {
1502 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1503 if ((PSR_C) == 1)
1504 SET_GPR (OP[0], 1);
1505 else
1506 SET_GPR (OP[0], 0);
1507 trace_output_void (sd);
1508 }
1509
1510 /* scc. */
1511 void
1512 OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
1513 {
1514 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1515 if ((PSR_C) == 0)
1516 SET_GPR (OP[0], 1);
1517 else
1518 SET_GPR (OP[0], 0);
1519 trace_output_void (sd);
1520 }
1521
1522 /* shi. */
1523 void
1524 OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
1525 {
1526 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1527 if ((PSR_L) == 1)
1528 SET_GPR (OP[0], 1);
1529 else
1530 SET_GPR (OP[0], 0);
1531 trace_output_void (sd);
1532 }
1533
1534 /* sls. */
1535 void
1536 OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
1537 {
1538 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1539 if ((PSR_L) == 0)
1540 SET_GPR (OP[0], 1);
1541 else
1542 SET_GPR (OP[0], 0);
1543 trace_output_void (sd);
1544 }
1545
1546 /* sgt. */
1547 void
1548 OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
1549 {
1550 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1551 if ((PSR_N) == 1)
1552 SET_GPR (OP[0], 1);
1553 else
1554 SET_GPR (OP[0], 0);
1555 trace_output_void (sd);
1556 }
1557
1558 /* sle. */
1559 void
1560 OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
1561 {
1562 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1563 if ((PSR_N) == 0)
1564 SET_GPR (OP[0], 1);
1565 else
1566 SET_GPR (OP[0], 0);
1567 trace_output_void (sd);
1568 }
1569
1570 /* sfs. */
1571 void
1572 OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
1573 {
1574 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1575 if ((PSR_F) == 1)
1576 SET_GPR (OP[0], 1);
1577 else
1578 SET_GPR (OP[0], 0);
1579 trace_output_void (sd);
1580 }
1581
1582 /* sfc. */
1583 void
1584 OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
1585 {
1586 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1587 if ((PSR_F) == 0)
1588 SET_GPR (OP[0], 1);
1589 else
1590 SET_GPR (OP[0], 0);
1591 trace_output_void (sd);
1592 }
1593
1594
1595 /* slo. */
1596 void
1597 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
1598 {
1599 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1600 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1601 SET_GPR (OP[0], 1);
1602 else
1603 SET_GPR (OP[0], 0);
1604 trace_output_void (sd);
1605 }
1606
1607 /* shs. */
1608 void
1609 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
1610 {
1611 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1612 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1613 SET_GPR (OP[0], 1);
1614 else
1615 SET_GPR (OP[0], 0);
1616 trace_output_void (sd);
1617 }
1618
1619 /* slt. */
1620 void
1621 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
1622 {
1623 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1624 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1625 SET_GPR (OP[0], 1);
1626 else
1627 SET_GPR (OP[0], 0);
1628 trace_output_void (sd);
1629 }
1630
1631 /* sge. */
1632 void
1633 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
1634 {
1635 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1636 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1637 SET_GPR (OP[0], 1);
1638 else
1639 SET_GPR (OP[0], 0);
1640 trace_output_void (sd);
1641 }
1642
1643 /* cbitb. */
1644 void
1645 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
1646 {
1647 uint8 a = OP[0] & 0xff;
1648 uint32 addr = OP[1], tmp;
1649 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1650 tmp = RB (addr);
1651 SET_PSR_F (tmp & (1 << a));
1652 tmp = tmp & ~(1 << a);
1653 SB (addr, tmp);
1654 trace_output_32 (sd, tmp);
1655 }
1656
1657 /* cbitb. */
1658 void
1659 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
1660 {
1661 uint8 a = OP[0] & 0xff;
1662 uint32 addr = OP[1], tmp;
1663 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1664 tmp = RB (addr);
1665 SET_PSR_F (tmp & (1 << a));
1666 tmp = tmp & ~(1 << a);
1667 SB (addr, tmp);
1668 trace_output_32 (sd, tmp);
1669 }
1670
1671 /* cbitb. */
1672 void
1673 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
1674 {
1675 uint8 a = (OP[0]) & 0xff;
1676 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1677 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1678 tmp = RB (addr);
1679 SET_PSR_F (tmp & (1 << a));
1680 tmp = tmp & ~(1 << a);
1681 SB (addr, tmp);
1682 trace_output_32 (sd, addr);
1683 }
1684
1685 /* cbitb. */
1686 void
1687 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
1688 {
1689 uint8 a = (OP[0]) & 0xff;
1690 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1691 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1692 tmp = RB (addr);
1693 SET_PSR_F (tmp & (1 << a));
1694 tmp = tmp & ~(1 << a);
1695 SB (addr, tmp);
1696 trace_output_32 (sd, addr);
1697 }
1698
1699 /* cbitb. */
1700 void
1701 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
1702 {
1703 uint8 a = (OP[0]) & 0xff;
1704 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1705 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1706 tmp = RB (addr);
1707 SET_PSR_F (tmp & (1 << a));
1708 tmp = tmp & ~(1 << a);
1709 SB (addr, tmp);
1710 trace_output_32 (sd, addr);
1711 }
1712
1713 /* cbitb. */
1714 void
1715 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
1716 {
1717 uint8 a = (OP[0]) & 0xff;
1718 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1719 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1720 tmp = RB (addr);
1721 SET_PSR_F (tmp & (1 << a));
1722 tmp = tmp & ~(1 << a);
1723 SB (addr, tmp);
1724 trace_output_32 (sd, addr);
1725 }
1726
1727 /* cbitb. */
1728 void
1729 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
1730 {
1731 uint8 a = (OP[0]) & 0xff;
1732 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1733 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1734 tmp = RB (addr);
1735 SET_PSR_F (tmp & (1 << a));
1736 tmp = tmp & ~(1 << a);
1737 SB (addr, tmp);
1738 trace_output_32 (sd, addr);
1739
1740 }
1741
1742 /* cbitb. */
1743 void
1744 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
1745 {
1746 uint8 a = (OP[0]) & 0xff;
1747 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1748 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1749 tmp = RB (addr);
1750 SET_PSR_F (tmp & (1 << a));
1751 tmp = tmp & ~(1 << a);
1752 SB (addr, tmp);
1753 trace_output_32 (sd, addr);
1754 }
1755
1756 /* cbitb. */
1757 void
1758 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
1759 {
1760 uint8 a = (OP[0]) & 0xff;
1761 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1762 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1763 tmp = RB (addr);
1764 SET_PSR_F (tmp & (1 << a));
1765 tmp = tmp & ~(1 << a);
1766 SB (addr, tmp);
1767 trace_output_32 (sd, addr);
1768 }
1769
1770
1771 /* cbitw. */
1772 void
1773 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
1774 {
1775 uint16 a = OP[0];
1776 uint32 addr = OP[1], tmp;
1777 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1778 tmp = RW (addr);
1779 SET_PSR_F (tmp & (1 << a));
1780 tmp = tmp & ~(1 << a);
1781 SW (addr, tmp);
1782 trace_output_32 (sd, tmp);
1783 }
1784
1785 /* cbitw. */
1786 void
1787 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
1788 {
1789 uint16 a = OP[0];
1790 uint32 addr = OP[1], tmp;
1791 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1792 tmp = RW (addr);
1793 SET_PSR_F (tmp & (1 << a));
1794 tmp = tmp & ~(1 << a);
1795 SW (addr, tmp);
1796 trace_output_32 (sd, tmp);
1797 }
1798
1799 /* cbitw. */
1800 void
1801 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
1802 {
1803 uint32 addr;
1804 uint16 a = (OP[0]), tmp;
1805 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1806
1807 if (OP[1] == 0)
1808 addr = (GPR32 (12)) + OP[2];
1809 else
1810 addr = (GPR32 (13)) + OP[2];
1811
1812 tmp = RW (addr);
1813 SET_PSR_F (tmp & (1 << a));
1814 tmp = tmp & ~(1 << a);
1815 SW (addr, tmp);
1816 trace_output_32 (sd, addr);
1817
1818 }
1819
1820 /* cbitw. */
1821 void
1822 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
1823 {
1824 uint16 a = (OP[0]);
1825 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1826 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1827 tmp = RW (addr);
1828 SET_PSR_F (tmp & (1 << a));
1829 tmp = tmp & ~(1 << a);
1830 SW (addr, tmp);
1831 trace_output_32 (sd, addr);
1832 }
1833
1834 /* cbitw. */
1835 void
1836 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
1837 {
1838 uint16 a = (OP[0]);
1839 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1840 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1841 tmp = RW (addr);
1842 SET_PSR_F (tmp & (1 << a));
1843 tmp = tmp & ~(1 << a);
1844 SW (addr, tmp);
1845 trace_output_32 (sd, addr);
1846 }
1847
1848
1849 /* cbitw. */
1850 void
1851 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
1852 {
1853 uint16 a = (OP[0]);
1854 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1855 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1856 tmp = RW (addr);
1857 SET_PSR_F (tmp & (1 << a));
1858 tmp = tmp & ~(1 << a);
1859 SW (addr, tmp);
1860 trace_output_32 (sd, addr);
1861 }
1862
1863 /* cbitw. */
1864 void
1865 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
1866 {
1867 uint16 a = (OP[0]);
1868 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1869 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1870 tmp = RW (addr);
1871 SET_PSR_F (tmp & (1 << a));
1872 tmp = tmp & ~(1 << a);
1873 SW (addr, tmp);
1874 trace_output_32 (sd, addr);
1875 }
1876
1877
1878 /* cbitw. */
1879 void
1880 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
1881 {
1882 uint16 a = (OP[0]);
1883 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1884 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1885 tmp = RW (addr);
1886 SET_PSR_F (tmp & (1 << a));
1887 tmp = tmp & ~(1 << a);
1888 SW (addr, tmp);
1889 trace_output_32 (sd, addr);
1890 }
1891
1892 /* cbitw. */
1893 void
1894 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
1895 {
1896 uint16 a = (OP[0]);
1897 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1898 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1899 tmp = RW (addr);
1900 SET_PSR_F (tmp & (1 << a));
1901 tmp = tmp & ~(1 << a);
1902 SW (addr, tmp);
1903 trace_output_32 (sd, addr);
1904 }
1905
1906 /* sbitb. */
1907 void
1908 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
1909 {
1910 uint8 a = OP[0] & 0xff;
1911 uint32 addr = OP[1], tmp;
1912 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1913 tmp = RB (addr);
1914 SET_PSR_F (tmp & (1 << a));
1915 tmp = tmp | (1 << a);
1916 SB (addr, tmp);
1917 trace_output_32 (sd, tmp);
1918 }
1919
1920 /* sbitb. */
1921 void
1922 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
1923 {
1924 uint8 a = OP[0] & 0xff;
1925 uint32 addr = OP[1], tmp;
1926 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1927 tmp = RB (addr);
1928 SET_PSR_F (tmp & (1 << a));
1929 tmp = tmp | (1 << a);
1930 SB (addr, tmp);
1931 trace_output_32 (sd, tmp);
1932 }
1933
1934 /* sbitb. */
1935 void
1936 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
1937 {
1938 uint8 a = OP[0] & 0xff;
1939 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1940 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1941 tmp = RB (addr);
1942 SET_PSR_F (tmp & (1 << a));
1943 tmp = tmp | (1 << a);
1944 SB (addr, tmp);
1945 trace_output_32 (sd, tmp);
1946 }
1947
1948 /* sbitb. */
1949 void
1950 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
1951 {
1952 uint8 a = OP[0] & 0xff;
1953 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1954 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1955 tmp = RB (addr);
1956 SET_PSR_F (tmp & (1 << a));
1957 tmp = tmp | (1 << a);
1958 SB (addr, tmp);
1959 trace_output_32 (sd, tmp);
1960 }
1961
1962 /* sbitb. */
1963 void
1964 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
1965 {
1966 uint8 a = OP[0] & 0xff;
1967 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1968 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1969 tmp = RB (addr);
1970 SET_PSR_F (tmp & (1 << a));
1971 tmp = tmp | (1 << a);
1972 SB (addr, tmp);
1973 trace_output_32 (sd, tmp);
1974 }
1975
1976
1977 /* sbitb. */
1978 void
1979 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
1980 {
1981 uint8 a = OP[0] & 0xff;
1982 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1983 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1984 tmp = RB (addr);
1985 SET_PSR_F (tmp & (1 << a));
1986 tmp = tmp | (1 << a);
1987 SB (addr, tmp);
1988 trace_output_32 (sd, tmp);
1989 }
1990
1991 /* sbitb. */
1992 void
1993 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
1994 {
1995 uint8 a = OP[0] & 0xff;
1996 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1997 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1998 tmp = RB (addr);
1999 SET_PSR_F (tmp & (1 << a));
2000 tmp = tmp | (1 << a);
2001 SB (addr, tmp);
2002 trace_output_32 (sd, tmp);
2003 }
2004
2005
2006 /* sbitb. */
2007 void
2008 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
2009 {
2010 uint8 a = OP[0] & 0xff;
2011 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2012 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2013 tmp = RB (addr);
2014 SET_PSR_F (tmp & (1 << a));
2015 tmp = tmp | (1 << a);
2016 SB (addr, tmp);
2017 trace_output_32 (sd, tmp);
2018 }
2019
2020
2021 /* sbitb. */
2022 void
2023 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
2024 {
2025 uint8 a = OP[0] & 0xff;
2026 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2027 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2028 tmp = RB (addr);
2029 SET_PSR_F (tmp & (1 << a));
2030 tmp = tmp | (1 << a);
2031 SB (addr, tmp);
2032 trace_output_32 (sd, tmp);
2033 }
2034
2035
2036 /* sbitw. */
2037 void
2038 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
2039 {
2040 uint16 a = OP[0];
2041 uint32 addr = OP[1], tmp;
2042 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2043 tmp = RW (addr);
2044 SET_PSR_F (tmp & (1 << a));
2045 tmp = tmp | (1 << a);
2046 SW (addr, tmp);
2047 trace_output_32 (sd, tmp);
2048 }
2049
2050 /* sbitw. */
2051 void
2052 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
2053 {
2054 uint16 a = OP[0];
2055 uint32 addr = OP[1], tmp;
2056 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2057 tmp = RW (addr);
2058 SET_PSR_F (tmp & (1 << a));
2059 tmp = tmp | (1 << a);
2060 SW (addr, tmp);
2061 trace_output_32 (sd, tmp);
2062 }
2063
2064 /* sbitw. */
2065 void
2066 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
2067 {
2068 uint32 addr;
2069 uint16 a = (OP[0]), tmp;
2070 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2071
2072 if (OP[1] == 0)
2073 addr = (GPR32 (12)) + OP[2];
2074 else
2075 addr = (GPR32 (13)) + OP[2];
2076
2077 tmp = RW (addr);
2078 SET_PSR_F (tmp & (1 << a));
2079 tmp = tmp | (1 << a);
2080 SW (addr, tmp);
2081 trace_output_32 (sd, addr);
2082 }
2083
2084 /* sbitw. */
2085 void
2086 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
2087 {
2088 uint16 a = (OP[0]);
2089 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2090 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2091 tmp = RW (addr);
2092 SET_PSR_F (tmp & (1 << a));
2093 tmp = tmp | (1 << a);
2094 SW (addr, tmp);
2095 trace_output_32 (sd, addr);
2096 }
2097
2098 /* sbitw. */
2099 void
2100 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
2101 {
2102 uint16 a = (OP[0]);
2103 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2104 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2105 tmp = RW (addr);
2106 SET_PSR_F (tmp & (1 << a));
2107 tmp = tmp | (1 << a);
2108 SW (addr, tmp);
2109 trace_output_32 (sd, addr);
2110 }
2111
2112 /* sbitw. */
2113 void
2114 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
2115 {
2116 uint16 a = (OP[0]);
2117 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2118 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2119 tmp = RW (addr);
2120 SET_PSR_F (tmp & (1 << a));
2121 tmp = tmp | (1 << a);
2122 SW (addr, tmp);
2123 trace_output_32 (sd, addr);
2124 }
2125
2126 /* sbitw. */
2127 void
2128 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
2129 {
2130 uint16 a = (OP[0]);
2131 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2132 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2133 tmp = RW (addr);
2134 SET_PSR_F (tmp & (1 << a));
2135 tmp = tmp | (1 << a);
2136 SW (addr, tmp);
2137 trace_output_32 (sd, addr);
2138 }
2139
2140 /* sbitw. */
2141 void
2142 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
2143 {
2144 uint16 a = (OP[0]);
2145 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2146 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2147 tmp = RW (addr);
2148 SET_PSR_F (tmp & (1 << a));
2149 tmp = tmp | (1 << a);
2150 SW (addr, tmp);
2151 trace_output_32 (sd, addr);
2152 }
2153
2154 /* sbitw. */
2155 void
2156 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
2157 {
2158 uint16 a = (OP[0]);
2159 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2160 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2161 tmp = RW (addr);
2162 SET_PSR_F (tmp & (1 << a));
2163 tmp = tmp | (1 << a);
2164 SW (addr, tmp);
2165 trace_output_32 (sd, addr);
2166 }
2167
2168
2169 /* tbitb. */
2170 void
2171 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
2172 {
2173 uint8 a = OP[0] & 0xff;
2174 uint32 addr = OP[1], tmp;
2175 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2176 tmp = RB (addr);
2177 SET_PSR_F (tmp & (1 << a));
2178 trace_output_32 (sd, tmp);
2179 }
2180
2181 /* tbitb. */
2182 void
2183 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
2184 {
2185 uint8 a = OP[0] & 0xff;
2186 uint32 addr = OP[1], tmp;
2187 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2188 tmp = RB (addr);
2189 SET_PSR_F (tmp & (1 << a));
2190 trace_output_32 (sd, tmp);
2191 }
2192
2193 /* tbitb. */
2194 void
2195 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
2196 {
2197 uint8 a = (OP[0]) & 0xff;
2198 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2199 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2200 tmp = RB (addr);
2201 SET_PSR_F (tmp & (1 << a));
2202 trace_output_32 (sd, addr);
2203 }
2204
2205 /* tbitb. */
2206 void
2207 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
2208 {
2209 uint8 a = (OP[0]) & 0xff;
2210 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2211 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2212 tmp = RB (addr);
2213 SET_PSR_F (tmp & (1 << a));
2214 trace_output_32 (sd, addr);
2215 }
2216
2217 /* tbitb. */
2218 void
2219 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
2220 {
2221 uint8 a = (OP[0]) & 0xff;
2222 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2223 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2224 tmp = RB (addr);
2225 SET_PSR_F (tmp & (1 << a));
2226 trace_output_32 (sd, addr);
2227 }
2228
2229 /* tbitb. */
2230 void
2231 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
2232 {
2233 uint8 a = (OP[0]) & 0xff;
2234 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2235 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2236 tmp = RB (addr);
2237 SET_PSR_F (tmp & (1 << a));
2238 trace_output_32 (sd, addr);
2239 }
2240
2241 /* tbitb. */
2242 void
2243 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
2244 {
2245 uint8 a = (OP[0]) & 0xff;
2246 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2247 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2248 tmp = RB (addr);
2249 SET_PSR_F (tmp & (1 << a));
2250 trace_output_32 (sd, addr);
2251 }
2252
2253 /* tbitb. */
2254 void
2255 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
2256 {
2257 uint8 a = (OP[0]) & 0xff;
2258 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2259 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2260 tmp = RB (addr);
2261 SET_PSR_F (tmp & (1 << a));
2262 trace_output_32 (sd, addr);
2263 }
2264
2265 /* tbitb. */
2266 void
2267 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
2268 {
2269 uint8 a = (OP[0]) & 0xff;
2270 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2271 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2272 tmp = RB (addr);
2273 SET_PSR_F (tmp & (1 << a));
2274 trace_output_32 (sd, addr);
2275 }
2276
2277
2278 /* tbitw. */
2279 void
2280 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
2281 {
2282 uint16 a = OP[0];
2283 uint32 addr = OP[1], tmp;
2284 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2285 tmp = RW (addr);
2286 SET_PSR_F (tmp & (1 << a));
2287 trace_output_32 (sd, tmp);
2288 }
2289
2290 /* tbitw. */
2291 void
2292 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
2293 {
2294 uint16 a = OP[0];
2295 uint32 addr = OP[1], tmp;
2296 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2297 tmp = RW (addr);
2298 SET_PSR_F (tmp & (1 << a));
2299 trace_output_32 (sd, tmp);
2300 }
2301
2302
2303 /* tbitw. */
2304 void
2305 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
2306 {
2307 uint32 addr;
2308 uint16 a = (OP[0]), tmp;
2309 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2310
2311 if (OP[1] == 0)
2312 addr = (GPR32 (12)) + OP[2];
2313 else
2314 addr = (GPR32 (13)) + OP[2];
2315
2316 tmp = RW (addr);
2317 SET_PSR_F (tmp & (1 << a));
2318 trace_output_32 (sd, addr);
2319 }
2320
2321 /* tbitw. */
2322 void
2323 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
2324 {
2325 uint16 a = (OP[0]);
2326 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2327 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2328 tmp = RW (addr);
2329 SET_PSR_F (tmp & (1 << a));
2330 trace_output_32 (sd, addr);
2331 }
2332
2333 /* tbitw. */
2334 void
2335 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
2336 {
2337 uint16 a = (OP[0]);
2338 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2339 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2340 tmp = RW (addr);
2341 SET_PSR_F (tmp & (1 << a));
2342 trace_output_32 (sd, addr);
2343 }
2344
2345 /* tbitw. */
2346 void
2347 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
2348 {
2349 uint16 a = (OP[0]);
2350 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2351 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2352 tmp = RW (addr);
2353 SET_PSR_F (tmp & (1 << a));
2354 trace_output_32 (sd, addr);
2355 }
2356
2357 /* tbitw. */
2358 void
2359 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
2360 {
2361 uint16 a = (OP[0]);
2362 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2363 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2364 tmp = RW (addr);
2365 SET_PSR_F (tmp & (1 << a));
2366 trace_output_32 (sd, addr);
2367 }
2368
2369 /* tbitw. */
2370 void
2371 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
2372 {
2373 uint16 a = (OP[0]);
2374 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2375 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2376 tmp = RW (addr);
2377 SET_PSR_F (tmp & (1 << a));
2378 trace_output_32 (sd, addr);
2379 }
2380
2381
2382 /* tbitw. */
2383 void
2384 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
2385 {
2386 uint16 a = (OP[0]);
2387 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2388 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2389 tmp = RW (addr);
2390 SET_PSR_F (tmp & (1 << a));
2391 trace_output_32 (sd, addr);
2392 }
2393
2394
2395 /* tbit. */
2396 void
2397 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
2398 {
2399 uint16 a = OP[0];
2400 uint16 b = (GPR (OP[1]));
2401 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2402 SET_PSR_F (b & (1 << a));
2403 trace_output_16 (sd, b);
2404 }
2405
2406 /* tbit. */
2407 void
2408 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
2409 {
2410 uint16 a = GPR (OP[0]);
2411 uint16 b = (GPR (OP[1]));
2412 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2413 SET_PSR_F (b & (1 << a));
2414 trace_output_16 (sd, b);
2415 }
2416
2417
2418 /* cmpb. */
2419 void
2420 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
2421 {
2422 uint8 a = (OP[0]) & 0xFF;
2423 uint8 b = (GPR (OP[1])) & 0xFF;
2424 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2425 SET_PSR_Z (a == b);
2426 SET_PSR_N ((int8)a > (int8)b);
2427 SET_PSR_L (a > b);
2428 trace_output_flag (sd);
2429 }
2430
2431 /* cmpb. */
2432 void
2433 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
2434 {
2435 uint8 a = (OP[0]) & 0xFF;
2436 uint8 b = (GPR (OP[1])) & 0xFF;
2437 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2438 SET_PSR_Z (a == b);
2439 SET_PSR_N ((int8)a > (int8)b);
2440 SET_PSR_L (a > b);
2441 trace_output_flag (sd);
2442 }
2443
2444 /* cmpb. */
2445 void
2446 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
2447 {
2448 uint8 a = (GPR (OP[0])) & 0xFF;
2449 uint8 b = (GPR (OP[1])) & 0xFF;
2450 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2451 SET_PSR_Z (a == b);
2452 SET_PSR_N ((int8)a > (int8)b);
2453 SET_PSR_L (a > b);
2454 trace_output_flag (sd);
2455 }
2456
2457 /* cmpw. */
2458 void
2459 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
2460 {
2461 uint16 a = (OP[0]);
2462 uint16 b = GPR (OP[1]);
2463 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2464 SET_PSR_Z (a == b);
2465 SET_PSR_N ((int16)a > (int16)b);
2466 SET_PSR_L (a > b);
2467 trace_output_flag (sd);
2468 }
2469
2470 /* cmpw. */
2471 void
2472 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
2473 {
2474 uint16 a = (OP[0]);
2475 uint16 b = GPR (OP[1]);
2476 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2477 SET_PSR_Z (a == b);
2478 SET_PSR_N ((int16)a > (int16)b);
2479 SET_PSR_L (a > b);
2480 trace_output_flag (sd);
2481 }
2482
2483 /* cmpw. */
2484 void
2485 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
2486 {
2487 uint16 a = GPR (OP[0]) ;
2488 uint16 b = GPR (OP[1]) ;
2489 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2490 SET_PSR_Z (a == b);
2491 SET_PSR_N ((int16)a > (int16)b);
2492 SET_PSR_L (a > b);
2493 trace_output_flag (sd);
2494 }
2495
2496 /* cmpd. */
2497 void
2498 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
2499 {
2500 uint32 a = (OP[0]);
2501 uint32 b = GPR32 (OP[1]);
2502 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2503 SET_PSR_Z (a == b);
2504 SET_PSR_N ((int32)a > (int32)b);
2505 SET_PSR_L (a > b);
2506 trace_output_flag (sd);
2507 }
2508
2509 /* cmpd. */
2510 void
2511 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
2512 {
2513 uint32 a = (SEXT16(OP[0]));
2514 uint32 b = GPR32 (OP[1]);
2515 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2516 SET_PSR_Z (a == b);
2517 SET_PSR_N ((int32)a > (int32)b);
2518 SET_PSR_L (a > b);
2519 trace_output_flag (sd);
2520 }
2521
2522 /* cmpd. */
2523 void
2524 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
2525 {
2526 uint32 a = GPR32 (OP[0]) ;
2527 uint32 b = GPR32 (OP[1]) ;
2528 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2529 SET_PSR_Z (a == b);
2530 SET_PSR_N ((int32)a > (int32)b);
2531 SET_PSR_L (a > b);
2532 trace_output_flag (sd);
2533 }
2534
2535 /* cmpd. */
2536 void
2537 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
2538 {
2539 uint32 a = (OP[0]);
2540 uint32 b = GPR32 (OP[1]);
2541 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2542 SET_PSR_Z (a == b);
2543 SET_PSR_N ((int32)a > (int32)b);
2544 SET_PSR_L (a > b);
2545 trace_output_flag (sd);
2546 }
2547
2548
2549 /* movb. */
2550 void
2551 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
2552 {
2553 uint8 tmp = OP[0] & 0xFF;
2554 uint16 a = (GPR (OP[1])) & 0xFF00;
2555 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2556 SET_GPR (OP[1], (a | tmp));
2557 trace_output_16 (sd, tmp);
2558 }
2559
2560 /* movb. */
2561 void
2562 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
2563 {
2564 uint8 tmp = OP[0] & 0xFF;
2565 uint16 a = (GPR (OP[1])) & 0xFF00;
2566 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2567 SET_GPR (OP[1], (a | tmp));
2568 trace_output_16 (sd, tmp);
2569 }
2570
2571 /* movb. */
2572 void
2573 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
2574 {
2575 uint8 tmp = (GPR (OP[0])) & 0xFF;
2576 uint16 a = (GPR (OP[1])) & 0xFF00;
2577 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2578 SET_GPR (OP[1], (a | tmp));
2579 trace_output_16 (sd, tmp);
2580 }
2581
2582 /* movw. */
2583 void
2584 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
2585 {
2586 uint16 tmp = OP[0];
2587 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2588 SET_GPR (OP[1], (tmp & 0xffff));
2589 trace_output_16 (sd, tmp);
2590 }
2591
2592 /* movw. */
2593 void
2594 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
2595 {
2596 int16 tmp = OP[0];
2597 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2598 SET_GPR (OP[1], (tmp & 0xffff));
2599 trace_output_16 (sd, tmp);
2600 }
2601
2602 /* movw. */
2603 void
2604 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
2605 {
2606 uint16 tmp = GPR (OP[0]);
2607 uint32 a = GPR32 (OP[1]);
2608 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2609 a = (a & 0xffff0000) | tmp;
2610 SET_GPR32 (OP[1], a);
2611 trace_output_16 (sd, tmp);
2612 }
2613
2614 /* movxb. */
2615 void
2616 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
2617 {
2618 uint8 tmp = (GPR (OP[0])) & 0xFF;
2619 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2620 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2621 trace_output_16 (sd, tmp);
2622 }
2623
2624 /* movzb. */
2625 void
2626 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
2627 {
2628 uint8 tmp = (GPR (OP[0])) & 0xFF;
2629 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2630 SET_GPR (OP[1], tmp);
2631 trace_output_16 (sd, tmp);
2632 }
2633
2634 /* movxw. */
2635 void
2636 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
2637 {
2638 uint16 tmp = GPR (OP[0]);
2639 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2640 SET_GPR32 (OP[1], SEXT16(tmp));
2641 trace_output_16 (sd, tmp);
2642 }
2643
2644 /* movzw. */
2645 void
2646 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
2647 {
2648 uint16 tmp = GPR (OP[0]);
2649 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2650 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2651 trace_output_16 (sd, tmp);
2652 }
2653
2654 /* movd. */
2655 void
2656 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
2657 {
2658 int32 tmp = OP[0];
2659 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2660 SET_GPR32 (OP[1], tmp);
2661 trace_output_32 (sd, tmp);
2662 }
2663
2664 /* movd. */
2665 void
2666 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
2667 {
2668 int32 tmp = SEXT16(OP[0]);
2669 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2670 SET_GPR32 (OP[1], tmp);
2671 trace_output_32 (sd, tmp);
2672 }
2673
2674 /* movd. */
2675 void
2676 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
2677 {
2678 uint32 tmp = GPR32 (OP[0]);
2679 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2680 SET_GPR32 (OP[1], tmp);
2681 trace_output_32 (sd, tmp);
2682 }
2683
2684 /* movd. */
2685 void
2686 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
2687 {
2688 uint32 tmp = OP[0];
2689 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2690 SET_GPR32 (OP[1], tmp);
2691 trace_output_32 (sd, tmp);
2692 }
2693
2694 /* movd. */
2695 void
2696 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
2697 {
2698 int32 tmp = OP[0];
2699 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2700 SET_GPR32 (OP[1], tmp);
2701 trace_output_32 (sd, tmp);
2702 }
2703
2704 /* loadm. */
2705 void
2706 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
2707 {
2708 uint32 addr = GPR (0);
2709 uint16 count = OP[0], reg = 2, tmp;
2710 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2711 if ((addr & 1))
2712 {
2713 trace_output_void (sd);
2714 EXCEPTION (SIM_SIGBUS);
2715 }
2716
2717 while (count)
2718 {
2719 tmp = RW (addr);
2720 SET_GPR (reg, tmp);
2721 addr +=2;
2722 --count;
2723 reg++;
2724 if (reg == 6) reg = 8;
2725 };
2726
2727 SET_GPR (0, addr);
2728 trace_output_void (sd);
2729 }
2730
2731
2732 /* loadmp. */
2733 void
2734 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
2735 {
2736 uint32 addr = GPR32 (0);
2737 uint16 count = OP[0], reg = 2, tmp;
2738 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2739 if ((addr & 1))
2740 {
2741 trace_output_void (sd);
2742 EXCEPTION (SIM_SIGBUS);
2743 }
2744
2745 while (count)
2746 {
2747 tmp = RW (addr);
2748 SET_GPR (reg, tmp);
2749 addr +=2;
2750 --count;
2751 reg++;
2752 if (reg == 6) reg = 8;
2753 };
2754
2755 SET_GPR32 (0, addr);
2756 trace_output_void (sd);
2757 }
2758
2759
2760 /* loadb. */
2761 void
2762 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
2763 {
2764 /* loadb ABS20, REG
2765 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2766 * REG = [ADDR]
2767 * NOTE: remap is
2768 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2769 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2770 * by the core to 16M-64k to 16M. */
2771
2772 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2773 uint32 addr = OP[0];
2774 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2775 if (addr > 0xEFFFF) addr |= 0xF00000;
2776 tmp = (RB (addr));
2777 SET_GPR (OP[1], (a | tmp));
2778 trace_output_16 (sd, tmp);
2779 }
2780
2781 /* loadb. */
2782 void
2783 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
2784 {
2785 /* loadb ABS24, REG
2786 * ADDR = abs24
2787 * REGR = [ADDR]. */
2788
2789 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2790 uint32 addr = OP[0];
2791 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2792 tmp = (RB (addr));
2793 SET_GPR (OP[1], (a | tmp));
2794 trace_output_16 (sd, tmp);
2795 }
2796
2797 /* loadb. */
2798 void
2799 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
2800 {
2801 /* loadb [Rindex]ABS20 REG
2802 * ADDR = Rindex + zext24(disp20)
2803 * REGR = [ADDR]. */
2804
2805 uint32 addr;
2806 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2807 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2808
2809 if (OP[0] == 0)
2810 addr = (GPR32 (12)) + OP[1];
2811 else
2812 addr = (GPR32 (13)) + OP[1];
2813
2814 tmp = (RB (addr));
2815 SET_GPR (OP[2], (a | tmp));
2816 trace_output_16 (sd, tmp);
2817 }
2818
2819
2820 /* loadb. */
2821 void
2822 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
2823 {
2824 /* loadb DIPS4(REGP) REG
2825 * ADDR = RPBASE + zext24(DISP4)
2826 * REG = [ADDR]. */
2827 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2828 uint32 addr = (GPR32 (OP[1])) + OP[0];
2829 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2830 tmp = (RB (addr));
2831 SET_GPR (OP[2], (a | tmp));
2832 trace_output_16 (sd, tmp);
2833 }
2834
2835 /* loadb. */
2836 void
2837 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
2838 {
2839 /* loadb [Rindex]disp0(RPbasex) REG
2840 * ADDR = Rpbasex + Rindex
2841 * REGR = [ADDR] */
2842
2843 uint32 addr;
2844 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2845 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2846
2847 addr = (GPR32 (OP[2])) + OP[1];
2848
2849 if (OP[0] == 0)
2850 addr = (GPR32 (12)) + addr;
2851 else
2852 addr = (GPR32 (13)) + addr;
2853
2854 tmp = (RB (addr));
2855 SET_GPR (OP[3], (a | tmp));
2856 trace_output_16 (sd, tmp);
2857 }
2858
2859 /* loadb. */
2860 void
2861 OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
2862 {
2863 /* loadb [Rindex]disp14(RPbasex) REG
2864 * ADDR = Rpbasex + Rindex + zext24(disp14)
2865 * REGR = [ADDR] */
2866
2867 uint32 addr;
2868 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2869
2870 addr = (GPR32 (OP[2])) + OP[1];
2871
2872 if (OP[0] == 0)
2873 addr = (GPR32 (12)) + addr;
2874 else
2875 addr = (GPR32 (13)) + addr;
2876
2877 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2878 tmp = (RB (addr));
2879 SET_GPR (OP[3], (a | tmp));
2880 trace_output_16 (sd, tmp);
2881 }
2882
2883
2884 /* loadb. */
2885 void
2886 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
2887 {
2888 /* loadb DISPE20(REG) REG
2889 * zext24(Rbase) + zext24(dispe20)
2890 * REG = [ADDR] */
2891
2892 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2893 uint32 addr = OP[0] + (GPR (OP[1]));
2894 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2895 tmp = (RB (addr));
2896 SET_GPR (OP[2], (a | tmp));
2897 trace_output_16 (sd, tmp);
2898 }
2899
2900 /* loadb. */
2901 void
2902 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
2903 {
2904 /* loadb DISP20(REG) REG
2905 * ADDR = zext24(Rbase) + zext24(disp20)
2906 * REG = [ADDR] */
2907
2908 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2909 uint32 addr = OP[0] + (GPR (OP[1]));
2910 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2911 tmp = (RB (addr));
2912 SET_GPR (OP[2], (a | tmp));
2913 trace_output_16 (sd, tmp);
2914 }
2915
2916 /* loadb. */
2917 void
2918 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
2919 {
2920 /* loadb disp16(REGP) REG
2921 * ADDR = RPbase + zext24(disp16)
2922 * REGR = [ADDR] */
2923
2924 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2925 uint32 addr = (GPR32 (OP[1])) + OP[0];
2926 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2927 tmp = (RB (addr));
2928 SET_GPR (OP[2], (a | tmp));
2929 trace_output_16 (sd, tmp);
2930 }
2931
2932 /* loadb. */
2933 void
2934 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
2935 {
2936 /* loadb disp20(REGP) REG
2937 * ADDR = RPbase + zext24(disp20)
2938 * REGR = [ADDR] */
2939 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2940 uint32 addr = (GPR32 (OP[1])) + OP[0];
2941 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2942 tmp = (RB (addr));
2943 SET_GPR (OP[2], (a | tmp));
2944 trace_output_16 (sd, tmp);
2945 }
2946
2947
2948 /* loadb. */
2949 void
2950 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
2951 {
2952 /* loadb -disp20(REGP) REG
2953 * ADDR = RPbase + zext24(-disp20)
2954 * REGR = [ADDR] */
2955 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2956 uint32 addr = (GPR32 (OP[1])) + OP[1];
2957 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2958 tmp = (RB (addr));
2959 SET_GPR (OP[2], (a | tmp));
2960 trace_output_16 (sd, tmp);
2961 }
2962
2963 /* loadb. */
2964 void
2965 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
2966 {
2967 /* loadb [Rindex]disp20(RPbasexb) REG
2968 * ADDR = RPbasex + Rindex + zext24(disp20)
2969 * REGR = [ADDR] */
2970
2971 uint32 addr;
2972 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2973 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2974
2975 addr = (GPR32 (OP[2])) + OP[1];
2976
2977 if (OP[0] == 0)
2978 addr = (GPR32 (12)) + addr;
2979 else
2980 addr = (GPR32 (13)) + addr;
2981
2982 tmp = (RB (addr));
2983 SET_GPR (OP[3], (a | tmp));
2984 trace_output_16 (sd, tmp);
2985 }
2986
2987
2988 /* loadw. */
2989 void
2990 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
2991 {
2992 /* loadw ABS20, REG
2993 * ADDR = zext24(abs20) | remap
2994 * REGR = [ADDR]
2995 * NOTE: remap is
2996 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2997 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2998 * by the core to 16M-64k to 16M. */
2999
3000 uint16 tmp;
3001 uint32 addr = OP[0];
3002 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3003 if (addr > 0xEFFFF) addr |= 0xF00000;
3004 tmp = (RW (addr));
3005 SET_GPR (OP[1], tmp);
3006 trace_output_16 (sd, tmp);
3007 }
3008
3009
3010 /* loadw. */
3011 void
3012 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
3013 {
3014 /* loadw ABS24, REG
3015 * ADDR = abs24
3016 * REGR = [ADDR] */
3017 uint16 tmp;
3018 uint32 addr = OP[0];
3019 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3020 tmp = (RW (addr));
3021 SET_GPR (OP[1], tmp);
3022 trace_output_16 (sd, tmp);
3023 }
3024
3025 /* loadw. */
3026 void
3027 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
3028 {
3029 /* loadw [Rindex]ABS20 REG
3030 * ADDR = Rindex + zext24(disp20)
3031 * REGR = [ADDR] */
3032
3033 uint32 addr;
3034 uint16 tmp;
3035 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3036
3037 if (OP[0] == 0)
3038 addr = (GPR32 (12)) + OP[1];
3039 else
3040 addr = (GPR32 (13)) + OP[1];
3041
3042 tmp = (RW (addr));
3043 SET_GPR (OP[2], tmp);
3044 trace_output_16 (sd, tmp);
3045 }
3046
3047
3048 /* loadw. */
3049 void
3050 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
3051 {
3052 /* loadw DIPS4(REGP) REGP
3053 * ADDR = RPBASE + zext24(DISP4)
3054 * REGP = [ADDR]. */
3055 uint16 tmp;
3056 uint32 addr, a;
3057 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3058 addr = (GPR32 (OP[1])) + OP[0];
3059 tmp = (RW (addr));
3060 if (OP[2] > 11)
3061 {
3062 a = (GPR32 (OP[2])) & 0xffff0000;
3063 SET_GPR32 (OP[2], (a | tmp));
3064 }
3065 else
3066 SET_GPR (OP[2], tmp);
3067
3068 trace_output_16 (sd, tmp);
3069 }
3070
3071
3072 /* loadw. */
3073 void
3074 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
3075 {
3076 /* loadw [Rindex]disp0(RPbasex) REG
3077 * ADDR = Rpbasex + Rindex
3078 * REGR = [ADDR] */
3079
3080 uint32 addr;
3081 uint16 tmp;
3082 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3083
3084 addr = (GPR32 (OP[2])) + OP[1];
3085
3086 if (OP[0] == 0)
3087 addr = (GPR32 (12)) + addr;
3088 else
3089 addr = (GPR32 (13)) + addr;
3090
3091 tmp = RW (addr);
3092 SET_GPR (OP[3], tmp);
3093 trace_output_16 (sd, tmp);
3094 }
3095
3096
3097 /* loadw. */
3098 void
3099 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
3100 {
3101 /* loadw [Rindex]disp14(RPbasex) REG
3102 * ADDR = Rpbasex + Rindex + zext24(disp14)
3103 * REGR = [ADDR] */
3104
3105 uint32 addr;
3106 uint16 tmp;
3107 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3108 addr = (GPR32 (OP[2])) + OP[1];
3109
3110 if (OP[0] == 0)
3111 addr = (GPR32 (12)) + addr;
3112 else
3113 addr = (GPR32 (13)) + addr;
3114
3115 tmp = (RW (addr));
3116 SET_GPR (OP[3], tmp);
3117 trace_output_16 (sd, tmp);
3118 }
3119
3120 /* loadw. */
3121 void
3122 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
3123 {
3124 /* loadw dispe20(REG) REGP
3125 * REGP = [DISPE20+[REG]] */
3126
3127 uint16 tmp;
3128 uint32 addr, a;
3129 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3130 addr = OP[0] + (GPR (OP[1]));
3131 tmp = (RW (addr));
3132 if (OP[2] > 11)
3133 {
3134 a = (GPR32 (OP[2])) & 0xffff0000;
3135 SET_GPR32 (OP[2], (a | tmp));
3136 }
3137 else
3138 SET_GPR (OP[2], tmp);
3139
3140 trace_output_16 (sd, tmp);
3141 }
3142
3143
3144 /* loadw. */
3145 void
3146 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
3147 {
3148 /* loadw DISP20(REG) REGP
3149 * ADDR = zext24(Rbase) + zext24(disp20)
3150 * REGP = [ADDR] */
3151
3152 uint16 tmp;
3153 uint32 addr, a;
3154 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3155 addr = OP[0] + (GPR (OP[1]));
3156 tmp = (RW (addr));
3157 if (OP[2] > 11)
3158 {
3159 a = (GPR32 (OP[2])) & 0xffff0000;
3160 SET_GPR32 (OP[2], (a | tmp));
3161 }
3162 else
3163 SET_GPR (OP[2], tmp);
3164
3165 trace_output_16 (sd, tmp);
3166 }
3167
3168 /* loadw. */
3169 void
3170 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
3171 {
3172 /* loadw disp16(REGP) REGP
3173 * ADDR = RPbase + zext24(disp16)
3174 * REGP = [ADDR] */
3175 uint16 tmp;
3176 uint32 addr, a;
3177 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3178 addr = (GPR32 (OP[1])) + OP[0];
3179 tmp = (RW (addr));
3180 if (OP[2] > 11)
3181 {
3182 a = (GPR32 (OP[2])) & 0xffff0000;
3183 SET_GPR32 (OP[2], (a | tmp));
3184 }
3185 else
3186 SET_GPR (OP[2], tmp);
3187
3188 trace_output_16 (sd, tmp);
3189 }
3190
3191 /* loadw. */
3192 void
3193 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
3194 {
3195 /* loadw disp20(REGP) REGP
3196 * ADDR = RPbase + zext24(disp20)
3197 * REGP = [ADDR] */
3198 uint16 tmp;
3199 uint32 addr, a;
3200 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3201 addr = (GPR32 (OP[1])) + OP[0];
3202 tmp = (RW (addr));
3203 if (OP[2] > 11)
3204 {
3205 a = (GPR32 (OP[2])) & 0xffff0000;
3206 SET_GPR32 (OP[2], (a | tmp));
3207 }
3208 else
3209 SET_GPR (OP[2], tmp);
3210
3211 trace_output_16 (sd, tmp);
3212 }
3213
3214 /* loadw. */
3215 void
3216 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
3217 {
3218 /* loadw -disp20(REGP) REG
3219 * ADDR = RPbase + zext24(-disp20)
3220 * REGR = [ADDR] */
3221
3222 uint16 tmp;
3223 uint32 addr, a;
3224 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3225 addr = (GPR32 (OP[1])) + OP[0];
3226 tmp = (RB (addr));
3227 if (OP[2] > 11)
3228 {
3229 a = (GPR32 (OP[2])) & 0xffff0000;
3230 SET_GPR32 (OP[2], (a | tmp));
3231 }
3232 else
3233 SET_GPR (OP[2], tmp);
3234
3235 trace_output_16 (sd, tmp);
3236 }
3237
3238
3239 /* loadw. */
3240 void
3241 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
3242 {
3243 /* loadw [Rindex]disp20(RPbasexb) REG
3244 * ADDR = RPbasex + Rindex + zext24(disp20)
3245 * REGR = [ADDR] */
3246
3247 uint32 addr;
3248 uint16 tmp;
3249 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3250
3251 if (OP[0] == 0)
3252 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3253 else
3254 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3255
3256 tmp = (RW (addr));
3257 SET_GPR (OP[3], tmp);
3258 trace_output_16 (sd, tmp);
3259 }
3260
3261
3262 /* loadd. */
3263 void
3264 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
3265 {
3266 /* loadd ABS20, REGP
3267 * ADDR = zext24(abs20) | remap
3268 * REGP = [ADDR]
3269 * NOTE: remap is
3270 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3271 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3272 * by the core to 16M-64k to 16M. */
3273
3274 uint32 addr, tmp;
3275 addr = OP[0];
3276 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3277 if (addr > 0xEFFFF) addr |= 0xF00000;
3278 tmp = RLW (addr);
3279 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3280 SET_GPR32 (OP[1], tmp);
3281 trace_output_32 (sd, tmp);
3282 }
3283
3284 /* loadd. */
3285 void
3286 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
3287 {
3288 /* loadd ABS24, REGP
3289 * ADDR = abs24
3290 * REGP = [ADDR] */
3291
3292 uint32 addr = OP[0];
3293 uint32 tmp;
3294 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3295 tmp = RLW (addr);
3296 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3297 SET_GPR32 (OP[1],tmp);
3298 trace_output_32 (sd, tmp);
3299 }
3300
3301
3302 /* loadd. */
3303 void
3304 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
3305 {
3306 /* loadd [Rindex]ABS20 REGP
3307 * ADDR = Rindex + zext24(disp20)
3308 * REGP = [ADDR] */
3309
3310 uint32 addr, tmp;
3311 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3312
3313 if (OP[0] == 0)
3314 addr = (GPR32 (12)) + OP[1];
3315 else
3316 addr = (GPR32 (13)) + OP[1];
3317
3318 tmp = RLW (addr);
3319 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3320 SET_GPR32 (OP[2], tmp);
3321 trace_output_32 (sd, tmp);
3322 }
3323
3324
3325 /* loadd. */
3326 void
3327 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
3328 {
3329 /* loadd dips4(regp) REGP
3330 * ADDR = Rpbase + zext24(disp4)
3331 * REGP = [ADDR] */
3332
3333 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3334 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3335 tmp = RLW (addr);
3336 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3337 SET_GPR32 (OP[2], tmp);
3338 trace_output_32 (sd, tmp);
3339 }
3340
3341
3342 /* loadd. */
3343 void
3344 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
3345 {
3346 /* loadd [Rindex]disp0(RPbasex) REGP
3347 * ADDR = Rpbasex + Rindex
3348 * REGP = [ADDR] */
3349
3350 uint32 addr, tmp;
3351 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3352
3353 if (OP[0] == 0)
3354 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3355 else
3356 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3357
3358 tmp = RLW (addr);
3359 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3360 SET_GPR32 (OP[3], tmp);
3361 trace_output_32 (sd, tmp);
3362 }
3363
3364
3365 /* loadd. */
3366 void
3367 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
3368 {
3369 /* loadd [Rindex]disp14(RPbasex) REGP
3370 * ADDR = Rpbasex + Rindex + zext24(disp14)
3371 * REGR = [ADDR] */
3372
3373 uint32 addr, tmp;
3374 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3375
3376 if (OP[0] == 0)
3377 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3378 else
3379 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3380
3381 tmp = RLW (addr);
3382 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3383 SET_GPR (OP[3],tmp);
3384 trace_output_32 (sd, tmp);
3385 }
3386
3387
3388 /* loadd. */
3389 void
3390 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
3391 {
3392 /* loadd dispe20(REG) REG
3393 * zext24(Rbase) + zext24(dispe20)
3394 * REG = [ADDR] */
3395
3396 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3397 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3398 tmp = RLW (addr);
3399 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3400 SET_GPR32 (OP[2], tmp);
3401 trace_output_32 (sd, tmp);
3402 }
3403
3404
3405 /* loadd. */
3406 void
3407 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
3408 {
3409 /* loadd DISP20(REG) REG
3410 * ADDR = zext24(Rbase) + zext24(disp20)
3411 * REG = [ADDR] */
3412
3413 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3414 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3415 tmp = RLW (addr);
3416 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3417 SET_GPR32 (OP[2], tmp);
3418 trace_output_32 (sd, tmp);
3419 }
3420
3421 /* loadd. */
3422 void
3423 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
3424 {
3425 /* loadd disp16(REGP) REGP
3426 * ADDR = RPbase + zext24(disp16)
3427 * REGR = [ADDR] */
3428 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3429 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3430 tmp = RLW (addr);
3431 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3432 SET_GPR32 (OP[2], tmp);
3433 trace_output_32 (sd, tmp);
3434 }
3435
3436
3437 /* loadd. */
3438 void
3439 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
3440 {
3441 /* loadd disp20(REGP) REGP
3442 * ADDR = RPbase + zext24(disp20)
3443 * REGP = [ADDR] */
3444 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3445 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3446 tmp = RLW (addr);
3447 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3448 SET_GPR32 (OP[2], tmp);
3449 trace_output_32 (sd, tmp);
3450 }
3451
3452 /* loadd. */
3453 void
3454 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
3455 {
3456 /* loadd -disp20(REGP) REGP
3457 * ADDR = RPbase + zext24(-disp20)
3458 * REGP = [ADDR] */
3459
3460 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3461 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3462 tmp = RLW (addr);
3463 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3464 SET_GPR32 (OP[2], tmp);
3465 trace_output_32 (sd, tmp);
3466 }
3467
3468 /* loadd. */
3469 void
3470 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
3471 {
3472 /* loadd [Rindex]disp20(RPbasexb) REGP
3473 * ADDR = RPbasex + Rindex + zext24(disp20)
3474 * REGP = [ADDR] */
3475
3476 uint32 addr, tmp;
3477 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3478
3479 if (OP[0] == 0)
3480 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3481 else
3482 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3483
3484 tmp = RLW (addr);
3485 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3486 SET_GPR32 (OP[3], tmp);
3487 trace_output_32 (sd, tmp);
3488 }
3489
3490
3491 /* storb. */
3492 void
3493 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
3494 {
3495 /* storb REG, ABS20
3496 * ADDR = zext24(abs20) | remap
3497 * [ADDR] = REGR
3498 * NOTE: remap is
3499 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3500 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3501 * by the core to 16M-64k to 16M. */
3502
3503 uint8 a = ((GPR (OP[0])) & 0xff);
3504 uint32 addr = OP[1];
3505 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3506 SB (addr, a);
3507 trace_output_32 (sd, addr);
3508 }
3509
3510 /* storb. */
3511 void
3512 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
3513 {
3514 /* storb REG, ABS24
3515 * ADDR = abs24
3516 * [ADDR] = REGR. */
3517
3518 uint8 a = ((GPR (OP[0])) & 0xff);
3519 uint32 addr = OP[1];
3520 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3521 SB (addr, a);
3522 trace_output_32 (sd, addr);
3523 }
3524
3525 /* storb. */
3526 void
3527 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
3528 {
3529 /* storb REG, [Rindex]ABS20
3530 * ADDR = Rindex + zext24(disp20)
3531 * [ADDR] = REGR */
3532
3533 uint32 addr;
3534 uint8 a = ((GPR (OP[0])) & 0xff);
3535 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3536
3537 if (OP[1] == 0)
3538 addr = (GPR32 (12)) + OP[2];
3539 else
3540 addr = (GPR32 (13)) + OP[2];
3541
3542 SB (addr, a);
3543 trace_output_32 (sd, addr);
3544 }
3545
3546 /* storb. */
3547 void
3548 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
3549 {
3550 /* storb REG, DIPS4(REGP)
3551 * ADDR = RPBASE + zext24(DISP4)
3552 * [ADDR] = REG. */
3553
3554 uint16 a = ((GPR (OP[0])) & 0xff);
3555 uint32 addr = (GPR32 (OP[2])) + OP[1];
3556 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3557 SB (addr, a);
3558 trace_output_32 (sd, addr);
3559 }
3560
3561 /* storb. */
3562 void
3563 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
3564 {
3565 /* storb [Rindex]disp0(RPbasex) REG
3566 * ADDR = Rpbasex + Rindex
3567 * [ADDR] = REGR */
3568
3569 uint32 addr;
3570 uint8 a = ((GPR (OP[0])) & 0xff);
3571 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3572
3573 if (OP[1] == 0)
3574 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3575 else
3576 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3577
3578 SB (addr, a);
3579 trace_output_32 (sd, addr);
3580 }
3581
3582 /* storb. */
3583 void
3584 OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
3585 {
3586 /* storb REG, [Rindex]disp14(RPbasex)
3587 * ADDR = Rpbasex + Rindex + zext24(disp14)
3588 * [ADDR] = REGR */
3589
3590 uint8 a = ((GPR (OP[0])) & 0xff);
3591 uint32 addr = (GPR32 (OP[2])) + OP[1];
3592 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3593 SB (addr, a);
3594 trace_output_32 (sd, addr);
3595 }
3596
3597 /* storb. */
3598 void
3599 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
3600 {
3601 /* storb REG, DISPE20(REG)
3602 * zext24(Rbase) + zext24(dispe20)
3603 * [ADDR] = REG */
3604
3605 uint8 a = ((GPR (OP[0])) & 0xff);
3606 uint32 addr = OP[1] + (GPR (OP[2]));
3607 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3608 SB (addr, a);
3609 trace_output_32 (sd, addr);
3610 }
3611
3612 /* storb. */
3613 void
3614 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
3615 {
3616 /* storb REG, DISP20(REG)
3617 * ADDR = zext24(Rbase) + zext24(disp20)
3618 * [ADDR] = REG */
3619
3620 uint8 a = (GPR (OP[0]) & 0xff);
3621 uint32 addr = OP[1] + (GPR (OP[2]));
3622 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3623 SB (addr, a);
3624 trace_output_32 (sd, addr);
3625 }
3626
3627 /* storb. */
3628 void
3629 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
3630 {
3631 /* storb REG, disp16(REGP)
3632 * ADDR = RPbase + zext24(disp16)
3633 * [ADDR] = REGP */
3634
3635 uint8 a = ((GPR (OP[0])) & 0xff);
3636 uint32 addr = (GPR32 (OP[2])) + OP[1];
3637 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3638 SB (addr, a);
3639 trace_output_32 (sd, addr);
3640 }
3641
3642 /* storb. */
3643 void
3644 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
3645 {
3646 /* storb REG, disp20(REGP)
3647 * ADDR = RPbase + zext24(disp20)
3648 * [ADDR] = REGP */
3649
3650 uint8 a = ((GPR (OP[0])) & 0xff);
3651 uint32 addr = (GPR32 (OP[2])) + OP[1];
3652 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3653 SB (addr, a);
3654 trace_output_32 (sd, addr);
3655 }
3656
3657 /* storb. */
3658 void
3659 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
3660 {
3661 /* storb REG, -disp20(REGP)
3662 * ADDR = RPbase + zext24(-disp20)
3663 * [ADDR] = REGP */
3664
3665 uint8 a = (GPR (OP[0]) & 0xff);
3666 uint32 addr = (GPR32 (OP[2])) + OP[1];
3667 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3668 SB (addr, a);
3669 trace_output_32 (sd, addr);
3670 }
3671
3672 /* storb. */
3673 void
3674 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
3675 {
3676 /* storb REG, [Rindex]disp20(RPbase)
3677 * ADDR = RPbasex + Rindex + zext24(disp20)
3678 * [ADDR] = REGP */
3679
3680 uint8 a = (GPR (OP[0])) & 0xff;
3681 uint32 addr = (GPR32 (OP[2])) + OP[1];
3682 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3683 SB (addr, a);
3684 trace_output_32 (sd, addr);
3685 }
3686
3687 /* STR_IMM instructions. */
3688 /* storb . */
3689 void
3690 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
3691 {
3692 uint8 a = (OP[0]) & 0xff;
3693 uint32 addr = OP[1];
3694 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3695 SB (addr, a);
3696 trace_output_32 (sd, addr);
3697 }
3698
3699 /* storb. */
3700 void
3701 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
3702 {
3703 uint8 a = (OP[0]) & 0xff;
3704 uint32 addr = OP[1];
3705 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3706 SB (addr, a);
3707 trace_output_32 (sd, addr);
3708 }
3709
3710 /* storb. */
3711 void
3712 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
3713 {
3714 uint32 addr;
3715 uint8 a = (OP[0]) & 0xff;
3716 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3717
3718 if (OP[1] == 0)
3719 addr = (GPR32 (12)) + OP[2];
3720 else
3721 addr = (GPR32 (13)) + OP[2];
3722
3723 SB (addr, a);
3724 trace_output_32 (sd, addr);
3725 }
3726
3727 /* storb. */
3728 void
3729 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
3730 {
3731 uint8 a = (OP[0]) & 0xff;
3732 uint32 addr = (GPR32 (OP[2])) + OP[1];
3733 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3734 SB (addr, a);
3735 trace_output_32 (sd, addr);
3736 }
3737
3738 /* storb. */
3739 void
3740 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
3741 {
3742 uint8 a = (OP[0]) & 0xff;
3743 uint32 addr = (GPR32 (OP[2])) + OP[1];
3744 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3745 SB (addr, a);
3746 trace_output_32 (sd, addr);
3747 }
3748
3749 /* storb. */
3750 void
3751 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
3752 {
3753 uint8 a = (OP[0]) & 0xff;
3754 uint32 addr = (GPR (OP[2])) + OP[1];
3755 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3756 SB (addr, a);
3757 trace_output_32 (sd, addr);
3758 }
3759
3760 /* storb. */
3761 void
3762 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
3763 {
3764 uint8 a = (OP[0]) & 0xff;
3765 uint32 addr = (GPR32 (OP[2])) + OP[1];
3766 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3767 SB (addr, a);
3768 trace_output_32 (sd, addr);
3769 }
3770
3771 /* storb. */
3772 void
3773 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
3774 {
3775 uint8 a = (OP[0]) & 0xff;
3776 uint32 addr = (GPR32 (OP[2])) + OP[1];
3777 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3778 SB (addr, a);
3779 trace_output_32 (sd, addr);
3780 }
3781
3782 /* storb. */
3783 void
3784 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
3785 {
3786 uint8 a = (OP[0]) & 0xff;
3787 uint32 addr = (GPR32 (OP[2])) + OP[1];
3788 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3789 SB (addr, a);
3790 trace_output_32 (sd, addr);
3791 }
3792 /* endif for STR_IMM. */
3793
3794 /* storw . */
3795 void
3796 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
3797 {
3798 uint16 a = GPR (OP[0]);
3799 uint32 addr = OP[1];
3800 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3801 SW (addr, a);
3802 trace_output_32 (sd, addr);
3803 }
3804
3805 /* storw. */
3806 void
3807 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
3808 {
3809 uint16 a = GPR (OP[0]);
3810 uint32 addr = OP[1];
3811 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3812 SW (addr, a);
3813 trace_output_32 (sd, addr);
3814 }
3815
3816 /* storw. */
3817 void
3818 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
3819 {
3820 uint32 addr;
3821 uint16 a = GPR (OP[0]);
3822 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3823
3824 if (OP[1] == 0)
3825 addr = (GPR32 (12)) + OP[2];
3826 else
3827 addr = (GPR32 (13)) + OP[2];
3828
3829 SW (addr, a);
3830 trace_output_32 (sd, addr);
3831 }
3832
3833
3834 /* storw. */
3835 void
3836 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
3837 {
3838 uint16 a = (GPR (OP[0]));
3839 uint32 addr = (GPR32 (OP[2])) + OP[1];
3840 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3841 SW (addr, a);
3842 trace_output_32 (sd, addr);
3843 }
3844
3845 /* storw. */
3846 void
3847 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
3848 {
3849 uint16 a = GPR (OP[0]);
3850 uint32 addr = (GPR32 (OP[2])) + OP[1];
3851 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3852 SW (addr, a);
3853 trace_output_32 (sd, addr);
3854 }
3855
3856 /* storw. */
3857 void
3858 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
3859 {
3860 uint16 a = GPR (OP[0]);
3861 uint32 addr = (GPR32 (OP[2])) + OP[1];
3862 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3863 SW (addr, a);
3864 trace_output_32 (sd, addr);
3865 }
3866
3867 /* storw. */
3868 void
3869 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
3870 {
3871 uint16 a = (GPR (OP[0]));
3872 uint32 addr = (GPR32 (OP[2])) + OP[1];
3873 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3874 SW (addr, a);
3875 trace_output_32 (sd, addr);
3876 }
3877
3878 /* storw. */
3879 void
3880 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
3881 {
3882 uint16 a = (GPR (OP[0]));
3883 uint32 addr = (GPR (OP[2])) + OP[1];
3884 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3885 SW (addr, a);
3886 trace_output_32 (sd, addr);
3887 }
3888
3889 /* storw. */
3890 void
3891 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
3892 {
3893 uint16 a = (GPR (OP[0]));
3894 uint32 addr = (GPR32 (OP[2])) + OP[1];
3895 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3896 SW (addr, a);
3897 trace_output_32 (sd, addr);
3898 }
3899
3900 /* storw. */
3901 void
3902 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
3903 {
3904 uint16 a = (GPR (OP[0]));
3905 uint32 addr = (GPR32 (OP[2])) + OP[1];
3906 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3907 SW (addr, a);
3908 trace_output_32 (sd, addr);
3909 }
3910
3911 /* storw. */
3912 void
3913 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
3914 {
3915 uint16 a = (GPR (OP[0]));
3916 uint32 addr = (GPR32 (OP[2])) + OP[1];
3917 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3918 SW (addr, a);
3919 trace_output_32 (sd, addr);
3920 }
3921
3922 /* storw. */
3923 void
3924 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
3925 {
3926 uint16 a = (GPR (OP[0]));
3927 uint32 addr = (GPR32 (OP[2])) + OP[1];
3928 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3929 SW (addr, a);
3930 trace_output_32 (sd, addr);
3931 }
3932
3933 /* STORE-w IMM instruction *****/
3934 /* storw . */
3935 void
3936 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
3937 {
3938 uint16 a = OP[0];
3939 uint32 addr = OP[1];
3940 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3941 SW (addr, a);
3942 trace_output_32 (sd, addr);
3943 }
3944
3945 /* storw. */
3946 void
3947 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
3948 {
3949 uint16 a = OP[0];
3950 uint32 addr = OP[1];
3951 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3952 SW (addr, a);
3953 trace_output_32 (sd, addr);
3954 }
3955
3956 /* storw. */
3957 void
3958 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
3959 {
3960 uint32 addr;
3961 uint16 a = OP[0];
3962 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3963
3964 if (OP[1] == 0)
3965 addr = (GPR32 (12)) + OP[2];
3966 else
3967 addr = (GPR32 (13)) + OP[2];
3968
3969 SW (addr, a);
3970 trace_output_32 (sd, addr);
3971 }
3972
3973 /* storw. */
3974 void
3975 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
3976 {
3977 uint16 a = OP[0];
3978 uint32 addr = (GPR32 (OP[2])) + OP[1];
3979 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3980 SW (addr, a);
3981 trace_output_32 (sd, addr);
3982 }
3983
3984 /* storw. */
3985 void
3986 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
3987 {
3988 uint16 a = OP[0];
3989 uint32 addr = (GPR32 (OP[2])) + OP[1];
3990 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3991 SW (addr, a);
3992 trace_output_32 (sd, addr);
3993 }
3994
3995 /* storw. */
3996 void
3997 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
3998 {
3999 uint16 a = OP[0];
4000 uint32 addr = (GPR32 (OP[2])) + OP[1];
4001 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
4002 SW (addr, a);
4003 trace_output_32 (sd, addr);
4004 }
4005
4006 /* storw. */
4007 void
4008 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
4009 {
4010 uint16 a = OP[0];
4011 uint32 addr = (GPR32 (OP[2])) + OP[1];
4012 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4013 SW (addr, a);
4014 trace_output_32 (sd, addr);
4015 }
4016
4017
4018 /* storw. */
4019 void
4020 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
4021 {
4022 uint16 a = OP[0];
4023 uint32 addr = (GPR32 (OP[2])) + OP[1];
4024 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4025 SW (addr, a);
4026 trace_output_32 (sd, addr);
4027 }
4028
4029 /* storw. */
4030 void
4031 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
4032 {
4033 uint16 a = OP[0];
4034 uint32 addr = (GPR32 (OP[2])) + OP[1];
4035 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4036 SW (addr, a);
4037 trace_output_32 (sd, addr);
4038 }
4039
4040
4041 /* stord. */
4042 void
4043 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
4044 {
4045 uint32 a = GPR32 (OP[0]);
4046 uint32 addr = OP[1];
4047 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4048 SLW (addr, a);
4049 trace_output_32 (sd, addr);
4050 }
4051
4052 /* stord. */
4053 void
4054 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
4055 {
4056 uint32 a = GPR32 (OP[0]);
4057 uint32 addr = OP[1];
4058 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4059 SLW (addr, a);
4060 trace_output_32 (sd, addr);
4061 }
4062
4063 /* stord. */
4064 void
4065 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
4066 {
4067 uint32 addr, a = GPR32 (OP[0]);
4068 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4069
4070 if (OP[1] == 0)
4071 addr = (GPR32 (12)) + OP[2];
4072 else
4073 addr = (GPR32 (13)) + OP[2];
4074
4075 SLW (addr, a);
4076 trace_output_32 (sd, addr);
4077 }
4078
4079 /* stord. */
4080 void
4081 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
4082 {
4083 uint32 a = GPR32 (OP[0]);
4084 uint32 addr = (GPR32 (OP[2])) + OP[1];
4085 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4086 SLW (addr, a);
4087 trace_output_32 (sd, addr);
4088 }
4089
4090 /* stord. */
4091 void
4092 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
4093 {
4094 uint32 a = GPR32 (OP[0]);
4095 uint32 addr = (GPR32 (OP[2])) + OP[1];
4096 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4097 SLW (addr, a);
4098 trace_output_32 (sd, addr);
4099 }
4100
4101 /* stord. */
4102 void
4103 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
4104 {
4105 uint32 a = GPR32 (OP[0]);
4106 uint32 addr = (GPR32 (OP[2])) + OP[1];
4107 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4108 SLW (addr, a);
4109 trace_output_32 (sd, addr);
4110 }
4111
4112 /* stord. */
4113 void
4114 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
4115 {
4116 uint32 a = GPR32 (OP[0]);
4117 uint32 addr = (GPR32 (OP[2])) + OP[1];
4118 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4119 SLW (addr, a);
4120 trace_output_32 (sd, addr);
4121 }
4122
4123 /* stord. */
4124 void
4125 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
4126 {
4127 uint32 a = GPR32 (OP[0]);
4128 uint32 addr = (GPR32 (OP[2])) + OP[1];
4129 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4130 SLW (addr, a);
4131 trace_output_32 (sd, addr);
4132 }
4133
4134 /* stord. */
4135 void
4136 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
4137 {
4138 uint32 a = GPR32 (OP[0]);
4139 uint32 addr = (GPR32 (OP[2])) + OP[1];
4140 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4141 SLW (addr, a);
4142 trace_output_32 (sd, addr);
4143 }
4144
4145 /* stord. */
4146 void
4147 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
4148 {
4149 uint32 a = GPR32 (OP[0]);
4150 uint32 addr = (GPR32 (OP[2])) + OP[1];
4151 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4152 SLW (addr, a);
4153 trace_output_32 (sd, addr);
4154 }
4155
4156 /* stord. */
4157 void
4158 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
4159 {
4160 uint32 a = GPR32 (OP[0]);
4161 uint32 addr = (GPR32 (OP[2])) + OP[1];
4162 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4163 SLW (addr, a);
4164 trace_output_32 (sd, addr);
4165 }
4166
4167 /* stord. */
4168 void
4169 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
4170 {
4171 uint32 a = GPR32 (OP[0]);
4172 uint32 addr = (GPR32 (OP[2])) + OP[1];
4173 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4174 SLW (addr, a);
4175 trace_output_32 (sd, addr);
4176 }
4177
4178 /* macqu. */
4179 void
4180 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
4181 {
4182 int32 tmp;
4183 int16 src1, src2;
4184 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4185 src1 = GPR (OP[0]);
4186 src2 = GPR (OP[1]);
4187 tmp = src1 * src2;
4188 /*REVISIT FOR SATURATION and Q FORMAT. */
4189 SET_GPR32 (OP[2], tmp);
4190 trace_output_32 (sd, tmp);
4191 }
4192
4193 /* macuw. */
4194 void
4195 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
4196 {
4197 uint32 tmp;
4198 uint16 src1, src2;
4199 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4200 src1 = GPR (OP[0]);
4201 src2 = GPR (OP[1]);
4202 tmp = src1 * src2;
4203 /*REVISIT FOR SATURATION. */
4204 SET_GPR32 (OP[2], tmp);
4205 trace_output_32 (sd, tmp);
4206 }
4207
4208 /* macsw. */
4209 void
4210 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
4211 {
4212 int32 tmp;
4213 int16 src1, src2;
4214 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4215 src1 = GPR (OP[0]);
4216 src2 = GPR (OP[1]);
4217 tmp = src1 * src2;
4218 /*REVISIT FOR SATURATION. */
4219 SET_GPR32 (OP[2], tmp);
4220 trace_output_32 (sd, tmp);
4221 }
4222
4223
4224 /* mulb. */
4225 void
4226 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
4227 {
4228 int16 tmp;
4229 int8 a = (OP[0]) & 0xff;
4230 int8 b = (GPR (OP[1])) & 0xff;
4231 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4232 tmp = (a * b) & 0xff;
4233 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4234 trace_output_16 (sd, tmp);
4235 }
4236
4237 /* mulb. */
4238 void
4239 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
4240 {
4241 int16 tmp;
4242 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4243 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4244 tmp = (a * b) & 0xff;
4245 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4246 trace_output_16 (sd, tmp);
4247 }
4248
4249
4250 /* mulb. */
4251 void
4252 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
4253 {
4254 int16 tmp;
4255 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4256 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4257 tmp = (a * b) & 0xff;
4258 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4259 trace_output_16 (sd, tmp);
4260 }
4261
4262
4263 /* mulw. */
4264 void
4265 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
4266 {
4267 int32 tmp;
4268 uint16 a = OP[0];
4269 int16 b = (GPR (OP[1]));
4270 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4271 tmp = (a * b) & 0xffff;
4272 SET_GPR (OP[1], tmp);
4273 trace_output_32 (sd, tmp);
4274 }
4275
4276 /* mulw. */
4277 void
4278 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
4279 {
4280 int32 tmp;
4281 int16 a = OP[0], b = (GPR (OP[1]));
4282 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4283 tmp = (a * b) & 0xffff;
4284 SET_GPR (OP[1], tmp);
4285 trace_output_32 (sd, tmp);
4286 }
4287
4288
4289 /* mulw. */
4290 void
4291 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
4292 {
4293 int32 tmp;
4294 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4295 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4296 tmp = (a * b) & 0xffff;
4297 SET_GPR (OP[1], tmp);
4298 trace_output_32 (sd, tmp);
4299 }
4300
4301
4302 /* mulsb. */
4303 void
4304 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
4305 {
4306 int16 tmp;
4307 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4308 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4309 tmp = a * b;
4310 SET_GPR (OP[1], tmp);
4311 trace_output_32 (sd, tmp);
4312 }
4313
4314 /* mulsw. */
4315 void
4316 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
4317 {
4318 int32 tmp;
4319 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4320 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4321 tmp = a * b;
4322 SET_GPR32 (OP[1], tmp);
4323 trace_output_32 (sd, tmp);
4324 }
4325
4326 /* muluw. */
4327 void
4328 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
4329 {
4330 uint32 tmp;
4331 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4332 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4333 tmp = a * b;
4334 SET_GPR32 (OP[1], tmp);
4335 trace_output_32 (sd, tmp);
4336 }
4337
4338
4339 /* nop. */
4340 void
4341 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
4342 {
4343 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4344
4345 #if 0
4346 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4347 switch (State.ins_type)
4348 {
4349 default:
4350 ins_type_counters[ (int)INS_UNKNOWN ]++;
4351 break;
4352
4353 }
4354 EXCEPTION (SIM_SIGTRAP);
4355 #endif
4356 trace_output_void (sd);
4357 }
4358
4359
4360 /* orb. */
4361 void
4362 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
4363 {
4364 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4365 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4366 tmp = a | b;
4367 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4368 trace_output_16 (sd, tmp);
4369 }
4370
4371 /* orb. */
4372 void
4373 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
4374 {
4375 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4376 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4377 tmp = a | b;
4378 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4379 trace_output_16 (sd, tmp);
4380 }
4381
4382 /* orb. */
4383 void
4384 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
4385 {
4386 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4387 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4388 tmp = a | b;
4389 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4390 trace_output_16 (sd, tmp);
4391 }
4392
4393 /* orw. */
4394 void
4395 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
4396 {
4397 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4398 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4399 tmp = a | b;
4400 SET_GPR (OP[1], tmp);
4401 trace_output_16 (sd, tmp);
4402 }
4403
4404
4405 /* orw. */
4406 void
4407 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
4408 {
4409 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4410 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4411 tmp = a | b;
4412 SET_GPR (OP[1], tmp);
4413 trace_output_16 (sd, tmp);
4414 }
4415
4416 /* orw. */
4417 void
4418 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
4419 {
4420 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4421 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4422 tmp = a | b;
4423 SET_GPR (OP[1], tmp);
4424 trace_output_16 (sd, tmp);
4425 }
4426
4427
4428 /* lshb. */
4429 void
4430 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
4431 {
4432 uint16 a = OP[0];
4433 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4434 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4435 /* A positive count specifies a shift to the left;
4436 * A negative count specifies a shift to the right. */
4437 if (sign_flag)
4438 tmp = b >> a;
4439 else
4440 tmp = b << a;
4441
4442 sign_flag = 0; /* Reset sign_flag. */
4443
4444 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4445 trace_output_16 (sd, tmp);
4446 }
4447
4448 /* lshb. */
4449 void
4450 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
4451 {
4452 uint16 a = (GPR (OP[0])) & 0xff;
4453 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4454 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4455 if (a & ((long)1 << 3))
4456 {
4457 sign_flag = 1;
4458 a = ~(a) + 1;
4459 }
4460 a = (unsigned int) (a & 0x7);
4461
4462 /* A positive count specifies a shift to the left;
4463 * A negative count specifies a shift to the right. */
4464 if (sign_flag)
4465 tmp = b >> a;
4466 else
4467 tmp = b << a;
4468
4469 sign_flag = 0; /* Reset sign_flag. */
4470 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4471 trace_output_16 (sd, tmp);
4472 }
4473
4474 /* lshw. */
4475 void
4476 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
4477 {
4478 uint16 tmp, b = GPR (OP[1]);
4479 int16 a = GPR (OP[0]);
4480 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4481 if (a & ((long)1 << 4))
4482 {
4483 sign_flag = 1;
4484 a = ~(a) + 1;
4485 }
4486 a = (unsigned int) (a & 0xf);
4487
4488 /* A positive count specifies a shift to the left;
4489 * A negative count specifies a shift to the right. */
4490 if (sign_flag)
4491 tmp = b >> a;
4492 else
4493 tmp = b << a;
4494
4495 sign_flag = 0; /* Reset sign_flag. */
4496 SET_GPR (OP[1], (tmp & 0xffff));
4497 trace_output_16 (sd, tmp);
4498 }
4499
4500 /* lshw. */
4501 void
4502 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
4503 {
4504 uint16 tmp, b = GPR (OP[1]);
4505 uint16 a = OP[0];
4506 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4507 /* A positive count specifies a shift to the left;
4508 * A negative count specifies a shift to the right. */
4509 if (sign_flag)
4510 tmp = b >> a;
4511 else
4512 tmp = b << a;
4513
4514 sign_flag = 0; /* Reset sign_flag. */
4515 SET_GPR (OP[1], (tmp & 0xffff));
4516 trace_output_16 (sd, tmp);
4517 }
4518
4519 /* lshd. */
4520 void
4521 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
4522 {
4523 uint32 tmp, b = GPR32 (OP[1]);
4524 uint16 a = OP[0];
4525 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4526 /* A positive count specifies a shift to the left;
4527 * A negative count specifies a shift to the right. */
4528 if (sign_flag)
4529 tmp = b >> a;
4530 else
4531 tmp = b << a;
4532
4533 sign_flag = 0; /* Reset sign flag. */
4534
4535 SET_GPR32 (OP[1], tmp);
4536 trace_output_32 (sd, tmp);
4537 }
4538
4539 /* lshd. */
4540 void
4541 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
4542 {
4543 uint32 tmp, b = GPR32 (OP[1]);
4544 uint16 a = GPR (OP[0]);
4545 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4546 if (a & ((long)1 << 5))
4547 {
4548 sign_flag = 1;
4549 a = ~(a) + 1;
4550 }
4551 a = (unsigned int) (a & 0x1f);
4552 /* A positive count specifies a shift to the left;
4553 * A negative count specifies a shift to the right. */
4554 if (sign_flag)
4555 tmp = b >> a;
4556 else
4557 tmp = b << a;
4558
4559 sign_flag = 0; /* Reset sign flag. */
4560
4561 SET_GPR32 (OP[1], tmp);
4562 trace_output_32 (sd, tmp);
4563 }
4564
4565 /* ashub. */
4566 void
4567 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
4568 {
4569 uint16 a = OP[0];
4570 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4571 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4572 /* A positive count specifies a shift to the left;
4573 * A negative count specifies a shift to the right. */
4574 if (sign_flag)
4575 tmp = b >> a;
4576 else
4577 tmp = b << a;
4578
4579 sign_flag = 0; /* Reset sign flag. */
4580
4581 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4582 trace_output_16 (sd, tmp);
4583 }
4584
4585 /* ashub. */
4586 void
4587 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
4588 {
4589 uint16 a = OP[0];
4590 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4591 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4592 /* A positive count specifies a shift to the left;
4593 * A negative count specifies a shift to the right. */
4594 if (sign_flag)
4595 tmp = b >> a;
4596 else
4597 tmp = b << a;
4598
4599 sign_flag = 0; /* Reset sign flag. */
4600
4601 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4602 trace_output_16 (sd, tmp);
4603 }
4604
4605
4606 /* ashub. */
4607 void
4608 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
4609 {
4610 int16 a = (GPR (OP[0]));
4611 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4612 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4613
4614 if (a & ((long)1 << 3))
4615 {
4616 sign_flag = 1;
4617 a = ~(a) + 1;
4618 }
4619 a = (unsigned int) (a & 0x7);
4620
4621 /* A positive count specifies a shift to the left;
4622 * A negative count specifies a shift to the right. */
4623 if (sign_flag)
4624 tmp = b >> a;
4625 else
4626 tmp = b << a;
4627
4628 sign_flag = 0; /* Reset sign flag. */
4629
4630 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4631 trace_output_16 (sd, tmp);
4632 }
4633
4634
4635 /* ashuw. */
4636 void
4637 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
4638 {
4639 int16 tmp, b = GPR (OP[1]);
4640 uint16 a = OP[0];
4641 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4642 /* A positive count specifies a shift to the left;
4643 * A negative count specifies a shift to the right. */
4644 if (sign_flag)
4645 tmp = b >> a;
4646 else
4647 tmp = b << a;
4648
4649 sign_flag = 0; /* Reset sign flag. */
4650
4651 SET_GPR (OP[1], (tmp & 0xffff));
4652 trace_output_16 (sd, tmp);
4653 }
4654
4655 /* ashuw. */
4656 void
4657 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
4658 {
4659 int16 tmp, b = GPR (OP[1]);
4660 uint16 a = OP[0];
4661 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4662 /* A positive count specifies a shift to the left;
4663 * A negative count specifies a shift to the right. */
4664 if (sign_flag)
4665 tmp = b >> a;
4666 else
4667 tmp = b << a;
4668
4669 sign_flag = 0; /* Reset sign flag. */
4670 SET_GPR (OP[1], (tmp & 0xffff));
4671 trace_output_16 (sd, tmp);
4672 }
4673
4674 /* ashuw. */
4675 void
4676 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
4677 {
4678 int16 tmp;
4679 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4680 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4681
4682 if (a & ((long)1 << 4))
4683 {
4684 sign_flag = 1;
4685 a = ~(a) + 1;
4686 }
4687 a = (unsigned int) (a & 0xf);
4688 /* A positive count specifies a shift to the left;
4689 * A negative count specifies a shift to the right. */
4690
4691 if (sign_flag)
4692 tmp = b >> a;
4693 else
4694 tmp = b << a;
4695
4696 sign_flag = 0; /* Reset sign flag. */
4697 SET_GPR (OP[1], (tmp & 0xffff));
4698 trace_output_16 (sd, tmp);
4699 }
4700
4701 /* ashud. */
4702 void
4703 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
4704 {
4705 int32 tmp,b = GPR32 (OP[1]);
4706 uint32 a = OP[0];
4707 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4708 /* A positive count specifies a shift to the left;
4709 * A negative count specifies a shift to the right. */
4710 if (sign_flag)
4711 tmp = b >> a;
4712 else
4713 tmp = b << a;
4714
4715 sign_flag = 0; /* Reset sign flag. */
4716 SET_GPR32 (OP[1], tmp);
4717 trace_output_32 (sd, tmp);
4718 }
4719
4720 /* ashud. */
4721 void
4722 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
4723 {
4724 int32 tmp;
4725 int32 a = OP[0], b = GPR32 (OP[1]);
4726 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4727 /* A positive count specifies a shift to the left;
4728 * A negative count specifies a shift to the right. */
4729 if (sign_flag)
4730 tmp = b >> a;
4731 else
4732 tmp = b << a;
4733
4734 sign_flag = 0; /* Reset sign flag. */
4735 SET_GPR32 (OP[1], tmp);
4736 trace_output_32 (sd, tmp);
4737 }
4738
4739 /* ashud. */
4740 void
4741 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
4742 {
4743 int32 tmp;
4744 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4745 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4746
4747 if (a & ((long)1 << 5))
4748 {
4749 sign_flag = 1;
4750 a = ~(a) + 1;
4751 }
4752 a = (unsigned int) (a & 0x1f);
4753 /* A positive count specifies a shift to the left;
4754 * A negative count specifies a shift to the right. */
4755 if (sign_flag)
4756 tmp = b >> a;
4757 else
4758 tmp = b << a;
4759
4760 sign_flag = 0; /* Reset sign flag. */
4761 SET_GPR32 (OP[1], tmp);
4762 trace_output_32 (sd, tmp);
4763 }
4764
4765
4766 /* storm. */
4767 void
4768 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
4769 {
4770 uint32 addr = GPR (1);
4771 uint16 count = OP[0], reg = 2;
4772 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4773 if ((addr & 1))
4774 {
4775 trace_output_void (sd);
4776 EXCEPTION (SIM_SIGBUS);
4777 }
4778
4779 while (count)
4780 {
4781 SW (addr, (GPR (reg)));
4782 addr +=2;
4783 --count;
4784 reg++;
4785 if (reg == 6) reg = 8;
4786 };
4787
4788 SET_GPR (1, addr);
4789
4790 trace_output_void (sd);
4791 }
4792
4793
4794 /* stormp. */
4795 void
4796 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
4797 {
4798 uint32 addr = GPR32 (6);
4799 uint16 count = OP[0], reg = 2;
4800 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4801 if ((addr & 1))
4802 {
4803 trace_output_void (sd);
4804 EXCEPTION (SIM_SIGBUS);
4805 }
4806
4807 while (count)
4808 {
4809 SW (addr, (GPR (reg)));
4810 addr +=2;
4811 --count;
4812 reg++;
4813 if (reg == 6) reg = 8;
4814 };
4815
4816 SET_GPR32 (6, addr);
4817 trace_output_void (sd);
4818 }
4819
4820 /* subb. */
4821 void
4822 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
4823 {
4824 uint8 a = OP[0];
4825 uint8 b = (GPR (OP[1])) & 0xff;
4826 uint16 tmp = (~a + 1 + b) & 0xff;
4827 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4828 /* see ../common/sim-alu.h for a more extensive discussion on how to
4829 compute the carry/overflow bits. */
4830 SET_PSR_C (tmp > 0xff);
4831 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4832 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4833 trace_output_16 (sd, tmp);
4834 }
4835
4836 /* subb. */
4837 void
4838 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
4839 {
4840 uint8 a = OP[0] & 0xFF;
4841 uint8 b = (GPR (OP[1])) & 0xFF;
4842 uint16 tmp = (~a + 1 + b) & 0xFF;
4843 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4844 /* see ../common/sim-alu.h for a more extensive discussion on how to
4845 compute the carry/overflow bits. */
4846 SET_PSR_C (tmp > 0xff);
4847 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4848 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4849 trace_output_16 (sd, tmp);
4850 }
4851
4852 /* subb. */
4853 void
4854 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
4855 {
4856 uint8 a = (GPR (OP[0])) & 0xFF;
4857 uint8 b = (GPR (OP[1])) & 0xFF;
4858 uint16 tmp = (~a + 1 + b) & 0xff;
4859 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4860 /* see ../common/sim-alu.h for a more extensive discussion on how to
4861 compute the carry/overflow bits. */
4862 SET_PSR_C (tmp > 0xff);
4863 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4864 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4865 trace_output_16 (sd, tmp);
4866 }
4867
4868 /* subw. */
4869 void
4870 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
4871 {
4872 uint16 a = OP[0];
4873 uint16 b = GPR (OP[1]);
4874 uint16 tmp = (~a + 1 + b);
4875 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4876 /* see ../common/sim-alu.h for a more extensive discussion on how to
4877 compute the carry/overflow bits. */
4878 SET_PSR_C (tmp > 0xffff);
4879 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4880 SET_GPR (OP[1], tmp);
4881 trace_output_16 (sd, tmp);
4882 }
4883
4884 /* subw. */
4885 void
4886 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
4887 {
4888 uint16 a = OP[0];
4889 uint16 b = GPR (OP[1]);
4890 uint32 tmp = (~a + 1 + b);
4891 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4892 /* see ../common/sim-alu.h for a more extensive discussion on how to
4893 compute the carry/overflow bits. */
4894 SET_PSR_C (tmp > 0xffff);
4895 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4896 SET_GPR (OP[1], tmp & 0xffff);
4897 trace_output_16 (sd, tmp);
4898 }
4899
4900 /* subw. */
4901 void
4902 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
4903 {
4904 uint16 a = GPR (OP[0]);
4905 uint16 b = GPR (OP[1]);
4906 uint32 tmp = (~a + 1 + b);
4907 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4908 /* see ../common/sim-alu.h for a more extensive discussion on how to
4909 compute the carry/overflow bits. */
4910 SET_PSR_C (tmp > 0xffff);
4911 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4912 SET_GPR (OP[1], tmp & 0xffff);
4913 trace_output_16 (sd, tmp);
4914 }
4915
4916 /* subcb. */
4917 void
4918 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
4919 {
4920 uint8 a = OP[0];
4921 uint8 b = (GPR (OP[1])) & 0xff;
4922 //uint16 tmp1 = a + 1;
4923 uint16 tmp1 = a + (PSR_C);
4924 uint16 tmp = (~tmp1 + 1 + b);
4925 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4926 /* see ../common/sim-alu.h for a more extensive discussion on how to
4927 compute the carry/overflow bits. */
4928 SET_PSR_C (tmp > 0xff);
4929 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4930 SET_GPR (OP[1], tmp);
4931 trace_output_16 (sd, tmp);
4932 }
4933
4934 /* subcb. */
4935 void
4936 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
4937 {
4938 uint16 a = OP[0];
4939 uint16 b = (GPR (OP[1])) & 0xff;
4940 //uint16 tmp1 = a + 1;
4941 uint16 tmp1 = a + (PSR_C);
4942 uint16 tmp = (~tmp1 + 1 + b);
4943 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4944 /* see ../common/sim-alu.h for a more extensive discussion on how to
4945 compute the carry/overflow bits. */
4946 SET_PSR_C (tmp > 0xff);
4947 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4948 SET_GPR (OP[1], tmp);
4949 trace_output_16 (sd, tmp);
4950 }
4951
4952 /* subcb. */
4953 void
4954 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
4955 {
4956 uint16 a = (GPR (OP[0])) & 0xff;
4957 uint16 b = (GPR (OP[1])) & 0xff;
4958 uint16 tmp1 = a + (PSR_C);
4959 uint16 tmp = (~tmp1 + 1 + b);
4960 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4961 /* see ../common/sim-alu.h for a more extensive discussion on how to
4962 compute the carry/overflow bits. */
4963 SET_PSR_C (tmp > 0xff);
4964 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4965 SET_GPR (OP[1], tmp);
4966 trace_output_16 (sd, tmp);
4967 }
4968
4969 /* subcw. */
4970 void
4971 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
4972 {
4973 uint16 a = OP[0], b = (GPR (OP[1]));
4974 uint16 tmp1 = a + (PSR_C);
4975 uint16 tmp = (~tmp1 + 1 + b);
4976 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4977 /* see ../common/sim-alu.h for a more extensive discussion on how to
4978 compute the carry/overflow bits. */
4979 SET_PSR_C (tmp > 0xffff);
4980 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4981 SET_GPR (OP[1], tmp);
4982 trace_output_16 (sd, tmp);
4983 }
4984
4985 /* subcw. */
4986 void
4987 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
4988 {
4989 int16 a = OP[0];
4990 uint16 b = GPR (OP[1]);
4991 uint16 tmp1 = a + (PSR_C);
4992 uint16 tmp = (~tmp1 + 1 + b);
4993 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4994 /* see ../common/sim-alu.h for a more extensive discussion on how to
4995 compute the carry/overflow bits. */
4996 SET_PSR_C (tmp > 0xffff);
4997 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4998 SET_GPR (OP[1], tmp);
4999 trace_output_16 (sd, tmp);
5000 }
5001
5002 /* subcw. */
5003 void
5004 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
5005 {
5006 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5007 uint16 tmp1 = a + (PSR_C);
5008 uint16 tmp = (~tmp1 + 1 + b);
5009 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5010 /* see ../common/sim-alu.h for a more extensive discussion on how to
5011 compute the carry/overflow bits. */
5012 SET_PSR_C (tmp > 0xffff);
5013 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5014 SET_GPR (OP[1], tmp);
5015 trace_output_16 (sd, tmp);
5016 }
5017
5018 /* subd. */
5019 void
5020 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
5021 {
5022 int32 a = OP[0];
5023 uint32 b = GPR32 (OP[1]);
5024 uint32 tmp = (~a + 1 + b);
5025 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5026 /* see ../common/sim-alu.h for a more extensive discussion on how to
5027 compute the carry/overflow bits. */
5028 SET_PSR_C (tmp > 0xffffffff);
5029 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5030 ((b & 0x80000000) != (tmp & 0x80000000)));
5031 SET_GPR32 (OP[1], tmp);
5032 trace_output_32 (sd, tmp);
5033 }
5034
5035 /* subd. */
5036 void
5037 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
5038 {
5039 uint32 a = GPR32 (OP[0]);
5040 uint32 b = GPR32 (OP[1]);
5041 uint32 tmp = (~a + 1 + b);
5042 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5043 /* see ../common/sim-alu.h for a more extensive discussion on how to
5044 compute the carry/overflow bits. */
5045 SET_PSR_C (tmp > 0xffffffff);
5046 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5047 ((b & 0x80000000) != (tmp & 0x80000000)));
5048 SET_GPR32 (OP[1], tmp);
5049 trace_output_32 (sd, tmp);
5050 }
5051
5052 /* excp. */
5053 void
5054 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
5055 {
5056 host_callback *cb = STATE_CALLBACK (sd);
5057 uint32 tmp;
5058 uint16 a;
5059 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5060 switch (OP[0])
5061 {
5062 default:
5063 #if (DEBUG & DEBUG_TRAP) == 0
5064 {
5065 #if 0
5066 uint16 vec = OP[0] + TRAP_VECTOR_START;
5067 SET_BPC (PC + 1);
5068 SET_BPSR (PSR);
5069 SET_PSR (PSR & PSR_SM_BIT);
5070 JMP (vec);
5071 break;
5072 #endif
5073 }
5074 #else /* if debugging use trap to print registers */
5075 {
5076 int i;
5077 static int first_time = 1;
5078
5079 if (first_time)
5080 {
5081 first_time = 0;
5082 sim_io_printf (sd, "Trap # PC ");
5083 for (i = 0; i < 16; i++)
5084 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5085 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
5086 }
5087
5088 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5089
5090 for (i = 0; i < 16; i++)
5091 sim_io_printf (sd, " %.4x", (int) GPR (i));
5092
5093 for (i = 0; i < 2; i++)
5094 sim_io_printf (sd, " %.2x%.8lx",
5095 ((int)(ACC (i) >> 32) & 0xff),
5096 ((unsigned long) ACC (i)) & 0xffffffff);
5097
5098 sim_io_printf (sd, " %d %d %d\n",
5099 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5100 sim_io_flush_stdout (sd);
5101 break;
5102 }
5103 #endif
5104 case 8: /* new system call trap */
5105 /* Trap 8 is used for simulating low-level I/O */
5106 {
5107 unsigned32 result = 0;
5108 errno = 0;
5109
5110 /* Registers passed to trap 0. */
5111
5112 #define FUNC GPR (0) /* function number. */
5113 #define PARM1 GPR (2) /* optional parm 1. */
5114 #define PARM2 GPR (3) /* optional parm 2. */
5115 #define PARM3 GPR (4) /* optional parm 3. */
5116 #define PARM4 GPR (5) /* optional parm 4. */
5117
5118 /* Registers set by trap 0 */
5119
5120 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5121 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5122 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5123
5124 /* Turn a pointer in a register into a pointer into real memory. */
5125
5126 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5127
5128 switch (FUNC)
5129 {
5130 #if !defined(__GO32__) && !defined(_WIN32)
5131 #ifdef TARGET_SYS_fork
5132 case TARGET_SYS_fork:
5133 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5134 RETVAL (fork ());
5135 trace_output_16 (sd, result);
5136 break;
5137 #endif
5138
5139 #define getpid() 47
5140 case TARGET_SYS_getpid:
5141 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5142 RETVAL (getpid ());
5143 trace_output_16 (sd, result);
5144 break;
5145
5146 case TARGET_SYS_kill:
5147 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5148 if (PARM1 == getpid ())
5149 {
5150 trace_output_void (sd);
5151 EXCEPTION (PARM2);
5152 }
5153 else
5154 {
5155 int os_sig = -1;
5156 switch (PARM2)
5157 {
5158 #ifdef SIGHUP
5159 case 1: os_sig = SIGHUP; break;
5160 #endif
5161 #ifdef SIGINT
5162 case 2: os_sig = SIGINT; break;
5163 #endif
5164 #ifdef SIGQUIT
5165 case 3: os_sig = SIGQUIT; break;
5166 #endif
5167 #ifdef SIGILL
5168 case 4: os_sig = SIGILL; break;
5169 #endif
5170 #ifdef SIGTRAP
5171 case 5: os_sig = SIGTRAP; break;
5172 #endif
5173 #ifdef SIGABRT
5174 case 6: os_sig = SIGABRT; break;
5175 #elif defined(SIGIOT)
5176 case 6: os_sig = SIGIOT; break;
5177 #endif
5178 #ifdef SIGEMT
5179 case 7: os_sig = SIGEMT; break;
5180 #endif
5181 #ifdef SIGFPE
5182 case 8: os_sig = SIGFPE; break;
5183 #endif
5184 #ifdef SIGKILL
5185 case 9: os_sig = SIGKILL; break;
5186 #endif
5187 #ifdef SIGBUS
5188 case 10: os_sig = SIGBUS; break;
5189 #endif
5190 #ifdef SIGSEGV
5191 case 11: os_sig = SIGSEGV; break;
5192 #endif
5193 #ifdef SIGSYS
5194 case 12: os_sig = SIGSYS; break;
5195 #endif
5196 #ifdef SIGPIPE
5197 case 13: os_sig = SIGPIPE; break;
5198 #endif
5199 #ifdef SIGALRM
5200 case 14: os_sig = SIGALRM; break;
5201 #endif
5202 #ifdef SIGTERM
5203 case 15: os_sig = SIGTERM; break;
5204 #endif
5205 #ifdef SIGURG
5206 case 16: os_sig = SIGURG; break;
5207 #endif
5208 #ifdef SIGSTOP
5209 case 17: os_sig = SIGSTOP; break;
5210 #endif
5211 #ifdef SIGTSTP
5212 case 18: os_sig = SIGTSTP; break;
5213 #endif
5214 #ifdef SIGCONT
5215 case 19: os_sig = SIGCONT; break;
5216 #endif
5217 #ifdef SIGCHLD
5218 case 20: os_sig = SIGCHLD; break;
5219 #elif defined(SIGCLD)
5220 case 20: os_sig = SIGCLD; break;
5221 #endif
5222 #ifdef SIGTTIN
5223 case 21: os_sig = SIGTTIN; break;
5224 #endif
5225 #ifdef SIGTTOU
5226 case 22: os_sig = SIGTTOU; break;
5227 #endif
5228 #ifdef SIGIO
5229 case 23: os_sig = SIGIO; break;
5230 #elif defined (SIGPOLL)
5231 case 23: os_sig = SIGPOLL; break;
5232 #endif
5233 #ifdef SIGXCPU
5234 case 24: os_sig = SIGXCPU; break;
5235 #endif
5236 #ifdef SIGXFSZ
5237 case 25: os_sig = SIGXFSZ; break;
5238 #endif
5239 #ifdef SIGVTALRM
5240 case 26: os_sig = SIGVTALRM; break;
5241 #endif
5242 #ifdef SIGPROF
5243 case 27: os_sig = SIGPROF; break;
5244 #endif
5245 #ifdef SIGWINCH
5246 case 28: os_sig = SIGWINCH; break;
5247 #endif
5248 #ifdef SIGLOST
5249 case 29: os_sig = SIGLOST; break;
5250 #endif
5251 #ifdef SIGUSR1
5252 case 30: os_sig = SIGUSR1; break;
5253 #endif
5254 #ifdef SIGUSR2
5255 case 31: os_sig = SIGUSR2; break;
5256 #endif
5257 }
5258
5259 if (os_sig == -1)
5260 {
5261 trace_output_void (sd);
5262 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5263 sim_io_flush_stdout (sd);
5264 EXCEPTION (SIM_SIGILL);
5265 }
5266 else
5267 {
5268 RETVAL (kill (PARM1, PARM2));
5269 trace_output_16 (sd, result);
5270 }
5271 }
5272 break;
5273
5274 #ifdef TARGET_SYS_execve
5275 case TARGET_SYS_execve:
5276 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5277 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5278 (char **)MEMPTR (PARM4)));
5279 trace_output_16 (sd, result);
5280 break;
5281 #endif
5282
5283 #ifdef TARGET_SYS_execv
5284 case TARGET_SYS_execv:
5285 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5286 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5287 trace_output_16 (sd, result);
5288 break;
5289 #endif
5290
5291 #ifdef TARGET_SYS_pipe
5292 case TARGET_SYS_pipe:
5293 {
5294 reg_t buf;
5295 int host_fd[2];
5296
5297 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5298 buf = PARM1;
5299 RETVAL (pipe (host_fd));
5300 SW (buf, host_fd[0]);
5301 buf += sizeof(uint16);
5302 SW (buf, host_fd[1]);
5303 trace_output_16 (sd, result);
5304 }
5305 break;
5306 #endif
5307
5308 #ifdef TARGET_SYS_wait
5309 case TARGET_SYS_wait:
5310 {
5311 int status;
5312 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5313 RETVAL (wait (&status));
5314 if (PARM1)
5315 SW (PARM1, status);
5316 trace_output_16 (sd, result);
5317 }
5318 break;
5319 #endif
5320 #else
5321 case TARGET_SYS_getpid:
5322 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5323 RETVAL (1);
5324 trace_output_16 (sd, result);
5325 break;
5326
5327 case TARGET_SYS_kill:
5328 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5329 trace_output_void (sd);
5330 EXCEPTION (PARM2);
5331 break;
5332 #endif
5333
5334 case TARGET_SYS_read:
5335 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5336 RETVAL (cb->read (cb, PARM1,
5337 MEMPTR (((unsigned long)PARM3 << 16)
5338 | ((unsigned long)PARM2)), PARM4));
5339 trace_output_16 (sd, result);
5340 break;
5341
5342 case TARGET_SYS_write:
5343 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5344 RETVAL ((int)cb->write (cb, PARM1,
5345 MEMPTR (((unsigned long)PARM3 << 16)
5346 | PARM2), PARM4));
5347 trace_output_16 (sd, result);
5348 break;
5349
5350 case TARGET_SYS_lseek:
5351 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5352 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5353 PARM4));
5354 trace_output_32 (sd, result);
5355 break;
5356
5357 case TARGET_SYS_close:
5358 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5359 RETVAL (cb->close (cb, PARM1));
5360 trace_output_16 (sd, result);
5361 break;
5362
5363 case TARGET_SYS_open:
5364 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5365 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5366 | PARM1), PARM3));
5367 trace_output_32 (sd, result);
5368 break;
5369
5370 #ifdef TARGET_SYS_rename
5371 case TARGET_SYS_rename:
5372 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5373 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5374 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
5375 trace_output_16 (sd, result);
5376 break;
5377 #endif
5378
5379 case 0x408: /* REVISIT: Added a dummy getenv call. */
5380 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5381 RETVAL32 (0);
5382 trace_output_32 (sd, result);
5383 break;
5384
5385 case TARGET_SYS_exit:
5386 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5387 trace_output_void (sd);
5388 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5389 break;
5390
5391 case TARGET_SYS_unlink:
5392 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5393 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
5394 trace_output_16 (sd, result);
5395 break;
5396
5397
5398 #ifdef TARGET_SYS_stat
5399 case TARGET_SYS_stat:
5400 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5401 /* stat system call. */
5402 {
5403 struct stat host_stat;
5404 reg_t buf;
5405
5406 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5407
5408 buf = PARM2;
5409
5410 /* The hard-coded offsets and sizes were determined by using
5411 * the CR16 compiler on a test program that used struct stat.
5412 */
5413 SW (buf, host_stat.st_dev);
5414 SW (buf+2, host_stat.st_ino);
5415 SW (buf+4, host_stat.st_mode);
5416 SW (buf+6, host_stat.st_nlink);
5417 SW (buf+8, host_stat.st_uid);
5418 SW (buf+10, host_stat.st_gid);
5419 SW (buf+12, host_stat.st_rdev);
5420 SLW (buf+16, host_stat.st_size);
5421 SLW (buf+20, host_stat.st_atime);
5422 SLW (buf+28, host_stat.st_mtime);
5423 SLW (buf+36, host_stat.st_ctime);
5424 }
5425 trace_output_16 (sd, result);
5426 break;
5427 #endif
5428
5429 #ifdef TARGET_SYS_chown
5430 case TARGET_SYS_chown:
5431 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5432 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5433 trace_output_16 (sd, result);
5434 break;
5435 #endif
5436
5437 case TARGET_SYS_chmod:
5438 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5439 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5440 trace_output_16 (sd, result);
5441 break;
5442
5443 #ifdef TARGET_SYS_utime
5444 case TARGET_SYS_utime:
5445 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5446 /* Cast the second argument to void *, to avoid type mismatch
5447 if a prototype is present. */
5448 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5449 trace_output_16 (sd, result);
5450 break;
5451 #endif
5452
5453 #ifdef TARGET_SYS_time
5454 case TARGET_SYS_time:
5455 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5456 RETVAL32 (time (NULL));
5457 trace_output_32 (sd, result);
5458 break;
5459 #endif
5460
5461 default:
5462 a = OP[0];
5463 switch (a)
5464 {
5465 case TRAP_BREAKPOINT:
5466 tmp = (PC);
5467 JMP(tmp);
5468 trace_output_void (sd);
5469 EXCEPTION (SIM_SIGTRAP);
5470 break;
5471 case SIGTRAP: /* supervisor call ? */
5472 trace_output_void (sd);
5473 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5474 break;
5475 default:
5476 cb->error (cb, "Unknown syscall %d", FUNC);
5477 break;
5478 }
5479 }
5480 if ((uint16) result == (uint16) -1)
5481 RETERR (cb->get_errno (cb));
5482 else
5483 RETERR (0);
5484 break;
5485 }
5486 }
5487 }
5488
5489
5490 /* push. */
5491 void
5492 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
5493 {
5494 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5495 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5496 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5497
5498 for (; i < a; ++i)
5499 {
5500 if ((b+i) <= 11)
5501 {
5502 SW (sp_addr, (GPR (b+i)));
5503 sp_addr +=2;
5504 }
5505 else
5506 {
5507 if (is_regp == 0)
5508 tmp = (GPR32 (b+i));
5509 else
5510 tmp = (GPR32 (b+i-1));
5511
5512 if ((a-i) > 1)
5513 {
5514 SLW (sp_addr, tmp);
5515 sp_addr +=4;
5516 }
5517 else
5518 {
5519 SW (sp_addr, tmp);
5520 sp_addr +=2;
5521 }
5522 ++i;
5523 is_regp = 1;
5524 }
5525 }
5526
5527 sp_addr +=4;
5528
5529 /* Store RA address. */
5530 tmp = (GPR32 (14));
5531 SLW(sp_addr,tmp);
5532
5533 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5534 SET_GPR32 (15, sp_addr); /* Update SP address. */
5535
5536 trace_output_void (sd);
5537 }
5538
5539 /* push. */
5540 void
5541 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
5542 {
5543 uint32 sp_addr, tmp, is_regp = 0;
5544 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5545 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5546
5547 if (c == 1)
5548 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5549 else
5550 sp_addr = (GPR32 (15)) - (a * 2);
5551
5552 for (; i < a; ++i)
5553 {
5554 if ((b+i) <= 11)
5555 {
5556 SW (sp_addr, (GPR (b+i)));
5557 sp_addr +=2;
5558 }
5559 else
5560 {
5561 if (is_regp == 0)
5562 tmp = (GPR32 (b+i));
5563 else
5564 tmp = (GPR32 (b+i-1));
5565
5566 if ((a-i) > 1)
5567 {
5568 SLW (sp_addr, tmp);
5569 sp_addr +=4;
5570 }
5571 else
5572 {
5573 SW (sp_addr, tmp);
5574 sp_addr +=2;
5575 }
5576 ++i;
5577 is_regp = 1;
5578 }
5579 }
5580
5581 if (c == 1)
5582 {
5583 /* Store RA address. */
5584 tmp = (GPR32 (14));
5585 SLW(sp_addr,tmp);
5586 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5587 }
5588 else
5589 sp_addr = (GPR32 (15)) - (a * 2);
5590
5591 SET_GPR32 (15, sp_addr); /* Update SP address. */
5592
5593 trace_output_void (sd);
5594 }
5595
5596
5597 /* push. */
5598 void
5599 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
5600 {
5601 uint32 sp_addr = (GPR32 (15)), tmp;
5602 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5603 tmp = (GPR32 (14));
5604 SLW(sp_addr-4,tmp); /* Store RA address. */
5605 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5606 trace_output_void (sd);
5607 }
5608
5609
5610 /* pop. */
5611 void
5612 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
5613 {
5614 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5615 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5616 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5617
5618 for (; i < a; ++i)
5619 {
5620 if ((b+i) <= 11)
5621 {
5622 SET_GPR ((b+i), RW(sp_addr));
5623 sp_addr +=2;
5624 }
5625 else
5626 {
5627 if ((a-i) > 1)
5628 {
5629 tmp = RLW(sp_addr);
5630 sp_addr +=4;
5631 }
5632 else
5633 {
5634 tmp = RW(sp_addr);
5635 sp_addr +=2;
5636
5637 if (is_regp == 0)
5638 tmp = (tmp << 16) | (GPR32 (b+i));
5639 else
5640 tmp = (tmp << 16) | (GPR32 (b+i-1));
5641 }
5642
5643 if (is_regp == 0)
5644 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5645 | ((tmp >> 16) & 0xffff)));
5646 else
5647 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5648 | ((tmp >> 16) & 0xffff)));
5649
5650 ++i;
5651 is_regp = 1;
5652 }
5653 }
5654
5655 tmp = RLW(sp_addr); /* store RA also. */
5656 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5657
5658 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5659
5660 trace_output_void (sd);
5661 }
5662
5663 /* pop. */
5664 void
5665 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
5666 {
5667 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5668 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5669 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5670
5671 for (; i < a; ++i)
5672 {
5673 if ((b+i) <= 11)
5674 {
5675 SET_GPR ((b+i), RW(sp_addr));
5676 sp_addr +=2;
5677 }
5678 else
5679 {
5680 if ((a-i) > 1)
5681 {
5682 tmp = RLW(sp_addr);
5683 sp_addr +=4;
5684 }
5685 else
5686 {
5687 tmp = RW(sp_addr);
5688 sp_addr +=2;
5689
5690 if (is_regp == 0)
5691 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5692 else
5693 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5694 }
5695
5696 if (is_regp == 0)
5697 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5698 else
5699 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5700 ++i;
5701 is_regp = 1;
5702 }
5703 }
5704
5705 if (c == 1)
5706 {
5707 tmp = RLW(sp_addr); /* Store RA Reg. */
5708 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5709 sp_addr +=4;
5710 }
5711
5712 SET_GPR32 (15, sp_addr); /* Update SP address. */
5713
5714 trace_output_void (sd);
5715 }
5716
5717 /* pop. */
5718 void
5719 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
5720 {
5721 uint32 sp_addr = GPR32 (15);
5722 uint32 tmp;
5723 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5724
5725 tmp = RLW(sp_addr);
5726 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5727 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5728
5729 trace_output_void (sd);
5730 }
5731
5732 /* popret. */
5733 void
5734 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
5735 {
5736 uint16 a = OP[0], b = OP[1];
5737 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5738 OP_5_9 (sd, cpu);
5739 JMP(((GPR32(14)) << 1) & 0xffffff);
5740
5741 trace_output_void (sd);
5742 }
5743
5744 /* popret. */
5745 void
5746 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
5747 {
5748 uint16 a = OP[0], b = OP[1];
5749 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5750 OP_2_8 (sd, cpu);
5751 JMP(((GPR32(14)) << 1) & 0xffffff);
5752
5753 trace_output_void (sd);
5754 }
5755
5756 /* popret. */
5757 void
5758 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
5759 {
5760 uint32 tmp;
5761 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5762 OP_21E_10 (sd, cpu);
5763 tmp = (((GPR32(14)) << 1) & 0xffffff);
5764 /* If the resulting PC value is less than 0x00_0000 or greater
5765 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5766
5767 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5768 {
5769 trace_output_void (sd);
5770 EXCEPTION (SIM_SIGBUS);
5771 }
5772 else
5773 JMP (tmp);
5774
5775 trace_output_32 (sd, tmp);
5776 }
5777
5778
5779 /* cinv[i]. */
5780 void
5781 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
5782 {
5783 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5784 SET_PSR_I (1);
5785 trace_output_void (sd);
5786 }
5787
5788 /* cinv[i,u]. */
5789 void
5790 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
5791 {
5792 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5793 SET_PSR_I (1);
5794 trace_output_void (sd);
5795 }
5796
5797 /* cinv[d]. */
5798 void
5799 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
5800 {
5801 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5802 SET_PSR_I (1);
5803 trace_output_void (sd);
5804 }
5805
5806 /* cinv[d,u]. */
5807 void
5808 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
5809 {
5810 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5811 SET_PSR_I (1);
5812 trace_output_void (sd);
5813 }
5814
5815 /* cinv[d,i]. */
5816 void
5817 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
5818 {
5819 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5820 SET_PSR_I (1);
5821 trace_output_void (sd);
5822 }
5823
5824 /* cinv[d,i,u]. */
5825 void
5826 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
5827 {
5828 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5829 SET_PSR_I (1);
5830 trace_output_void (sd);
5831 }
5832
5833 /* retx. */
5834 void
5835 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
5836 {
5837 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5838 SET_PSR_I (1);
5839 trace_output_void (sd);
5840 }
5841
5842 /* di. */
5843 void
5844 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
5845 {
5846 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5847 SET_PSR_I (1);
5848 trace_output_void (sd);
5849 }
5850
5851 /* ei. */
5852 void
5853 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
5854 {
5855 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5856 SET_PSR_I (1);
5857 trace_output_void (sd);
5858 }
5859
5860 /* wait. */
5861 void
5862 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
5863 {
5864 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5865 trace_output_void (sd);
5866 EXCEPTION (SIM_SIGTRAP);
5867 }
5868
5869 /* ewait. */
5870 void
5871 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
5872 {
5873 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5874 SET_PSR_I (1);
5875 trace_output_void (sd);
5876 }
5877
5878 /* xorb. */
5879 void
5880 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
5881 {
5882 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5883 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5884 tmp = a ^ b;
5885 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5886 trace_output_16 (sd, tmp);
5887 }
5888
5889 /* xorb. */
5890 void
5891 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
5892 {
5893 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5894 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5895 tmp = a ^ b;
5896 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5897 trace_output_16 (sd, tmp);
5898 }
5899
5900 /* xorb. */
5901 void
5902 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
5903 {
5904 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5905 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5906 tmp = a ^ b;
5907 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5908 trace_output_16 (sd, tmp);
5909 }
5910
5911 /* xorw. */
5912 void
5913 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
5914 {
5915 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5916 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5917 tmp = a ^ b;
5918 SET_GPR (OP[1], tmp);
5919 trace_output_16 (sd, tmp);
5920 }
5921
5922 /* xorw. */
5923 void
5924 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
5925 {
5926 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5927 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5928 tmp = a ^ b;
5929 SET_GPR (OP[1], tmp);
5930 trace_output_16 (sd, tmp);
5931 }
5932
5933 /* xorw. */
5934 void
5935 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
5936 {
5937 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5938 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5939 tmp = a ^ b;
5940 SET_GPR (OP[1], tmp);
5941 trace_output_16 (sd, tmp);
5942 }
5943
5944 /*REVISIT FOR LPR/SPR . */
5945
5946 /* lpr. */
5947 void
5948 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
5949 {
5950 uint16 a = GPR (OP[0]);
5951 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5952 SET_CREG (OP[1], a);
5953 trace_output_16 (sd, a);
5954 }
5955
5956 /* lprd. */
5957 void
5958 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
5959 {
5960 uint32 a = GPR32 (OP[0]);
5961 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5962 SET_CREG (OP[1], a);
5963 trace_output_flag (sd);
5964 }
5965
5966 /* spr. */
5967 void
5968 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
5969 {
5970 uint16 a = CREG (OP[0]);
5971 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5972 SET_GPR (OP[1], a);
5973 trace_output_16 (sd, a);
5974 }
5975
5976 /* sprd. */
5977 void
5978 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
5979 {
5980 uint32 a = CREG (OP[0]);
5981 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5982 SET_GPR32 (OP[1], a);
5983 trace_output_32 (sd, a);
5984 }
5985
5986 /* null. */
5987 void
5988 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
5989 {
5990 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
5991 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
5992 }
GDB Binutils - Deliverables
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