sim/cris/cris-desc.h

   1 /* CPU data header for cris.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2020 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifndef CRIS_CPU_H
  25 #define CRIS_CPU_H
  26
  27 #define CGEN_ARCH cris
  28
  29 /* Given symbol S, return cris_cgen_<S>.  */
  30 #define CGEN_SYM(s) cris##_cgen_##s
  31
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_CRISV0F
  35 #define HAVE_CPU_CRISV3F
  36 #define HAVE_CPU_CRISV8F
  37 #define HAVE_CPU_CRISV10F
  38 #define HAVE_CPU_CRISV32F
  39
  40 #define CGEN_INSN_LSB0_P 1
  41
  42 /* Minimum size of any insn (in bytes).  */
  43 #define CGEN_MIN_INSN_SIZE 2
  44
  45 /* Maximum size of any insn (in bytes).  */
  46 #define CGEN_MAX_INSN_SIZE 6
  47
  48 #define CGEN_INT_INSN_P 0
  49
  50 /* Maximum number of syntax elements in an instruction.  */
  51 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
  52
  53 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  54    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  55    we can't hash on everything up to the space.  */
  56 #define CGEN_MNEMONIC_OPERANDS
  57
  58 /* Maximum number of fields in an instruction.  */
  59 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6
  60
  61 /* Enums.  */
  62
  63 /* Enum declaration for .  */
  64 typedef enum gr_names_pcreg {
  65   H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1
  66  , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5
  67  , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9
  68  , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13
  69  , H_GR_REAL_PC_R14 = 14
  70 } GR_NAMES_PCREG;
  71
  72 /* Enum declaration for .  */
  73 typedef enum gr_names_acr {
  74   H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1
  75  , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
  76  , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
  77  , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
  78  , H_GR_R14 = 14
  79 } GR_NAMES_ACR;
  80
  81 /* Enum declaration for .  */
  82 typedef enum gr_names_v32 {
  83   H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1
  84  , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5
  85  , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9
  86  , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13
  87  , H_GR_V32_R14 = 14
  88 } GR_NAMES_V32;
  89
  90 /* Enum declaration for .  */
  91 typedef enum p_names_v10 {
  92   H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10
  93  , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15
  94  , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1
  95  , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5
  96  , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9
  97  , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13
  98  , H_SR_PRE_V32_P14 = 14
  99 } P_NAMES_V10;
 100
 101 /* Enum declaration for .  */
 102 typedef enum p_names_v32 {
 103   H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4
 104  , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8
 105  , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13
 106  , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11
 107  , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3
 108  , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7
 109  , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11
 110  , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14
 111 } P_NAMES_V32;
 112
 113 /* Enum declaration for .  */
 114 typedef enum p_names_v32_x {
 115   H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4
 116  , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8
 117  , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13
 118  , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11
 119  , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3
 120  , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7
 121  , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11
 122  , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14
 123 } P_NAMES_V32_X;
 124
 125 /* Enum declaration for Standard instruction operand size.  */
 126 typedef enum insn_size {
 127   SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED
 128 } INSN_SIZE;
 129
 130 /* Enum declaration for Standard instruction addressing modes.  */
 131 typedef enum insn_mode {
 132   MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT
 133 } INSN_MODE;
 134
 135 /* Enum declaration for Whether the operand is indirect.  */
 136 typedef enum insn_memoryness_mode {
 137   MODEMEMP_NO, MODEMEMP_YES
 138 } INSN_MEMORYNESS_MODE;
 139
 140 /* Enum declaration for Whether the indirect operand is autoincrement.  */
 141 typedef enum insn_memincness_mode {
 142   MODEINCP_NO, MODEINCP_YES
 143 } INSN_MEMINCNESS_MODE;
 144
 145 /* Enum declaration for Signed instruction operand size.  */
 146 typedef enum insn_signed_size {
 147   SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD
 148 } INSN_SIGNED_SIZE;
 149
 150 /* Enum declaration for Unsigned instruction operand size.  */
 151 typedef enum insn_unsigned_size {
 152   UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3
 153 } INSN_UNSIGNED_SIZE;
 154
 155 /* Enum declaration for Insns for MODE_QUICK_IMMEDIATE.  */
 156 typedef enum insn_qi_opc {
 157   Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3
 158  , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3
 159  , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ
 160  , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ
 161 } INSN_QI_OPC;
 162
 163 /* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode.  */
 164 typedef enum insn_qihi_opc {
 165   QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3
 166 } INSN_QIHI_OPC;
 167
 168 /* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 169 typedef enum insn_r_opc {
 170   R_ADDX, R_MOVX, R_SUBX, R_LSL
 171  , R_ADDI, R_BIAP, R_NEG, R_BOUND
 172  , R_ADD, R_MOVE, R_SUB, R_CMP
 173  , R_AND, R_OR, R_ASR, R_LSR
 174 } INSN_R_OPC;
 175
 176 /* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED.  */
 177 typedef enum insn_rfix_opc {
 178   RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST
 179  , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF
 180  , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP
 181  , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP
 182 } INSN_RFIX_OPC;
 183
 184 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 185 typedef enum insn_indir_opc {
 186   INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX
 187  , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND
 188  , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP
 189  , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M
 190 } INSN_INDIR_OPC;
 191
 192 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED.  */
 193 typedef enum insn_infix_opc {
 194   INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX
 195  , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M
 196  , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE
 197  , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M
 198 } INSN_INFIX_OPC;
 199
 200 /* Attributes.  */
 201
 202 /* Enum declaration for machine type selection.  */
 203 typedef enum mach_attr {
 204   MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8
 205  , MACH_CRISV10, MACH_CRISV32, MACH_MAX
 206 } MACH_ATTR;
 207
 208 /* Enum declaration for instruction set selection.  */
 209 typedef enum isa_attr {
 210   ISA_CRIS, ISA_MAX
 211 } ISA_ATTR;
 212
 213 /* Number of architecture variants.  */
 214 #define MAX_ISAS  1
 215 #define MAX_MACHS ((int) MACH_MAX)
 216
 217 /* Ifield support.  */
 218
 219 /* Ifield attribute indices.  */
 220
 221 /* Enum declaration for cgen_ifld attrs.  */
 222 typedef enum cgen_ifld_attr {
 223   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 224  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 225  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 226 } CGEN_IFLD_ATTR;
 227
 228 /* Number of non-boolean elements in cgen_ifld_attr.  */
 229 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 230
 231 /* cgen_ifld attribute accessor macros.  */
 232 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 233 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 234 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 235 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 236 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
 237 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 238 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
 239
 240 /* Enum declaration for cris ifield types.  */
 241 typedef enum ifield_type {
 242   CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE
 243  , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE
 244  , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC
 245  , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4
 246  , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9
 247  , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL
 248  , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX
 249 } IFIELD_TYPE;
 250
 251 #define MAX_IFLD ((int) CRIS_F_MAX)
 252
 253 /* Hardware attribute indices.  */
 254
 255 /* Enum declaration for cgen_hw attrs.  */
 256 typedef enum cgen_hw_attr {
 257   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 258  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 259 } CGEN_HW_ATTR;
 260
 261 /* Number of non-boolean elements in cgen_hw_attr.  */
 262 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 263
 264 /* cgen_hw attribute accessor macros.  */
 265 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 266 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
 267 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 268 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
 269 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
 270
 271 /* Enum declaration for cris hardware types.  */
 272 typedef enum cgen_hw_type {
 273   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 274  , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP
 275  , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR
 276  , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR
 277  , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE
 278  , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X
 279  , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT
 280  , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT
 281  , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT
 282  , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT
 283  , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X
 284  , HW_H_PREFIXREG, HW_MAX
 285 } CGEN_HW_TYPE;
 286
 287 #define MAX_HW ((int) HW_MAX)
 288
 289 /* Operand attribute indices.  */
 290
 291 /* Enum declaration for cgen_operand attrs.  */
 292 typedef enum cgen_operand_attr {
 293   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 294  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 295  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 296 } CGEN_OPERAND_ATTR;
 297
 298 /* Number of non-boolean elements in cgen_operand_attr.  */
 299 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 300
 301 /* cgen_operand attribute accessor macros.  */
 302 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 303 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 304 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 305 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 306 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 307 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
 308 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 309 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
 310 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 311
 312 /* Enum declaration for cris operand types.  */
 313 typedef enum cgen_operand_type {
 314   CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT
 315  , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT
 316  , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT
 317  , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT
 318  , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS
 319  , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD
 320  , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO
 321  , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16
 322  , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD
 323  , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC
 324  , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX
 325 } CGEN_OPERAND_TYPE;
 326
 327 /* Number of operands types.  */
 328 #define MAX_OPERANDS 43
 329
 330 /* Maximum number of operands referenced by any insn.  */
 331 #define MAX_OPERAND_INSTANCES 8
 332
 333 /* Insn attribute indices.  */
 334
 335 /* Enum declaration for cgen_insn attrs.  */
 336 typedef enum cgen_insn_attr {
 337   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 338  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 339  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 340  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 341 } CGEN_INSN_ATTR;
 342
 343 /* Number of non-boolean elements in cgen_insn_attr.  */
 344 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 345
 346 /* cgen_insn attribute accessor macros.  */
 347 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 348 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
 349 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
 350 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 351 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
 352 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 353 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 354 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
 355 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
 356 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
 357 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
 358
 359 /* cgen.h uses things we just defined.  */
 360 #include "opcode/cgen.h"
 361
 362 extern const struct cgen_ifld cris_cgen_ifld_table[];
 363
 364 /* Attributes.  */
 365 extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[];
 366 extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[];
 367 extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[];
 368 extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[];
 369
 370 /* Hardware decls.  */
 371
 372 extern CGEN_KEYWORD cris_cgen_opval_h_inc;
 373 extern CGEN_KEYWORD cris_cgen_opval_h_ccode;
 374 extern CGEN_KEYWORD cris_cgen_opval_h_swap;
 375 extern CGEN_KEYWORD cris_cgen_opval_h_flagbits;
 376 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 377 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 378 extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr;
 379 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 380 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 381 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 382 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 383 extern CGEN_KEYWORD cris_cgen_opval_p_names_v32;
 384 extern CGEN_KEYWORD cris_cgen_opval_h_supr;
 385
 386 extern const CGEN_HW_ENTRY cris_cgen_hw_table[];
 387
 388
 389
 390 #endif /* CRIS_CPU_H */