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[deliverable/binutils-gdb.git] / sim / frv / Makefile.in
1 # Makefile template for Configure for the frv simulator
2 # Copyright (C) 1998-2022 Free Software Foundation, Inc.
3 # Contributed by Red Hat.
4 #
5 # This program is free software; you can redistribute it and/or modify
6 # it under the terms of the GNU General Public License as published by
7 # the Free Software Foundation; either version 3 of the License, or
8 # (at your option) any later version.
9 #
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
14 #
15 # You should have received a copy of the GNU General Public License
16 # along with this program. If not, see <http://www.gnu.org/licenses/>.
17
18 ## COMMON_PRE_CONFIG_FRAG
19
20 FRV_OBJS = frv.o cpu.o decode.o sem.o model.o mloop.o cgen-par.o
21
22 SIM_OBJS = \
23 $(SIM_NEW_COMMON_OBJS) \
24 cgen-utils.o cgen-trace.o cgen-scache.o cgen-fpu.o cgen-accfp.o \
25 cgen-run.o \
26 sim-if.o arch.o \
27 $(FRV_OBJS) \
28 traps.o interrupts.o memory.o cache.o pipeline.o \
29 profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \
30 reset.o registers.o
31
32 # Extra headers included by sim-main.h.
33 SIM_EXTRA_DEPS = \
34 $(CGEN_INCLUDE_DEPS) \
35 arch.h cpuall.h frv-sim.h $(srcdir)/../../opcodes/frv-desc.h cache.h \
36 registers.h profile.h eng.h \
37 $(sim-options_h)
38
39 SIM_EXTRA_CFLAGS = @SIM_FRV_TRAPDUMP_FLAGS@
40
41 SIM_EXTRA_CLEAN = frv-clean
42
43 # Code doesn't build cleanly yet.
44 SIM_WERROR_CFLAGS =
45
46 ## COMMON_POST_CONFIG_FRAG
47
48 arch = frv
49
50 # FRV objs
51
52 FRVBF_INCLUDE_DEPS = \
53 $(CGEN_MAIN_CPU_DEPS) \
54 $(SIM_EXTRA_DEPS) \
55 cpu.h decode.h eng.h
56
57 # FIXME: Use of `mono' is wip.
58 mloop.c eng.h: stamp-mloop
59 stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
60 $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
61 -mono -scache -parallel-generic-write -parallel-only \
62 -cpu frvbf -infile $(srcdir)/mloop.in
63 $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
64 $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
65 touch stamp-mloop
66
67 frv-clean:
68 rm -f mloop.c eng.h stamp-mloop
69 rm -f tmp-*
70 rm -f stamp-arch stamp-cpu
71
72 stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srcdir)/../../cpu/frv.cpu
73 $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
74 archfile=$(srcdir)/../../cpu/frv.cpu \
75 FLAGS="with-scache"
76 touch stamp-arch
77 arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
78 # @true
79
80 stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
81 $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
82 cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \
83 archfile=$(srcdir)/../../cpu/frv.cpu \
84 FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
85 EXTRAFILES="$(CGEN_CPU_SEM)"
86 touch stamp-cpu
87 cpu.h sem.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
88 # @true
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