sim/i960/cpu.h

   1 /* CPU family header for i960base.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_I960BASE_H
  26 #define CPU_I960BASE_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 1
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[32];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* condition code */
  48   SI h_cc;
  49 #define GET_H_CC() CPU (h_cc)
  50 #define SET_H_CC(x) (CPU (h_cc) = (x))
  51   } hardware;
  52 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  53 } I960BASE_CPU_DATA;
  54
  55 /* Cover fns for register access.  */
  56 USI i960base_h_pc_get (SIM_CPU *);
  57 void i960base_h_pc_set (SIM_CPU *, USI);
  58 SI i960base_h_gr_get (SIM_CPU *, UINT);
  59 void i960base_h_gr_set (SIM_CPU *, UINT, SI);
  60 SI i960base_h_cc_get (SIM_CPU *);
  61 void i960base_h_cc_set (SIM_CPU *, SI);
  62
  63 /* These must be hand-written.  */
  64 extern CPUREG_FETCH_FN i960base_fetch_register;
  65 extern CPUREG_STORE_FN i960base_store_register;
  66
  67 typedef struct {
  68   int empty;
  69 } MODEL_I960KA_DATA;
  70
  71 typedef struct {
  72   int empty;
  73 } MODEL_I960CA_DATA;
  74
  75 /* Instruction argument buffer.  */
  76
  77 union sem_fields {
  78   struct { /* no operands */
  79     int empty;
  80   } fmt_empty;
  81   struct { /*  */
  82     IADDR i_ctrl_disp;
  83   } sfmt_bno;
  84   struct { /*  */
  85     SI* i_br_src1;
  86     unsigned char out_br_src1;
  87   } sfmt_testno_reg;
  88   struct { /*  */
  89     IADDR i_br_disp;
  90     SI* i_br_src2;
  91     UINT f_br_src1;
  92     unsigned char in_br_src2;
  93   } sfmt_cmpobe_lit;
  94   struct { /*  */
  95     IADDR i_br_disp;
  96     SI* i_br_src1;
  97     SI* i_br_src2;
  98     unsigned char in_br_src1;
  99     unsigned char in_br_src2;
 100   } sfmt_cmpobe_reg;
 101   struct { /*  */
 102     SI* i_dst;
 103     UINT f_src1;
 104     UINT f_src2;
 105     UINT f_srcdst;
 106     unsigned char out_dst;
 107     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 108   } sfmt_emul3;
 109   struct { /*  */
 110     SI* i_dst;
 111     SI* i_src1;
 112     UINT f_src2;
 113     UINT f_srcdst;
 114     unsigned char in_src1;
 115     unsigned char out_dst;
 116     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 117   } sfmt_emul2;
 118   struct { /*  */
 119     SI* i_dst;
 120     SI* i_src2;
 121     UINT f_src1;
 122     UINT f_srcdst;
 123     unsigned char in_src2;
 124     unsigned char out_dst;
 125     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 126   } sfmt_emul1;
 127   struct { /*  */
 128     SI* i_dst;
 129     SI* i_src1;
 130     SI* i_src2;
 131     UINT f_srcdst;
 132     unsigned char in_src1;
 133     unsigned char in_src2;
 134     unsigned char out_dst;
 135     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 136   } sfmt_emul;
 137   struct { /*  */
 138     SI* i_abase;
 139     SI* i_st_src;
 140     UINT f_offset;
 141     UINT f_srcdst;
 142     unsigned char in_abase;
 143     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
 144     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
 145     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
 146     unsigned char in_st_src;
 147   } sfmt_stq_indirect_offset;
 148   struct { /*  */
 149     SI* i_abase;
 150     SI* i_dst;
 151     UINT f_offset;
 152     UINT f_srcdst;
 153     unsigned char in_abase;
 154     unsigned char out_dst;
 155     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 156     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
 157     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
 158   } sfmt_ldq_indirect_offset;
 159   struct { /*  */
 160     SI* i_abase;
 161     SI* i_index;
 162     SI* i_st_src;
 163     UINT f_optdisp;
 164     UINT f_scale;
 165     UINT f_srcdst;
 166     unsigned char in_abase;
 167     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
 168     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
 169     unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
 170     unsigned char in_index;
 171     unsigned char in_st_src;
 172   } sfmt_stq_indirect_index_disp;
 173   struct { /*  */
 174     SI* i_abase;
 175     SI* i_dst;
 176     SI* i_index;
 177     UINT f_optdisp;
 178     UINT f_scale;
 179     UINT f_srcdst;
 180     unsigned char in_abase;
 181     unsigned char in_index;
 182     unsigned char out_dst;
 183     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 184     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
 185     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
 186   } sfmt_ldq_indirect_index_disp;
 187   struct { /*  */
 188     SI* i_dst;
 189     SI* i_src1;
 190     UINT f_src1;
 191     UINT f_srcdst;
 192     unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_1;
 193     unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_2;
 194     unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_3;
 195     unsigned char in_src1;
 196     unsigned char out_dst;
 197     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
 198     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
 199     unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
 200   } sfmt_movq;
 201   struct { /*  */
 202     UINT f_optdisp;
 203     unsigned char in_h_gr_0;
 204     unsigned char in_h_gr_1;
 205     unsigned char in_h_gr_10;
 206     unsigned char in_h_gr_11;
 207     unsigned char in_h_gr_12;
 208     unsigned char in_h_gr_13;
 209     unsigned char in_h_gr_14;
 210     unsigned char in_h_gr_15;
 211     unsigned char in_h_gr_2;
 212     unsigned char in_h_gr_3;
 213     unsigned char in_h_gr_31;
 214     unsigned char in_h_gr_4;
 215     unsigned char in_h_gr_5;
 216     unsigned char in_h_gr_6;
 217     unsigned char in_h_gr_7;
 218     unsigned char in_h_gr_8;
 219     unsigned char in_h_gr_9;
 220     unsigned char out_h_gr_0;
 221     unsigned char out_h_gr_1;
 222     unsigned char out_h_gr_10;
 223     unsigned char out_h_gr_11;
 224     unsigned char out_h_gr_12;
 225     unsigned char out_h_gr_13;
 226     unsigned char out_h_gr_14;
 227     unsigned char out_h_gr_15;
 228     unsigned char out_h_gr_2;
 229     unsigned char out_h_gr_3;
 230     unsigned char out_h_gr_31;
 231     unsigned char out_h_gr_4;
 232     unsigned char out_h_gr_5;
 233     unsigned char out_h_gr_6;
 234     unsigned char out_h_gr_7;
 235     unsigned char out_h_gr_8;
 236     unsigned char out_h_gr_9;
 237   } sfmt_callx_disp;
 238   struct { /*  */
 239     SI* i_abase;
 240     UINT f_offset;
 241     unsigned char in_abase;
 242     unsigned char in_h_gr_0;
 243     unsigned char in_h_gr_1;
 244     unsigned char in_h_gr_10;
 245     unsigned char in_h_gr_11;
 246     unsigned char in_h_gr_12;
 247     unsigned char in_h_gr_13;
 248     unsigned char in_h_gr_14;
 249     unsigned char in_h_gr_15;
 250     unsigned char in_h_gr_2;
 251     unsigned char in_h_gr_3;
 252     unsigned char in_h_gr_31;
 253     unsigned char in_h_gr_4;
 254     unsigned char in_h_gr_5;
 255     unsigned char in_h_gr_6;
 256     unsigned char in_h_gr_7;
 257     unsigned char in_h_gr_8;
 258     unsigned char in_h_gr_9;
 259     unsigned char out_h_gr_0;
 260     unsigned char out_h_gr_1;
 261     unsigned char out_h_gr_10;
 262     unsigned char out_h_gr_11;
 263     unsigned char out_h_gr_12;
 264     unsigned char out_h_gr_13;
 265     unsigned char out_h_gr_14;
 266     unsigned char out_h_gr_15;
 267     unsigned char out_h_gr_2;
 268     unsigned char out_h_gr_3;
 269     unsigned char out_h_gr_31;
 270     unsigned char out_h_gr_4;
 271     unsigned char out_h_gr_5;
 272     unsigned char out_h_gr_6;
 273     unsigned char out_h_gr_7;
 274     unsigned char out_h_gr_8;
 275     unsigned char out_h_gr_9;
 276   } sfmt_callx_indirect_offset;
 277 #if WITH_SCACHE_PBB
 278   /* Writeback handler.  */
 279   struct {
 280     /* Pointer to argbuf entry for insn whose results need writing back.  */
 281     const struct argbuf *abuf;
 282   } write;
 283   /* x-before handler */
 284   struct {
 285     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 286     int first_p;
 287   } before;
 288   /* x-after handler */
 289   struct {
 290     int empty;
 291   } after;
 292   /* This entry is used to terminate each pbb.  */
 293   struct {
 294     /* Number of insns in pbb.  */
 295     int insn_count;
 296     /* Next pbb to execute.  */
 297     SCACHE *next;
 298     SCACHE *branch_target;
 299   } chain;
 300 #endif
 301 };
 302
 303 /* The ARGBUF struct.  */
 304 struct argbuf {
 305   /* These are the baseclass definitions.  */
 306   IADDR addr;
 307   const IDESC *idesc;
 308   char trace_p;
 309   char profile_p;
 310   /* ??? Temporary hack for skip insns.  */
 311   char skip_count;
 312   char unused;
 313   /* cpu specific data follows */
 314   union sem semantic;
 315   int written;
 316   union sem_fields fields;
 317 };
 318
 319 /* A cached insn.
 320
 321    ??? SCACHE used to contain more than just argbuf.  We could delete the
 322    type entirely and always just use ARGBUF, but for future concerns and as
 323    a level of abstraction it is left in.  */
 324
 325 struct scache {
 326   struct argbuf argbuf;
 327 };
 328
 329 /* Macros to simplify extraction, reading and semantic code.
 330    These define and assign the local vars that contain the insn's fields.  */
 331
 332 #define EXTRACT_IFMT_EMPTY_VARS \
 333   unsigned int length;
 334 #define EXTRACT_IFMT_EMPTY_CODE \
 335   length = 0; \
 336
 337 #define EXTRACT_IFMT_MULO_VARS \
 338   UINT f_opcode; \
 339   UINT f_srcdst; \
 340   UINT f_src2; \
 341   UINT f_m3; \
 342   UINT f_m2; \
 343   UINT f_m1; \
 344   UINT f_opcode2; \
 345   UINT f_zero; \
 346   UINT f_src1; \
 347   unsigned int length;
 348 #define EXTRACT_IFMT_MULO_CODE \
 349   length = 4; \
 350   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 351   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 352   f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 353   f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 354   f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 355   f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
 356   f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
 357   f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 358   f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 359
 360 #define EXTRACT_IFMT_MULO1_VARS \
 361   UINT f_opcode; \
 362   UINT f_srcdst; \
 363   UINT f_src2; \
 364   UINT f_m3; \
 365   UINT f_m2; \
 366   UINT f_m1; \
 367   UINT f_opcode2; \
 368   UINT f_zero; \
 369   UINT f_src1; \
 370   unsigned int length;
 371 #define EXTRACT_IFMT_MULO1_CODE \
 372   length = 4; \
 373   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 374   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 375   f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 376   f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 377   f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 378   f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
 379   f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
 380   f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 381   f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 382
 383 #define EXTRACT_IFMT_MULO2_VARS \
 384   UINT f_opcode; \
 385   UINT f_srcdst; \
 386   UINT f_src2; \
 387   UINT f_m3; \
 388   UINT f_m2; \
 389   UINT f_m1; \
 390   UINT f_opcode2; \
 391   UINT f_zero; \
 392   UINT f_src1; \
 393   unsigned int length;
 394 #define EXTRACT_IFMT_MULO2_CODE \
 395   length = 4; \
 396   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 397   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 398   f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 399   f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 400   f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 401   f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
 402   f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
 403   f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 404   f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 405
 406 #define EXTRACT_IFMT_MULO3_VARS \
 407   UINT f_opcode; \
 408   UINT f_srcdst; \
 409   UINT f_src2; \
 410   UINT f_m3; \
 411   UINT f_m2; \
 412   UINT f_m1; \
 413   UINT f_opcode2; \
 414   UINT f_zero; \
 415   UINT f_src1; \
 416   unsigned int length;
 417 #define EXTRACT_IFMT_MULO3_CODE \
 418   length = 4; \
 419   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 420   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 421   f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 422   f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 423   f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 424   f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
 425   f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
 426   f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 427   f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 428
 429 #define EXTRACT_IFMT_LDA_OFFSET_VARS \
 430   UINT f_opcode; \
 431   UINT f_srcdst; \
 432   UINT f_abase; \
 433   UINT f_modea; \
 434   UINT f_zeroa; \
 435   UINT f_offset; \
 436   unsigned int length;
 437 #define EXTRACT_IFMT_LDA_OFFSET_CODE \
 438   length = 4; \
 439   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 440   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 441   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 442   f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 443   f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 444   f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
 445
 446 #define EXTRACT_IFMT_LDA_INDIRECT_VARS \
 447   UINT f_opcode; \
 448   UINT f_srcdst; \
 449   UINT f_abase; \
 450   UINT f_modeb; \
 451   UINT f_scale; \
 452   UINT f_zerob; \
 453   UINT f_index; \
 454   unsigned int length;
 455 #define EXTRACT_IFMT_LDA_INDIRECT_CODE \
 456   length = 4; \
 457   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 458   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 459   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 460   f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
 461   f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
 462   f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 463   f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 464
 465 #define EXTRACT_IFMT_LDA_DISP_VARS \
 466   UINT f_opcode; \
 467   UINT f_optdisp; \
 468   UINT f_srcdst; \
 469   UINT f_abase; \
 470   UINT f_modeb; \
 471   UINT f_scale; \
 472   UINT f_zerob; \
 473   UINT f_index; \
 474   /* Contents of trailing part of insn.  */ \
 475   UINT word_1; \
 476   unsigned int length;
 477 #define EXTRACT_IFMT_LDA_DISP_CODE \
 478   length = 8; \
 479   word_1 = GETIMEMUSI (current_cpu, pc + 4); \
 480   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 481   f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
 482   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 483   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 484   f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
 485   f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
 486   f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 487   f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 488
 489 #define EXTRACT_IFMT_ST_OFFSET_VARS \
 490   UINT f_opcode; \
 491   UINT f_srcdst; \
 492   UINT f_abase; \
 493   UINT f_modea; \
 494   UINT f_zeroa; \
 495   UINT f_offset; \
 496   unsigned int length;
 497 #define EXTRACT_IFMT_ST_OFFSET_CODE \
 498   length = 4; \
 499   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 500   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 501   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 502   f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 503   f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
 504   f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
 505
 506 #define EXTRACT_IFMT_ST_INDIRECT_VARS \
 507   UINT f_opcode; \
 508   UINT f_srcdst; \
 509   UINT f_abase; \
 510   UINT f_modeb; \
 511   UINT f_scale; \
 512   UINT f_zerob; \
 513   UINT f_index; \
 514   unsigned int length;
 515 #define EXTRACT_IFMT_ST_INDIRECT_CODE \
 516   length = 4; \
 517   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 518   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 519   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 520   f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
 521   f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
 522   f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 523   f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 524
 525 #define EXTRACT_IFMT_ST_DISP_VARS \
 526   UINT f_opcode; \
 527   UINT f_optdisp; \
 528   UINT f_srcdst; \
 529   UINT f_abase; \
 530   UINT f_modeb; \
 531   UINT f_scale; \
 532   UINT f_zerob; \
 533   UINT f_index; \
 534   /* Contents of trailing part of insn.  */ \
 535   UINT word_1; \
 536   unsigned int length;
 537 #define EXTRACT_IFMT_ST_DISP_CODE \
 538   length = 8; \
 539   word_1 = GETIMEMUSI (current_cpu, pc + 4); \
 540   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 541   f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
 542   f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 543   f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 544   f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
 545   f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
 546   f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
 547   f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
 548
 549 #define EXTRACT_IFMT_CMPOBE_REG_VARS \
 550   UINT f_opcode; \
 551   UINT f_br_src1; \
 552   UINT f_br_src2; \
 553   UINT f_br_m1; \
 554   SI f_br_disp; \
 555   UINT f_br_zero; \
 556   unsigned int length;
 557 #define EXTRACT_IFMT_CMPOBE_REG_CODE \
 558   length = 4; \
 559   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 560   f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 561   f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 562   f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 563   f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
 564   f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
 565
 566 #define EXTRACT_IFMT_CMPOBE_LIT_VARS \
 567   UINT f_opcode; \
 568   UINT f_br_src1; \
 569   UINT f_br_src2; \
 570   UINT f_br_m1; \
 571   SI f_br_disp; \
 572   UINT f_br_zero; \
 573   unsigned int length;
 574 #define EXTRACT_IFMT_CMPOBE_LIT_CODE \
 575   length = 4; \
 576   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 577   f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
 578   f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
 579   f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
 580   f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
 581   f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
 582
 583 #define EXTRACT_IFMT_BNO_VARS \
 584   UINT f_opcode; \
 585   SI f_ctrl_disp; \
 586   UINT f_ctrl_zero; \
 587   unsigned int length;
 588 #define EXTRACT_IFMT_BNO_CODE \
 589   length = 4; \
 590   f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
 591   f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); \
 592   f_ctrl_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
 593
 594 /* Collection of various things for the trace handler to use.  */
 595
 596 typedef struct trace_record {
 597   IADDR pc;
 598   /* FIXME:wip */
 599 } TRACE_RECORD;
 600
 601 #endif /* CPU_I960BASE_H */