2ffe48de1bdd97dc6783fddbaeac0bc966df7522
[deliverable/binutils-gdb.git] / sim / lm32 / lm32.c
1 /* Lattice Mico32 simulator support code.
2 Contributed by Jon Beniston <jon@beniston.com>
3
4 Copyright (C) 2009-2021 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 /* This must come before any other includes. */
22 #include "defs.h"
23
24 #define WANT_CPU lm32bf
25 #define WANT_CPU_LM32BF
26
27 #include "sim-main.h"
28 #include "cgen-mem.h"
29 #include "cgen-ops.h"
30
31 /* The contents of BUF are in target byte order. */
32
33 int
34 lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
35 int len)
36 {
37 if (rn < 32)
38 SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn));
39 else
40 switch (rn)
41 {
42 case SIM_LM32_PC_REGNUM:
43 SETTSI (buf, lm32bf_h_pc_get (current_cpu));
44 break;
45 default:
46 return 0;
47 }
48
49 return -1;
50 }
51
52 /* The contents of BUF are in target byte order. */
53
54 int
55 lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
56 int len)
57 {
58 if (rn < 32)
59 lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf));
60 else
61 switch (rn)
62 {
63 case SIM_LM32_PC_REGNUM:
64 lm32bf_h_pc_set (current_cpu, GETTSI (buf));
65 break;
66 default:
67 return 0;
68 }
69
70 return -1;
71 }
72
73
74
75 #if WITH_PROFILE_MODEL_P
76
77 /* Initialize cycle counting for an insn.
78 FIRST_P is non-zero if this is the first insn in a set of parallel
79 insns. */
80
81 void
82 lm32bf_model_insn_before (SIM_CPU * cpu, int first_p)
83 {
84 }
85
86 /* Record the cycles computed for an insn.
87 LAST_P is non-zero if this is the last insn in a set of parallel insns,
88 and we update the total cycle count.
89 CYCLES is the cycle count of the insn. */
90
91 void
92 lm32bf_model_insn_after (SIM_CPU * cpu, int last_p, int cycles)
93 {
94 }
95
96 int
97 lm32bf_model_lm32_u_exec (SIM_CPU * cpu, const IDESC * idesc,
98 int unit_num, int referenced)
99 {
100 return idesc->timing->units[unit_num].done;
101 }
102
103 #endif /* WITH_PROFILE_MODEL_P */
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