sim/m32r/m32r.c

   1 /* m32r simulator support code
   2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #define WANT_CPU
  22 #define WANT_CPU_M32R
  23
  24 #include "sim-main.h"
  25 #include <signal.h>
  26 #include "libiberty.h"
  27 #include "bfd.h"
  28 /* FIXME: need to provide general mechanism for accessing target files
  29    these.  For now this is a hack to avoid getting the host version.  */
  30 #include "../../libgloss/m32r/sys/syscall.h"
  31 #include "targ-vals.h"
  32 \f
  33 /* The contents of BUF are in target byte order.  */
  34
  35 void
  36 m32r_fetch_register (sd, rn, buf)
  37      SIM_DESC sd;
  38      int rn;
  39      unsigned char *buf;
  40 {
  41   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
  42
  43   if (rn < 16)
  44     SETTWI (buf, GET_H_GR (rn));
  45   else if (rn < 21)
  46     SETTWI (buf, GET_H_CR (rn - 16));
  47   else switch (rn) {
  48     case PC_REGNUM:
  49       SETTWI (buf, GET_H_PC ());
  50       break;
  51     case ACCL_REGNUM:
  52       SETTWI (buf, GETLODI (GET_H_ACCUM ()));
  53       break;
  54     case ACCH_REGNUM:
  55       SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
  56       break;
  57 #if 0
  58     case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond;              break;
  59     case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm;                break;
  60     case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm;               break;
  61     case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie;                break;
  62     case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie;               break;
  63     case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry;            break; /* rename: bc */
  64     case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI));   break; /* duplicate */
  65 #endif
  66     default: abort ();
  67   }
  68 }
  69
  70 /* The contents of BUF are in target byte order.  */
  71
  72 void
  73 m32r_store_register (sd, rn, buf)
  74      SIM_DESC sd;
  75      int rn;
  76      unsigned char *buf;
  77 {
  78   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
  79
  80   if (rn < 16)
  81     SET_H_GR (rn, GETTWI (buf));
  82   else if (rn < 21)
  83     SET_H_CR (rn - 16, GETTWI (buf));
  84   else switch (rn) {
  85     case PC_REGNUM:
  86       SET_H_PC (GETTWI (buf));
  87       break;
  88     case ACCL_REGNUM:
  89       SETLODI (CPU (h_accum), GETTWI (buf));
  90       break;
  91     case ACCH_REGNUM:
  92       SETHIDI (CPU (h_accum), GETTWI (buf));
  93       break;
  94 #if 0
  95     case 23: STATE_CPU_CPU (sd, 0)->h_cond   = *reg;                    break;
  96     case 24: STATE_CPU_CPU (sd, 0)->h_sm     = *reg;                    break;
  97     case 25: STATE_CPU_CPU (sd, 0)->h_bsm    = *reg;                    break;
  98     case 26: STATE_CPU_CPU (sd, 0)->h_ie     = *reg;                    break;
  99     case 27: STATE_CPU_CPU (sd, 0)->h_bie    = *reg;                    break;
 100     case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg;                    break; /* rename: bc */
 101     case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI));   break; /* duplicate */
 102 #endif
 103   }
 104 }
 105 \f
 106 /* Handling the MSPR register is done by creating a device in the core
 107    mapping that winds up here.  */
 108
 109 device m32r_mspr_device;
 110
 111 int
 112 device_io_read_buffer (device *me, const void *source, int space,
 113                         address_word addr, unsigned nr_bytes,
 114                         SIM_CPU *cpu, sim_cia cia)
 115 {
 116   abort ();
 117 }
 118
 119 int
 120 device_io_write_buffer (device *me, const void *source, int space,
 121                         address_word addr, unsigned nr_bytes,
 122                         SIM_CPU *cpu, sim_cia cia)
 123 {
 124 #if WITH_SCACHE
 125   if (addr == MSPR_ADDR
 126       && (*(char *) source & 1) != 0)
 127     scache_flush (CPU_STATE (cpu));
 128 #endif
 129   return nr_bytes;
 130 }
 131
 132 void device_error () {}
 133 \f
 134 #if WITH_PROFILE_MODEL_P
 135
 136 void
 137 m32r_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
 138 {
 139   if ((CPU_CGEN_PROFILE (cpu)->h_gr & abuf->h_gr_get) != 0)
 140     {
 141       PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2;
 142       if (TRACE_INSN_P (cpu))
 143         cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
 144     }
 145 }
 146
 147 void
 148 m32r_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
 149 {
 150 }
 151
 152 void
 153 m32r_model_mark_busy_reg (SIM_CPU *cpu, ARGBUF *abuf)
 154 {
 155   CPU_CGEN_PROFILE (cpu)->h_gr = abuf->h_gr_set;
 156 }
 157
 158 void
 159 m32r_model_mark_unbusy_reg (SIM_CPU *cpu, ARGBUF *abuf)
 160 {
 161   CPU_CGEN_PROFILE (cpu)->h_gr = 0;
 162 }
 163
 164 #endif /* WITH_PROFILE_MODEL_P */
 165
 166 USI
 167 m32r_h_cr_get (SIM_CPU *current_cpu, UINT cr)
 168 {
 169   /* FIXME: Create enums H_CR_FOO, etc.  */
 170   switch (cr)
 171     {
 172     case 0 : /* psw */
 173       return ((CPU (h_bsm) << 15)
 174               | (CPU (h_bie) << 14)
 175               | (CPU (h_bcond) << 8)
 176               | (CPU (h_sm) << 7)
 177               | (CPU (h_ie) << 6)
 178               | (CPU (h_cond) << 0));
 179     case 1 : /* condition bit */
 180       return CPU (h_cond);
 181     case 2 : /* interrupt stack pointer */
 182       if (! CPU (h_sm))
 183         return CPU (h_gr[15]);
 184       else
 185         return CPU (h_cr[2]);
 186     case 3 : /* user stack pointer */
 187       if (CPU (h_sm))
 188         return CPU (h_gr[15]);
 189       else
 190         return CPU (h_cr[3]);
 191     case 6 : /* backup pc */
 192       /* ??? We don't really support this yet.  */
 193     case 4 : /* unused */
 194     case 5 : /* unused */
 195       return CPU (h_cr[cr]);
 196     default :
 197       return 0;
 198     }
 199 }
 200
 201 void
 202 m32r_h_cr_set (SIM_CPU *current_cpu, UINT cr, USI newval)
 203 {
 204   /* FIXME: Create enums H_CR_FOO, etc.  */
 205   switch (cr)
 206     {
 207     case 0 : /* psw */
 208       {
 209         int old_sm = CPU (h_sm);
 210         CPU (h_bsm) = (newval & (1 << 15)) != 0;
 211         CPU (h_bie) = (newval & (1 << 14)) != 0;
 212         CPU (h_bcond) = (newval & (1 << 8)) != 0;
 213         CPU (h_sm) = (newval & (1 << 7)) != 0;
 214         CPU (h_ie) = (newval & (1 << 6)) != 0;
 215         CPU (h_cond) = (newval & (1 << 0)) != 0;
 216         /* When switching stack modes, update the registers.  */
 217         if (old_sm != CPU (h_sm))
 218           {
 219             if (old_sm)
 220               {
 221                 /* Switching user -> system.  */
 222                 CPU (h_cr[3]) = CPU (h_gr[15]);
 223                 CPU (h_gr[15]) = CPU (h_cr[2]);
 224               }
 225             else
 226               {
 227                 /* Switching system -> user.  */
 228                 CPU (h_cr[2]) = CPU (h_gr[15]);
 229                 CPU (h_gr[15]) = CPU (h_cr[3]);
 230               }
 231           }
 232         break;
 233       }
 234     case 1 : /* condition bit */
 235       CPU (h_cond) = (newval & 1) != 0;
 236       break;
 237     case 2 : /* interrupt stack pointer */
 238       if (! CPU (h_sm))
 239         CPU (h_gr[15]) = newval;
 240       else
 241         CPU (h_cr[2]) = newval;
 242       break;
 243     case 3 : /* user stack pointer */
 244       if (CPU (h_sm))
 245         CPU (h_gr[15]) = newval;
 246       else
 247         CPU (h_cr[3]) = newval;
 248       break;
 249     case 4 : /* unused */
 250     case 5 : /* unused */
 251     case 6 : /* backup pc */
 252       CPU (h_cr[cr]) = newval;
 253       break;
 254     default :
 255       /* ignore */
 256       break;
 257     }
 258 }