1 /* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation
2 Copyright 1999-2022 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
24 #include "sim-assert.h"
25 #include "sim-module.h"
26 #include "sim-options.h"
27 #include "sim-signal.h"
32 OPTION_CPU_RESET
= OPTION_START
,
39 static DECLARE_OPTION_HANDLER (cpu_option_handler
);
41 static const OPTION cpu_options
[] =
43 { {"cpu-reset", no_argument
, NULL
, OPTION_CPU_RESET
},
44 '\0', NULL
, "Reset the CPU",
47 { {"emulos", no_argument
, NULL
, OPTION_EMUL_OS
},
48 '\0', NULL
, "Emulate some OS system calls (read, write, ...)",
51 { {"cpu-config", required_argument
, NULL
, OPTION_CPU_CONFIG
},
52 '\0', NULL
, "Specify the initial CPU configuration register",
55 { {"bootstrap", no_argument
, NULL
, OPTION_CPU_BOOTSTRAP
},
56 '\0', NULL
, "Start the processing in bootstrap mode",
59 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
64 cpu_option_handler (SIM_DESC sd
, sim_cpu
*cpu
,
65 int opt
, char *arg
, int is_command
)
69 cpu
= STATE_CPU (sd
, 0);
72 case OPTION_CPU_RESET
:
77 cpu
->cpu_emul_syscall
= 1;
80 case OPTION_CPU_CONFIG
:
81 if (sscanf(arg
, "0x%x", &val
) == 1
82 || sscanf(arg
, "%d", &val
) == 1)
84 cpu
->cpu_config
= val
;
85 cpu
->cpu_use_local_config
= 1;
88 cpu
->cpu_use_local_config
= 0;
91 case OPTION_CPU_BOOTSTRAP
:
92 cpu
->cpu_start_mode
= "bootstrap";
104 cpu_call (sim_cpu
*cpu
, uint16 addr
)
107 cpu_set_pc (cpu
, addr
);
111 cpu_return (sim_cpu
*cpu
)
115 /* Set the stack pointer and re-compute the current frame. */
117 cpu_set_sp (sim_cpu
*cpu
, uint16 val
)
119 cpu
->cpu_regs
.sp
= val
;
123 cpu_get_reg (sim_cpu
*cpu
, uint8 reg
)
128 return cpu_get_x (cpu
);
131 return cpu_get_y (cpu
);
134 return cpu_get_sp (cpu
);
137 return cpu_get_pc (cpu
);
145 cpu_get_src_reg (sim_cpu
*cpu
, uint8 reg
)
150 return cpu_get_a (cpu
);
153 return cpu_get_b (cpu
);
156 return cpu_get_ccr (cpu
);
159 return cpu_get_tmp3 (cpu
);
162 return cpu_get_d (cpu
);
165 return cpu_get_x (cpu
);
168 return cpu_get_y (cpu
);
171 return cpu_get_sp (cpu
);
179 cpu_set_dst_reg (sim_cpu
*cpu
, uint8 reg
, uint16 val
)
184 cpu_set_a (cpu
, val
);
188 cpu_set_b (cpu
, val
);
192 cpu_set_ccr (cpu
, val
);
196 cpu_set_tmp2 (cpu
, val
);
200 cpu_set_d (cpu
, val
);
204 cpu_set_x (cpu
, val
);
208 cpu_set_y (cpu
, val
);
212 cpu_set_sp (cpu
, val
);
221 cpu_set_reg (sim_cpu
*cpu
, uint8 reg
, uint16 val
)
226 cpu_set_x (cpu
, val
);
230 cpu_set_y (cpu
, val
);
234 cpu_set_sp (cpu
, val
);
238 cpu_set_pc (cpu
, val
);
246 /* Returns the address of a 68HC12 indexed operand.
247 Pre and post modifications are handled on the source register. */
249 cpu_get_indexed_operand_addr (sim_cpu
*cpu
, int restricted
)
256 code
= cpu_fetch8 (cpu
);
258 /* n,r with 5-bit signed constant. */
259 if ((code
& 0x20) == 0)
261 reg
= (code
>> 6) & 3;
262 sval
= (code
& 0x1f);
266 addr
= cpu_get_reg (cpu
, reg
);
270 /* Auto pre/post increment/decrement. */
271 else if ((code
& 0xc0) != 0xc0)
273 reg
= (code
>> 6) & 3;
274 sval
= (code
& 0x0f);
283 addr
= cpu_get_reg (cpu
, reg
);
284 cpu_set_reg (cpu
, reg
, addr
+ sval
);
285 if ((code
& 0x10) == 0)
291 /* [n,r] 16-bits offset indexed indirect. */
292 else if ((code
& 0x07) == 3)
298 reg
= (code
>> 3) & 0x03;
299 addr
= cpu_get_reg (cpu
, reg
);
300 addr
+= cpu_fetch16 (cpu
);
301 addr
= memory_read16 (cpu
, addr
);
302 cpu_add_cycles (cpu
, 1);
304 else if ((code
& 0x4) == 0)
310 reg
= (code
>> 3) & 0x03;
311 addr
= cpu_get_reg (cpu
, reg
);
314 sval
= cpu_fetch16 (cpu
);
315 cpu_add_cycles (cpu
, 1);
319 sval
= cpu_fetch8 (cpu
);
322 cpu_add_cycles (cpu
, 1);
328 reg
= (code
>> 3) & 0x03;
329 addr
= cpu_get_reg (cpu
, reg
);
333 addr
+= cpu_get_a (cpu
);
336 addr
+= cpu_get_b (cpu
);
339 addr
+= cpu_get_d (cpu
);
343 addr
+= cpu_get_d (cpu
);
344 addr
= memory_read16 (cpu
, addr
);
345 cpu_add_cycles (cpu
, 1);
354 cpu_get_indexed_operand8 (sim_cpu
*cpu
, int restricted
)
358 addr
= cpu_get_indexed_operand_addr (cpu
, restricted
);
359 return memory_read8 (cpu
, addr
);
363 cpu_get_indexed_operand16 (sim_cpu
*cpu
, int restricted
)
367 addr
= cpu_get_indexed_operand_addr (cpu
, restricted
);
368 return memory_read16 (cpu
, addr
);
372 cpu_move8 (sim_cpu
*cpu
, uint8 code
)
380 src
= cpu_fetch8 (cpu
);
381 addr
= cpu_fetch16 (cpu
);
385 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
386 src
= cpu_fetch8 (cpu
);
390 addr
= cpu_fetch16 (cpu
);
391 src
= memory_read8 (cpu
, addr
);
392 addr
= cpu_fetch16 (cpu
);
396 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
397 src
= memory_read8 (cpu
, cpu_fetch16 (cpu
));
401 src
= cpu_get_indexed_operand8 (cpu
, 1);
402 addr
= cpu_fetch16 (cpu
);
406 src
= cpu_get_indexed_operand8 (cpu
, 1);
407 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
411 sim_engine_abort (CPU_STATE (cpu
), cpu
, 0,
412 "Invalid code 0x%0x -- internal error?", code
);
415 memory_write8 (cpu
, addr
, src
);
419 cpu_move16 (sim_cpu
*cpu
, uint8 code
)
427 src
= cpu_fetch16 (cpu
);
428 addr
= cpu_fetch16 (cpu
);
432 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
433 src
= cpu_fetch16 (cpu
);
437 addr
= cpu_fetch16 (cpu
);
438 src
= memory_read16 (cpu
, addr
);
439 addr
= cpu_fetch16 (cpu
);
443 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
444 src
= memory_read16 (cpu
, cpu_fetch16 (cpu
));
448 src
= cpu_get_indexed_operand16 (cpu
, 1);
449 addr
= cpu_fetch16 (cpu
);
453 src
= cpu_get_indexed_operand16 (cpu
, 1);
454 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
458 sim_engine_abort (CPU_STATE (cpu
), cpu
, 0,
459 "Invalid code 0x%0x -- internal error?", code
);
462 memory_write16 (cpu
, addr
, src
);
466 cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
468 sim_add_option_table (sd
, 0, cpu_options
);
470 memset (&cpu
->cpu_regs
, 0, sizeof(cpu
->cpu_regs
));
472 cpu
->cpu_absolute_cycle
= 0;
473 cpu
->cpu_current_cycle
= 0;
474 cpu
->cpu_emul_syscall
= 1;
475 cpu
->cpu_running
= 1;
476 cpu
->cpu_stop_on_interrupt
= 0;
477 cpu
->cpu_frequency
= 8 * 1000 * 1000;
478 cpu
->cpu_use_elf_start
= 0;
479 cpu
->cpu_elf_start
= 0;
480 cpu
->cpu_use_local_config
= 0;
484 cpu
->cpu_config
= M6811_NOSEC
| M6811_NOCOP
| M6811_ROMON
|
486 interrupts_initialize (sd
, cpu
);
488 cpu
->cpu_is_initialized
= 1;
493 /* Reinitialize the processor after a reset. */
495 cpu_reset (sim_cpu
*cpu
)
497 /* Initialize the config register.
498 It is only initialized at reset time. */
499 memset (cpu
->ios
, 0, sizeof (cpu
->ios
));
500 if (cpu
->cpu_configured_arch
->arch
== bfd_arch_m68hc11
)
501 cpu
->ios
[M6811_INIT
] = 0x1;
503 cpu
->ios
[M6811_INIT
] = 0;
505 /* Output compare registers set to 0xFFFF. */
506 cpu
->ios
[M6811_TOC1_H
] = 0xFF;
507 cpu
->ios
[M6811_TOC1_L
] = 0xFF;
508 cpu
->ios
[M6811_TOC2_H
] = 0xFF;
509 cpu
->ios
[M6811_TOC2_L
] = 0xFF;
510 cpu
->ios
[M6811_TOC3_H
] = 0xFF;
511 cpu
->ios
[M6811_TOC4_L
] = 0xFF;
512 cpu
->ios
[M6811_TOC5_H
] = 0xFF;
513 cpu
->ios
[M6811_TOC5_L
] = 0xFF;
515 /* Setup the processor registers. */
516 memset (&cpu
->cpu_regs
, 0, sizeof(cpu
->cpu_regs
));
517 cpu
->cpu_absolute_cycle
= 0;
518 cpu
->cpu_current_cycle
= 0;
519 cpu
->cpu_is_initialized
= 0;
521 /* Reset interrupts. */
522 interrupts_reset (&cpu
->cpu_interrupts
);
524 /* Reinitialize the CPU operating mode. */
525 cpu
->ios
[M6811_HPRIO
] = cpu
->cpu_mode
;
529 /* Reinitialize the processor after a reset. */
531 cpu_restart (sim_cpu
*cpu
)
535 /* Get CPU starting address depending on the CPU mode. */
536 if (cpu
->cpu_use_elf_start
== 0)
538 switch ((cpu
->ios
[M6811_HPRIO
]) & (M6811_SMOD
| M6811_MDA
))
543 addr
= memory_read16 (cpu
, 0xFFFE);
546 /* Expanded Multiplexed */
548 addr
= memory_read16 (cpu
, 0xFFFE);
551 /* Special Bootstrap */
557 case M6811_MDA
| M6811_SMOD
:
558 addr
= memory_read16 (cpu
, 0xFFFE);
564 addr
= cpu
->cpu_elf_start
;
567 /* Setup the processor registers. */
568 cpu
->cpu_insn_pc
= addr
;
569 cpu
->cpu_regs
.pc
= addr
;
570 cpu
->cpu_regs
.ccr
= M6811_X_BIT
| M6811_I_BIT
| M6811_S_BIT
;
571 cpu
->cpu_absolute_cycle
= 0;
572 cpu
->cpu_is_initialized
= 1;
573 cpu
->cpu_current_cycle
= 0;
575 cpu_call (cpu
, addr
);
581 print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
, int mode
)
585 if (val
& desc
->mask
)
586 sim_io_printf (sd
, "%s",
587 mode
== 0 ? desc
->short_name
: desc
->long_name
);
593 print_io_byte (SIM_DESC sd
, const char *name
, io_reg_desc
*desc
,
594 uint8 val
, uint16 addr
)
596 sim_io_printf (sd
, " %-9.9s @ 0x%04x 0x%02x ", name
, addr
, val
);
598 print_io_reg_desc (sd
, desc
, val
, 0);
602 print_io_word (SIM_DESC sd
, const char *name
, io_reg_desc
*desc
,
603 uint16 val
, uint16 addr
)
605 sim_io_printf (sd
, " %-9.9s @ 0x%04x 0x%04x ", name
, addr
, val
);
607 print_io_reg_desc (sd
, desc
, val
, 0);
611 cpu_ccr_update_tst8 (sim_cpu
*cpu
, uint8 val
)
613 cpu_set_ccr_V (cpu
, 0);
614 cpu_set_ccr_N (cpu
, val
& 0x80 ? 1 : 0);
615 cpu_set_ccr_Z (cpu
, val
== 0 ? 1 : 0);
620 cpu_fetch_relbranch (sim_cpu
*cpu
)
622 uint16 addr
= (uint16
) cpu_fetch8 (cpu
);
628 addr
+= cpu
->cpu_regs
.pc
;
633 cpu_fetch_relbranch16 (sim_cpu
*cpu
)
635 uint16 addr
= cpu_fetch16 (cpu
);
637 addr
+= cpu
->cpu_regs
.pc
;
641 /* Push all the CPU registers (when an interruption occurs). */
643 cpu_push_all (sim_cpu
*cpu
)
645 if (cpu
->cpu_configured_arch
->arch
== bfd_arch_m68hc11
)
647 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.pc
);
648 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.iy
);
649 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.ix
);
650 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.d
);
651 cpu_m68hc11_push_uint8 (cpu
, cpu
->cpu_regs
.ccr
);
655 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.pc
);
656 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.iy
);
657 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.ix
);
658 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.d
);
659 cpu_m68hc12_push_uint8 (cpu
, cpu
->cpu_regs
.ccr
);
663 /* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations. */
665 cpu_dbcc (sim_cpu
*cpu
)
672 code
= cpu_fetch8 (cpu
);
675 case 0x80: /* ibcc */
678 case 0x40: /* tbcc */
689 addr
= cpu_fetch8 (cpu
);
693 addr
+= cpu_get_pc (cpu
);
694 reg
= cpu_get_src_reg (cpu
, code
& 0x07);
697 /* Branch according to register value. */
698 if ((reg
!= 0 && (code
& 0x20)) || (reg
== 0 && !(code
& 0x20)))
700 cpu_set_pc (cpu
, addr
);
702 cpu_set_dst_reg (cpu
, code
& 0x07, reg
);
706 cpu_exg (sim_cpu
*cpu
, uint8 code
)
712 r1
= (code
>> 4) & 0x07;
716 src1
= cpu_get_src_reg (cpu
, r1
);
717 src2
= cpu_get_src_reg (cpu
, r2
);
718 if (r2
== 1 || r2
== 2)
721 cpu_set_dst_reg (cpu
, r2
, src1
);
722 cpu_set_dst_reg (cpu
, r1
, src2
);
726 src1
= cpu_get_src_reg (cpu
, r1
);
728 /* Sign extend the 8-bit registers (A, B, CCR). */
729 if ((r1
== 0 || r1
== 1 || r1
== 2) && (src1
& 0x80))
732 cpu_set_dst_reg (cpu
, r2
, src1
);
736 /* Handle special instructions. */
738 cpu_special (sim_cpu
*cpu
, enum M6811_Special special
)
746 ccr
= cpu_m68hc11_pop_uint8 (cpu
);
747 cpu_set_ccr (cpu
, ccr
);
748 cpu_set_d (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
749 cpu_set_x (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
750 cpu_set_y (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
751 cpu_set_pc (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
760 ccr
= cpu_m68hc12_pop_uint8 (cpu
);
761 cpu_set_ccr (cpu
, ccr
);
762 cpu_set_d (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
763 cpu_set_x (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
764 cpu_set_y (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
765 cpu_set_pc (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
771 /* In the ELF-start mode, we are in a special mode where
772 the WAI corresponds to an exit. */
773 if (cpu
->cpu_use_elf_start
)
775 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
776 sim_engine_halt (CPU_STATE (cpu
), cpu
,
777 NULL
, NULL_CIA
, sim_exited
,
781 /* SCz: not correct... */
786 interrupts_raise (&cpu
->cpu_interrupts
, M6811_INT_SWI
);
787 interrupts_process (&cpu
->cpu_interrupts
);
790 case M6811_EMUL_SYSCALL
:
792 if (cpu
->cpu_emul_syscall
)
794 uint8 op
= memory_read8 (cpu
,
795 cpu_get_pc (cpu
) - 1);
798 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
799 sim_engine_halt (CPU_STATE (cpu
), cpu
,
800 NULL
, NULL_CIA
, sim_exited
,
811 interrupts_raise (&cpu
->cpu_interrupts
, M6811_INT_ILLEGAL
);
812 interrupts_process (&cpu
->cpu_interrupts
);
820 sd
= CPU_STATE (cpu
);
822 /* Breakpoint instruction if we are under gdb. */
823 if (STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
)
826 sim_engine_halt (CPU_STATE (cpu
), cpu
,
827 0, cpu_get_pc (cpu
), sim_stopped
,
830 /* else this is a nop but not in test factory mode. */
836 int32 src1
= (int16
) cpu_get_d (cpu
);
837 int32 src2
= (int16
) cpu_get_x (cpu
);
841 cpu_set_ccr_C (cpu
, 1);
845 cpu_set_d (cpu
, src1
% src2
);
847 cpu_set_x (cpu
, src1
);
848 cpu_set_ccr_C (cpu
, 0);
849 cpu_set_ccr_Z (cpu
, src1
== 0);
850 cpu_set_ccr_N (cpu
, src1
& 0x8000);
851 cpu_set_ccr_V (cpu
, src1
>= 32768 || src1
< -32768);
858 uint32 src1
= (uint32
) cpu_get_x (cpu
);
859 uint32 src2
= (uint32
) (cpu_get_y (cpu
) << 16)
860 | (uint32
) (cpu_get_d (cpu
));
864 cpu_set_ccr_C (cpu
, 1);
868 cpu_set_ccr_C (cpu
, 0);
869 cpu_set_d (cpu
, src2
% src1
);
871 cpu_set_y (cpu
, src2
);
872 cpu_set_ccr_Z (cpu
, src2
== 0);
873 cpu_set_ccr_N (cpu
, (src2
& 0x8000) != 0);
874 cpu_set_ccr_V (cpu
, (src2
& 0xffff0000) != 0);
881 int32 src1
= (int16
) cpu_get_x (cpu
);
882 int32 src2
= (uint32
) (cpu_get_y (cpu
) << 16)
883 | (uint32
) (cpu_get_d (cpu
));
887 cpu_set_ccr_C (cpu
, 1);
891 cpu_set_ccr_C (cpu
, 0);
892 cpu_set_d (cpu
, src2
% src1
);
894 cpu_set_y (cpu
, src2
);
895 cpu_set_ccr_Z (cpu
, src2
== 0);
896 cpu_set_ccr_N (cpu
, (src2
& 0x8000) != 0);
897 cpu_set_ccr_V (cpu
, src2
> 32767 || src2
< -32768);
906 src1
= (int16
) cpu_get_d (cpu
);
907 src2
= (int16
) cpu_get_y (cpu
);
909 cpu_set_d (cpu
, src1
& 0x0ffff);
910 cpu_set_y (cpu
, src1
>> 16);
911 cpu_set_ccr_Z (cpu
, src1
== 0);
912 cpu_set_ccr_N (cpu
, (src1
& 0x80000000) != 0);
913 cpu_set_ccr_C (cpu
, (src1
& 0x00008000) != 0);
922 addr
= cpu_fetch16 (cpu
);
923 src1
= (int16
) memory_read16 (cpu
, cpu_get_x (cpu
));
924 src2
= (int16
) memory_read16 (cpu
, cpu_get_y (cpu
));
926 src2
= (((uint32
) memory_read16 (cpu
, addr
)) << 16)
927 | (uint32
) memory_read16 (cpu
, addr
+ 2);
929 memory_write16 (cpu
, addr
, (src1
+ src2
) >> 16);
930 memory_write16 (cpu
, addr
+ 2, (src1
+ src2
));
941 addr
= cpu_fetch16 (cpu
);
942 page
= cpu_fetch8 (cpu
);
944 cpu_m68hc12_push_uint16 (cpu
, cpu_get_pc (cpu
));
945 cpu_m68hc12_push_uint8 (cpu
, cpu_get_page (cpu
));
947 cpu_set_page (cpu
, page
);
948 cpu_set_pc (cpu
, addr
);
952 case M6812_CALL_INDIRECT
:
958 code
= memory_read8 (cpu
, cpu_get_pc (cpu
));
959 /* Indirect addressing call has the page specified in the
960 memory location pointed to by the address. */
961 if ((code
& 0xE3) == 0xE3)
963 addr
= cpu_get_indexed_operand_addr (cpu
, 0);
964 page
= memory_read8 (cpu
, addr
+ 2);
965 addr
= memory_read16 (cpu
, addr
);
969 /* Otherwise, page is in the opcode. */
970 addr
= cpu_get_indexed_operand16 (cpu
, 0);
971 page
= cpu_fetch8 (cpu
);
973 cpu_m68hc12_push_uint16 (cpu
, cpu_get_pc (cpu
));
974 cpu_m68hc12_push_uint8 (cpu
, cpu_get_page (cpu
));
975 cpu_set_page (cpu
, page
);
976 cpu_set_pc (cpu
, addr
);
982 uint8 page
= cpu_m68hc12_pop_uint8 (cpu
);
983 uint16 addr
= cpu_m68hc12_pop_uint16 (cpu
);
985 cpu_set_page (cpu
, page
);
986 cpu_set_pc (cpu
, addr
);
992 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
,
993 cpu_get_pc (cpu
), sim_stopped
,
1001 cpu_single_step (sim_cpu
*cpu
)
1003 cpu
->cpu_current_cycle
= 0;
1004 cpu
->cpu_insn_pc
= cpu_get_pc (cpu
);
1006 /* Handle the pending interrupts. If an interrupt is handled,
1007 treat this as an single step. */
1008 if (interrupts_process (&cpu
->cpu_interrupts
))
1010 cpu
->cpu_absolute_cycle
+= cpu
->cpu_current_cycle
;
1014 /* printf("PC = 0x%04x\n", cpu_get_pc (cpu));*/
1015 cpu
->cpu_interpretor (cpu
);
1016 cpu
->cpu_absolute_cycle
+= cpu
->cpu_current_cycle
;
1021 sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
1022 uint16 addr
, const char *message
, ...)
1027 va_start (args
, message
);
1028 vsprintf (buf
, message
, args
);
1031 sim_io_printf (CPU_STATE (cpu
), "%s\n", buf
);
1032 cpu_memory_exception (cpu
, excep
, addr
, buf
);
1037 cpu_memory_exception (sim_cpu
*cpu
, SIM_SIGNAL excep
,
1038 uint16 addr
, const char *message
)
1040 if (cpu
->cpu_running
== 0)
1043 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
1044 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
,
1045 cpu_get_pc (cpu
), sim_stopped
, excep
);
1048 cpu
->mem_exception
= excep
;
1049 cpu
->fault_addr
= addr
;
1050 cpu
->fault_msg
= strdup (message
);
1052 if (cpu
->cpu_use_handler
)
1054 longjmp (&cpu
->cpu_exception_handler
, 1);
1056 (* cpu
->callback
->printf_filtered
)
1057 (cpu
->callback
, "Fault at 0x%04x: %s\n", addr
, message
);
1062 cpu_info (SIM_DESC sd
, sim_cpu
*cpu
)
1064 sim_io_printf (sd
, "CPU info:\n");
1065 sim_io_printf (sd
, " Absolute cycle: %s\n",
1066 cycle_to_string (cpu
, cpu
->cpu_absolute_cycle
,
1067 PRINT_TIME
| PRINT_CYCLE
));
1069 sim_io_printf (sd
, " Syscall emulation: %s\n",
1070 cpu
->cpu_emul_syscall
? "yes, via 0xcd <n>" : "no");
1071 sim_io_printf (sd
, " Memory errors detection: %s\n",
1072 cpu
->cpu_check_memory
? "yes" : "no");
1073 sim_io_printf (sd
, " Stop on interrupt: %s\n",
1074 cpu
->cpu_stop_on_interrupt
? "yes" : "no");
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