sim/mips/micromips.igen

   1 // Simulator definition for the micromips ASE.
   2 // Copyright (C) 2005-2020 Free Software Foundation, Inc.
   3 // Contributed by Imagination Technologies, Ltd.
   4 // Written by Andrew Bennett <andrew.bennett@imgtec.com>
   5 //
   6 // This file is part of the MIPS sim.
   7 //
   8 // This program is free software; you can redistribute it and/or modify
   9 // it under the terms of the GNU General Public License as published by
  10 // the Free Software Foundation; either version 3 of the License, or
  11 // (at your option) any later version.
  12 //
  13 // This program is distributed in the hope that it will be useful,
  14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 // GNU General Public License for more details.
  17 //
  18 // You should have received a copy of the GNU General Public License
  19 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20
  21 :compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)
  22 :compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)
  23 :compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)
  24 :compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)
  25 :compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)
  26 :compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))
  27 :compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))
  28
  29 :compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))
  30 :compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))
  31 :compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))
  32 :compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))
  33 :compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)
  34 :compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)
  35
  36 :compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)
  37
  38 :compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)
  39 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
  40
  41 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
  42 *micromips32:
  43 *micromips64:
  44 *micromipsdsp:
  45 {
  46   instruction_word delay_insn;
  47   sim_events_slip (SD, 1);
  48   DSPC = CIA;
  49   CIA = nia;
  50   STATE |= simDELAYSLOT;
  51   ENGINE_ISSUE_PREFIX_HOOK();
  52   micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);
  53   STATE &= ~simDELAYSLOT;
  54   return target;
  55 }
  56
  57 :function:::address_word:process_isa_mode:address_word target
  58 *micromips32:
  59 *micromips64:
  60 {
  61   SD->isa_mode = target & 0x1;
  62   return (target & (-(1 << 1)));
  63 }
  64
  65 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
  66 *micromips32:
  67 *micromips64:
  68 {
  69   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  70   return (process_isa_mode (SD_,
  71         delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
  72 }
  73
  74 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
  75 *micromips32:
  76 *micromips64:
  77 {
  78   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  79   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
  80 }
  81
  82
  83 :function:::unsigned32:compute_movep_src_reg:int reg
  84 *micromips32:
  85 *micromips64:
  86 {
  87   switch(reg)
  88     {
  89     case 0: return 0;
  90     case 1: return 17;
  91     case 2: return 2;
  92     case 3: return 3;
  93     case 4: return 16;
  94     case 5: return 18;
  95     case 6: return 19;
  96     case 7: return 20;
  97     default: return 0;
  98     }
  99 }
 100
 101 :function:::unsigned32:compute_andi16_imm:int encoded_imm
 102 *micromips32:
 103 *micromips64:
 104 {
 105   switch (encoded_imm)
 106     {
 107     case 0: return 128;
 108     case 1: return 1;
 109     case 2: return 2;
 110     case 3: return 3;
 111     case 4: return 4;
 112     case 5: return 7;
 113     case 6: return 8;
 114     case 7: return 15;
 115     case 8: return 16;
 116     case 9: return 31;
 117     case 10: return 32;
 118     case 11: return 63;
 119     case 12: return 64;
 120     case 13: return 255;
 121     case 14: return 32768;
 122     case 15: return 65535;
 123     default: return 0;
 124     }
 125 }
 126
 127 :function:::FP_formats:convert_fmt_micromips:int fmt
 128 *micromips32:
 129 *micromips64:
 130 {
 131   switch (fmt)
 132     {
 133     case 0: return fmt_single;
 134     case 1: return fmt_double;
 135     case 2: return fmt_ps;
 136     default: return fmt_unknown;
 137     }
 138 }
 139
 140 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
 141 *micromips32:
 142 *micromips64:
 143 {
 144   switch (fmt)
 145     {
 146     case 0: return fmt_single;
 147     case 1: return fmt_word;
 148     case 2: return fmt_long;
 149     default: return fmt_unknown;
 150     }
 151 }
 152
 153
 154 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
 155 *micromips32:
 156 *micromips64:
 157 {
 158   switch (fmt)
 159     {
 160     case 0: return fmt_double;
 161     case 1: return fmt_word;
 162     case 2: return fmt_long;
 163     default: return fmt_unknown;
 164     }
 165 }
 166
 167
 168 011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP
 169 "addiur1sp r<TRD>, <IMMEDIATE>"
 170 *micromips32:
 171 *micromips64:
 172 {
 173   do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);
 174 }
 175
 176
 177 011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2
 178 "addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"
 179 *micromips32:
 180 *micromips64:
 181 {
 182   do_addiu (SD_, TRS, TRD, IMM_DEC1);
 183 }
 184
 185
 186 010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5
 187 "addius5 r<RD>, <IMM_DEC2>"
 188 *micromips32:
 189 *micromips64:
 190 {
 191   do_addiu (SD_, RD, RD, IMM_DEC2);
 192 }
 193
 194
 195 010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP
 196 "addiusp <IMM_DEC3>"
 197 *micromips32:
 198 *micromips64:
 199 {
 200   do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);
 201 }
 202
 203
 204 000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16
 205 "addu16 r<TRD>, r<TRS>, r<TRT>"
 206 *micromips32:
 207 *micromips64:
 208 {
 209   do_addu (SD_, TRS, TRT, TRD);
 210 }
 211
 212
 213 001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16
 214 "andi16 r<TRD>, r<TRS>, <IMM_DEC4>"
 215 *micromips32:
 216 *micromips64:
 217 {
 218   do_andi (SD_, TRS, TRD, IMM_DEC4);
 219 }
 220
 221
 222 010001,0010,3.RT,3.RS:POOL16C:16::AND16
 223 "and16 r<TRT>, r<TRS>"
 224 *micromips32:
 225 *micromips64:
 226 {
 227   do_and (SD_, TRS, TRT, TRT);
 228 }
 229
 230
 231 110011,10.IMMEDIATE:MICROMIPS:16::B16
 232 "b16 <IMMEDIATE>"
 233 *micromips32:
 234 *micromips64:
 235 {
 236   NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),
 237                                   NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 238 }
 239
 240
 241 100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16
 242 "beqz16 r<TRS>, <IMMEDIATE>"
 243 *micromips32:
 244 *micromips64:
 245 {
 246   if (GPR[TRS] == 0)
 247     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 248                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 249 }
 250
 251
 252 101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16
 253 "bnez16 r<TRS>, <IMMEDIATE>"
 254 *micromips32:
 255 *micromips64:
 256 {
 257   if (GPR[TRS] != 0)
 258     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 259                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 260 }
 261
 262
 263 010001,101000,4.CODE:POOL16C:16::BREAK16
 264 "break16 %#lx<CODE>"
 265 *micromips32:
 266 *micromips64:
 267 {
 268   do_break16 (SD_, instruction_0);
 269 }
 270
 271
 272 010001,01110,5.RS:POOL16C:16::JALR16
 273 "jalr16 r<RS>"
 274 *micromips32:
 275 *micromips64:
 276 {
 277   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
 278 }
 279
 280
 281 010001,01111,5.RS:POOL16C:16::JALRS16
 282 "jalrs16 r<RS>"
 283 *micromips32:
 284 *micromips64:
 285 {
 286   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
 287 }
 288
 289
 290 010001,01100,5.RS:POOL16C:16::JR16
 291 "jr16 r<RS>"
 292 *micromips32:
 293 *micromips64:
 294 {
 295   NIA = process_isa_mode (SD_,
 296         delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
 297 }
 298
 299
 300 010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP
 301 "jraddiusp <IMMEDIATE>"
 302 *micromips32:
 303 *micromips64:
 304 {
 305   address_word temp = RA;
 306   do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);
 307   NIA = process_isa_mode (SD_, temp);
 308 }
 309
 310
 311 010001,01101,5.RS:POOL16C:16::JRC
 312 "jrc r<RS>"
 313 *micromips32:
 314 *micromips64:
 315 {
 316   NIA = process_isa_mode (SD_, GPR[RS]);
 317 }
 318
 319
 320 000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16
 321 "lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"
 322 *micromips32:
 323 *micromips64:
 324 {
 325   /* LBU can have a negative offset.  As the offset argument to do_load is
 326      unsigned we need to do the address calcuation before the function call so
 327      that the load address has been correctly calculated */
 328
 329   GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
 330 }
 331
 332
 333 001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16
 334 "lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 335 *micromips32:
 336 *micromips64:
 337 {
 338   GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
 339 }
 340
 341
 342 111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16
 343 "li16 r<TRD>, <IMM_DEC6>"
 344 *micromips32:
 345 *micromips64:
 346 {
 347   GPR[TRD] = IMM_DEC6;
 348 }
 349
 350
 351 011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16
 352 "lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 353 *micromips32:
 354 *micromips64:
 355 {
 356   GPR[TRT] = EXTEND32 (
 357         do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));
 358 }
 359
 360 :%s::::LWMREGS:int lwmregs
 361 *micromips32:
 362 *micromips64:
 363 {
 364   if (lwmregs == 3)
 365     return "s0, s1, s2, s3, ra";
 366   else if (lwmregs == 2)
 367     return "s0, s1, s2, ra";
 368   else if (lwmregs == 1)
 369     return "s0, s1, ra";
 370   else if (lwmregs == 0)
 371     return "s0, ra";
 372   else
 373     return "";
 374 }
 375
 376 010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16
 377 "lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 378 *micromips32:
 379 *micromips64:
 380 {
 381   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 382   int reg_offset;
 383
 384   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 385     GPR[16 + reg_offset] = EXTEND32 (
 386         do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 387
 388   RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 389 }
 390
 391
 392 011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP
 393 "lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"
 394 *micromips32:
 395 *micromips64:
 396 {
 397   GPR[TRT] = EXTEND32 (
 398         do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));
 399 }
 400
 401
 402 010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP
 403 "lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 404 *micromips32:
 405 *micromips64:
 406 {
 407   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));
 408 }
 409
 410
 411 010001,10000,5.RD:POOL16C:16::MFHI16
 412 "mfhi16 r<RD>"
 413 *micromips32:
 414 *micromips64:
 415 {
 416   do_mfhi (SD_, RD);
 417 }
 418
 419
 420 010001,10010,5.RD:POOL16C:16::MFLO16
 421 "mflo16 r<RD>"
 422 *micromips32:
 423 *micromips64:
 424 {
 425   do_mflo (SD_, RD);
 426 }
 427
 428
 429 000011,5.RD,5.RS:MICROMIPS:16::MOVE16
 430 "nop":RD==0&&RS==0
 431 "move16 r<RD>, r<RS>"
 432 *micromips32:
 433 *micromips64:
 434 {
 435   GPR[RD] = GPR[RS];
 436 }
 437
 438
 439 :%s::::DESTREGS:int regs
 440 *micromips32:
 441 *micromips64:
 442 {
 443   switch (regs)
 444     {
 445     case 0: return "a1, a2,";
 446     case 1: return "a1, a3,";
 447     case 2: return "a2, a3,";
 448     case 3: return "a0, s5,";
 449     case 4: return "a0, s6,";
 450     case 5: return "a0, a1,";
 451     case 6: return "a0, a2,";
 452     case 7: return "a0, a3,";
 453     default: return "";
 454     }
 455 }
 456
 457 100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP
 458 "movep %s<DESTREGS> r<ERS>, r<ERT>"
 459 *micromips32:
 460 *micromips64:
 461 {
 462   int rd;
 463   int re;
 464   int dest = DESTREGS;
 465
 466   if (dest == 0 || dest == 1)
 467     rd = 5;
 468   else if (dest == 2)
 469     rd = 6;
 470   else
 471     rd = 4;
 472
 473   if (dest == 0 || dest == 6)
 474     re = 6;
 475   else if (dest == 1 || dest == 2 || dest == 7)
 476     re = 7;
 477   else if (dest == 3)
 478     re = 21;
 479   else if (dest == 4)
 480     re = 22;
 481   /* assume dest is 5 */
 482   else
 483     re = 5;
 484
 485   GPR[rd] = GPR[ERS];
 486   GPR[re] = GPR[ERT];
 487 }
 488
 489
 490 010001,0000,3.RT,3.RS:POOL16C:16::NOT16
 491 "not16 r<TRT>, r<TRS>"
 492 *micromips32:
 493 *micromips64:
 494 {
 495   do_nor (SD_, 0, TRS, TRT);
 496 }
 497
 498
 499 010001,0011,3.RT,3.RS:POOL16C:16::OR16
 500 "or16 r<TRT>, r<TRS>"
 501 *micromips32:
 502 *micromips64:
 503 {
 504   do_or (SD_, TRS, TRT, TRT);
 505 }
 506
 507
 508 100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16
 509 "sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"
 510 *micromips32:
 511 *micromips64:
 512 {
 513   do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);
 514 }
 515
 516
 517 010001,101100,4.CODE:POOL16C:16::SDBBP16
 518 "sdbbp16 %#lx<CODE>"
 519 *micromips32:
 520 *micromips64:
 521 {
 522   SignalException (DebugBreakPoint, instruction_0);
 523 }
 524
 525
 526 101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16
 527 "sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 528 *micromips32:
 529 *micromips64:
 530 {
 531   do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);
 532 }
 533
 534
 535 001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16
 536 "sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 537 *micromips32:
 538 *micromips64:
 539 {
 540   do_sll (SD_, TRT, TRD, SHIFT_DEC);
 541 }
 542
 543
 544 001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16
 545 "srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 546 *micromips32:
 547 *micromips64:
 548 {
 549   do_srl (SD_, TRT, TRD, SHIFT_DEC);
 550 }
 551
 552
 553 000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16
 554 "subu16 r<TRD>, r<TRS>, r<TRT>"
 555 *micromips32:
 556 *micromips64:
 557 {
 558   do_subu (SD_, TRS, TRT, TRD);
 559 }
 560
 561
 562 111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16
 563 "sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 564 *micromips32:
 565 *micromips64:
 566 {
 567   do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);
 568 }
 569
 570
 571 110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP
 572 "swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 573 *micromips32:
 574 *micromips64:
 575 {
 576   do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);
 577 }
 578
 579
 580 010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16
 581 "swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 582 *micromips32:
 583 *micromips64:
 584 {
 585   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 586   int reg_offset;
 587
 588   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 589     do_store (SD_, AccessLength_WORD, address, reg_offset * 4,
 590         GPR[16 + reg_offset]);
 591
 592   do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);
 593 }
 594
 595
 596 010001,0001,3.RT,3.RS:POOL16C:16::XOR16
 597 "xor16 r<TRT>, r<TRS>"
 598 *micromips32:
 599 *micromips64:
 600 {
 601   do_xor (SD_, TRS, TRT, TRT);
 602 }
 603
 604
 605 000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD
 606 "add r<RD>, r<RS>, r<RT>"
 607 *micromips32:
 608 *micromips64:
 609 {
 610   do_add (SD_, RS, RT, RD);
 611 }
 612
 613
 614 000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI
 615 "addi r<RT>, r<RS>, <IMMEDIATE>"
 616 *micromips32:
 617 *micromips64:
 618 {
 619   do_addi (SD_, RS, RT, IMMEDIATE);
 620 }
 621
 622
 623 001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU
 624 "li r<RT>, <IMMEDIATE>":RS==0
 625 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 626 *micromips32:
 627 *micromips64:
 628 {
 629   do_addiu (SD_, RS, RT, IMMEDIATE);
 630 }
 631
 632
 633 011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC
 634 "addiupc r<TRS>, <IMM_SHIFT_2BIT>"
 635 *micromips32:
 636 *micromips64:
 637 {
 638   GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));
 639 }
 640
 641
 642 000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU
 643 "addu r<RD>, r<RS>, r<RT>"
 644 *micromips32:
 645 *micromips64:
 646 {
 647   do_addu (SD_, RS, RT, RD);
 648 }
 649
 650
 651 000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND
 652 "and r<RD>, r<RS>, r<RT>"
 653 *micromips32:
 654 *micromips64:
 655 {
 656   do_and (SD_, RS, RT, RD);
 657 }
 658
 659
 660 110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI
 661 "andi r<RT>, r<RS>, <IMMEDIATE>"
 662 *micromips32:
 663 *micromips64:
 664 {
 665   do_andi (SD_, RS, RT, IMMEDIATE);
 666 }
 667
 668
 669 010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a
 670 "bc1%s<TF> <IMMEDIATE>":CC == 0
 671 "bc1%s<TF> <CC>, <IMMEDIATE>"
 672 *micromips32:
 673 *micromips64:
 674 {
 675   check_fpu (SD_);
 676   if (GETFCC(CC) == TF)
 677     {
 678       address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);
 679       NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 680     }
 681 }
 682
 683
 684 010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a
 685 "bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0
 686 "bc2%s<TF> <CC>, <IMMEDIATE>"
 687 *micromips32:
 688 *micromips64:
 689
 690
 691 100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ
 692 "b <IMMEDIATE>":RT == 0 && RS == 0
 693 "beq r<RS>, r<RT>, <IMMEDIATE>"
 694 *micromips32:
 695 *micromips64:
 696 {
 697   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 698   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 699     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 700                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 701 }
 702
 703 010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ
 704 "bgez r<RS>, <IMMEDIATE>"
 705 *micromips32:
 706 *micromips64:
 707 {
 708   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 709   if ((signed_word) GPR[RS] >= 0)
 710     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 711                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 712 }
 713
 714
 715 010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC
 716 "beqzc r<RS>, <IMMEDIATE>"
 717 *micromips32:
 718 *micromips64:
 719 {
 720   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 721   if (GPR[RS] == 0)
 722     NIA = NIA + offset;
 723 }
 724
 725
 726 010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL
 727 "bal <IMMEDIATE>":RS == 0
 728 "bgezal r<RS>, <IMMEDIATE>"
 729 *micromips32:
 730 *micromips64:
 731 {
 732   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 733   if (RS == 31)
 734     Unpredictable ();
 735   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 736   if ((signed_word) GPR[RS] >= 0)
 737     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 738                                MICROMIPS_DELAYSLOT_SIZE_32);
 739 }
 740
 741
 742 010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ
 743 "bgtz r<RS>, <IMMEDIATE>"
 744 *micromips32:
 745 *micromips64:
 746 {
 747   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 748   if ((signed_word) GPR[RS] > 0)
 749     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 750                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 751 }
 752
 753
 754 010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS
 755 "bal <IMMEDIATE>":RS == 0
 756 "bgezals r<RS>, <IMMEDIATE>"
 757 *micromips32:
 758 *micromips64:
 759 {
 760   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 761   if (RS == 31)
 762     Unpredictable ();
 763   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 764   if ((signed_word) GPR[RS] >= 0)
 765     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 766                                MICROMIPS_DELAYSLOT_SIZE_16);
 767 }
 768
 769
 770 010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ
 771 "blez r<RS>, <IMMEDIATE>"
 772 *micromips32:
 773 *micromips64:
 774 {
 775   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 776   /* NOTE: The branch occurs AFTER the next instruction has been
 777      executed */
 778   if ((signed_word) GPR[RS] <= 0)
 779     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 780                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 781 }
 782
 783
 784 010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ
 785 "bltz r<RS>, <IMMEDIATE>"
 786 *micromips32:
 787 *micromips64:
 788 {
 789   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 790   if ((signed_word) GPR[RS] < 0)
 791     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 792                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 793 }
 794
 795
 796 010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL
 797 "bltzal r<RS>, <IMMEDIATE>"
 798 *micromips32:
 799 *micromips64:
 800 {
 801   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 802   if (RS == 31)
 803     Unpredictable ();
 804   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 805   /* NOTE: The branch occurs AFTER the next instruction has been
 806      executed */
 807   if ((signed_word) GPR[RS] < 0)
 808     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 809                                MICROMIPS_DELAYSLOT_SIZE_32);
 810 }
 811
 812 010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS
 813 "bltzals r<RS>, <IMMEDIATE>"
 814 *micromips32:
 815 *micromips64:
 816 {
 817   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 818   if (RS == 31)
 819     Unpredictable ();
 820   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 821   if ((signed_word) GPR[RS] < 0)
 822     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 823                                MICROMIPS_DELAYSLOT_SIZE_16);
 824 }
 825
 826
 827 101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE
 828 "bne r<RS>, r<RT>, <IMMEDIATE>"
 829 *micromips32:
 830 *micromips64:
 831 {
 832   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 833   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 834     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 835                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 836 }
 837
 838
 839 010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC
 840 "bnezc r<RS>, <IMMEDIATE>"
 841 *micromips32:
 842 *micromips64:
 843 {
 844   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 845   if ((signed_word) GPR[RS] != 0)
 846     NIA = NIA + offset;
 847 }
 848
 849
 850 000000,20.CODE,000111:POOL32A:32::BREAK
 851 "break %#lx<CODE>"
 852 *micromips32:
 853 *micromips64:
 854 {
 855   do_break (SD_, instruction_0);
 856 }
 857
 858
 859 001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE
 860 "cache <OP>, <IMMEDIATE>(r<BASE>)"
 861 *micromips32:
 862 *micromips64:
 863 {
 864   address_word base = GPR[BASE];
 865   address_word offset = EXTEND12 (IMMEDIATE);
 866   address_word vaddr = loadstore_ea (SD_, base, offset);
 867   address_word paddr = vaddr;
 868   CacheOp (OP, vaddr, paddr, instruction_0);
 869 }
 870
 871
 872 011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE
 873 "cachee <OP>, <IMMEDIATE>(r<BASE>)"
 874 *micromips32:
 875 *micromips64:
 876
 877
 878 010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1
 879 "cfc1 r<RT>, f<FS>"
 880 *micromips32:
 881 *micromips64:
 882 {
 883   do_cfc1 (SD_, RT, FS);
 884 }
 885
 886
 887 000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2
 888 "cfc2 r<RT>, <IMPL>"
 889 *micromips32:
 890 *micromips64:
 891
 892
 893 000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO
 894 "clo r<RT>, r<RS>"
 895 *micromips32:
 896 *micromips64:
 897 {
 898   do_clo (SD_, RT, RS);
 899 }
 900
 901
 902 000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ
 903 "clz r<RT>, r<RS>"
 904 *micromips32:
 905 *micromips64:
 906 {
 907   do_clz (SD_, RT, RS);
 908 }
 909
 910
 911 000000,23.COFUN,010:POOL32A:32::COP2
 912 "cop2 <COFUN>"
 913 *micromips32:
 914 *micromips64:
 915
 916
 917 010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1
 918 "ctc1 r<RT>, f<FS>"
 919 *micromips32:
 920 *micromips64:
 921 {
 922   do_ctc1 (SD_, RT, FS);
 923 }
 924
 925
 926 000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2
 927 "ctc2 r<RT>, <IMPL>"
 928 *micromips32:
 929 *micromips64:
 930
 931
 932 000000,00000000001110001101,111100:POOL32A:32::DERET
 933 "deret"
 934 *micromips32:
 935 *micromips64:
 936
 937
 938 000000,00000,5.RS,0100011101,111100:POOL32A:32::DI
 939 "di":RS == 0
 940 "di r<RS>"
 941 *micromips32:
 942 *micromips64:
 943 {
 944   do_di (SD_, RS);
 945 }
 946
 947 000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV
 948 "div r<RS>, r<RT>"
 949 *micromips32:
 950 *micromips64:
 951 {
 952   do_div (SD_, RS, RT);
 953 }
 954
 955
 956 000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU
 957 "divu r<RS>, r<RT>"
 958 *micromips32:
 959 *micromips64:
 960 {
 961   do_divu (SD_, RS, RT);
 962 }
 963
 964
 965 000000,00000000000001100000,000000:POOL32A:32::EHB
 966 "ehb"
 967 *micromips32:
 968 *micromips64:
 969
 970
 971 000000,00000,5.RS,0101011101,111100:POOL32A:32::EI
 972 "ei":RS == 0
 973 "ei r<RS>"
 974 *micromips32:
 975 *micromips64:
 976 {
 977   do_ei (SD_, RS);
 978 }
 979
 980 000000,00000000001111001101,111100:POOL32A:32::ERET
 981 "eret"
 982 *micromips32:
 983 *micromips64:
 984 {
 985   if (SR & status_ERL)
 986     {
 987       /* Oops, not yet available */
 988       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
 989       NIA = EPC;
 990       SR &= ~status_ERL;
 991     }
 992   else
 993     {
 994       NIA = EPC;
 995       SR &= ~status_EXL;
 996     }
 997 }
 998
 999
1000 000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT
1001 "ext r<RT>, r<RS>, <LSB>, <MSBD+1>"
1002 *micromips32:
1003 *micromips64:
1004 {
1005   do_ext (SD_, RT, RS, LSB, MSBD);
1006 }
1007
1008
1009 000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS
1010 "ins r<RT>, r<RS>, <LSB>, <MSBD-LSB+1>"
1011 *micromips32:
1012 *micromips64:
1013 {
1014   do_ins (SD_, RT, RS, LSB, MSBD);
1015 }
1016
1017
1018 110101,26.IMMEDIATE:MICROMIPS:32::J
1019 "j <IMM_SHIFT_1BIT>"
1020 *micromips32:
1021 *micromips64:
1022 {
1023   address_word region = (NIA & MASK (63, 27));
1024   NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA,
1025                              MICROMIPS_DELAYSLOT_SIZE_ANY);
1026 }
1027
1028
1029 111101,26.IMMEDIATE:MICROMIPS:32::JAL
1030 "jal <IMM_SHIFT_1BIT>"
1031 *micromips32:
1032 *micromips64:
1033 {
1034   /* NOTE: The region used is that of the delay slot and NOT the
1035      current instruction */
1036   address_word region = (NIA & MASK (63, 27));
1037   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1038                           MICROMIPS_DELAYSLOT_SIZE_32);
1039 }
1040
1041
1042 011101,26.IMMEDIATE:MICROMIPS:32::JALS
1043 "jals <IMM_SHIFT_1BIT>"
1044 *micromips32:
1045 *micromips64:
1046 {
1047   address_word region = (NIA & MASK (63, 27));
1048   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1049                           MICROMIPS_DELAYSLOT_SIZE_16);
1050 }
1051
1052 000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR
1053 "jalr r<RS>":RT == 31
1054 "jalr r<RT>, r<RS>"
1055 *micromips32:
1056 *micromips64:
1057 {
1058   if (RS == RT)
1059     Unpredictable ();
1060   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1061 }
1062
1063 000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS
1064 "jalrs r<RT>, r<RS>"
1065 *micromips32:
1066 *micromips64:
1067 {
1068   if (RS == RT)
1069     Unpredictable ();
1070   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1071 }
1072
1073
1074 111100,26.IMMEDIATE:MICROMIPS:32::JALX
1075 "jalx <IMM_SHIFT_2BIT>"
1076 *micromips32:
1077 *micromips64:
1078 {
1079   address_word region = (NIA & MASK (63, 26));
1080   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
1081                           NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1082   SD->isa_mode = ISA_MODE_MIPS32;
1083 }
1084
1085 000000,00000,5.RS,0000111100,111100:POOL32A:32::JR
1086 "jr r<RS>"
1087 *micromips32:
1088 *micromips64:
1089 {
1090   NIA = process_isa_mode (SD_,
1091                           delayslot_micromips (SD_, GPR[RS], NIA,
1092                                                MICROMIPS_DELAYSLOT_SIZE_32));
1093 }
1094
1095
1096 000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB
1097 "jalr.hb r<RT>, r<RS>"
1098 *micromips32:
1099 *micromips64:
1100 {
1101   if (RS == RT)
1102     Unpredictable ();
1103   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1104 }
1105
1106
1107 000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB
1108 "jalrs.hb r<RT>, r<RS>"
1109 *micromips32:
1110 *micromips64:
1111 {
1112   if (RS == RT)
1113     Unpredictable ();
1114   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1115 }
1116
1117
1118 000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB
1119 "jr.hb r<RS>"
1120 *micromips32:
1121 *micromips64:
1122 {
1123   NIA = process_isa_mode (SD_,
1124                           delayslot_micromips (SD_, GPR[RS], NIA,
1125                                                MICROMIPS_DELAYSLOT_SIZE_32));
1126 }
1127
1128
1129 000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB
1130 "lb r<RT>, <IMMEDIATE>(r<BASE>)"
1131 *micromips32:
1132 *micromips64:
1133 {
1134   do_lb (SD_, RT, IMMEDIATE, BASE);
1135 }
1136
1137
1138 011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE
1139 "lbe r<RT>, <IMMEDIATE>(r<BASE>)"
1140 *micromips32:
1141 *micromips64:
1142
1143
1144 000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU
1145 "lbu r<RT>, <IMMEDIATE>(r<BASE>)"
1146 *micromips32:
1147 *micromips64:
1148 {
1149   do_lbu (SD_, RT, IMMEDIATE, BASE);
1150 }
1151
1152
1153 011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE
1154 "lbue r<RT>, <IMMEDIATE>(r<BASE>)"
1155 *micromips32:
1156 *micromips64:
1157
1158
1159 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a
1160 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1161 *micromips32:
1162 {
1163   check_fpu (SD_);
1164   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE)));
1165 }
1166
1167
1168 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b
1169 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1170 *micromips64:
1171 {
1172   check_fpu (SD_);
1173   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
1174                           EXTEND16 (IMMEDIATE)));
1175 }
1176
1177
1178 001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2
1179 "ldc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1180 *micromips32:
1181 *micromips64:
1182
1183
1184 001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH
1185 "lh r<RT>, <IMMEDIATE>(r<BASE>)"
1186 *micromips32:
1187 *micromips64:
1188 {
1189   do_lh (SD_, RT, IMMEDIATE, BASE);
1190 }
1191
1192
1193 011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE
1194 "lhe r<RT>, <IMMEDIATE>(r<BASE>)"
1195 *micromips32:
1196 *micromips64:
1197
1198
1199 001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU
1200 "lhu r<RT>, <IMMEDIATE>(r<BASE>)"
1201 *micromips32:
1202 *micromips64:
1203 {
1204   do_lhu (SD_, RT, IMMEDIATE, BASE);
1205 }
1206
1207
1208 011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE
1209 "lhue r<RT>, <IMMEDIATE>(r<BASE>)"
1210 *micromips32:
1211 *micromips64:
1212
1213
1214 011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL
1215 "ll r<RT>, <IMMEDIATE>(r<BASE>)"
1216 *micromips32:
1217 *micromips64:
1218 {
1219   do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1220 }
1221
1222
1223 011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE
1224 "lle r<RT>, <IMMEDIATE>(r<BASE>)"
1225 *micromips32:
1226 *micromips64:
1227
1228
1229 010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI
1230 "lui r<RS>, <IMMEDIATE>"
1231 *micromips32:
1232 *micromips64:
1233 {
1234   do_lui (SD_, RS, IMMEDIATE);
1235 }
1236
1237
1238 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1
1239 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1240 *micromips32:
1241 {
1242   do_luxc1_32 (SD_, FD, INDEX, BASE);
1243 }
1244
1245
1246 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1
1247 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1248 *micromips64:
1249 {
1250   check_fpu (SD_);
1251   check_u64 (SD_, instruction_0);
1252   do_luxc1_64 (SD_, FD, INDEX, BASE);
1253 }
1254
1255
1256 111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW
1257 "lw r<RT>, <IMMEDIATE>(r<BASE>)"
1258 *micromips32:
1259 *micromips64:
1260 {
1261   do_lw (SD_, RT, IMMEDIATE, BASE);
1262 }
1263
1264
1265 100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1
1266 "lwc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1267 *micromips32:
1268 *micromips64:
1269 {
1270   do_lwc1 (SD_, FT, IMMEDIATE, BASE);
1271 }
1272
1273
1274 001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2
1275 "lwc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1276 *micromips32:
1277 *micromips64:
1278
1279
1280 011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE
1281 "lwe r<RT>, <IMMEDIATE>(r<BASE>)"
1282 *micromips32:
1283 *micromips64:
1284
1285
1286 011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE
1287 "lwee r<RT>, <IMMEDIATE>(r<BASE>)"
1288 *micromips32:
1289 *micromips64:
1290
1291
1292 011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL
1293 "lwl r<RT>, <IMMEDIATE>(r<BASE>)"
1294 *micromips32:
1295 *micromips64:
1296 {
1297   do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1298 }
1299
1300
1301 011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE
1302 "lwle r<RT>, <IMMEDIATE>(r<BASE>)"
1303 *micromips32:
1304 *micromips64:
1305
1306 :%s::::LWM32REGS:int lwmregs
1307 *micromips32:
1308 *micromips64:
1309 {
1310   if (lwmregs & 0x10)
1311     {
1312       switch(lwmregs & 0xf)
1313         {
1314         case 0:
1315           return "ra";
1316         case 1:
1317           return "s0, ra";
1318         case 2:
1319           return "s0, s1, ra";
1320         case 3:
1321           return "s0, s1, s2, ra";
1322         case 4:
1323           return "s0, s1, s2, s3, ra";
1324         case 5:
1325           return "s0, s1, s2, s3, s4, ra";
1326         case 6:
1327           return "s0, s1, s2, s3, s4, s5, ra";
1328         case 7:
1329           return "s0, s1, s2, s3, s4, s5, s6, ra";
1330         case 8:
1331           return "s0, s1, s2, s3, s4, s5, s6, s7, ra";
1332         case 9:
1333           return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra";
1334         default:
1335           return "";
1336         }
1337     }
1338   else
1339     {
1340       switch(lwmregs & 0xf)
1341         {
1342         case 1:
1343           return "s0";
1344         case 2:
1345           return "s0, s1";
1346         case 3:
1347           return "s0, s1, s2";
1348         case 4:
1349           return "s0, s1, s2, s3";
1350         case 5:
1351           return "s0, s1, s2, s3, s4";
1352         case 6:
1353           return "s0, s1, s2, s3, s4, s5";
1354         case 7:
1355           return "s0, s1, s2, s3, s4, s5, s6";
1356         case 8:
1357           return "s0, s1, s2, s3, s4, s5, s6, s7";
1358         case 9:
1359           return "s0, s1, s2, s3, s4, s5, s6, s7, s8";
1360         default:
1361           return "";
1362         }
1363     }
1364 }
1365
1366 001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32
1367 "lwm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
1368 *micromips32:
1369 *micromips64:
1370 {
1371   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
1372   int reg_offset;
1373   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
1374     {
1375       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
1376       GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1377                                     4 * reg_offset));
1378     }
1379
1380   if (LWM32REGS & 0x10)
1381     RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1382                             4 * reg_offset));
1383 }
1384
1385
1386 001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP
1387 "lwp r<RD>, <IMMEDIATE>(r<BASE>)"
1388 *micromips32:
1389 *micromips64:
1390 {
1391   if (BASE == RD || RD == 31)
1392     Unpredictable ();
1393   else
1394     {
1395       do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE);
1396       do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
1397     }
1398 }
1399
1400
1401 011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR
1402 "lwr r<RT>, <IMMEDIATE>(r<BASE>)"
1403 *micromips32:
1404 *micromips64:
1405 {
1406   do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1407 }
1408
1409
1410 011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU
1411 "lwu r<RT>, <IMMEDIATE>(r<BASE>)"
1412 *micromips32:
1413 *micromips64:
1414 {
1415   do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0);
1416 }
1417
1418
1419 010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1
1420 "lwxc1 f<FD>, <INDEX>(r<BASE>)"
1421 *micromips32:
1422 *micromips64:
1423 {
1424   do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
1425 }
1426
1427
1428 000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS
1429 "lwxs r<RD>, r<INDEX>(r<BASE>)"
1430 *micromips32:
1431 *micromips64:
1432 {
1433   GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE],
1434                                GPR[INDEX] * 4));
1435 }
1436
1437
1438 000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD
1439 "madd r<RS>, r<RT>"
1440 *micromips32:
1441 *micromips64:
1442 {
1443   do_madd (SD_, RS, RT);
1444 }
1445
1446
1447 000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU
1448 "maddu r<RS>, r<RT>"
1449 *micromips32:
1450 *micromips64:
1451 {
1452   do_maddu (SD_, RS, RT);
1453 }
1454
1455
1456 000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0
1457 "mfc0 r<RS>, r<RT>": SEL == 0
1458 "mfc0 r<RS>, r<RT>, <SEL>"
1459 *micromips32:
1460 *micromips64:
1461 {
1462   DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL);
1463 }
1464
1465
1466 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
1467 "mfc1 r<RT>, f<FS>"
1468 *micromips32:
1469 *micromips64:
1470 {
1471   do_mfc1b (SD_, RT, FS);
1472 }
1473
1474
1475 000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2
1476 "mfc2 r<RT>, <IMPL>"
1477 *micromips32:
1478 *micromips64:
1479
1480
1481 010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1
1482 "mfhc1 r<RT>, f<FS>"
1483 *micromips32:
1484 *micromips64:
1485 {
1486   do_mfhc1 (SD_, RT, FS);
1487 }
1488
1489
1490 000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2
1491 "mfhc2 r<RT>, <IMPL>"
1492 *micromips32:
1493 *micromips64:
1494
1495
1496 000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI
1497 "mfhi r<RS>"
1498 *micromips32:
1499 *micromips64:
1500 {
1501   do_mfhi (SD_, RS);
1502 }
1503
1504
1505 000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO
1506 "mflo r<RS>"
1507 *micromips32:
1508 *micromips64:
1509 {
1510   do_mflo (SD_, RS);
1511 }
1512
1513
1514 // MOVF
1515 // MOVT
1516 010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf
1517 "mov%s<TF> r<RT>, r<RS>, CC"
1518 *micromips32:
1519 *micromips64:
1520 {
1521   do_movtf (SD_, TF, RT, RS, CC);
1522 }
1523
1524
1525 000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN
1526 "movn r<RD>, r<RS>, r<RT>"
1527 *micromips32:
1528 *micromips64:
1529 {
1530   do_movn (SD_, RD, RS, RT);
1531 }
1532
1533
1534 000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ
1535 "movz r<RD>, r<RS>, r<RT>"
1536 *micromips32:
1537 *micromips64:
1538 {
1539   do_movz (SD_, RD, RS, RT);
1540 }
1541
1542
1543 000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB
1544 "msub r<RS>, r<RT>"
1545 *micromips32:
1546 *micromips64:
1547 {
1548   do_msub (SD_, RS, RT);
1549 }
1550
1551
1552 000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU
1553 "msubu r<RS>, r<RT>"
1554 *micromips32:
1555 *micromips64:
1556 {
1557   do_msubu (SD_, RS, RT);
1558 }
1559
1560
1561 000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0
1562 "mtc0 r<RS>, r<RT>": SEL == 0
1563 "mtc0 r<RS>, r<RT>, <SEL>"
1564 *micromips32:
1565 *micromips64:
1566 {
1567   DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL);
1568 }
1569
1570
1571 010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1
1572 "mtc1 r<RT>, f<FS>"
1573 *micromips32:
1574 *micromips64:
1575 {
1576   do_mtc1b (SD_, RT, FS);
1577 }
1578
1579
1580 000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2
1581 "mtc2 r<RT>, <IMPL>"
1582 *micromips32:
1583 *micromips64:
1584
1585
1586 010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1
1587 "mthc1 r<RT>, f<FS>"
1588 *micromips32:
1589 *micromips64:
1590 {
1591   do_mthc1 (SD_, RT, FS);
1592 }
1593
1594
1595 000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2
1596 "mthc2 r<RT>, <IMPL>"
1597 *micromips32:
1598 *micromips64:
1599
1600
1601 000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI
1602 "mthi r<RS>"
1603 *micromips32:
1604 *micromips64:
1605 {
1606   do_mthi (SD_, RS);
1607 }
1608
1609
1610 000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO
1611 "mtlo r<RS>"
1612 *micromips32:
1613 *micromips64:
1614 {
1615   do_mtlo (SD_, RS);
1616 }
1617
1618
1619 000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL
1620 "mul r<RD>, r<RS>, r<RT>"
1621 *micromips32:
1622 *micromips64:
1623 {
1624   do_mul (SD_, RD, RS, RT);
1625 }
1626
1627
1628 000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT
1629 "mult r<RS>, r<RT>"
1630 *micromips32:
1631 *micromips64:
1632 {
1633   do_mult (SD_, RS, RT, 0);
1634 }
1635
1636
1637 000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU
1638 "multu r<RS> r<RT>"
1639 *micromips32:
1640 *micromips64:
1641 {
1642   do_multu (SD_, RS, RT, 0);
1643 }
1644
1645
1646 000000,00000000000000000000,000000:POOL32A:32::NOP
1647 "nop"
1648 *micromips32:
1649 *micromips64:
1650 {
1651 }
1652
1653
1654 000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR
1655 "nor r<RD>, r<RS>, r<RT>"
1656 *micromips32:
1657 *micromips64:
1658 {
1659   do_nor (SD_, RS, RT, RD);
1660 }
1661
1662
1663 000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR
1664 "or r<RD>, r<RS>, r<RT>"
1665 *micromips32:
1666 *micromips64:
1667 {
1668   do_or (SD_, RS, RT, RD);
1669 }
1670
1671
1672 010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI
1673 "ori r<RT>, r<RS>, <IMMEDIATE>"
1674 *micromips32:
1675 *micromips64:
1676 {
1677   do_ori (SD_, RS, RT, IMMEDIATE);
1678 }
1679
1680
1681 000000,00000000000010100000,000000:POOL32A:32::PAUSE
1682 "pause"
1683 *micromips32:
1684 *micromips64:
1685
1686
1687 011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF
1688 "pref <HINT>, <IMMEDIATE>(r<BASE>)"
1689 *micromips32:
1690 *micromips64:
1691 {
1692   do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE);
1693 }
1694
1695
1696 011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE
1697 "prefe <HINT>, <IMMEDIATE>(r<BASE>)"
1698 *micromips32:
1699 *micromips64:
1700
1701
1702 010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX
1703 "prefx <HINT>, r<INDEX>(r<BASE>)"
1704 *micromips32:
1705 *micromips64:
1706 {
1707   do_prefx (SD_, HINT, INDEX, BASE);
1708 }
1709
1710 000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR
1711 "rdhwr r<RS>, r<RT>"
1712 *micromips32:
1713 *micromips64:
1714 {
1715   do_rdhwr (SD_, RT, RS);
1716 }
1717
1718 000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR
1719 "rdpgpr r<RS>, r<RT>"
1720 *micromips32:
1721 *micromips64:
1722
1723
1724 000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR
1725 "rotr r<RT>, r<RS>, <SHIFT>"
1726 *micromips32:
1727 *micromips64:
1728 {
1729   GPR[RT] = do_ror (SD_, GPR[RS], SHIFT);
1730 }
1731
1732
1733 000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV
1734 "rotrv r<RD>, r<RT>, r<RS>"
1735 *micromips32:
1736 *micromips64:
1737 {
1738   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
1739 }
1740
1741
1742 000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB
1743 "sb r<RT>, <IMMEDIATE>(r<BASE>)"
1744 *micromips32:
1745 *micromips64:
1746 {
1747   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1748 }
1749
1750
1751 011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE
1752 "sbe r<RT>, <IMMEDIATE>(r<BASE>)"
1753 *micromips32:
1754 *micromips64:
1755
1756
1757 011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC
1758 "sc r<RT>, <IMMEDIATE>(r<BASE>)"
1759 *micromips32:
1760 *micromips64:
1761 {
1762   do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0);
1763 }
1764
1765
1766 011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE
1767 "sce r<RT>, <IMMEDIATE>(r<BASE>)"
1768 *micromips32:
1769 *micromips64:
1770
1771
1772 000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP
1773 "sdbbp %#lx<CODE>"
1774 *micromips32:
1775 *micromips64:
1776 {
1777   SignalException (DebugBreakPoint, instruction_0);
1778 }
1779
1780
1781 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a
1782 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1783 *micromips32:
1784 {
1785   do_sdc1 (SD_, FT, IMMEDIATE, BASE);
1786 }
1787
1788
1789 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b
1790 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1791 *micromips64:
1792 {
1793   check_fpu (SD_);
1794   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1795             COP_SD (1, FT));
1796 }
1797
1798
1799 001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2
1800 "sdc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1801 *micromips32:
1802 *micromips64:
1803
1804
1805 000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB
1806 "seb r<RT>, r<RS>"
1807 *micromips32:
1808 *micromips64:
1809 {
1810   do_seb (SD_, RT, RS);
1811 }
1812
1813
1814 000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH
1815 "seh r<RT>, r<RS>"
1816 *micromips32:
1817 *micromips64:
1818 {
1819   do_seh (SD_, RT, RS);
1820 }
1821
1822
1823 001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH
1824 "sh r<RT>, <IMMEDIATE>(r<BASE>)"
1825 *micromips32:
1826 *micromips64:
1827 {
1828   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1829             GPR[RT]);
1830 }
1831
1832
1833 011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE
1834 "she r<RT>, <IMMEDIATE>(r<BASE>)"
1835 *micromips32:
1836 *micromips64:
1837
1838
1839 000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL
1840 "sll r<RT>, r<RS>, <SHIFT>"
1841 *micromips32:
1842 *micromips64:
1843 {
1844   do_sll (SD_, RS, RT, SHIFT);
1845 }
1846
1847
1848 000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV
1849 "sllv r<RD>, r<RT>, r<RS>"
1850 *micromips32:
1851 *micromips64:
1852 {
1853   do_sllv (SD_, RS, RT, RD);
1854 }
1855
1856
1857 000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT
1858 "slt r<RD>, r<RS>, r<RT>"
1859 *micromips32:
1860 *micromips64:
1861 {
1862   do_slt (SD_, RS, RT, RD);
1863 }
1864
1865
1866 100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI
1867 "slti r<RT>, r<RS>, <IMMEDIATE>"
1868 *micromips32:
1869 *micromips64:
1870 {
1871   do_slti (SD_, RS, RT, IMMEDIATE);
1872 }
1873
1874
1875 101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU
1876 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
1877 *micromips32:
1878 *micromips64:
1879 {
1880   do_sltiu (SD_, RS, RT, IMMEDIATE);
1881 }
1882
1883
1884 000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU
1885 "sltu r<RD>, r<RS>, r<RT>"
1886 *micromips32:
1887 *micromips64:
1888 {
1889   do_sltu (SD_, RS, RT, RD);
1890 }
1891
1892
1893 000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA
1894 "sra r<RT>, r<RS>, <SHIFT>"
1895 *micromips32:
1896 *micromips64:
1897 {
1898   do_sra (SD_, RS, RT, SHIFT);
1899 }
1900
1901
1902 000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV
1903 "srav r<RD>, r<RT>, r<RS>"
1904 *micromips32:
1905 *micromips64:
1906 {
1907   do_srav (SD_, RS, RT, RD);
1908 }
1909
1910
1911 000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL
1912 "srl r<RT>, r<RS>, <SHIFT>"
1913 *micromips32:
1914 *micromips64:
1915 {
1916   do_srl (SD_, RS, RT, SHIFT);
1917 }
1918
1919
1920 000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV
1921 "srlv r<RD>, r<RT>, r<RS>"
1922 *micromips32:
1923 *micromips64:
1924 {
1925   do_srlv (SD_, RS, RT, RD);
1926 }
1927
1928
1929 000000,00000000000000100000,000000:POOL32A:32::SSNOP
1930 "ssnop"
1931 *micromips32:
1932 *micromips64:
1933 {
1934 }
1935
1936
1937 000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB
1938 "sub r<RD>, r<RS>, r<RT>"
1939 *micromips32:
1940 *micromips64:
1941 {
1942   do_sub (SD_, RD, RS, RT);
1943 }
1944
1945
1946 000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU
1947 "subu r<RD>, r<RS>, r<RT>"
1948 *micromips32:
1949 *micromips64:
1950 {
1951   do_subu (SD_, RS, RT, RD);
1952 }
1953
1954
1955 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1
1956 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1957 *micromips32:
1958 {
1959   do_suxc1_32 (SD_, FD, INDEX, BASE);
1960 }
1961
1962
1963 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1
1964 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1965 *micromips64:
1966 {
1967   check_fpu (SD_);
1968   check_u64 (SD_, instruction_0);
1969   do_suxc1_64 (SD_, FD, INDEX, BASE);
1970 }
1971
1972 111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW
1973 "sw r<RT>, <IMMEDIATE>(r<BASE>)"
1974 *micromips32:
1975 *micromips64:
1976 {
1977   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1978 }
1979
1980
1981 100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1
1982 "swc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1983 *micromips32:
1984 *micromips64:
1985 {
1986   do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0);
1987 }
1988
1989
1990 001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2
1991 "swc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1992 *micromips32:
1993 *micromips64:
1994
1995
1996 011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE
1997 "swe r<RT>, <IMMEDIATE>(r<BASE>)"
1998 *micromips32:
1999 *micromips64:
2000
2001
2002 011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL
2003 "swl r<RT>, <IMMEDIATE>(r<BASE>)"
2004 *micromips32:
2005 *micromips64:
2006 {
2007   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2008                  GPR[RT]);
2009 }
2010
2011
2012 011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE
2013 "swle r<RT>, <IMMEDIATE>(r<BASE>)"
2014 *micromips32:
2015 *micromips64:
2016
2017
2018 001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32
2019 "swm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
2020 *micromips32:
2021 *micromips64:
2022 {
2023   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
2024   int reg_offset;
2025   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2026     {
2027       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2028       do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset,
2029                 GPR[src]);
2030     }
2031
2032   if (LWM32REGS & 0x10)
2033     do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA);
2034 }
2035
2036
2037 001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP
2038 "swp r<RS1>, <IMMEDIATE>(r<BASE>)"
2039 *micromips32:
2040 *micromips64:
2041 {
2042   if (RS1 == 31)
2043     Unpredictable ();
2044   else
2045     {
2046       do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE);
2047       do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
2048     }
2049 }
2050
2051
2052 011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR
2053 "swr r<RT>, <IMMEDIATE>(r<BASE>)"
2054 *micromips32:
2055 *micromips64:
2056 {
2057   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2058                   GPR[RT]);
2059 }
2060
2061
2062 011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE
2063 "swre r<RT>, <IMMEDIATE>(r<BASE>)"
2064 *micromips32:
2065 *micromips64:
2066
2067
2068 010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1
2069 "swxc1 f<FD>, r<INDEX>(r<BASE>)"
2070 *micromips32:
2071 *micromips64:
2072 {
2073   do_swxc1 (SD_, FD, INDEX, BASE, instruction_0);
2074 }
2075
2076
2077 000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC
2078 "sync <STYPE>"
2079 *micromips32:
2080 *micromips64:
2081 {
2082   SyncOperation (STYPE);
2083 }
2084
2085
2086 010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI
2087 "synci <IMMEDIATE>(r<BASE>)"
2088 *micromips32:
2089 *micromips64:
2090 {
2091 }
2092
2093 000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL
2094 "syscall %#lx<CODE>"
2095 *micromips32:
2096 *micromips64:
2097 {
2098   SignalException (SystemCall, instruction_0);
2099 }
2100
2101
2102 000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ
2103 "teq r<RS>, r<RT>"
2104 *micromips32:
2105 *micromips64:
2106 {
2107   do_teq (SD_, RS, RT, instruction_0);
2108 }
2109
2110
2111 010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI
2112 "teqi r<RS>, <IMMEDIATE>"
2113 *micromips32:
2114 *micromips64:
2115 {
2116   do_teqi (SD_, RS, IMMEDIATE, instruction_0);
2117 }
2118
2119
2120 000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE
2121 "tge r<RS>, r<RT>"
2122 *micromips32:
2123 *micromips64:
2124 {
2125   do_tge (SD_, RS, RT, instruction_0);
2126 }
2127
2128
2129 010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI
2130 "tgei r<RS>, <IMMEDIATE>"
2131 *micromips32:
2132 *micromips64:
2133 {
2134   do_tgei (SD_, RS, IMMEDIATE, instruction_0);
2135 }
2136
2137
2138 010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU
2139 "tgeiu r<RS>, <IMMEDIATE>"
2140 *micromips32:
2141 *micromips64:
2142 {
2143   do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
2144 }
2145
2146
2147 000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU
2148 "tgeu r<RS>, r<RT>"
2149 *micromips32:
2150 *micromips64:
2151 {
2152   do_tgeu (SD_, RS, RT, instruction_0);
2153 }
2154
2155
2156 000000,00000000000000001101,111100:POOL32A:32::TLBP
2157 "tlbp"
2158 *micromips32:
2159 *micromips64:
2160
2161
2162 000000,00000000000001001101,111100:POOL32A:32::TLBR
2163 "tlbr"
2164 *micromips32:
2165 *micromips64:
2166
2167
2168 000000,00000000000010001101,111100:POOL32A:32::TLBWI
2169 "tlbwi"
2170 *micromips32:
2171 *micromips64:
2172
2173
2174 000000,00000000000011001101,111100:POOL32A:32::TLBWR
2175 "tlbwr"
2176 *micromips32:
2177 *micromips64:
2178
2179
2180 000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT
2181 "tlt r<RS>, r<RT>, %#lx<CODE>"
2182 *micromips32:
2183 *micromips64:
2184 {
2185   do_tlt (SD_, RS, RT, instruction_0);
2186 }
2187
2188
2189 010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI
2190 "tlti r<RS>, <IMMEDIATE>"
2191 *micromips32:
2192 *micromips64:
2193 {
2194   do_tlti (SD_, RS, IMMEDIATE, instruction_0);
2195 }
2196
2197
2198 010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU
2199 "tltiu r<RS>, <IMMEDIATE>"
2200 *micromips32:
2201 *micromips64:
2202 {
2203   do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
2204 }
2205
2206
2207 000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU
2208 "tltu r<RS>, r<RT>"
2209 *micromips32:
2210 *micromips64:
2211 {
2212   do_tltu (SD_, RS, RT, instruction_0);
2213 }
2214
2215
2216 000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE
2217 "tne r<RS>, r<RT>"
2218 *micromips32:
2219 *micromips64:
2220 {
2221   do_tne (SD_, RS, RT, instruction_0);
2222 }
2223
2224
2225 010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI
2226 "tnei r<RS>, <IMMEDIATE>"
2227 *micromips32:
2228 *micromips64:
2229 {
2230   do_tnei (SD_, RS, IMMEDIATE, instruction_0);
2231 }
2232
2233
2234 000000,10.CODE,1001001101,111100:POOL32A:32::WAIT
2235 "wait"
2236 *micromips32:
2237 *micromips64:
2238
2239
2240 000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR
2241 "wrpgpr r<RS>, r<RT>"
2242 *micromips32:
2243 *micromips64:
2244
2245
2246 000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH
2247 "wsbh r<RT>, r<RS>"
2248 *micromips32:
2249 *micromips64:
2250 {
2251   do_wsbh (SD_, RT, RS);
2252 }
2253
2254
2255 000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR
2256 "xor r<RD>, r<RS>, r<RT>"
2257 *micromips32:
2258 *micromips64:
2259 {
2260   do_xor (SD_, RS, RT, RD);
2261 }
2262
2263
2264 011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI
2265 "xori r<RT>, r<RS>, <IMMEDIATE>"
2266 *micromips32:
2267 *micromips64:
2268 {
2269   do_xori (SD_, RS, RT, IMMEDIATE);
2270 }
2271
2272
2273 :%s::::FMT_MICROMIPS:int fmt
2274 *micromips32:
2275 *micromips64:
2276 {
2277   switch (fmt)
2278     {
2279     case 0: return "s";
2280     case 1: return "d";
2281     case 2: return "ps";
2282     default: return "?";
2283     }
2284 }
2285
2286
2287 :%s::::FMT_MICROMIPS_CVT_D:int fmt
2288 *micromips32:
2289 *micromips64:
2290 {
2291   switch (fmt)
2292     {
2293     case 0: return "s";
2294     case 1: return "w";
2295     case 2: return "l";
2296     default: return "?";
2297     }
2298 }
2299
2300
2301 :%s::::FMT_MICROMIPS_CVT_S:int fmt
2302 *micromips32:
2303 *micromips64:
2304 {
2305   switch (fmt)
2306     {
2307     case 0: return "d";
2308     case 1: return "w";
2309     case 2: return "l";
2310     default: return "?";
2311     }
2312 }
2313
2314
2315 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt
2316 "abs.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2317 *micromips32:
2318 *micromips64:
2319 {
2320   do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2321               instruction_0);
2322 }
2323
2324
2325 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt
2326 "add.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2327 *micromips32:
2328 *micromips64:
2329 {
2330   do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2331               instruction_0);
2332 }
2333
2334
2335 010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS
2336 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
2337 *micromips32:
2338 *micromips64:
2339 {
2340   do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
2341 }
2342
2343
2344 010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt
2345 "c.%s<COND>.%s<FMT_MICROMIPS> f<FS>, f<FT>":CC == 0
2346 "c.%s<COND>.%s<FMT_MICROMIPS> <CC>, f<FS>, f<FT>"
2347 *micromips32:
2348 *micromips64:
2349 {
2350   do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC,
2351                  FS, FT, instruction_0);
2352 }
2353
2354
2355 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt
2356 "ceil.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2357 *micromips32:
2358 *micromips64:
2359 {
2360   do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0);
2361 }
2362
2363
2364 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt
2365 "ceil.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2366 *micromips32:
2367 *micromips64:
2368 {
2369   do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0);
2370 }
2371
2372
2373 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt
2374 "cvt.d.%s<FMT_MICROMIPS_CVT_D> f<FT>, f<FS>"
2375 *micromips32:
2376 *micromips64:
2377 {
2378   do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D),
2379                 FT, FS, instruction_0);
2380 }
2381
2382
2383 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt
2384 "cvt.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2385 *micromips32:
2386 *micromips64:
2387 {
2388   do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2389 }
2390
2391
2392 010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S
2393 "cvt.ps.s f<FD>, f<FS>, f<FT>"
2394 *micromips32:
2395 *micromips64:
2396 {
2397   do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
2398 }
2399
2400
2401 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt
2402 "cvt.s.%s<FMT_MICROMIPS_CVT_S> f<FT>, f<FS>"
2403 *micromips32:
2404 *micromips64:
2405 {
2406   do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S),
2407                 FT, FS, instruction_0);
2408 }
2409
2410
2411 010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL
2412 "cvt.s.pl f<FT>, f<FS>"
2413 *micromips32:
2414 *micromips64:
2415 {
2416   do_cvt_s_pl (SD_, FT, FS, instruction_0);
2417 }
2418
2419
2420 010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU
2421 "cvt.s.pu f<FT>, f<FS>"
2422 *micromips32:
2423 *micromips64:
2424 {
2425   do_cvt_s_pu (SD_, FT, FS, instruction_0);
2426 }
2427
2428
2429 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt
2430 "cvt.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2431 *micromips32:
2432 *micromips64:
2433 {
2434   do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2435 }
2436
2437
2438 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt
2439 "div.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2440 *micromips32:
2441 *micromips64:
2442 {
2443   do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0);
2444 }
2445
2446
2447 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt
2448 "floor.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2449 *micromips32:
2450 *micromips64:
2451 {
2452   do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2453 }
2454
2455
2456 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt
2457 "floor.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2458 *micromips32:
2459 *micromips64:
2460 {
2461   do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2462 }
2463
2464
2465 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt
2466 "madd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2467 *micromips32:
2468 *micromips64:
2469 {
2470   do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2471                FT, instruction_0);
2472 }
2473
2474 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt
2475 "mov.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2476 *micromips32:
2477 *micromips64:
2478 {
2479   do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2480               instruction_0);
2481 }
2482
2483
2484 010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt
2485 "mov%s<TF>.%s<FMT_MICROMIPS> f<FT>, f<FS>, <CC>"
2486 *micromips32:
2487 *micromips64:
2488 {
2489   do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT,
2490                 FS, CC);
2491 }
2492
2493
2494 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt
2495 "movn.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2496 *micromips32:
2497 *micromips64:
2498 {
2499   do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2500 }
2501
2502 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt
2503 "movz.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2504 *micromips32:
2505 *micromips64:
2506 {
2507   do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2508 }
2509
2510
2511 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt
2512 "msub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2513 *micromips32:
2514 *micromips64:
2515 {
2516   do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2517                FT, instruction_0);
2518 }
2519
2520 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt
2521 "mul.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2522 *micromips32:
2523 *micromips64:
2524 {
2525   do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2526               instruction_0);
2527 }
2528
2529
2530 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt
2531 "neg.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2532 *micromips32:
2533 *micromips64:
2534 {
2535   do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2536               instruction_0);
2537 }
2538
2539
2540 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt
2541 "nmadd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2542 *micromips32:
2543 *micromips64:
2544 {
2545   do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2546                 FT, instruction_0);
2547 }
2548
2549 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt
2550 "nmsub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2551 *micromips32:
2552 *micromips64:
2553 {
2554   do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2555                 FT, instruction_0);
2556 }
2557
2558
2559 010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS
2560 "pll.ps f<FD>, f<FS>, f<FT>"
2561 *micromips32:
2562 *micromips64:
2563 {
2564   do_pll_ps (SD_, FD, FS, FT, instruction_0);
2565 }
2566
2567
2568 010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS
2569 "plu.ps f<FD>, f<FS>, f<FT>"
2570 *micromips32:
2571 *micromips64:
2572 {
2573   do_plu_ps (SD_, FD, FS, FT, instruction_0);
2574 }
2575
2576
2577 010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS
2578 "pul.ps f<FD>, f<FS>, f<FT>"
2579 *micromips32:
2580 *micromips64:
2581 {
2582   do_pul_ps (SD_, FD, FS, FT, instruction_0);
2583 }
2584
2585
2586 010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS
2587 "puu.ps f<FD>, f<FS>, f<FT>"
2588 *micromips32:
2589 *micromips64:
2590 {
2591   do_puu_ps (SD_, FD, FS, FT, instruction_0);
2592 }
2593
2594
2595 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt
2596 "recip.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2597 *micromips32:
2598 *micromips64:
2599 {
2600   do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS);
2601 }
2602
2603
2604 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt
2605 "round.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2606 *micromips32:
2607 *micromips64:
2608 {
2609   do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2610 }
2611
2612
2613 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt
2614 "round.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2615 *micromips32:
2616 *micromips64:
2617 {
2618   do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2619 }
2620
2621
2622 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt
2623 "rsqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2624 *micromips32:
2625 *micromips64:
2626 {
2627   do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2628 }
2629
2630
2631 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt
2632 "sqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2633 *micromips32:
2634 *micromips64:
2635 {
2636   do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2637 }
2638
2639
2640 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt
2641 "sub.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2642 *micromips32:
2643 *micromips64:
2644 {
2645   do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2646               instruction_0);
2647 }
2648
2649
2650 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt
2651 "trunc.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2652 *micromips32:
2653 *micromips64:
2654 {
2655   do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2656 }
2657
2658
2659 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt
2660 "trunc.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2661 *micromips32:
2662 *micromips64:
2663 {
2664   do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2665 }
2666
2667 001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM
2668 "ldm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2669 *micromips64:
2670 {
2671   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2672   int reg_offset;
2673   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2674     {
2675       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
2676       GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2677                                     8 * reg_offset));
2678     }
2679
2680   if (LWM32REGS & 0x10)
2681     RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2682                             8 * reg_offset));
2683 }
2684
2685 001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP
2686 "ldp r<RD>, <OFFSET>(r<BASE>)"
2687 *micromips64:
2688 {
2689   if (BASE == RD || RD == 31)
2690     Unpredictable ();
2691   else
2692     {
2693       check_u64 (SD_, instruction_0);
2694       GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2695                                    EXTEND12 (OFFSET)));
2696       GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2697                                        EXTEND12 (OFFSET) + 8));
2698     }
2699 }
2700
2701 001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM
2702 "sdm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2703 *micromips64:
2704 {
2705   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2706   int reg_offset;
2707   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2708     {
2709       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2710       do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset,
2711                 GPR[src]);
2712     }
2713
2714   if (LWM32REGS & 0x10)
2715     do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA);
2716 }
2717
2718 001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP
2719 "sdp r<RD>, <OFFSET>(r<BASE>)"
2720 *micromips64:
2721 {
2722   if (RD == 31)
2723     Unpredictable ();
2724   else
2725     {
2726       check_u64 (SD_, instruction_0);
2727       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
2728                 GPR[RD]);
2729       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8,
2730                 GPR[RD + 1]);
2731     }
2732 }
2733
2734 010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD
2735 "dadd r<RD>, r<RS>, r<RT>"
2736 *micromips64:
2737 {
2738   check_u64 (SD_, instruction_0);
2739   do_dadd (SD_, RD, RS, RT);
2740 }
2741
2742 010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI
2743 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2744 *micromips64:
2745 {
2746   check_u64 (SD_, instruction_0);
2747   do_daddi (SD_, RT, RS, IMMEDIATE);
2748 }
2749
2750 010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU
2751 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2752 *micromips64:
2753 {
2754   check_u64 (SD_, instruction_0);
2755   do_daddiu (SD_, RS, RT, IMMEDIATE);
2756 }
2757
2758 010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU
2759 "daddu r<RD>, r<RS>, r<RT>"
2760 *micromips64:
2761 {
2762   check_u64 (SD_, instruction_0);
2763   do_daddu (SD_, RS, RT, RD);
2764 }
2765
2766 010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO
2767 "dclo r<RT>, r<RS>"
2768 *micromips64:
2769 {
2770   check_u64 (SD_, instruction_0);
2771   do_dclo (SD_, RT, RS);
2772 }
2773
2774 010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ
2775 "dclz r<RT>, r<RS>"
2776 *micromips64:
2777 {
2778   check_u64 (SD_, instruction_0);
2779   do_dclz (SD_, RT, RS);
2780 }
2781
2782 010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV
2783 "ddiv r<RS>, r<RT>"
2784 *micromips64:
2785 {
2786   check_u64 (SD_, instruction_0);
2787   do_ddiv (SD_, RS, RT);
2788 }
2789
2790 010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU
2791 "ddivu r<RS>, r<RT>"
2792 *micromips64:
2793 {
2794   check_u64 (SD_, instruction_0);
2795   do_ddivu (SD_, RS, RT);
2796 }
2797
2798 010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT
2799 "dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
2800 *micromips64:
2801 {
2802   check_u64 (SD_, instruction_0);
2803   do_dext (SD_, RT, RS, LSB, SIZE);
2804 }
2805
2806 010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM
2807 "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
2808 *micromips64:
2809 {
2810   check_u64 (SD_, instruction_0);
2811   do_dextm (SD_, RT, RS, LSB, SIZE);
2812 }
2813
2814 010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU
2815 "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
2816 *micromips64:
2817 {
2818   check_u64 (SD_, instruction_0);
2819   do_dextu (SD_, RT, RS, LSB, SIZE);
2820 }
2821
2822 010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS
2823 "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
2824 *micromips64:
2825 {
2826   check_u64 (SD_, instruction_0);
2827   do_dins (SD_, RT, RS, LSB, MSB);
2828 }
2829
2830 010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM
2831 "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
2832 *micromips64:
2833 {
2834   check_u64 (SD_, instruction_0);
2835   do_dinsm (SD_, RT, RS, LSB, MSB);
2836 }
2837
2838 010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU
2839 "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
2840 *micromips64:
2841 {
2842   check_u64 (SD_, instruction_0);
2843   do_dinsu (SD_, RT, RS, LSB, MSB);
2844 }
2845
2846 010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0
2847 "dmfc0 r<RT>, r<RS>": SEL == 0
2848 "dmfc0 r<RT>, r<RS>, <SEL>"
2849 *micromips64:
2850 {
2851   check_u64 (SD_, instruction_0);
2852   DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL);
2853 }
2854
2855 010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1
2856 "dmfc1 r<RT>, f<FS>"
2857 *micromips64:
2858 {
2859   check_fpu (SD_);
2860   check_u64 (SD_, instruction_0);
2861   do_dmfc1b (SD_, RT, FS);
2862 }
2863
2864 010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0
2865 "dmtc0 r<RT>, r<RS>": SEL == 0
2866 "dmtc0 r<RT>, r<RS>, <SEL>"
2867 *micromips64:
2868 {
2869   check_u64 (SD_, instruction_0);
2870   DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL);
2871 }
2872
2873 010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1
2874 "dmtc1 r<RT>, f<FS>"
2875 *micromips64:
2876 {
2877   check_fpu (SD_);
2878   check_u64 (SD_, instruction_0);
2879   do_dmtc1b (SD_, RT, FS);
2880 }
2881
2882 010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT
2883 "dmult r<RS>, r<RT>"
2884 *micromips64:
2885 {
2886   check_u64 (SD_, instruction_0);
2887   do_dmult (SD_, RS, RT, 0);
2888 }
2889
2890 010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU
2891 "dmultu r<RS>, r<RT>"
2892 *micromips64:
2893 {
2894   check_u64 (SD_, instruction_0);
2895   do_dmultu (SD_, RS, RT, 0);
2896 }
2897
2898 010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR
2899 "drotr r<RT>, r<RS>, <SA>"
2900 *micromips64:
2901 {
2902   check_u64 (SD_, instruction_0);
2903   GPR[RT] = do_dror (SD_, GPR[RS], SA);
2904 }
2905
2906 010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32
2907 "drotr32 r<RT>, r<RS>, <SA+32>"
2908 *micromips64:
2909 {
2910   check_u64 (SD_, instruction_0);
2911   GPR[RT] = do_dror (SD_, GPR[RS], SA + 32);
2912 }
2913
2914 010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV
2915 "drotrv r<RD>, r<RT>, r<RS>"
2916 *micromips64:
2917 {
2918   check_u64 (SD_, instruction_0);
2919   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2920 }
2921
2922 010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH
2923 "dsbh r<RT>, r<RS>"
2924 *micromips64:
2925 {
2926   check_u64 (SD_, instruction_0);
2927   do_dsbh (SD_, RT, RS);
2928 }
2929
2930 010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD
2931 "dshd r<RT>, r<RS>"
2932 *micromips64:
2933 {
2934   check_u64 (SD_, instruction_0);
2935   do_dshd (SD_, RS, RT);
2936 }
2937
2938 010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL
2939 "dsll r<RT>, r<RS>, <SA>"
2940 *micromips64:
2941 {
2942   check_u64 (SD_, instruction_0);
2943   do_dsll (SD_, RS, RT, SA);
2944 }
2945
2946 010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32
2947 "dsll32 r<RT>, r<RS>, <SA>"
2948 *micromips64:
2949 {
2950   check_u64 (SD_, instruction_0);
2951   do_dsll32 (SD_, RT, RS, SA);
2952 }
2953
2954 010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV
2955 "dsllv r<RD>, r<RT>, r<RS>"
2956 *micromips64:
2957 {
2958   check_u64 (SD_, instruction_0);
2959   do_dsllv (SD_, RS, RT, RD);
2960 }
2961
2962 010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA
2963 "dsra r<RT>, r<RS>, <SA>"
2964 *micromips64:
2965 {
2966   check_u64 (SD_, instruction_0);
2967   do_dsra (SD_, RS, RT, SA);
2968 }
2969
2970 010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32
2971 "dsra32 r<RT>, r<RS>, <SA>"
2972 *micromips64:
2973 {
2974   check_u64 (SD_, instruction_0);
2975   do_dsra32 (SD_, RT, RS, SA);
2976 }
2977
2978 010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV
2979 "dsrav r<RD>, r<RS>, r<RT>"
2980 *micromips64:
2981 {
2982   check_u64 (SD_, instruction_0);
2983   do_dsrav (SD_, RS, RT, RD);
2984 }
2985
2986 010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL
2987 "dsrl r<RT>, r<RS>, <SA>"
2988 *micromips64:
2989 {
2990   check_u64 (SD_, instruction_0);
2991   do_dsrl (SD_, RS, RT, SA);
2992 }
2993
2994 010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32
2995 "dsrl32 r<RT>, r<RS>, <SA>"
2996 *micromips64:
2997 {
2998   check_u64 (SD_, instruction_0);
2999   do_dsrl32 (SD_, RT, RS, SA);
3000 }
3001
3002 010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV
3003 "dsrlv r<RD>, r<RT>, r<RS>"
3004 *micromips64:
3005 {
3006   check_u64 (SD_, instruction_0);
3007   do_dsrlv (SD_, RS, RT, RD);
3008 }
3009
3010 010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB
3011 "dsub r<RD>, r<RS>, r<RT>"
3012 *micromips64:
3013 {
3014   check_u64 (SD_, instruction_0);
3015   do_dsub (SD_, RD, RS, RT);
3016 }
3017
3018 010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU
3019 "dsubu r<RD>, r<RS>, r<RT>"
3020 *micromips64:
3021 {
3022   check_u64 (SD_, instruction_0);
3023   do_dsubu (SD_, RS, RT, RD);
3024 }
3025
3026 110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD
3027 "ld r<RT>, <OFFSET>(r<BASE>)"
3028 *micromips64:
3029 {
3030   check_u64 (SD_, instruction_0);
3031   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3032                                EXTEND16 (OFFSET)));
3033 }
3034
3035 011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL
3036 "ldl r<RT>, <OFFSET>(r<BASE>)"
3037 *micromips64:
3038 {
3039   check_u64 (SD_, instruction_0);
3040   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3041                           EXTEND12 (OFFSET), GPR[RT]);
3042 }
3043
3044 011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR
3045 "ldr r<RT>, <OFFSET>(r<BASE>)"
3046 *micromips64:
3047 {
3048   check_u64 (SD_, instruction_0);
3049   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3050                            EXTEND12 (OFFSET), GPR[RT]);
3051 }
3052
3053 010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1
3054 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3055 *micromips64:
3056 {
3057   check_fpu (SD_);
3058   check_u64 (SD_, instruction_0);
3059   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3060 }
3061
3062 011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD
3063 "lld r<RT>, <OFFSET>(r<BASE>)"
3064 *micromips64:
3065 {
3066   check_u64 (SD_, instruction_0);
3067   do_lld (SD_, RT, OFFSET, BASE);
3068 }
3069
3070 011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD
3071 "scd r<RT>, <OFFSET>(r<BASE>)"
3072 *micromips64:
3073 {
3074   check_u64 (SD_, instruction_0);
3075   do_scd (SD_, RT, OFFSET, BASE);
3076 }
3077
3078 110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD
3079 "sd r<RT>, <OFFSET>(r<BASE>)"
3080 *micromips64:
3081 {
3082   check_u64 (SD_, instruction_0);
3083   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET),
3084             GPR[RT]);
3085 }
3086
3087 011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL
3088 "sdl r<RT>, <OFFSET>(r<BASE>)"
3089 *micromips64:
3090 {
3091   check_u64 (SD_, instruction_0);
3092   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3093                  GPR[RT]);
3094 }
3095
3096 011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR
3097 "sdr r<RT>, <OFFSET>(r<BASE>)"
3098 *micromips64:
3099 {
3100   check_u64 (SD_, instruction_0);
3101   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3102                   GPR[RT]);
3103 }
3104
3105 010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1
3106 "sdxc1 f<FD>, r<INDEX>(r<BASE>)"
3107 *micromips64:
3108 {
3109   check_fpu (SD_);
3110   check_u64 (SD_, instruction_0);
3111   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX],
3112             COP_SD (1, FD));
3113 }