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* am33.igen: Add most am33 DSP instructions.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // Helper:
2 //
3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
6 //
7 //
8
9 :function:::int:translate_rreg:int rreg
10 {
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20 }
21
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
24 "mov"
25 *am33
26 {
27 PC = cia;
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
29 }
30
31
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
34 "mov"
35 *am33
36 {
37 PC = cia;
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
39 }
40
41
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
44 "mov"
45 *am33
46 {
47 PC = cia;
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
49 }
50
51
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
54 "mov"
55 *am33
56 {
57 PC = cia;
58 State.regs[REG_A0 + AN0] = PC;
59 }
60
61
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
64 "mov"
65 *am33
66 {
67 PC = cia;
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
69 }
70
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
73 "mov"
74 *am33
75 {
76 PC = cia;
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
78 }
79
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
82 "mov"
83 *am33
84 {
85 PC = cia;
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
87 }
88
89
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
92 "syscall"
93 *am33
94 {
95 unsigned int sp, next_pc;
96
97 PC = cia;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
103 nia = PC;
104 }
105
106
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
109 "mov"
110 *am33
111 {
112 PC = cia;
113 State.regs[REG_D0 + DN0] = PSW;
114 }
115
116
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
119 "mov"
120 *am33
121 {
122 PC = cia;
123 PSW = State.regs[REG_D0 + DM1];
124 }
125
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
128 "mov"
129 *am33
130 {
131 int destreg = translate_rreg (SD_, RN0);
132
133 PC = cia;
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
135 }
136
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
139 "mov"
140 *am33
141 {
142 int destreg = translate_rreg (SD_, RN0);
143
144 PC = cia;
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
146 }
147
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
150 "mov"
151 *am33
152 {
153 int destreg = translate_rreg (SD_, RM1);
154
155 PC = cia;
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
157 }
158
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
161 "mov"
162 *am33
163 {
164 int destreg = translate_rreg (SD_, RM1);
165
166 PC = cia;
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
168 }
169
170
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
173 "movm"
174 *am33
175 {
176 unsigned long usp = State.regs[REG_USP];
177 unsigned long mask;
178
179 PC = cia;
180 mask = REGS;
181
182 if (mask & 0x8)
183 {
184 usp += 4;
185 State.regs[REG_LAR] = load_word (usp);
186 usp += 4;
187 State.regs[REG_LIR] = load_word (usp);
188 usp += 4;
189 State.regs[REG_MDR] = load_word (usp);
190 usp += 4;
191 State.regs[REG_A0 + 1] = load_word (usp);
192 usp += 4;
193 State.regs[REG_A0] = load_word (usp);
194 usp += 4;
195 State.regs[REG_D0 + 1] = load_word (usp);
196 usp += 4;
197 State.regs[REG_D0] = load_word (usp);
198 usp += 4;
199 }
200
201 if (mask & 0x10)
202 {
203 State.regs[REG_A0 + 3] = load_word (usp);
204 usp += 4;
205 }
206
207 if (mask & 0x20)
208 {
209 State.regs[REG_A0 + 2] = load_word (usp);
210 usp += 4;
211 }
212
213 if (mask & 0x40)
214 {
215 State.regs[REG_D0 + 3] = load_word (usp);
216 usp += 4;
217 }
218
219 if (mask & 0x80)
220 {
221 State.regs[REG_D0 + 2] = load_word (usp);
222 usp += 4;
223 }
224
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
227 {
228 if (mask & 0x1)
229 {
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 usp += 16;
232 State.regs[REG_E0 + 1] = load_word (usp);
233 usp += 4;
234 State.regs[REG_E0 + 0] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x2)
239 {
240 State.regs[REG_E0 + 7] = load_word (usp);
241 usp += 4;
242 State.regs[REG_E0 + 6] = load_word (usp);
243 usp += 4;
244 State.regs[REG_E0 + 5] = load_word (usp);
245 usp += 4;
246 State.regs[REG_E0 + 4] = load_word (usp);
247 usp += 4;
248 }
249
250 if (mask & 0x4)
251 {
252 State.regs[REG_E0 + 3] = load_word (usp);
253 usp += 4;
254 State.regs[REG_E0 + 2] = load_word (usp);
255 usp += 4;
256 }
257 }
258 /* end-sanitize-am33 */
259
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
262 }
263
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
266 "movm"
267 *am33
268 {
269 unsigned long usp = State.regs[REG_USP];
270 unsigned long mask;
271
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
273 {
274 if (mask & 0x4)
275 {
276 usp -= 4;
277 store_word (usp, State.regs[REG_E0 + 2]);
278 usp -= 4;
279 store_word (usp, State.regs[REG_E0 + 3]);
280 }
281
282 if (mask & 0x2)
283 {
284 usp -= 4;
285 store_word (usp, State.regs[REG_E0 + 4]);
286 usp -= 4;
287 store_word (usp, State.regs[REG_E0 + 5]);
288 usp -= 4;
289 store_word (usp, State.regs[REG_E0 + 6]);
290 usp -= 4;
291 store_word (usp, State.regs[REG_E0 + 7]);
292 }
293
294 if (mask & 0x1)
295 {
296 usp -= 4;
297 store_word (usp, State.regs[REG_E0 + 0]);
298 usp -= 4;
299 store_word (usp, State.regs[REG_E0 + 1]);
300 usp -= 16;
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
302 }
303 }
304 /* end-sanitize-am33 */
305
306 if (mask & 0x80)
307 {
308 usp -= 4;
309 store_word (usp, State.regs[REG_D0 + 2]);
310 }
311
312 if (mask & 0x40)
313 {
314 usp -= 4;
315 store_word (usp, State.regs[REG_D0 + 3]);
316 }
317
318 if (mask & 0x20)
319 {
320 usp -= 4;
321 store_word (usp, State.regs[REG_A0 + 2]);
322 }
323
324 if (mask & 0x10)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_A0 + 3]);
328 }
329
330 if (mask & 0x8)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0]);
334 usp -= 4;
335 store_word (usp, State.regs[REG_D0 + 1]);
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0]);
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 1]);
340 usp -= 4;
341 store_word (usp, State.regs[REG_MDR]);
342 usp -= 4;
343 store_word (usp, State.regs[REG_LIR]);
344 usp -= 4;
345 store_word (usp, State.regs[REG_LAR]);
346 usp -= 4;
347 }
348
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
351 }
352
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
355 "and"
356 *am33
357 {
358 PC = cia;
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
360 }
361
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
364 "or"
365 *am33
366 {
367 PC = cia;
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
369 }
370
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
373 "mov"
374 *am33
375 {
376 int srcreg, dstreg;
377
378 PC = cia;
379
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
383 }
384
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
387 "mov"
388 *am33
389 {
390 int srcreg;
391
392 PC = cia;
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
396 else
397 State.regs[REG_MDR] = 0;
398 }
399
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
402 "extb"
403 *am33
404 {
405 int srcreg, dstreg;
406
407 PC = cia;
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
411 }
412
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
415 "extbu"
416 *am33
417 {
418 int srcreg, dstreg;
419
420 PC = cia;
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
424 }
425
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
428 "exth"
429 *am33
430 {
431 int srcreg, dstreg;
432
433 PC = cia;
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
437 }
438
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
441 "exthu"
442 *am33
443 {
444 int srcreg, dstreg;
445
446 PC = cia;
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
450 }
451
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
454 "clr"
455 *am33
456 {
457 int dstreg;
458
459 PC = cia;
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
462 PSW |= PSW_Z;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
464 }
465
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
468 "add"
469 *am33
470 {
471 int srcreg, dstreg;
472
473 PC = cia;
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
477 }
478
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
481 "addc"
482 *am33
483 {
484 int srcreg, dstreg;
485 int z, c, n, v;
486 unsigned long reg1, reg2, sum;
487
488 PC = cia;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
491
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
496
497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
502
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
506 }
507
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
510 "sub"
511 *am33
512 {
513 int srcreg, dstreg;
514
515 PC = cia;
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
519 }
520
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
523 "subc"
524 *am33
525 {
526 int srcreg, dstreg;
527 int z, c, n, v;
528 unsigned long reg1, reg2, difference;
529
530 PC = cia;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
533
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
538
539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
540 n = (difference & 0x80000000);
541 c = (reg1 > reg2);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
544
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
548 }
549
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
552 "inc"
553 *am33
554 {
555 int dstreg;
556
557 PC = cia;
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
560 }
561
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
564 "inc4"
565 *am33
566 {
567 int dstreg;
568
569 PC = cia;
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
572 }
573
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
576 "cmp"
577 *am33
578 {
579 int srcreg1, srcreg2;
580
581 PC = cia;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
585 }
586
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
589 "mov"
590 *am33
591 {
592 int dstreg;
593
594 PC = cia;
595 dstreg = translate_rreg (SD_, RN0);
596
597 if (XRM2 == 0)
598 {
599 State.regs[dstreg] = State.regs[REG_SP];
600 }
601 else
602 abort ();
603 }
604
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
607 "mov"
608 *am33
609 {
610 int srcreg;
611
612 PC = cia;
613 srcreg = translate_rreg (SD_, RM2);
614
615 if (XRN0 == 0)
616 {
617 State.regs[REG_SP] = State.regs[srcreg];
618 }
619 else
620 abort ();
621 }
622
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
625 "and"
626 *am33
627 {
628 int srcreg, dstreg;
629 int z, n;
630
631 PC = cia;
632
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
635
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
641 }
642
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
645 "or"
646 *am33
647 {
648 int srcreg, dstreg;
649 int z, n;
650
651 PC = cia;
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
654
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
660 }
661
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
664 "xor"
665 *am33
666 {
667 int srcreg, dstreg;
668 int z, n;
669
670 PC = cia;
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
673
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
679 }
680
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
683 "not"
684 *am33
685 {
686 int dstreg;
687 int z, n;
688
689 PC = cia;
690 dstreg = translate_rreg (SD_, RN0);
691
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
697 }
698
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
701 "asr"
702 *am33
703 {
704 int srcreg, dstreg;
705 long temp;
706 int c, z, n;
707
708 PC = cia;
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
711
712 temp = State.regs[dstreg];
713 c = temp & 1;
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
720 }
721
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
724 "lsr"
725 *am33
726 {
727 int srcreg, dstreg;
728 int z, n, c;
729
730 PC = cia;
731
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
734
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
741 }
742
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
745 "asl"
746 *am33
747 {
748 int srcreg, dstreg;
749 int z, n;
750
751 PC = cia;
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
754
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
760 }
761
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
764 "asl2"
765 *am33
766 {
767 int dstreg;
768 int n, z;
769
770 PC = cia;
771 dstreg = translate_rreg (SD_, RN0);
772
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
778 }
779
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
782 "ror"
783 *am33
784 {
785 int dstreg;
786 int c, n, z;
787 unsigned long value;
788
789 PC = cia;
790 dstreg = translate_rreg (SD_, RN0);
791
792 value = State.regs[dstreg];
793 c = (value & 0x1);
794
795 value >>= 1;
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
798 z = (value == 0);
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
802 }
803
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
806 "rol"
807 *am33
808 {
809 int dstreg;
810 int c, n, z;
811 unsigned long value;
812
813 PC = cia;
814 dstreg = translate_rreg (SD_, RN0);
815
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
818
819 value <<= 1;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
822 z = (value == 0);
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
826 }
827
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
830 "mul"
831 *am33
832 {
833 int srcreg, dstreg;
834 unsigned long long temp;
835 int n, z;
836
837 PC = cia;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
840
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849 }
850
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
853 "mulu"
854 *am33
855 {
856 int srcreg, dstreg;
857 unsigned long long temp;
858 int n, z;
859
860 PC = cia;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
863
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
872 }
873
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
876 "div"
877 *am33
878 {
879 int srcreg, dstreg;
880 long long temp;
881 int n, z;
882
883 PC = cia;
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
886
887 temp = State.regs[REG_MDR];
888 temp <<= 32;
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (signed32)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
897 }
898
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
901 "divu"
902 *am33
903 {
904 int srcreg, dstreg;
905 unsigned long long temp;
906 int n, z;
907
908 PC = cia;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
911
912 temp = State.regs[REG_MDR];
913 temp <<= 32;
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
922 }
923
924
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
927 "mov"
928 *am33
929 {
930 int srcreg, dstreg;
931
932 PC = cia;
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
936 }
937
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
940 "mov"
941 *am33
942 {
943 int srcreg, dstreg;
944
945 PC = cia;
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
949 }
950
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
953 "movbu"
954 *am33
955 {
956 int srcreg, dstreg;
957
958 PC = cia;
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
962 }
963
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
966 "movbu"
967 *am33
968 {
969 int srcreg, dstreg;
970
971 PC = cia;
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
975 }
976
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
979 "movhu"
980 *am33
981 {
982 int srcreg, dstreg;
983
984 PC = cia;
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
988 }
989
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
992 "movhu"
993 *am33
994 {
995 int srcreg, dstreg;
996
997 PC = cia;
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1001 }
1002
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1005 "mov"
1006 *am33
1007 {
1008 int srcreg, dstreg;
1009
1010 PC = cia;
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1015 }
1016
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1019 "mov"
1020 *am33
1021 {
1022 int srcreg, dstreg;
1023
1024 PC = cia;
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1029 }
1030
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1033 "mov"
1034 *am33
1035 {
1036 int dstreg;
1037
1038 PC = cia;
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1041 }
1042
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1045 "mov"
1046 *am33
1047 {
1048 int srcreg;
1049
1050 PC = cia;
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1053 }
1054
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1057 "movbu"
1058 *am33
1059 {
1060 int dstreg;
1061
1062 PC = cia;
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1065 }
1066
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1069 "movbu"
1070 *am33
1071 {
1072 int srcreg;
1073
1074 PC = cia;
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1077 }
1078
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1081 "movhu"
1082 *am33
1083 {
1084 int dstreg;
1085
1086 PC = cia;
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1089 }
1090
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1093 "movhu"
1094 *am33
1095 {
1096 int srcreg;
1097
1098 PC = cia;
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1101 }
1102
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1105 "movhu"
1106 *am33
1107 {
1108 int srcreg, dstreg;
1109
1110 PC = cia;
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1115 }
1116
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1119 "movhu"
1120 *am33
1121 {
1122 int srcreg, dstreg;
1123
1124 PC = cia;
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1129 }
1130
1131
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1134 "mac"
1135 *am33
1136 {
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1139 int c, v;
1140
1141 PC = cia;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1144
1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1150 temp >>= 32;
1151 temp &= 0xffffffff;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1156 if (v)
1157 State.regs[REG_MCVF] = 1;
1158 }
1159
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1162 "macu"
1163 *am33
1164 {
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1167 int c, v;
1168
1169 PC = cia;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1172
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1178 temp >>= 32;
1179 temp &= 0xffffffff;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1184 if (v)
1185 State.regs[REG_MCVF] = 1;
1186 }
1187
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1190 "macb"
1191 *am33
1192 {
1193 int srcreg1, srcreg2;
1194 long temp, sum;
1195 int v;
1196
1197 PC = cia;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1200
1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1207 if (v)
1208 State.regs[REG_MCVF] = 1;
1209 }
1210
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1213 "macbu"
1214 *am33
1215 {
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1218 int v;
1219
1220 PC = cia;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1223
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1230 if (v)
1231 State.regs[REG_MCVF] = 1;
1232 }
1233
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1236 "mach"
1237 *am33
1238 {
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1241 int c, v;
1242
1243 PC = cia;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1246
1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1252 temp >>= 32;
1253 temp &= 0xffffffff;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1258 if (v)
1259 State.regs[REG_MCVF] = 1;
1260 }
1261
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1264 "machu"
1265 *am33
1266 {
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1269 int c, v;
1270
1271 PC = cia;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1274
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1280 temp >>= 32;
1281 temp &= 0xffffffff;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1286 if (v)
1287 State.regs[REG_MCVF] = 1;
1288 }
1289
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1292 "dmach"
1293 *am33
1294 {
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1297 int v;
1298
1299 PC = cia;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1302
1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1311 if (v)
1312 State.regs[REG_MCVF] = 1;
1313 }
1314
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1317 "dmachu"
1318 *am33
1319 {
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1322 int v;
1323
1324 PC = cia;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1327
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1336 if (v)
1337 State.regs[REG_MCVF] = 1;
1338 }
1339
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1342 "dmulh"
1343 *am33
1344 {
1345 int srcreg, dstreg;
1346 long temp;
1347
1348 PC = cia;
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1351
1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1358 }
1359
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1362 "dmachu"
1363 *am33
1364 {
1365 int srcreg, dstreg;
1366 unsigned long temp;
1367
1368 PC = cia;
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1371
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1378 }
1379
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1382 "sat16"
1383 *am33
1384 {
1385 int srcreg, dstreg;
1386 int value, z, n;
1387
1388 PC = cia;
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1391
1392 value = State.regs[srcreg];
1393
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1398 else
1399 State.regs[dstreg] = value;
1400
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1405 }
1406
1407 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1408 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1409 "mcste"
1410 *am33
1411 {
1412 int srcreg, dstreg;
1413
1414 PC = cia;
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1417
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1420
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1423 {
1424 long long tmp;
1425
1426 tmp = State.regs[REG_MCRH];
1427 tmp <<= 32;
1428 tmp += State.regs[REG_MCRL];
1429
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1434 else
1435 State.regs[dstreg] = tmp;
1436 }
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1439 {
1440 long long tmp;
1441
1442 tmp = State.regs[REG_MCRH];
1443 tmp <<= 32;
1444 tmp += State.regs[REG_MCRL];
1445
1446 if (tmp > 0x7fff)
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1450 else
1451 State.regs[dstreg] = tmp;
1452 }
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1455 {
1456 long long tmp;
1457
1458 tmp = State.regs[REG_MCRH];
1459 tmp <<= 32;
1460 tmp += State.regs[REG_MCRL];
1461
1462 if (tmp > 0x7f)
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1466 else
1467 State.regs[dstreg] = tmp;
1468 }
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1471 {
1472 long long tmp;
1473
1474 tmp = State.regs[REG_MCRH];
1475 tmp <<= 32;
1476 tmp += State.regs[REG_MCRL];
1477
1478 if (tmp > 0x80)
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1482 else
1483 State.regs[dstreg] = tmp;
1484 }
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1487 {
1488 long long tmp;
1489
1490 tmp = State.regs[REG_MCRH];
1491 tmp <<= 32;
1492 tmp += State.regs[REG_MCRL];
1493
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1498
1499 tmp >>= 16;
1500 State.regs[dstreg] = tmp;
1501 }
1502 }
1503
1504 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1505 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1506 "swap"
1507 *am33
1508 {
1509 int srcreg, dstreg;
1510
1511 PC = cia;
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
1514
1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
1519 }
1520
1521 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1522 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1523 "swaph"
1524 *am33
1525 {
1526 int srcreg, dstreg;
1527
1528 PC = cia;
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
1531
1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1536 }
1537
1538 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1539 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1540 "swhw"
1541 *am33
1542 {
1543 int srcreg, dstreg;
1544
1545 PC = cia;
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
1548
1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
1551 }
1552
1553 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1554 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1555 "bsch"
1556 *am33
1557 {
1558 int temp, c, i;
1559 int srcreg, dstreg;
1560 int start;
1561
1562 PC = cia;
1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
1565
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1568 if (start == -1)
1569 start = 31;
1570
1571 for (i = start; i >= 0; i--)
1572 {
1573 if (temp & (1 << i))
1574 {
1575 c = 1;
1576 State.regs[dstreg] = i;
1577 break;
1578 }
1579 }
1580
1581 if (i < 0)
1582 {
1583 c = 0;
1584 State.regs[dstreg] = 0;
1585 }
1586 PSW &= ~(PSW_C);
1587 PSW |= (c ? PSW_C : 0);
1588 }
1589
1590
1591 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1592 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1593 "mov"
1594 *am33
1595 {
1596 int dstreg;
1597
1598 PC = cia;
1599 dstreg = translate_rreg (SD_, RN0);
1600 State.regs[dstreg] = EXTEND8 (IMM8);
1601 }
1602
1603 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1604 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1605 "movu"
1606 *am33
1607 {
1608 int dstreg;
1609
1610 PC = cia;
1611 dstreg = translate_rreg (SD_, RN0);
1612 State.regs[dstreg] = IMM8 & 0xff;
1613 }
1614
1615 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1616 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1617 "add"
1618 *am33
1619 {
1620 int dstreg;
1621
1622 PC = cia;
1623 dstreg = translate_rreg (SD_, RN0);
1624 genericAdd (EXTEND8 (IMM8), dstreg);
1625 }
1626
1627 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1628 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1629 "addc"
1630 *am33
1631 {
1632 int dstreg, imm;
1633 int z, c, n, v;
1634 unsigned long reg1, reg2, sum;
1635
1636 PC = cia;
1637 dstreg = translate_rreg (SD_, RN0);
1638
1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1643
1644 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1649
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1653 }
1654
1655 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1656 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1657 "sub"
1658 *am33
1659 {
1660 int dstreg;
1661
1662 PC = cia;
1663 dstreg = translate_rreg (SD_, RN0);
1664
1665 genericSub (EXTEND8 (IMM8), dstreg);
1666 }
1667
1668 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1669 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1670 "subc"
1671 *am33
1672 {
1673 int imm, dstreg;
1674 int z, c, n, v;
1675 unsigned long reg1, reg2, difference;
1676
1677 PC = cia;
1678 dstreg = translate_rreg (SD_, RN0);
1679
1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
1684
1685 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1686 n = (difference & 0x80000000);
1687 c = (imm > reg2);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
1690
1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1694 }
1695
1696 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1697 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1698 "cmp"
1699 *am33
1700 {
1701 int srcreg;
1702
1703 PC = cia;
1704 srcreg = translate_rreg (SD_, RN0);
1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1706 }
1707
1708 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1709 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1710 "mov"
1711 *am33
1712 {
1713 int dstreg;
1714
1715 PC = cia;
1716
1717 if (XRN0 == 0)
1718 State.regs[REG_SP] = IMM8;
1719 else
1720 abort ();
1721 }
1722
1723 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1724 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1725 "and"
1726 *am33
1727 {
1728 int dstreg;
1729 int z, n;
1730
1731 PC = cia;
1732 dstreg = translate_rreg (SD_, RN0);
1733
1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1739 }
1740
1741 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1742 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1743 "or"
1744 *am33
1745 {
1746 int dstreg;
1747 int z, n;
1748
1749 PC = cia;
1750 dstreg = translate_rreg (SD_, RN0);
1751
1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1757 }
1758
1759 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1760 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1761 "xor"
1762 *am33
1763 {
1764 int dstreg;
1765 int z, n;
1766
1767 PC = cia;
1768 dstreg = translate_rreg (SD_, RN0);
1769
1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1775 }
1776
1777 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1778 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1779 "asr"
1780 *am33
1781 {
1782 int dstreg;
1783 long temp;
1784 int c, z, n;
1785
1786 PC = cia;
1787 dstreg = translate_rreg (SD_, RN0);
1788
1789 temp = State.regs[dstreg];
1790 c = temp & 1;
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1797 }
1798
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1801 "lsr"
1802 *am33
1803 {
1804 int dstreg;
1805 int z, n, c;
1806
1807 PC = cia;
1808 dstreg = translate_rreg (SD_, RN0);
1809
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1816 }
1817
1818 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1819 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1820 "asl"
1821 *am33
1822 {
1823 int srcreg, dstreg;
1824 int z, n;
1825
1826 PC = cia;
1827 dstreg = translate_rreg (SD_, RN0);
1828
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1834 }
1835
1836 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1837 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1838 "mul"
1839 *am33
1840 {
1841 int dstreg;
1842 unsigned long long temp;
1843 int z, n;
1844
1845 PC = cia;
1846 dstreg = translate_rreg (SD_, RN0);
1847
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1856 }
1857
1858 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1859 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1860 "mulu"
1861 *am33
1862 {
1863 int dstreg;
1864 unsigned long long temp;
1865 int z, n;
1866
1867 PC = cia;
1868 dstreg = translate_rreg (SD_, RN0);
1869
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1878 }
1879
1880 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1881 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1882 "btst"
1883 *am33
1884 {
1885 int srcreg;
1886
1887 PC = cia;
1888 srcreg = translate_rreg (SD_, RM0);
1889 genericBtst(IMM8, State.regs[srcreg]);
1890 }
1891
1892 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1893 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1894 "mov"
1895 *am33
1896 {
1897 int srcreg, dstreg;
1898
1899 PC = cia;
1900 srcreg = translate_rreg (SD_, RM0);
1901 dstreg = translate_rreg (SD_, RN2);
1902 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1903 }
1904
1905 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1906 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1907 "mov"
1908 {
1909 int srcreg, dstreg;
1910
1911 PC = cia;
1912 srcreg = translate_rreg (SD_, RM2);
1913 dstreg = translate_rreg (SD_, RN0);
1914 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1915 }
1916
1917 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1918 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1919 "movbu"
1920 {
1921 int srcreg, dstreg;
1922
1923 PC = cia;
1924 srcreg = translate_rreg (SD_, RM0);
1925 dstreg = translate_rreg (SD_, RN2);
1926 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1927 }
1928
1929 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1930 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1931 "movbu"
1932 {
1933 int srcreg, dstreg;
1934
1935 PC = cia;
1936 srcreg = translate_rreg (SD_, RM2);
1937 dstreg = translate_rreg (SD_, RN0);
1938 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1939 }
1940
1941 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1942 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1943 "movhu"
1944 {
1945 int srcreg, dstreg;
1946
1947 PC = cia;
1948 srcreg = translate_rreg (SD_, RM0);
1949 dstreg = translate_rreg (SD_, RN2);
1950 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1951 }
1952
1953 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1954 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1955 "movhu"
1956 {
1957 int srcreg, dstreg;
1958
1959 PC = cia;
1960 srcreg = translate_rreg (SD_, RM2);
1961 dstreg = translate_rreg (SD_, RN0);
1962 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1963 }
1964
1965 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1966 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1967 "mov"
1968 *am33
1969 {
1970 int srcreg, dstreg;
1971
1972 PC = cia;
1973 srcreg = translate_rreg (SD_, RM0);
1974 dstreg = translate_rreg (SD_, RN2);
1975 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1976 State.regs[srcreg] += 4;
1977 }
1978
1979 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1980 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1981 "mov"
1982 {
1983 int srcreg, dstreg;
1984
1985 PC = cia;
1986 srcreg = translate_rreg (SD_, RM2);
1987 dstreg = translate_rreg (SD_, RN0);
1988 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1989 State.regs[dstreg] += 4;
1990 }
1991
1992
1993 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1994 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1995 "mov"
1996 {
1997 int dstreg;
1998
1999 PC = cia;
2000 dstreg = translate_rreg (SD_, RN2);
2001 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2002 }
2003
2004 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2005 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2006 "mov"
2007 {
2008 int srcreg;
2009
2010 PC = cia;
2011 srcreg = translate_rreg (SD_, RM2);
2012 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2013 }
2014
2015 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2016 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2017 "movbu"
2018 {
2019 int dstreg;
2020
2021 PC = cia;
2022 dstreg = translate_rreg (SD_, RN2);
2023 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2024 }
2025
2026 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2027 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2028 "movbu"
2029 {
2030 int srcreg;
2031
2032 PC = cia;
2033 srcreg = translate_rreg (SD_, RM2);
2034 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2035 }
2036
2037 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2038 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2039 "movhu"
2040 {
2041 int dstreg;
2042
2043 PC = cia;
2044 dstreg = translate_rreg (SD_, RN2);
2045 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2046 }
2047
2048 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2049 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2050 "movhu"
2051 {
2052 int srcreg;
2053
2054 PC = cia;
2055 srcreg = translate_rreg (SD_, RM2);
2056 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2057 }
2058
2059 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2060 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2061 "movhu"
2062 *am33
2063 {
2064 int srcreg, dstreg;
2065
2066 PC = cia;
2067 srcreg = translate_rreg (SD_, RM0);
2068 dstreg = translate_rreg (SD_, RN2);
2069 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2070 State.regs[srcreg] += 2;
2071 }
2072
2073 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2074 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2075 "movhu"
2076 {
2077 int srcreg, dstreg;
2078
2079 PC = cia;
2080 srcreg = translate_rreg (SD_, RM2);
2081 dstreg = translate_rreg (SD_, RN0);
2082 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2083 State.regs[dstreg] += 2;
2084 }
2085
2086
2087 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2088 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2089 "mac"
2090 {
2091 int srcreg;
2092 long long temp, sum;
2093 int c, v;
2094
2095 PC = cia;
2096 srcreg = translate_rreg (SD_, RN2);
2097
2098 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2099 * (signed64)(signed32)State.regs[srcreg]);
2100 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2101 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2102 State.regs[REG_MCRL] = sum;
2103 temp >>= 32;
2104 temp &= 0xffffffff;
2105 sum = State.regs[REG_MCRH] + temp + c;
2106 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2107 && (temp & 0x80000000) != (sum & 0x80000000));
2108 State.regs[REG_MCRH] = sum;
2109 if (v)
2110 State.regs[REG_MCVF] = 1;
2111 }
2112
2113 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2114 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2115 "macu"
2116 {
2117 int srcreg;
2118 long long temp, sum;
2119 int c, v;
2120
2121 PC = cia;
2122 srcreg = translate_rreg (SD_, RN2);
2123
2124 temp = ((unsigned64) (IMM8)
2125 * (unsigned64)State.regs[srcreg]);
2126 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2127 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2128 State.regs[REG_MCRL] = sum;
2129 temp >>= 32;
2130 temp &= 0xffffffff;
2131 sum = State.regs[REG_MCRH] + temp + c;
2132 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2133 && (temp & 0x80000000) != (sum & 0x80000000));
2134 State.regs[REG_MCRH] = sum;
2135 if (v)
2136 State.regs[REG_MCVF] = 1;
2137 }
2138
2139 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2140 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2141 "macb"
2142 {
2143 int srcreg;
2144 long long temp, sum;
2145 int c, v;
2146
2147 PC = cia;
2148 srcreg = translate_rreg (SD_, RN2);
2149
2150 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2151 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2152 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2153 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2154 State.regs[REG_MCRL] = sum;
2155 temp >>= 32;
2156 temp &= 0xffffffff;
2157 sum = State.regs[REG_MCRH] + temp + c;
2158 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2159 && (temp & 0x80000000) != (sum & 0x80000000));
2160 State.regs[REG_MCRH] = sum;
2161 if (v)
2162 State.regs[REG_MCVF] = 1;
2163 }
2164
2165 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2166 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2167 "macbu"
2168 {
2169 int srcreg;
2170 long long temp, sum;
2171 int c, v;
2172
2173 PC = cia;
2174 srcreg = translate_rreg (SD_, RN2);
2175
2176 temp = ((unsigned64) (IMM8)
2177 * (unsigned64)State.regs[srcreg] & 0xff);
2178 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2179 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2180 State.regs[REG_MCRL] = sum;
2181 temp >>= 32;
2182 temp &= 0xffffffff;
2183 sum = State.regs[REG_MCRH] + temp + c;
2184 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2185 && (temp & 0x80000000) != (sum & 0x80000000));
2186 State.regs[REG_MCRH] = sum;
2187 if (v)
2188 State.regs[REG_MCVF] = 1;
2189 }
2190
2191 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2192 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2193 "mach"
2194 {
2195 int srcreg;
2196 long long temp, sum;
2197 int c, v;
2198
2199 PC = cia;
2200 srcreg = translate_rreg (SD_, RN2);
2201
2202 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2203 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2204 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2205 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2206 State.regs[REG_MCRL] = sum;
2207 temp >>= 32;
2208 temp &= 0xffffffff;
2209 sum = State.regs[REG_MCRH] + temp + c;
2210 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2211 && (temp & 0x80000000) != (sum & 0x80000000));
2212 State.regs[REG_MCRH] = sum;
2213 if (v)
2214 State.regs[REG_MCVF] = 1;
2215 }
2216
2217 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2218 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2219 "machu"
2220 {
2221 int srcreg;
2222 long long temp, sum;
2223 int c, v;
2224
2225 PC = cia;
2226 srcreg = translate_rreg (SD_, RN2);
2227
2228 temp = ((unsigned64) (IMM8)
2229 * (unsigned64)State.regs[srcreg] & 0xffff);
2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2233 temp >>= 32;
2234 temp &= 0xffffffff;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2239 if (v)
2240 State.regs[REG_MCVF] = 1;
2241 }
2242
2243 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2244 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2245 "mcste"
2246 {
2247 int dstreg;
2248
2249 PC = cia;
2250 dstreg = translate_rreg (SD_, RN0);
2251
2252 PSW &= ~(PSW_V | PSW_C);
2253 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2254
2255 /* 32bit saturation. */
2256 if (IMM8 == 0x20)
2257 {
2258 long long tmp;
2259
2260 tmp = State.regs[REG_MCRH];
2261 tmp <<= 32;
2262 tmp += State.regs[REG_MCRL];
2263
2264 if (tmp > 0x7fffffff)
2265 State.regs[dstreg] = 0x7fffffff;
2266 else if (tmp < 0xffffffff80000000LL)
2267 State.regs[dstreg] = 0x80000000;
2268 else
2269 State.regs[dstreg] = tmp;
2270 }
2271 /* 16bit saturation */
2272 else if (IMM8 == 0x10)
2273 {
2274 long long tmp;
2275
2276 tmp = State.regs[REG_MCRH];
2277 tmp <<= 32;
2278 tmp += State.regs[REG_MCRL];
2279
2280 if (tmp > 0x7fff)
2281 State.regs[dstreg] = 0x7fff;
2282 else if (tmp < 0xffffffffffff8000LL)
2283 State.regs[dstreg] = 0x8000;
2284 else
2285 State.regs[dstreg] = tmp;
2286 }
2287 /* 8 bit saturation */
2288 else if (IMM8 == 0x8)
2289 {
2290 long long tmp;
2291
2292 tmp = State.regs[REG_MCRH];
2293 tmp <<= 32;
2294 tmp += State.regs[REG_MCRL];
2295
2296 if (tmp > 0x7f)
2297 State.regs[dstreg] = 0x7f;
2298 else if (tmp < 0xffffffffffffff80LL)
2299 State.regs[dstreg] = 0x80;
2300 else
2301 State.regs[dstreg] = tmp;
2302 }
2303 /* 9 bit saturation */
2304 else if (IMM8 == 0x9)
2305 {
2306 long long tmp;
2307
2308 tmp = State.regs[REG_MCRH];
2309 tmp <<= 32;
2310 tmp += State.regs[REG_MCRL];
2311
2312 if (tmp > 0x80)
2313 State.regs[dstreg] = 0x80;
2314 else if (tmp < 0xffffffffffffff81LL)
2315 State.regs[dstreg] = 0x81;
2316 else
2317 State.regs[dstreg] = tmp;
2318 }
2319 /* 9 bit saturation */
2320 else if (IMM8 == 0x30)
2321 {
2322 long long tmp;
2323
2324 tmp = State.regs[REG_MCRH];
2325 tmp <<= 32;
2326 tmp += State.regs[REG_MCRL];
2327
2328 if (tmp > 0x7fffffffffffLL)
2329 tmp = 0x7fffffffffffLL;
2330 else if (tmp < 0xffff800000000000LL)
2331 tmp = 0xffff800000000000LL;
2332
2333 tmp >>= 16;
2334 State.regs[dstreg] = tmp;
2335 }
2336 }
2337
2338 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2339 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2340 "add"
2341 *am33
2342 {
2343 int z, c, n, v;
2344 unsigned long sum, source1, source2;
2345 int srcreg1, srcreg2, dstreg;
2346
2347 PC = cia;
2348 srcreg1 = translate_rreg (SD_, RM2);
2349 srcreg2 = translate_rreg (SD_, RN0);
2350 dstreg = translate_rreg (SD_, RD0);
2351
2352 source1 = State.regs[srcreg1];
2353 source2 = State.regs[srcreg2];
2354 sum = source1 + source2;
2355 State.regs[dstreg] = sum;
2356
2357 z = (sum == 0);
2358 n = (sum & 0x80000000);
2359 c = (sum < source1) || (sum < source2);
2360 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2361 && (source1 & 0x80000000) != (sum & 0x80000000));
2362
2363 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2364 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2365 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2366 }
2367
2368 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2369 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2370 "addc"
2371 *am33
2372 {
2373 int z, c, n, v;
2374 unsigned long sum, source1, source2;
2375 int srcreg1, srcreg2, dstreg;
2376
2377 PC = cia;
2378 srcreg1 = translate_rreg (SD_, RM2);
2379 srcreg2 = translate_rreg (SD_, RN0);
2380 dstreg = translate_rreg (SD_, RD0);
2381
2382 source1 = State.regs[srcreg1];
2383 source2 = State.regs[srcreg2];
2384 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2385 State.regs[dstreg] = sum;
2386
2387 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2388 n = (sum & 0x80000000);
2389 c = (sum < source1) || (sum < source2);
2390 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2391 && (source1 & 0x80000000) != (sum & 0x80000000));
2392
2393 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2394 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2395 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2396 }
2397
2398 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2399 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2400 "sub"
2401 *am33
2402 {
2403 int z, c, n, v;
2404 unsigned long difference, source1, source2;
2405 int srcreg1, srcreg2, dstreg;
2406
2407 PC = cia;
2408 srcreg1 = translate_rreg (SD_, RM2);
2409 srcreg2 = translate_rreg (SD_, RN0);
2410 dstreg = translate_rreg (SD_, RD0);
2411
2412 source1 = State.regs[srcreg1];
2413 source2 = State.regs[srcreg2];
2414 difference = source2 - source1;
2415 State.regs[dstreg] = difference;
2416
2417 z = (difference == 0);
2418 n = (difference & 0x80000000);
2419 c = (source1 > source1);
2420 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2421 && (source1 & 0x80000000) != (difference & 0x80000000));
2422
2423 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2424 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2425 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2426 }
2427
2428 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2429 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2430 "subc"
2431 *am33
2432 {
2433 int z, c, n, v;
2434 unsigned long difference, source1, source2;
2435 int srcreg1, srcreg2, dstreg;
2436
2437 PC = cia;
2438 srcreg1 = translate_rreg (SD_, RM2);
2439 srcreg2 = translate_rreg (SD_, RN0);
2440 dstreg = translate_rreg (SD_, RD0);
2441
2442 source1 = State.regs[srcreg1];
2443 source2 = State.regs[srcreg2];
2444 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2445 State.regs[dstreg] = difference;
2446
2447 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2448 n = (difference & 0x80000000);
2449 c = (source1 > source2);
2450 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2451 && (source1 & 0x80000000) != (difference & 0x80000000));
2452
2453 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2454 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2455 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2456 }
2457
2458 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2459 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2460 "and"
2461 *am33
2462 {
2463 int z, n;
2464 int srcreg1, srcreg2, dstreg;
2465
2466 PC = cia;
2467 srcreg1 = translate_rreg (SD_, RM2);
2468 srcreg2 = translate_rreg (SD_, RN0);
2469 dstreg = translate_rreg (SD_, RD0);
2470
2471 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2472
2473 z = (State.regs[dstreg] == 0);
2474 n = (State.regs[dstreg] & 0x80000000);
2475
2476 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2477 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2478 }
2479
2480 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2481 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2482 "or"
2483 *am33
2484 {
2485 int z, n;
2486 int srcreg1, srcreg2, dstreg;
2487
2488 PC = cia;
2489 srcreg1 = translate_rreg (SD_, RM2);
2490 srcreg2 = translate_rreg (SD_, RN0);
2491 dstreg = translate_rreg (SD_, RD0);
2492
2493 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2494
2495 z = (State.regs[dstreg] == 0);
2496 n = (State.regs[dstreg] & 0x80000000);
2497
2498 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2499 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2500 }
2501
2502 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2503 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2504 "xor"
2505 *am33
2506 {
2507 int z, n;
2508 int srcreg1, srcreg2, dstreg;
2509
2510 PC = cia;
2511 srcreg1 = translate_rreg (SD_, RM2);
2512 srcreg2 = translate_rreg (SD_, RN0);
2513 dstreg = translate_rreg (SD_, RD0);
2514
2515 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2516
2517 z = (State.regs[dstreg] == 0);
2518 n = (State.regs[dstreg] & 0x80000000);
2519
2520 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2521 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2522 }
2523
2524 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2525 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2526 "asr"
2527 *am33
2528 {
2529 int z, c, n;
2530 long temp;
2531 int srcreg1, srcreg2, dstreg;
2532
2533 PC = cia;
2534 srcreg1 = translate_rreg (SD_, RM2);
2535 srcreg2 = translate_rreg (SD_, RN0);
2536 dstreg = translate_rreg (SD_, RD0);
2537
2538 temp = State.regs[srcreg2];
2539 c = temp & 1;
2540 temp >>= State.regs[srcreg1];
2541 State.regs[dstreg] = temp;
2542
2543 z = (State.regs[dstreg] == 0);
2544 n = (State.regs[dstreg] & 0x80000000);
2545
2546 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2547 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2548 }
2549
2550 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2551 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2552 "lsr"
2553 *am33
2554 {
2555 int z, c, n;
2556 int srcreg1, srcreg2, dstreg;
2557
2558 PC = cia;
2559 srcreg1 = translate_rreg (SD_, RM2);
2560 srcreg2 = translate_rreg (SD_, RN0);
2561 dstreg = translate_rreg (SD_, RD0);
2562
2563 c = State.regs[srcreg2] & 1;
2564 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2565
2566 z = (State.regs[dstreg] == 0);
2567 n = (State.regs[dstreg] & 0x80000000);
2568
2569 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2570 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2571 }
2572
2573 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2574 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2575 "asl"
2576 *am33
2577 {
2578 int z, n;
2579 int srcreg1, srcreg2, dstreg;
2580
2581 PC = cia;
2582 srcreg1 = translate_rreg (SD_, RM2);
2583 srcreg2 = translate_rreg (SD_, RN0);
2584 dstreg = translate_rreg (SD_, RD0);
2585
2586 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2587
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2590
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2593 }
2594
2595 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2596 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2597 "mul"
2598 *am33
2599 {
2600 int srcreg1, srcreg2, dstreg1, dstreg2;
2601 signed long long temp;
2602 int n, z;
2603
2604 PC = cia;
2605 srcreg1 = translate_rreg (SD_, RM2);
2606 srcreg2 = translate_rreg (SD_, RN0);
2607 dstreg1 = translate_rreg (SD_, RD0);
2608 dstreg2 = translate_rreg (SD_, RD2);
2609
2610 temp = ((signed64)(signed32)State.regs[srcreg1]
2611 * (signed64)(signed32)State.regs[srcreg2]);
2612 State.regs[dstreg1] = temp & 0xffffffff;
2613 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2614
2615 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2616 n = (State.regs[dstreg2] & 0x80000000);
2617
2618 PSW &= ~(PSW_Z | PSW_N);
2619 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2620 }
2621
2622 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2623 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2624 "mulu"
2625 *am33
2626 {
2627 int srcreg1, srcreg2, dstreg1, dstreg2;
2628 signed long long temp;
2629 int n, z;
2630
2631 PC = cia;
2632 srcreg1 = translate_rreg (SD_, RM2);
2633 srcreg2 = translate_rreg (SD_, RN0);
2634 dstreg1 = translate_rreg (SD_, RD0);
2635 dstreg2 = translate_rreg (SD_, RD2);
2636
2637 temp = ((unsigned64)State.regs[srcreg1]
2638 * (unsigned64)State.regs[srcreg2]);
2639 State.regs[dstreg1] = temp & 0xffffffff;
2640 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2641
2642 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2643 n = (State.regs[dstreg2] & 0x80000000);
2644
2645 PSW &= ~(PSW_Z | PSW_N);
2646 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2647 }
2648
2649 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2650 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2651 "mov"
2652 *am33
2653 {
2654 int dstreg;
2655
2656 PC = cia;
2657 dstreg = translate_rreg (SD_, RN2);
2658 State.regs[dstreg] = load_word (IMM8);
2659 }
2660
2661 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2662 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2663 "mov"
2664 *am33
2665 {
2666 int srcreg;
2667
2668 PC = cia;
2669 srcreg = translate_rreg (SD_, RM2);
2670 store_word (IMM8, State.regs[srcreg]);
2671 }
2672
2673 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2674 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2675 "movbu"
2676 *am33
2677 {
2678 int dstreg;
2679
2680 PC = cia;
2681 dstreg = translate_rreg (SD_, RN2);
2682 State.regs[dstreg] = load_byte (IMM8);
2683 }
2684
2685 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2686 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2687 "movbu"
2688 *am33
2689 {
2690 int srcreg;
2691
2692 PC = cia;
2693 srcreg = translate_rreg (SD_, RM2);
2694 store_byte (IMM8, State.regs[srcreg]);
2695 }
2696
2697 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2698 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2699 "movhu"
2700 *am33
2701 {
2702 int dstreg;
2703
2704 PC = cia;
2705 dstreg = translate_rreg (SD_, RN2);
2706 State.regs[dstreg] = load_half (IMM8);
2707 }
2708
2709 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2710 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2711 "movhu"
2712 *am33
2713 {
2714 int srcreg;
2715
2716 PC = cia;
2717 srcreg = translate_rreg (SD_, RM2);
2718 store_half (IMM8, State.regs[srcreg]);
2719 }
2720
2721 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2722 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2723 "mov"
2724 *am33
2725 {
2726 int srcreg1, srcreg2, dstreg;
2727
2728 PC = cia;
2729 srcreg1 = translate_rreg (SD_, RM0);
2730 srcreg1 = translate_rreg (SD_, RI0);
2731 dstreg = translate_rreg (SD_, RN0);
2732 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2733 }
2734
2735 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2736 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2737 "mov"
2738 *am33
2739 {
2740 int srcreg, dstreg1, dstreg2;
2741
2742 PC = cia;
2743 srcreg = translate_rreg (SD_, RM0);
2744 dstreg1 = translate_rreg (SD_, RI0);
2745 dstreg2 = translate_rreg (SD_, RN0);
2746 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2747 }
2748
2749 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2750 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2751 "movbu"
2752 *am33
2753 {
2754 int srcreg1, srcreg2, dstreg;
2755
2756 PC = cia;
2757 srcreg1 = translate_rreg (SD_, RM0);
2758 srcreg1 = translate_rreg (SD_, RI0);
2759 dstreg = translate_rreg (SD_, RN0);
2760 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2761 }
2762
2763 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2764 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2765 "movbu"
2766 *am33
2767 {
2768 int srcreg, dstreg1, dstreg2;
2769
2770 PC = cia;
2771 srcreg = translate_rreg (SD_, RM0);
2772 dstreg1 = translate_rreg (SD_, RI0);
2773 dstreg2 = translate_rreg (SD_, RN0);
2774 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2775 }
2776
2777 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2778 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2779 "movhu"
2780 *am33
2781 {
2782 int srcreg1, srcreg2, dstreg;
2783
2784 PC = cia;
2785 srcreg1 = translate_rreg (SD_, RM0);
2786 srcreg1 = translate_rreg (SD_, RI0);
2787 dstreg = translate_rreg (SD_, RN0);
2788 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2789 }
2790
2791 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2792 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2793 "movhu"
2794 *am33
2795 {
2796 int srcreg, dstreg1, dstreg2;
2797
2798 PC = cia;
2799 srcreg = translate_rreg (SD_, RM0);
2800 dstreg1 = translate_rreg (SD_, RI0);
2801 dstreg2 = translate_rreg (SD_, RN0);
2802 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2803 }
2804
2805 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2806 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2807 "mac"
2808 *am33
2809 {
2810 int srcreg1, srcreg2, dstreg1, dstreg2;
2811 signed long long temp;
2812 unsigned long sum;
2813 int c, v;
2814
2815 PC = cia;
2816 srcreg1 = translate_rreg (SD_, RM2);
2817 srcreg2 = translate_rreg (SD_, RN0);
2818 dstreg1 = translate_rreg (SD_, RD0);
2819 dstreg2 = translate_rreg (SD_, RD2);
2820
2821 temp = ((signed64)(signed32)State.regs[srcreg1]
2822 * (signed64)(signed32)State.regs[srcreg2]);
2823
2824 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2825 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2826 State.regs[dstreg2] = sum;
2827 temp >>= 32;
2828 temp &= 0xffffffff;
2829 sum = State.regs[dstreg1] + temp + c;
2830 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2831 && (temp & 0x80000000) != (sum & 0x80000000));
2832 State.regs[dstreg1] = sum;
2833 if (v)
2834 {
2835 State.regs[REG_MCVF] = 1;
2836 PSW &= ~(PSW_V);
2837 PSW |= (( v ? PSW_V : 0));
2838 }
2839 }
2840
2841 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2842 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2843 "macu"
2844 *am33
2845 {
2846 int srcreg1, srcreg2, dstreg1, dstreg2;
2847 signed long long temp;
2848 unsigned long sum;
2849 int c, v;
2850
2851 PC = cia;
2852 srcreg1 = translate_rreg (SD_, RM2);
2853 srcreg2 = translate_rreg (SD_, RN0);
2854 dstreg1 = translate_rreg (SD_, RD0);
2855 dstreg2 = translate_rreg (SD_, RD2);
2856
2857 temp = ((unsigned64)State.regs[srcreg1]
2858 * (unsigned64)State.regs[srcreg2]);
2859
2860 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2861 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2862 State.regs[dstreg2] = sum;
2863 temp >>= 32;
2864 temp &= 0xffffffff;
2865 sum = State.regs[dstreg1] + temp + c;
2866 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2867 && (temp & 0x80000000) != (sum & 0x80000000));
2868 State.regs[dstreg1] = sum;
2869 if (v)
2870 {
2871 State.regs[REG_MCVF] = 1;
2872 PSW &= ~(PSW_V);
2873 PSW |= (( v ? PSW_V : 0));
2874 }
2875 }
2876
2877 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2878 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2879 "macb"
2880 *am33
2881 {
2882 int srcreg1, srcreg2, dstreg;
2883 long temp, sum;
2884 int v;
2885
2886 PC = cia;
2887 srcreg1 = translate_rreg (SD_, RM2);
2888 srcreg2 = translate_rreg (SD_, RN0);
2889 dstreg = translate_rreg (SD_, RD0);
2890
2891 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2892 * (signed32)(State.regs[srcreg1] & 0xff));
2893 sum = State.regs[dstreg] + temp;
2894 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2895 && (temp & 0x80000000) != (sum & 0x80000000));
2896 State.regs[dstreg] = sum;
2897 if (v)
2898 {
2899 State.regs[REG_MCVF] = 1;
2900 PSW &= ~(PSW_V);
2901 PSW |= ((v ? PSW_V : 0));
2902 }
2903 }
2904
2905 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2906 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2907 "macbu"
2908 *am33
2909 {
2910 int srcreg1, srcreg2, dstreg;
2911 long temp, sum;
2912 int v;
2913
2914 PC = cia;
2915 srcreg1 = translate_rreg (SD_, RM2);
2916 srcreg2 = translate_rreg (SD_, RN0);
2917 dstreg = translate_rreg (SD_, RD0);
2918
2919 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2920 * (unsigned32)(State.regs[srcreg1] & 0xff));
2921 sum = State.regs[dstreg] + temp;
2922 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2923 && (temp & 0x80000000) != (sum & 0x80000000));
2924 State.regs[dstreg] = sum;
2925 if (v)
2926 {
2927 State.regs[REG_MCVF] = 1;
2928 PSW &= ~(PSW_V);
2929 PSW |= ((v ? PSW_V : 0));
2930 }
2931 }
2932
2933 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2934 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2935 "mach"
2936 *am33
2937 {
2938 int srcreg1, srcreg2, dstreg;
2939 long temp, sum;
2940 int v;
2941
2942 PC = cia;
2943 srcreg1 = translate_rreg (SD_, RM2);
2944 srcreg2 = translate_rreg (SD_, RN0);
2945 dstreg = translate_rreg (SD_, RD0);
2946
2947 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2948 * (signed32)(State.regs[srcreg1] & 0xffff));
2949 sum = State.regs[dstreg] + temp;
2950 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2951 && (temp & 0x80000000) != (sum & 0x80000000));
2952 State.regs[dstreg] = sum;
2953 if (v)
2954 {
2955 State.regs[REG_MCVF] = 1;
2956 PSW &= ~(PSW_V);
2957 PSW |= ((v ? PSW_V : 0));
2958 }
2959 }
2960
2961 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2962 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2963 "machu"
2964 *am33
2965 {
2966 int srcreg1, srcreg2, dstreg;
2967 long temp, sum;
2968 int v;
2969
2970 PC = cia;
2971 srcreg1 = translate_rreg (SD_, RM2);
2972 srcreg2 = translate_rreg (SD_, RN0);
2973 dstreg = translate_rreg (SD_, RD0);
2974
2975 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2976 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2977 sum = State.regs[dstreg] + temp;
2978 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2979 && (temp & 0x80000000) != (sum & 0x80000000));
2980 State.regs[dstreg] = sum;
2981 if (v)
2982 {
2983 State.regs[REG_MCVF] = 1;
2984 PSW &= ~(PSW_V);
2985 PSW |= ((v ? PSW_V : 0));
2986 }
2987 }
2988
2989 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2990 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2991 "dmach"
2992 *am33
2993 {
2994 int srcreg1, srcreg2, dstreg;
2995 long temp, temp2, sum;
2996 int v;
2997
2998 PC = cia;
2999 srcreg1 = translate_rreg (SD_, RM2);
3000 srcreg2 = translate_rreg (SD_, RN0);
3001 dstreg = translate_rreg (SD_, RD0);
3002
3003 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3004 * (signed32)(State.regs[srcreg1] & 0xffff));
3005 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3006 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3007 sum = temp + temp2 + State.regs[dstreg];
3008 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3009 && (temp & 0x80000000) != (sum & 0x80000000));
3010 State.regs[dstreg] = sum;
3011 if (v)
3012 {
3013 State.regs[REG_MCVF] = 1;
3014 PSW &= ~(PSW_V);
3015 PSW |= ((v ? PSW_V : 0));
3016 }
3017 }
3018
3019 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3020 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3021 "dmachu"
3022 *am33
3023 {
3024 int srcreg1, srcreg2, dstreg;
3025 long temp, temp2, sum;
3026 int v;
3027
3028 PC = cia;
3029 srcreg1 = translate_rreg (SD_, RM2);
3030 srcreg2 = translate_rreg (SD_, RN0);
3031 dstreg = translate_rreg (SD_, RD0);
3032
3033 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3034 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3035 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3036 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3037 sum = temp + temp2 + State.regs[dstreg];
3038 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3039 && (temp & 0x80000000) != (sum & 0x80000000));
3040 State.regs[dstreg] = sum;
3041 if (v)
3042 {
3043 State.regs[REG_MCVF] = 1;
3044 PSW &= ~(PSW_V);
3045 PSW |= ((v ? PSW_V : 0));
3046 }
3047 }
3048
3049 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3050 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3051 "dmulh"
3052 *am33
3053 {
3054 int srcreg1, srcreg2, dstreg1, dstreg2;
3055 signed long long temp;
3056
3057 PC = cia;
3058 srcreg1 = translate_rreg (SD_, RM2);
3059 srcreg2 = translate_rreg (SD_, RN0);
3060 dstreg1 = translate_rreg (SD_, RD0);
3061 dstreg2 = translate_rreg (SD_, RD2);
3062
3063 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3064 * (signed32)(State.regs[srcreg1] & 0xffff));
3065 State.regs[dstreg2] = temp;
3066 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3067 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3068 State.regs[dstreg1] = temp;
3069 }
3070
3071 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3072 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3073 "dmulhu"
3074 *am33
3075 {
3076 int srcreg1, srcreg2, dstreg1, dstreg2;
3077 signed long long temp;
3078
3079 PC = cia;
3080 srcreg1 = translate_rreg (SD_, RM2);
3081 srcreg2 = translate_rreg (SD_, RN0);
3082 dstreg1 = translate_rreg (SD_, RD0);
3083 dstreg2 = translate_rreg (SD_, RD2);
3084
3085 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3086 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3087 State.regs[dstreg2] = temp;
3088 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3089 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3090 State.regs[dstreg1] = temp;
3091 }
3092
3093 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3094 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3095 "sat24"
3096 *am33
3097 {
3098 int srcreg, dstreg;
3099 int value, n, z;
3100
3101 PC = cia;
3102 srcreg = translate_rreg (SD_, RM2);
3103 dstreg = translate_rreg (SD_, RN0);
3104
3105 value = State.regs[srcreg];
3106
3107 if (value >= 0x7fffff)
3108 State.regs[dstreg] = 0x7fffff;
3109 else if (value <= 0xff800000)
3110 State.regs[dstreg] = 0xff800000;
3111 else
3112 State.regs[dstreg] = value;
3113
3114 n = (State.regs[dstreg] & 0x800000) != 0;
3115 z = (State.regs[dstreg] == 0);
3116 PSW &= ~(PSW_Z | PSW_N);
3117 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3118 }
3119
3120 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3121 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3122 "bsch"
3123 *am33
3124 {
3125 int temp, c, i;
3126 int srcreg1, srcreg2, dstreg;
3127 int start;
3128
3129 PC = cia;
3130 srcreg1 = translate_rreg (SD_, RM2);
3131 srcreg2 = translate_rreg (SD_, RN0);
3132 dstreg = translate_rreg (SD_, RD0);
3133
3134 temp = State.regs[srcreg1];
3135 start = (State.regs[srcreg2] & 0x1f) - 1;
3136 if (start == -1)
3137 start = 31;
3138
3139 for (i = start; i >= 0; i--)
3140 {
3141 if (temp & (1 << i))
3142 {
3143 c = 1;
3144 State.regs[dstreg] = i;
3145 break;
3146 }
3147 }
3148
3149 if (i < 0)
3150 {
3151 c = 0;
3152 State.regs[dstreg] = 0;
3153 }
3154 PSW &= ~(PSW_C);
3155 PSW |= (c ? PSW_C : 0);
3156 }
3157
3158 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3159 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3160 "mov"
3161 *am33
3162 {
3163 int dstreg;
3164
3165 PC = cia;
3166 dstreg = translate_rreg (SD_, RN0);
3167 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3168 }
3169
3170 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3171 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3172 "movu"
3173 *am33
3174 {
3175 int dstreg;
3176
3177 PC = cia;
3178 dstreg = translate_rreg (SD_, RN0);
3179 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3180 }
3181
3182 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3183 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3184 "add"
3185 *am33
3186 {
3187 int dstreg;
3188
3189 PC = cia;
3190 dstreg = translate_rreg (SD_, RN0);
3191 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3192 }
3193
3194 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3195 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3196 "addc"
3197 *am33
3198 {
3199 int dstreg, z, n, c, v;
3200 unsigned long sum, imm, reg2;
3201
3202 PC = cia;
3203 dstreg = translate_rreg (SD_, RN0);
3204
3205 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3206 reg2 = State.regs[dstreg];
3207 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3208 State.regs[dstreg] = sum;
3209
3210 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3211 n = (sum & 0x80000000);
3212 c = (sum < imm) || (sum < reg2);
3213 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3214 && (reg2 & 0x80000000) != (sum & 0x80000000));
3215
3216 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3217 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3218 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3219 }
3220
3221 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3222 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3223 "sub"
3224 *am33
3225 {
3226 int dstreg;
3227
3228 PC = cia;
3229 dstreg = translate_rreg (SD_, RN0);
3230 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3231 }
3232
3233 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3234 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3235 "subc"
3236 *am33
3237 {
3238 int dstreg, z, n, c, v;
3239 unsigned long difference, imm, reg2;
3240
3241 PC = cia;
3242 dstreg = translate_rreg (SD_, RN0);
3243
3244 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3245 reg2 = State.regs[dstreg];
3246 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3247 State.regs[dstreg] = difference;
3248
3249 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3250 n = (difference & 0x80000000);
3251 c = (imm > reg2);
3252 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3253 && (reg2 & 0x80000000) != (difference & 0x80000000));
3254
3255 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3256 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3257 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3258 }
3259
3260 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3261 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3262 "cmp"
3263 *am33
3264 {
3265 int srcreg;
3266
3267 PC = cia;
3268 srcreg = translate_rreg (SD_, RN0);
3269 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3270 }
3271
3272 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3273 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3274 "mov"
3275 *am33
3276 {
3277 PC = cia;
3278
3279 if (XRN0 == 0)
3280 {
3281 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3282 }
3283 else
3284 abort ();
3285 }
3286
3287 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3288 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3289 "and"
3290 *am33
3291 {
3292 int dstreg;
3293 int z,n;
3294
3295 PC = cia;
3296 dstreg = translate_rreg (SD_, RN0);
3297
3298 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3299 z = (State.regs[dstreg] == 0);
3300 n = (State.regs[dstreg] & 0x80000000) != 0;
3301 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3302 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3303 }
3304
3305 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3306 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3307 "or"
3308 *am33
3309 {
3310 int dstreg;
3311 int z,n;
3312
3313 PC = cia;
3314 dstreg = translate_rreg (SD_, RN0);
3315
3316 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3317 z = (State.regs[dstreg] == 0);
3318 n = (State.regs[dstreg] & 0x80000000) != 0;
3319 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3320 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3321 }
3322
3323 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3324 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3325 "xor"
3326 *am33
3327 {
3328 int dstreg;
3329 int z,n;
3330
3331 PC = cia;
3332 dstreg = translate_rreg (SD_, RN0);
3333
3334 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3335 z = (State.regs[dstreg] == 0);
3336 n = (State.regs[dstreg] & 0x80000000) != 0;
3337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3338 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3339 }
3340
3341 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3342 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3343 "asr"
3344 *am33
3345 {
3346 int dstreg;
3347 long temp;
3348 int c, z, n;
3349
3350 PC = cia;
3351 dstreg = translate_rreg (SD_, RN0);
3352
3353 temp = State.regs[dstreg];
3354 c = temp & 1;
3355 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3356 State.regs[dstreg] = temp;
3357 z = (State.regs[dstreg] == 0);
3358 n = (State.regs[dstreg] & 0x80000000) != 0;
3359 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3360 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3361 }
3362
3363
3364 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3365 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3366 "lsr"
3367 *am33
3368 {
3369 int dstreg;
3370 int z, n, c;
3371
3372 PC = cia;
3373 dstreg = translate_rreg (SD_, RN0);
3374
3375 c = State.regs[dstreg] & 1;
3376 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3377 z = (State.regs[dstreg] == 0);
3378 n = (State.regs[dstreg] & 0x80000000) != 0;
3379 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3380 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3381 }
3382
3383 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3384 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3385 "asl"
3386 *am33
3387 {
3388 int srcreg, dstreg;
3389 int z, n;
3390
3391 PC = cia;
3392 dstreg = translate_rreg (SD_, RN0);
3393
3394 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3395 z = (State.regs[dstreg] == 0);
3396 n = (State.regs[dstreg] & 0x80000000) != 0;
3397 PSW &= ~(PSW_Z | PSW_N);
3398 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3399 }
3400
3401 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3402 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3403 "mul"
3404 *am33
3405 {
3406 int dstreg;
3407 unsigned long long temp;
3408 int z, n;
3409
3410 PC = cia;
3411 dstreg = translate_rreg (SD_, RN0);
3412
3413 temp = ((signed64)(signed32)State.regs[dstreg]
3414 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3415 State.regs[dstreg] = temp & 0xffffffff;
3416 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3417 z = (State.regs[dstreg] == 0);
3418 n = (State.regs[dstreg] & 0x80000000) != 0;
3419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3421 }
3422
3423 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3424 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3425 "mulu"
3426 *am33
3427 {
3428 int dstreg;
3429 unsigned long long temp;
3430 int z, n;
3431
3432 PC = cia;
3433 dstreg = translate_rreg (SD_, RN0);
3434
3435 temp = ((unsigned64)State.regs[dstreg]
3436 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3437 State.regs[dstreg] = temp & 0xffffffff;
3438 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3439 z = (State.regs[dstreg] == 0);
3440 n = (State.regs[dstreg] & 0x80000000) != 0;
3441 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3442 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3443 }
3444
3445 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3446 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3447 "btst"
3448 *am33
3449 {
3450 int srcreg;
3451
3452 PC = cia;
3453 srcreg = translate_rreg (SD_, RN0);
3454 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3455 }
3456
3457 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3458 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3459 "mov"
3460 *am33
3461 {
3462 int srcreg, dstreg;
3463
3464 PC = cia;
3465 srcreg = translate_rreg (SD_, RM0);
3466 dstreg = translate_rreg (SD_, RN2);
3467 State.regs[dstreg] = load_word (State.regs[srcreg]
3468 + EXTEND24 (FETCH24 (IMM24A,
3469 IMM24B, IMM24C)));
3470 }
3471
3472 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3473 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3474 "mov"
3475 *am33
3476 {
3477 int srcreg, dstreg;
3478
3479 PC = cia;
3480 srcreg = translate_rreg (SD_, RM2);
3481 dstreg = translate_rreg (SD_, RN0);
3482 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3483 State.regs[srcreg]);
3484 }
3485
3486 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3487 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3488 "movbu"
3489 *am33
3490 {
3491 int srcreg, dstreg;
3492
3493 PC = cia;
3494 srcreg = translate_rreg (SD_, RM0);
3495 dstreg = translate_rreg (SD_, RN2);
3496 State.regs[dstreg] = load_byte (State.regs[srcreg]
3497 + EXTEND24 (FETCH24 (IMM24A,
3498 IMM24B, IMM24C)));
3499 }
3500
3501 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3502 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3503 "movbu"
3504 *am33
3505 {
3506 int srcreg, dstreg;
3507
3508 PC = cia;
3509 srcreg = translate_rreg (SD_, RM2);
3510 dstreg = translate_rreg (SD_, RN0);
3511 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3512 State.regs[srcreg]);
3513 }
3514
3515 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3516 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3517 "movhu"
3518 *am33
3519 {
3520 int srcreg, dstreg;
3521
3522 PC = cia;
3523 srcreg = translate_rreg (SD_, RM0);
3524 dstreg = translate_rreg (SD_, RN2);
3525 State.regs[dstreg] = load_half (State.regs[srcreg]
3526 + EXTEND24 (FETCH24 (IMM24A,
3527 IMM24B, IMM24C)));
3528 }
3529
3530 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3531 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3532 "movhu"
3533 *am33
3534 {
3535 int srcreg, dstreg;
3536
3537 PC = cia;
3538 srcreg = translate_rreg (SD_, RM2);
3539 dstreg = translate_rreg (SD_, RN0);
3540 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3541 State.regs[srcreg]);
3542 }
3543
3544 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3545 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3546 "mov"
3547 *am33
3548 {
3549 int srcreg, dstreg;
3550
3551 PC = cia;
3552 srcreg = translate_rreg (SD_, RM0);
3553 dstreg = translate_rreg (SD_, RN2);
3554 State.regs[dstreg] = load_word (State.regs[srcreg]
3555 + EXTEND24 (FETCH24 (IMM24A,
3556 IMM24B, IMM24C)));
3557 State.regs[srcreg] += 4;
3558 }
3559
3560 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3561 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3562 "mov"
3563 *am33
3564 {
3565 int srcreg, dstreg;
3566
3567 PC = cia;
3568 srcreg = translate_rreg (SD_, RM2);
3569 dstreg = translate_rreg (SD_, RN0);
3570 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3571 State.regs[srcreg]);
3572 State.regs[dstreg] += 4;
3573 }
3574
3575
3576 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3577 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3578 "mov"
3579 *am33
3580 {
3581 int dstreg;
3582
3583 PC = cia;
3584 dstreg = translate_rreg (SD_, RN2);
3585 State.regs[dstreg] = load_word (State.regs[REG_SP]
3586 + EXTEND24 (FETCH24 (IMM24A,
3587 IMM24B, IMM24C)));
3588 }
3589
3590 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3591 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3592 "mov"
3593 *am33
3594 {
3595 int srcreg;
3596
3597 PC = cia;
3598 srcreg = translate_rreg (SD_, RM2);
3599 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3600 State.regs[srcreg]);
3601 }
3602
3603 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3604 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3605 "movbu"
3606 *am33
3607 {
3608 int dstreg;
3609
3610 PC = cia;
3611 dstreg = translate_rreg (SD_, RN2);
3612 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3613 + EXTEND24 (FETCH24 (IMM24A,
3614 IMM24B, IMM24C)));
3615 }
3616
3617 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3618 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3619 "movbu"
3620 *am33
3621 {
3622 int srcreg;
3623
3624 PC = cia;
3625 srcreg = translate_rreg (SD_, RM2);
3626 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3627 State.regs[srcreg]);
3628 }
3629
3630 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3631 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3632 "movhu"
3633 *am33
3634 {
3635 int dstreg;
3636
3637 PC = cia;
3638 dstreg = translate_rreg (SD_, RN2);
3639 State.regs[dstreg] = load_half (State.regs[REG_SP]
3640 + EXTEND24 (FETCH24 (IMM24A,
3641 IMM24B, IMM24C)));
3642 }
3643
3644 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3645 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3646 "movhu"
3647 *am33
3648 {
3649 int srcreg;
3650
3651 PC = cia;
3652 srcreg = translate_rreg (SD_, RM2);
3653 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3654 State.regs[srcreg]);
3655 }
3656
3657 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3658 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3659 "movhu"
3660 *am33
3661 {
3662 int srcreg, dstreg;
3663
3664 PC = cia;
3665 srcreg = translate_rreg (SD_, RM0);
3666 dstreg = translate_rreg (SD_, RN2);
3667 State.regs[dstreg] = load_half (State.regs[srcreg]
3668 + EXTEND24 (FETCH24 (IMM24A,
3669 IMM24B, IMM24C)));
3670 State.regs[dstreg] += 2;
3671 }
3672
3673 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3674 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3675 "movhu"
3676 *am33
3677 {
3678 int srcreg, dstreg;
3679
3680 PC = cia;
3681 srcreg = translate_rreg (SD_, RM2);
3682 dstreg = translate_rreg (SD_, RN0);
3683 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3684 State.regs[srcreg]);
3685 State.regs[srcreg] += 2;
3686 }
3687
3688 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3689 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3690 "mac"
3691 *am33
3692 {
3693 int srcreg;
3694 long long temp, sum;
3695 int c, v;
3696
3697 PC = cia;
3698 srcreg = translate_rreg (SD_, RN2);
3699
3700 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3701 * (signed64)State.regs[srcreg]);
3702 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3703 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3704 State.regs[REG_MCRL] = sum;
3705 temp >>= 32;
3706 temp &= 0xffffffff;
3707 sum = State.regs[REG_MCRH] + temp + c;
3708 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3709 && (temp & 0x80000000) != (sum & 0x80000000));
3710 State.regs[REG_MCRH] = sum;
3711 if (v)
3712 State.regs[REG_MCVF] = 1;
3713 }
3714
3715 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3716 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3717 "macu"
3718 *am33
3719 {
3720 int srcreg;
3721 long long temp, sum;
3722 int c, v;
3723
3724 PC = cia;
3725 srcreg = translate_rreg (SD_, RN2);
3726
3727 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3728 * (unsigned64)State.regs[srcreg]);
3729 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3730 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3731 State.regs[REG_MCRL] = sum;
3732 temp >>= 32;
3733 temp &= 0xffffffff;
3734 sum = State.regs[REG_MCRH] + temp + c;
3735 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3736 && (temp & 0x80000000) != (sum & 0x80000000));
3737 State.regs[REG_MCRH] = sum;
3738 if (v)
3739 State.regs[REG_MCVF] = 1;
3740 }
3741
3742 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3743 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3744 "macb"
3745 *am33
3746 {
3747 int srcreg;
3748 long long temp, sum;
3749 int c, v;
3750
3751 PC = cia;
3752 srcreg = translate_rreg (SD_, RN2);
3753
3754 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3755 * (signed64)State.regs[srcreg] & 0xff);
3756 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3757 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3758 State.regs[REG_MCRL] = sum;
3759 temp >>= 32;
3760 temp &= 0xffffffff;
3761 sum = State.regs[REG_MCRH] + temp + c;
3762 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3763 && (temp & 0x80000000) != (sum & 0x80000000));
3764 State.regs[REG_MCRH] = sum;
3765 if (v)
3766 State.regs[REG_MCVF] = 1;
3767 }
3768
3769 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3770 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3771 "macbu"
3772 *am33
3773 {
3774 int srcreg;
3775 long long temp, sum;
3776 int c, v;
3777
3778 PC = cia;
3779 srcreg = translate_rreg (SD_, RN2);
3780
3781 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3782 * (unsigned64)State.regs[srcreg] & 0xff);
3783 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3784 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3785 State.regs[REG_MCRL] = sum;
3786 temp >>= 32;
3787 temp &= 0xffffffff;
3788 sum = State.regs[REG_MCRH] + temp + c;
3789 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3790 && (temp & 0x80000000) != (sum & 0x80000000));
3791 State.regs[REG_MCRH] = sum;
3792 if (v)
3793 State.regs[REG_MCVF] = 1;
3794 }
3795
3796 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3797 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3798 "mach"
3799 *am33
3800 {
3801 int srcreg;
3802 long long temp, sum;
3803 int c, v;
3804
3805 PC = cia;
3806 srcreg = translate_rreg (SD_, RN2);
3807
3808 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3809 * (signed64)State.regs[srcreg] & 0xffff);
3810 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3811 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3812 State.regs[REG_MCRL] = sum;
3813 temp >>= 32;
3814 temp &= 0xffffffff;
3815 sum = State.regs[REG_MCRH] + temp + c;
3816 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3817 && (temp & 0x80000000) != (sum & 0x80000000));
3818 State.regs[REG_MCRH] = sum;
3819 if (v)
3820 State.regs[REG_MCVF] = 1;
3821 }
3822
3823 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3824 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3825 "machu"
3826 *am33
3827 {
3828 int srcreg;
3829 long long temp, sum;
3830 int c, v;
3831
3832 PC = cia;
3833 srcreg = translate_rreg (SD_, RN2);
3834
3835 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3836 * (unsigned64)State.regs[srcreg] & 0xffff);
3837 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3838 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3839 State.regs[REG_MCRL] = sum;
3840 temp >>= 32;
3841 temp &= 0xffffffff;
3842 sum = State.regs[REG_MCRH] + temp + c;
3843 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3844 && (temp & 0x80000000) != (sum & 0x80000000));
3845 State.regs[REG_MCRH] = sum;
3846 if (v)
3847 State.regs[REG_MCVF] = 1;
3848 }
3849
3850 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3851 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3852 "mov"
3853 *am33
3854 {
3855 int dstreg;
3856
3857 PC = cia;
3858 dstreg = translate_rreg (SD_, RN2);
3859 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3860 }
3861
3862 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3863 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3864 "mov"
3865 *am33
3866 {
3867 int srcreg;
3868
3869 PC = cia;
3870 srcreg = translate_rreg (SD_, RM2);
3871 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3872 }
3873
3874
3875 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3876 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3877 "movbu"
3878 *am33
3879 {
3880 int dstreg;
3881
3882 PC = cia;
3883 dstreg = translate_rreg (SD_, RN2);
3884 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3885 }
3886
3887 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3888 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3889 "movbu"
3890 *am33
3891 {
3892 int srcreg;
3893
3894 PC = cia;
3895 srcreg = translate_rreg (SD_, RM2);
3896 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3897 }
3898
3899
3900 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3901 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3902 "movhu"
3903 *am33
3904 {
3905 int dstreg;
3906
3907 PC = cia;
3908 dstreg = translate_rreg (SD_, RN2);
3909 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3910 }
3911
3912 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3913 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3914 "movhu"
3915 *am33
3916 {
3917 int srcreg;
3918
3919 PC = cia;
3920 srcreg = translate_rreg (SD_, RM2);
3921 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3922 }
3923
3924
3925 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3926 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3927 "mov"
3928 *am33
3929 {
3930 int dstreg;
3931
3932 PC = cia;
3933 dstreg = translate_rreg (SD_, RN0);
3934 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3935 }
3936
3937 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3938 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3939 "movu"
3940 *am33
3941 {
3942 int dstreg;
3943
3944 PC = cia;
3945 dstreg = translate_rreg (SD_, RN0);
3946 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3947 }
3948
3949 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3950 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3951 "add"
3952 *am33
3953 {
3954 int dstreg;
3955
3956 PC = cia;
3957 dstreg = translate_rreg (SD_, RN0);
3958 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3959 }
3960
3961 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3962 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3963 "addc"
3964 *am33
3965 {
3966 int dstreg;
3967 unsigned int imm, reg2, sum;
3968 int z, n, c, v;
3969
3970 PC = cia;
3971 dstreg = translate_rreg (SD_, RN0);
3972
3973 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3974 reg2 = State.regs[dstreg];
3975 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3976 State.regs[dstreg] = sum;
3977
3978 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3979 n = (sum & 0x80000000);
3980 c = (sum < imm) || (sum < reg2);
3981 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3982 && (reg2 & 0x80000000) != (sum & 0x80000000));
3983
3984 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3985 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3986 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3987 }
3988
3989 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3990 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3991 "sub"
3992 *am33
3993 {
3994 int dstreg;
3995
3996 PC = cia;
3997 dstreg = translate_rreg (SD_, RN0);
3998 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3999 }
4000
4001 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4002 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4003 "subc"
4004 *am33
4005 {
4006 int dstreg;
4007 unsigned int imm, reg2, difference;
4008 int z, n, c, v;
4009
4010 PC = cia;
4011 dstreg = translate_rreg (SD_, RN0);
4012
4013 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4014 reg2 = State.regs[dstreg];
4015 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4016 State.regs[dstreg] = difference;
4017
4018 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4019 n = (difference & 0x80000000);
4020 c = (imm > reg2);
4021 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4022 && (reg2 & 0x80000000) != (difference & 0x80000000));
4023
4024 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4025 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4026 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4027 }
4028
4029 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4030 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4031 "cmp"
4032 *am33
4033 {
4034 int srcreg;
4035
4036 PC = cia;
4037 srcreg = translate_rreg (SD_, RN0);
4038 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4039 }
4040
4041 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4042 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4043 "mov"
4044 *am33
4045 {
4046 PC = cia;
4047
4048 if (XRN0 == 0)
4049 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4050 else
4051 abort ();
4052 }
4053
4054 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4055 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4056 "and"
4057 *am33
4058 {
4059 int dstreg;
4060 int z,n;
4061
4062 PC = cia;
4063 dstreg = translate_rreg (SD_, RN0);
4064
4065 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4066 z = (State.regs[dstreg] == 0);
4067 n = (State.regs[dstreg] & 0x80000000) != 0;
4068 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4069 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4070 }
4071
4072 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4073 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4074 "or"
4075 *am33
4076 {
4077 int dstreg;
4078 int z,n;
4079
4080 PC = cia;
4081 dstreg = translate_rreg (SD_, RN0);
4082
4083 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4084 z = (State.regs[dstreg] == 0);
4085 n = (State.regs[dstreg] & 0x80000000) != 0;
4086 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4087 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4088 }
4089
4090 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4091 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4092 "xor"
4093 *am33
4094 {
4095 int dstreg;
4096 int z,n;
4097
4098 PC = cia;
4099 dstreg = translate_rreg (SD_, RN0);
4100
4101 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4102 z = (State.regs[dstreg] == 0);
4103 n = (State.regs[dstreg] & 0x80000000) != 0;
4104 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4105 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4106 }
4107
4108 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4109 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4110 "asr"
4111 *am33
4112 {
4113 int dstreg;
4114 long temp;
4115 int c, z, n;
4116
4117 PC = cia;
4118 dstreg = translate_rreg (SD_, RN0);
4119
4120 temp = State.regs[dstreg];
4121 c = temp & 1;
4122 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4123 State.regs[dstreg] = temp;
4124 z = (State.regs[dstreg] == 0);
4125 n = (State.regs[dstreg] & 0x80000000) != 0;
4126 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4127 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4128 }
4129
4130 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4131 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4132 "lsr"
4133 *am33
4134 {
4135 int dstreg;
4136 int z, n, c;
4137
4138 PC = cia;
4139 dstreg = translate_rreg (SD_, RN0);
4140
4141 c = State.regs[dstreg] & 1;
4142 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4143 z = (State.regs[dstreg] == 0);
4144 n = (State.regs[dstreg] & 0x80000000) != 0;
4145 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4146 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4147 }
4148
4149 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4150 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4151 "asl"
4152 *am33
4153 {
4154 int srcreg, dstreg;
4155 int z, n;
4156
4157 PC = cia;
4158 dstreg = translate_rreg (SD_, RN0);
4159
4160 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4161 z = (State.regs[dstreg] == 0);
4162 n = (State.regs[dstreg] & 0x80000000) != 0;
4163 PSW &= ~(PSW_Z | PSW_N);
4164 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4165 }
4166
4167 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4168 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4169 "mul"
4170 *am33
4171 {
4172 int dstreg;
4173 unsigned long long temp;
4174 int z, n;
4175
4176 PC = cia;
4177 dstreg = translate_rreg (SD_, RN0);
4178
4179 temp = ((signed64)(signed32)State.regs[dstreg]
4180 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4181 State.regs[dstreg] = temp & 0xffffffff;
4182 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4183 z = (State.regs[dstreg] == 0);
4184 n = (State.regs[dstreg] & 0x80000000) != 0;
4185 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4186 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4187 }
4188
4189 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4190 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4191 "mulu"
4192 *am33
4193 {
4194 int dstreg;
4195 unsigned long long temp;
4196 int z, n;
4197
4198 PC = cia;
4199 dstreg = translate_rreg (SD_, RN0);
4200
4201 temp = ((unsigned64)State.regs[dstreg]
4202 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4203 State.regs[dstreg] = temp & 0xffffffff;
4204 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4205 z = (State.regs[dstreg] == 0);
4206 n = (State.regs[dstreg] & 0x80000000) != 0;
4207 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4208 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4209 }
4210
4211 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4212 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4213 "btst"
4214 *am33
4215 {
4216 int srcreg;
4217
4218 PC = cia;
4219 srcreg = translate_rreg (SD_, RN0);
4220 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4221 }
4222
4223 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4224 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4225 "mov"
4226 *am33
4227 {
4228 int srcreg, dstreg;
4229
4230 PC = cia;
4231 srcreg = translate_rreg (SD_, RM0);
4232 dstreg = translate_rreg (SD_, RN2);
4233 State.regs[dstreg] = load_word (State.regs[srcreg]
4234 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4235 }
4236
4237 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4238 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4239 "mov"
4240 *am33
4241 {
4242 int srcreg, dstreg;
4243
4244 PC = cia;
4245 srcreg = translate_rreg (SD_, RM2);
4246 dstreg = translate_rreg (SD_, RN0);
4247 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4248 State.regs[srcreg]);
4249 }
4250
4251 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4252 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4253 "movbu"
4254 *am33
4255 {
4256 int srcreg, dstreg;
4257
4258 PC = cia;
4259 srcreg = translate_rreg (SD_, RM0);
4260 dstreg = translate_rreg (SD_, RN2);
4261 State.regs[dstreg] = load_byte (State.regs[srcreg]
4262 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4263 }
4264
4265 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4266 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4267 "movbu"
4268 *am33
4269 {
4270 int srcreg, dstreg;
4271
4272 PC = cia;
4273 srcreg = translate_rreg (SD_, RM2);
4274 dstreg = translate_rreg (SD_, RN0);
4275 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4276 State.regs[srcreg]);
4277 }
4278
4279 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4280 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4281 "movhu"
4282 *am33
4283 {
4284 int srcreg, dstreg;
4285
4286 PC = cia;
4287 srcreg = translate_rreg (SD_, RM0);
4288 dstreg = translate_rreg (SD_, RN2);
4289 State.regs[dstreg] = load_half (State.regs[srcreg]
4290 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4291 }
4292
4293 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4294 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4295 "movhu"
4296 *am33
4297 {
4298 int srcreg, dstreg;
4299
4300 PC = cia;
4301 srcreg = translate_rreg (SD_, RM2);
4302 dstreg = translate_rreg (SD_, RN0);
4303 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4304 State.regs[srcreg]);
4305 }
4306
4307 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4308 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4309 "mov"
4310 *am33
4311 {
4312 int srcreg, dstreg;
4313
4314 PC = cia;
4315 srcreg = translate_rreg (SD_, RM0);
4316 dstreg = translate_rreg (SD_, RN2);
4317 State.regs[dstreg] = load_word (State.regs[srcreg]
4318 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4319 State.regs[srcreg] += 4;
4320 }
4321
4322 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4323 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4324 "mov"
4325 *am33
4326 {
4327 int srcreg, dstreg;
4328
4329 PC = cia;
4330 srcreg = translate_rreg (SD_, RM2);
4331 dstreg = translate_rreg (SD_, RN0);
4332 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4333 State.regs[srcreg]);
4334 State.regs[dstreg] += 4;
4335 }
4336
4337
4338 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4339 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4340 "mov"
4341 *am33
4342 {
4343 int dstreg;
4344
4345 PC = cia;
4346 dstreg = translate_rreg (SD_, RN2);
4347 State.regs[dstreg] = load_word (State.regs[REG_SP]
4348 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4349 }
4350
4351 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4352 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4353 "mov"
4354 *am33
4355 {
4356 int srcreg;
4357
4358 PC = cia;
4359 srcreg = translate_rreg (SD_, RM2);
4360 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4361 State.regs[srcreg]);
4362 }
4363
4364 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4365 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4366 "movbu"
4367 *am33
4368 {
4369 int dstreg;
4370
4371 PC = cia;
4372 dstreg = translate_rreg (SD_, RN2);
4373 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4374 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4375 }
4376
4377 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4378 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4379 "movbu"
4380 *am33
4381 {
4382 int srcreg;
4383
4384 PC = cia;
4385 srcreg = translate_rreg (SD_, RM2);
4386 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4387 State.regs[srcreg]);
4388 }
4389
4390 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4391 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4392 "movhu"
4393 *am33
4394 {
4395 int dstreg;
4396
4397 PC = cia;
4398 dstreg = translate_rreg (SD_, RN2);
4399 State.regs[dstreg] = load_half (State.regs[REG_SP]
4400 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4401 }
4402
4403 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4404 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4405 "movhu"
4406 *am33
4407 {
4408 int srcreg;
4409
4410 PC = cia;
4411 srcreg = translate_rreg (SD_, RM2);
4412 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4413 State.regs[srcreg]);
4414 }
4415
4416
4417 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4418 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4419 "movhu"
4420 *am33
4421 {
4422 int srcreg, dstreg;
4423
4424 PC = cia;
4425 srcreg = translate_rreg (SD_, RM0);
4426 dstreg = translate_rreg (SD_, RN2);
4427 State.regs[dstreg] = load_half (State.regs[srcreg]
4428 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4429 State.regs[srcreg] += 2;
4430 }
4431
4432 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4433 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4434 "movhu"
4435 *am33
4436 {
4437 int srcreg, dstreg;
4438
4439 PC = cia;
4440 srcreg = translate_rreg (SD_, RM2);
4441 dstreg = translate_rreg (SD_, RN0);
4442 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4443 State.regs[srcreg]);
4444 State.regs[dstreg] += 2;
4445 }
4446
4447
4448 // ??? mac
4449 // ??? macu
4450 // ??? macb
4451 // ??? macbu
4452 // ??? mach
4453 // ??? machu
4454 // ??? dmach
4455 // ??? dmachu
4456 // ??? dmulh
4457 // ??? dmulhu
4458
4459 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4460 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4461 "mov"
4462 *am33
4463 {
4464 int dstreg;
4465
4466 PC = cia;
4467 dstreg = translate_rreg (SD_, RN2);
4468 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4469 }
4470
4471 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4472 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4473 "mov"
4474 *am33
4475 {
4476 int srcreg;
4477
4478 PC = cia;
4479 srcreg = translate_rreg (SD_, RM2);
4480 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4481 }
4482
4483 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4484 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4485 "movbu"
4486 *am33
4487 {
4488 int dstreg;
4489
4490 PC = cia;
4491 dstreg = translate_rreg (SD_, RN2);
4492 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4493 }
4494
4495 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4496 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4497 "movbu"
4498 *am33
4499 {
4500 int srcreg;
4501
4502 PC = cia;
4503 srcreg = translate_rreg (SD_, RM2);
4504 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4505 }
4506
4507 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4508 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4509 "movhu"
4510 *am33
4511 {
4512 int dstreg;
4513
4514 PC = cia;
4515 dstreg = translate_rreg (SD_, RN2);
4516 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4517 }
4518
4519 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4520 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4521 "movhu"
4522 *am33
4523 {
4524 int srcreg;
4525
4526 PC = cia;
4527 srcreg = translate_rreg (SD_, RM2);
4528 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4529 }
4530
4531 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4532 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4533 "add_add"
4534 *am33
4535 {
4536 int srcreg1, srcreg2, dstreg1, dstreg2;
4537
4538 PC = cia;
4539 srcreg1 = translate_rreg (SD_, RM1);
4540 srcreg2 = translate_rreg (SD_, RM2);
4541 dstreg1 = translate_rreg (SD_, RN1);
4542 dstreg2 = translate_rreg (SD_, RN2);
4543
4544 State.regs[dstreg1] += State.regs[srcreg1];
4545 State.regs[dstreg2] += State.regs[srcreg2];
4546 }
4547
4548 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4549 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4550 "add_add"
4551 *am33
4552 {
4553 int srcreg1, dstreg1, dstreg2;
4554
4555 PC = cia;
4556 srcreg1 = translate_rreg (SD_, RM1);
4557 dstreg1 = translate_rreg (SD_, RN1);
4558 dstreg2 = translate_rreg (SD_, RN2);
4559
4560 State.regs[dstreg1] += State.regs[srcreg1];
4561 State.regs[dstreg2] += EXTEND4 (IMM4);
4562 }
4563
4564 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4565 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4566 "add_sub"
4567 *am33
4568 {
4569 int srcreg1, srcreg2, dstreg1, dstreg2;
4570
4571 PC = cia;
4572 srcreg1 = translate_rreg (SD_, RM1);
4573 srcreg2 = translate_rreg (SD_, RM2);
4574 dstreg1 = translate_rreg (SD_, RN1);
4575 dstreg2 = translate_rreg (SD_, RN2);
4576
4577 State.regs[dstreg1] += State.regs[srcreg1];
4578 State.regs[dstreg2] -= State.regs[srcreg2];
4579 }
4580
4581 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4582 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4583 "add_sub"
4584 *am33
4585 {
4586 int srcreg1, dstreg1, dstreg2;
4587
4588 PC = cia;
4589 srcreg1 = translate_rreg (SD_, RM1);
4590 dstreg1 = translate_rreg (SD_, RN1);
4591 dstreg2 = translate_rreg (SD_, RN2);
4592
4593 State.regs[dstreg1] += State.regs[srcreg1];
4594 State.regs[dstreg2] -= EXTEND4 (IMM4);
4595 }
4596
4597 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4598 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4599 "add_cmp"
4600 *am33
4601 {
4602 int srcreg1, srcreg2, dstreg1, dstreg2;
4603
4604 PC = cia;
4605 srcreg1 = translate_rreg (SD_, RM1);
4606 srcreg2 = translate_rreg (SD_, RM2);
4607 dstreg1 = translate_rreg (SD_, RN1);
4608 dstreg2 = translate_rreg (SD_, RN2);
4609
4610 State.regs[dstreg1] += State.regs[srcreg1];
4611 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4612 }
4613
4614 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4615 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4616 "add_cmp"
4617 *am33
4618 {
4619 int srcreg1, dstreg1, dstreg2;
4620
4621 PC = cia;
4622 srcreg1 = translate_rreg (SD_, RM1);
4623 dstreg1 = translate_rreg (SD_, RN1);
4624 dstreg2 = translate_rreg (SD_, RN2);
4625
4626 State.regs[dstreg1] += State.regs[srcreg1];
4627 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4628 }
4629
4630 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4631 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4632 "add_mov"
4633 *am33
4634 {
4635 int srcreg1, srcreg2, dstreg1, dstreg2;
4636
4637 PC = cia;
4638 srcreg1 = translate_rreg (SD_, RM1);
4639 srcreg2 = translate_rreg (SD_, RM2);
4640 dstreg1 = translate_rreg (SD_, RN1);
4641 dstreg2 = translate_rreg (SD_, RN2);
4642
4643 State.regs[dstreg1] += State.regs[srcreg1];
4644 State.regs[dstreg2] = State.regs[srcreg2];
4645 }
4646
4647 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4648 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4649 "add_mov"
4650 *am33
4651 {
4652 int srcreg1, dstreg1, dstreg2;
4653
4654 PC = cia;
4655 srcreg1 = translate_rreg (SD_, RM1);
4656 dstreg1 = translate_rreg (SD_, RN1);
4657 dstreg2 = translate_rreg (SD_, RN2);
4658
4659 State.regs[dstreg1] += State.regs[srcreg1];
4660 State.regs[dstreg2] = EXTEND4 (IMM4);
4661 }
4662
4663 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4664 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4665 "add_asr"
4666 *am33
4667 {
4668 int srcreg1, srcreg2, dstreg1, dstreg2;
4669 signed int temp;
4670
4671 PC = cia;
4672 srcreg1 = translate_rreg (SD_, RM1);
4673 srcreg2 = translate_rreg (SD_, RM2);
4674 dstreg1 = translate_rreg (SD_, RN1);
4675 dstreg2 = translate_rreg (SD_, RN2);
4676
4677 State.regs[dstreg1] += State.regs[srcreg1];
4678 temp = State.regs[dstreg2];
4679 temp >>= State.regs[srcreg2];
4680 State.regs[dstreg2] = temp;
4681 }
4682
4683 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4684 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4685 "add_asr"
4686 *am33
4687 {
4688 int srcreg1, dstreg1, dstreg2;
4689 signed int temp;
4690
4691 PC = cia;
4692 srcreg1 = translate_rreg (SD_, RM1);
4693 dstreg1 = translate_rreg (SD_, RN1);
4694 dstreg2 = translate_rreg (SD_, RN2);
4695
4696 State.regs[dstreg1] += State.regs[srcreg1];
4697 temp = State.regs[dstreg2];
4698 temp >>= IMM4;
4699 State.regs[dstreg2] = temp;
4700 }
4701
4702 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4703 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4704 "add_lsr"
4705 *am33
4706 {
4707 int srcreg1, srcreg2, dstreg1, dstreg2;
4708
4709 PC = cia;
4710 srcreg1 = translate_rreg (SD_, RM1);
4711 srcreg2 = translate_rreg (SD_, RM2);
4712 dstreg1 = translate_rreg (SD_, RN1);
4713 dstreg2 = translate_rreg (SD_, RN2);
4714
4715 State.regs[dstreg1] += State.regs[srcreg1];
4716 State.regs[dstreg2] >>= State.regs[srcreg2];
4717 }
4718
4719 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4720 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4721 "add_lsr"
4722 *am33
4723 {
4724 int srcreg1, dstreg1, dstreg2;
4725 signed int temp;
4726
4727 PC = cia;
4728 srcreg1 = translate_rreg (SD_, RM1);
4729 dstreg1 = translate_rreg (SD_, RN1);
4730 dstreg2 = translate_rreg (SD_, RN2);
4731
4732 State.regs[dstreg1] += State.regs[srcreg1];
4733 State.regs[dstreg2] >>= IMM4;
4734 }
4735
4736
4737 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
4738 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4739 "add_asl"
4740 *am33
4741 {
4742 int srcreg1, srcreg2, dstreg1, dstreg2;
4743
4744 PC = cia;
4745 srcreg1 = translate_rreg (SD_, RM1);
4746 srcreg2 = translate_rreg (SD_, RM2);
4747 dstreg1 = translate_rreg (SD_, RN1);
4748 dstreg2 = translate_rreg (SD_, RN2);
4749
4750 State.regs[dstreg1] += State.regs[srcreg1];
4751 State.regs[dstreg2] <<= State.regs[srcreg2];
4752 }
4753
4754 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
4755 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4756 "add_asl"
4757 *am33
4758 {
4759 int srcreg1, dstreg1, dstreg2;
4760 signed int temp;
4761
4762 PC = cia;
4763 srcreg1 = translate_rreg (SD_, RM1);
4764 dstreg1 = translate_rreg (SD_, RN1);
4765 dstreg2 = translate_rreg (SD_, RN2);
4766
4767 State.regs[dstreg1] += State.regs[srcreg1];
4768 State.regs[dstreg2] <<= IMM4;
4769 }
4770
4771 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
4772 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
4773 "cmp_add"
4774 *am33
4775 {
4776 int srcreg1, srcreg2, dstreg1, dstreg2;
4777
4778 PC = cia;
4779 srcreg1 = translate_rreg (SD_, RM1);
4780 srcreg2 = translate_rreg (SD_, RM2);
4781 dstreg1 = translate_rreg (SD_, RN1);
4782 dstreg2 = translate_rreg (SD_, RN2);
4783
4784 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4785 State.regs[dstreg2] += State.regs[srcreg2];
4786 }
4787
4788 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
4789 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
4790 "cmp_add"
4791 *am33
4792 {
4793 int srcreg1, dstreg1, dstreg2;
4794
4795 PC = cia;
4796 srcreg1 = translate_rreg (SD_, RM1);
4797 dstreg1 = translate_rreg (SD_, RN1);
4798 dstreg2 = translate_rreg (SD_, RN2);
4799
4800 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4801 State.regs[dstreg2] += EXTEND4 (IMM4);
4802 }
4803
4804 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
4805 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
4806 "cmp_sub"
4807 *am33
4808 {
4809 int srcreg1, srcreg2, dstreg1, dstreg2;
4810
4811 PC = cia;
4812 srcreg1 = translate_rreg (SD_, RM1);
4813 srcreg2 = translate_rreg (SD_, RM2);
4814 dstreg1 = translate_rreg (SD_, RN1);
4815 dstreg2 = translate_rreg (SD_, RN2);
4816
4817 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4818 State.regs[dstreg2] -= State.regs[srcreg2];
4819 }
4820
4821 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
4822 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
4823 "cmp_sub"
4824 *am33
4825 {
4826 int srcreg1, dstreg1, dstreg2;
4827
4828 PC = cia;
4829 srcreg1 = translate_rreg (SD_, RM1);
4830 dstreg1 = translate_rreg (SD_, RN1);
4831 dstreg2 = translate_rreg (SD_, RN2);
4832
4833 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4834 State.regs[dstreg2] -= EXTEND4 (IMM4);
4835 }
4836
4837 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
4838 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
4839 "cmp_mov"
4840 *am33
4841 {
4842 int srcreg1, srcreg2, dstreg1, dstreg2;
4843
4844 PC = cia;
4845 srcreg1 = translate_rreg (SD_, RM1);
4846 srcreg2 = translate_rreg (SD_, RM2);
4847 dstreg1 = translate_rreg (SD_, RN1);
4848 dstreg2 = translate_rreg (SD_, RN2);
4849
4850 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4851 State.regs[dstreg2] = State.regs[srcreg2];
4852 }
4853
4854 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
4855 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
4856 "cmp_mov"
4857 *am33
4858 {
4859 int srcreg1, dstreg1, dstreg2;
4860
4861 PC = cia;
4862 srcreg1 = translate_rreg (SD_, RM1);
4863 dstreg1 = translate_rreg (SD_, RN1);
4864 dstreg2 = translate_rreg (SD_, RN2);
4865
4866 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4867 State.regs[dstreg2] = EXTEND4 (IMM4);
4868 }
4869
4870 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
4871 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
4872 "cmp_asr"
4873 *am33
4874 {
4875 int srcreg1, srcreg2, dstreg1, dstreg2;
4876 signed int temp;
4877
4878 PC = cia;
4879 srcreg1 = translate_rreg (SD_, RM1);
4880 srcreg2 = translate_rreg (SD_, RM2);
4881 dstreg1 = translate_rreg (SD_, RN1);
4882 dstreg2 = translate_rreg (SD_, RN2);
4883
4884 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4885 temp = State.regs[dstreg2];
4886 temp >>= State.regs[srcreg2];
4887 State.regs[dstreg2] = temp;
4888 }
4889
4890 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
4891 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
4892 "cmp_asr"
4893 *am33
4894 {
4895 int srcreg1, dstreg1, dstreg2;
4896 signed int temp;
4897
4898 PC = cia;
4899 srcreg1 = translate_rreg (SD_, RM1);
4900 dstreg1 = translate_rreg (SD_, RN1);
4901 dstreg2 = translate_rreg (SD_, RN2);
4902
4903 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4904 temp = State.regs[dstreg2];
4905 temp >>= IMM4;
4906 State.regs[dstreg2] = temp;
4907 }
4908
4909 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
4910 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
4911 "cmp_lsr"
4912 *am33
4913 {
4914 int srcreg1, srcreg2, dstreg1, dstreg2;
4915
4916 PC = cia;
4917 srcreg1 = translate_rreg (SD_, RM1);
4918 srcreg2 = translate_rreg (SD_, RM2);
4919 dstreg1 = translate_rreg (SD_, RN1);
4920 dstreg2 = translate_rreg (SD_, RN2);
4921
4922 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4923 State.regs[dstreg2] >>= State.regs[srcreg2];
4924 }
4925
4926 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
4927 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
4928 "cmp_lsr"
4929 *am33
4930 {
4931 int srcreg1, dstreg1, dstreg2;
4932 signed int temp;
4933
4934 PC = cia;
4935 srcreg1 = translate_rreg (SD_, RM1);
4936 dstreg1 = translate_rreg (SD_, RN1);
4937 dstreg2 = translate_rreg (SD_, RN2);
4938
4939 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4940 State.regs[dstreg2] >>= IMM4;
4941 }
4942
4943
4944 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
4945 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
4946 "cmp_asl"
4947 *am33
4948 {
4949 int srcreg1, srcreg2, dstreg1, dstreg2;
4950
4951 PC = cia;
4952 srcreg1 = translate_rreg (SD_, RM1);
4953 srcreg2 = translate_rreg (SD_, RM2);
4954 dstreg1 = translate_rreg (SD_, RN1);
4955 dstreg2 = translate_rreg (SD_, RN2);
4956
4957 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4958 State.regs[dstreg2] <<= State.regs[srcreg2];
4959 }
4960
4961 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
4962 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
4963 "cmp_asl"
4964 *am33
4965 {
4966 int srcreg1, dstreg1, dstreg2;
4967 signed int temp;
4968
4969 PC = cia;
4970 srcreg1 = translate_rreg (SD_, RM1);
4971 dstreg1 = translate_rreg (SD_, RN1);
4972 dstreg2 = translate_rreg (SD_, RN2);
4973
4974 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4975 State.regs[dstreg2] <<= IMM4;
4976 }
4977
4978 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
4979 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
4980 "sub_add"
4981 *am33
4982 {
4983 int srcreg1, srcreg2, dstreg1, dstreg2;
4984
4985 PC = cia;
4986 srcreg1 = translate_rreg (SD_, RM1);
4987 srcreg2 = translate_rreg (SD_, RM2);
4988 dstreg1 = translate_rreg (SD_, RN1);
4989 dstreg2 = translate_rreg (SD_, RN2);
4990
4991 State.regs[dstreg1] -= State.regs[srcreg1];
4992 State.regs[dstreg2] += State.regs[srcreg2];
4993 }
4994
4995 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
4996 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
4997 "sub_add"
4998 *am33
4999 {
5000 int srcreg1, dstreg1, dstreg2;
5001
5002 PC = cia;
5003 srcreg1 = translate_rreg (SD_, RM1);
5004 dstreg1 = translate_rreg (SD_, RN1);
5005 dstreg2 = translate_rreg (SD_, RN2);
5006
5007 State.regs[dstreg1] -= State.regs[srcreg1];
5008 State.regs[dstreg2] += EXTEND4 (IMM4);
5009 }
5010
5011 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5012 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5013 "sub_sub"
5014 *am33
5015 {
5016 int srcreg1, srcreg2, dstreg1, dstreg2;
5017
5018 PC = cia;
5019 srcreg1 = translate_rreg (SD_, RM1);
5020 srcreg2 = translate_rreg (SD_, RM2);
5021 dstreg1 = translate_rreg (SD_, RN1);
5022 dstreg2 = translate_rreg (SD_, RN2);
5023
5024 State.regs[dstreg1] -= State.regs[srcreg1];
5025 State.regs[dstreg2] -= State.regs[srcreg2];
5026 }
5027
5028 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5029 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5030 "sub_sub"
5031 *am33
5032 {
5033 int srcreg1, dstreg1, dstreg2;
5034
5035 PC = cia;
5036 srcreg1 = translate_rreg (SD_, RM1);
5037 dstreg1 = translate_rreg (SD_, RN1);
5038 dstreg2 = translate_rreg (SD_, RN2);
5039
5040 State.regs[dstreg1] -= State.regs[srcreg1];
5041 State.regs[dstreg2] -= EXTEND4 (IMM4);
5042 }
5043
5044 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5045 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5046 "sub_cmp"
5047 *am33
5048 {
5049 int srcreg1, srcreg2, dstreg1, dstreg2;
5050
5051 PC = cia;
5052 srcreg1 = translate_rreg (SD_, RM1);
5053 srcreg2 = translate_rreg (SD_, RM2);
5054 dstreg1 = translate_rreg (SD_, RN1);
5055 dstreg2 = translate_rreg (SD_, RN2);
5056
5057 State.regs[dstreg1] -= State.regs[srcreg1];
5058 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5059 }
5060
5061 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5062 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5063 "sub_cmp"
5064 *am33
5065 {
5066 int srcreg1, dstreg1, dstreg2;
5067
5068 PC = cia;
5069 srcreg1 = translate_rreg (SD_, RM1);
5070 dstreg1 = translate_rreg (SD_, RN1);
5071 dstreg2 = translate_rreg (SD_, RN2);
5072
5073 State.regs[dstreg1] -= State.regs[srcreg1];
5074 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5075 }
5076
5077 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5078 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5079 "sub_mov"
5080 *am33
5081 {
5082 int srcreg1, srcreg2, dstreg1, dstreg2;
5083
5084 PC = cia;
5085 srcreg1 = translate_rreg (SD_, RM1);
5086 srcreg2 = translate_rreg (SD_, RM2);
5087 dstreg1 = translate_rreg (SD_, RN1);
5088 dstreg2 = translate_rreg (SD_, RN2);
5089
5090 State.regs[dstreg1] -= State.regs[srcreg1];
5091 State.regs[dstreg2] = State.regs[srcreg2];
5092 }
5093
5094 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5095 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5096 "sub_mov"
5097 *am33
5098 {
5099 int srcreg1, dstreg1, dstreg2;
5100
5101 PC = cia;
5102 srcreg1 = translate_rreg (SD_, RM1);
5103 dstreg1 = translate_rreg (SD_, RN1);
5104 dstreg2 = translate_rreg (SD_, RN2);
5105
5106 State.regs[dstreg1] -= State.regs[srcreg1];
5107 State.regs[dstreg2] = EXTEND4 (IMM4);
5108 }
5109
5110 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5111 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5112 "sub_asr"
5113 *am33
5114 {
5115 int srcreg1, srcreg2, dstreg1, dstreg2;
5116 signed int temp;
5117
5118 PC = cia;
5119 srcreg1 = translate_rreg (SD_, RM1);
5120 srcreg2 = translate_rreg (SD_, RM2);
5121 dstreg1 = translate_rreg (SD_, RN1);
5122 dstreg2 = translate_rreg (SD_, RN2);
5123
5124 State.regs[dstreg1] -= State.regs[srcreg1];
5125 temp = State.regs[dstreg2];
5126 temp >>= State.regs[srcreg2];
5127 State.regs[dstreg2] = temp;
5128 }
5129
5130 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5131 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5132 "sub_asr"
5133 *am33
5134 {
5135 int srcreg1, dstreg1, dstreg2;
5136 signed int temp;
5137
5138 PC = cia;
5139 srcreg1 = translate_rreg (SD_, RM1);
5140 dstreg1 = translate_rreg (SD_, RN1);
5141 dstreg2 = translate_rreg (SD_, RN2);
5142
5143 State.regs[dstreg1] -= State.regs[srcreg1];
5144 temp = State.regs[dstreg2];
5145 temp >>= IMM4;
5146 State.regs[dstreg2] = temp;
5147 }
5148
5149 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5150 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5151 "sub_lsr"
5152 *am33
5153 {
5154 int srcreg1, srcreg2, dstreg1, dstreg2;
5155
5156 PC = cia;
5157 srcreg1 = translate_rreg (SD_, RM1);
5158 srcreg2 = translate_rreg (SD_, RM2);
5159 dstreg1 = translate_rreg (SD_, RN1);
5160 dstreg2 = translate_rreg (SD_, RN2);
5161
5162 State.regs[dstreg1] -= State.regs[srcreg1];
5163 State.regs[dstreg2] >>= State.regs[srcreg2];
5164 }
5165
5166 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5167 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5168 "sub_lsr"
5169 *am33
5170 {
5171 int srcreg1, dstreg1, dstreg2;
5172 signed int temp;
5173
5174 PC = cia;
5175 srcreg1 = translate_rreg (SD_, RM1);
5176 dstreg1 = translate_rreg (SD_, RN1);
5177 dstreg2 = translate_rreg (SD_, RN2);
5178
5179 State.regs[dstreg1] -= State.regs[srcreg1];
5180 State.regs[dstreg2] >>= IMM4;
5181 }
5182
5183
5184 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5185 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5186 "sub_asl"
5187 *am33
5188 {
5189 int srcreg1, srcreg2, dstreg1, dstreg2;
5190
5191 PC = cia;
5192 srcreg1 = translate_rreg (SD_, RM1);
5193 srcreg2 = translate_rreg (SD_, RM2);
5194 dstreg1 = translate_rreg (SD_, RN1);
5195 dstreg2 = translate_rreg (SD_, RN2);
5196
5197 State.regs[dstreg1] -= State.regs[srcreg1];
5198 State.regs[dstreg2] <<= State.regs[srcreg2];
5199 }
5200
5201 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5202 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5203 "sub_asl"
5204 *am33
5205 {
5206 int srcreg1, dstreg1, dstreg2;
5207 signed int temp;
5208
5209 PC = cia;
5210 srcreg1 = translate_rreg (SD_, RM1);
5211 dstreg1 = translate_rreg (SD_, RN1);
5212 dstreg2 = translate_rreg (SD_, RN2);
5213
5214 State.regs[dstreg1] -= State.regs[srcreg1];
5215 State.regs[dstreg2] <<= IMM4;
5216 }
5217
5218 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5219 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5220 "mov_add"
5221 *am33
5222 {
5223 int srcreg1, srcreg2, dstreg1, dstreg2;
5224
5225 PC = cia;
5226 srcreg1 = translate_rreg (SD_, RM1);
5227 srcreg2 = translate_rreg (SD_, RM2);
5228 dstreg1 = translate_rreg (SD_, RN1);
5229 dstreg2 = translate_rreg (SD_, RN2);
5230
5231 State.regs[dstreg1] = State.regs[srcreg1];
5232 State.regs[dstreg2] += State.regs[srcreg2];
5233 }
5234
5235 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5236 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5237 "mov_add"
5238 *am33
5239 {
5240 int srcreg1, dstreg1, dstreg2;
5241
5242 PC = cia;
5243 srcreg1 = translate_rreg (SD_, RM1);
5244 dstreg1 = translate_rreg (SD_, RN1);
5245 dstreg2 = translate_rreg (SD_, RN2);
5246
5247 State.regs[dstreg1] = State.regs[srcreg1];
5248 State.regs[dstreg2] += EXTEND4 (IMM4);
5249 }
5250
5251 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5252 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5253 "mov_sub"
5254 *am33
5255 {
5256 int srcreg1, srcreg2, dstreg1, dstreg2;
5257
5258 PC = cia;
5259 srcreg1 = translate_rreg (SD_, RM1);
5260 srcreg2 = translate_rreg (SD_, RM2);
5261 dstreg1 = translate_rreg (SD_, RN1);
5262 dstreg2 = translate_rreg (SD_, RN2);
5263
5264 State.regs[dstreg1] = State.regs[srcreg1];
5265 State.regs[dstreg2] -= State.regs[srcreg2];
5266 }
5267
5268 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5269 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5270 "mov_sub"
5271 *am33
5272 {
5273 int srcreg1, dstreg1, dstreg2;
5274
5275 PC = cia;
5276 srcreg1 = translate_rreg (SD_, RM1);
5277 dstreg1 = translate_rreg (SD_, RN1);
5278 dstreg2 = translate_rreg (SD_, RN2);
5279
5280 State.regs[dstreg1] = State.regs[srcreg1];
5281 State.regs[dstreg2] -= EXTEND4 (IMM4);
5282 }
5283
5284 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5285 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5286 "mov_cmp"
5287 *am33
5288 {
5289 int srcreg1, srcreg2, dstreg1, dstreg2;
5290
5291 PC = cia;
5292 srcreg1 = translate_rreg (SD_, RM1);
5293 srcreg2 = translate_rreg (SD_, RM2);
5294 dstreg1 = translate_rreg (SD_, RN1);
5295 dstreg2 = translate_rreg (SD_, RN2);
5296
5297 State.regs[dstreg1] = State.regs[srcreg1];
5298 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5299 }
5300
5301 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5302 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5303 "mov_cmp"
5304 *am33
5305 {
5306 int srcreg1, dstreg1, dstreg2;
5307
5308 PC = cia;
5309 srcreg1 = translate_rreg (SD_, RM1);
5310 dstreg1 = translate_rreg (SD_, RN1);
5311 dstreg2 = translate_rreg (SD_, RN2);
5312
5313 State.regs[dstreg1] = State.regs[srcreg1];
5314 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5315 }
5316
5317 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5318 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5319 "mov_mov"
5320 *am33
5321 {
5322 int srcreg1, srcreg2, dstreg1, dstreg2;
5323
5324 PC = cia;
5325 srcreg1 = translate_rreg (SD_, RM1);
5326 srcreg2 = translate_rreg (SD_, RM2);
5327 dstreg1 = translate_rreg (SD_, RN1);
5328 dstreg2 = translate_rreg (SD_, RN2);
5329
5330 State.regs[dstreg1] = State.regs[srcreg1];
5331 State.regs[dstreg2] = State.regs[srcreg2];
5332 }
5333
5334 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5335 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5336 "mov_mov"
5337 *am33
5338 {
5339 int srcreg1, dstreg1, dstreg2;
5340
5341 PC = cia;
5342 srcreg1 = translate_rreg (SD_, RM1);
5343 dstreg1 = translate_rreg (SD_, RN1);
5344 dstreg2 = translate_rreg (SD_, RN2);
5345
5346 State.regs[dstreg1] = State.regs[srcreg1];
5347 State.regs[dstreg2] = EXTEND4 (IMM4);
5348 }
5349
5350 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5351 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5352 "mov_asr"
5353 *am33
5354 {
5355 int srcreg1, srcreg2, dstreg1, dstreg2;
5356 signed int temp;
5357
5358 PC = cia;
5359 srcreg1 = translate_rreg (SD_, RM1);
5360 srcreg2 = translate_rreg (SD_, RM2);
5361 dstreg1 = translate_rreg (SD_, RN1);
5362 dstreg2 = translate_rreg (SD_, RN2);
5363
5364 State.regs[dstreg1] = State.regs[srcreg1];
5365 temp = State.regs[dstreg2];
5366 temp >>= State.regs[srcreg2];
5367 State.regs[dstreg2] = temp;
5368 }
5369
5370 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5371 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5372 "mov_asr"
5373 *am33
5374 {
5375 int srcreg1, dstreg1, dstreg2;
5376 signed int temp;
5377
5378 PC = cia;
5379 srcreg1 = translate_rreg (SD_, RM1);
5380 dstreg1 = translate_rreg (SD_, RN1);
5381 dstreg2 = translate_rreg (SD_, RN2);
5382
5383 State.regs[dstreg1] = State.regs[srcreg1];
5384 temp = State.regs[dstreg2];
5385 temp >>= IMM4;
5386 State.regs[dstreg2] = temp;
5387 }
5388
5389 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5390 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5391 "mov_lsr"
5392 *am33
5393 {
5394 int srcreg1, srcreg2, dstreg1, dstreg2;
5395
5396 PC = cia;
5397 srcreg1 = translate_rreg (SD_, RM1);
5398 srcreg2 = translate_rreg (SD_, RM2);
5399 dstreg1 = translate_rreg (SD_, RN1);
5400 dstreg2 = translate_rreg (SD_, RN2);
5401
5402 State.regs[dstreg1] = State.regs[srcreg1];
5403 State.regs[dstreg2] >>= State.regs[srcreg2];
5404 }
5405
5406 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5407 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5408 "mov_lsr"
5409 *am33
5410 {
5411 int srcreg1, dstreg1, dstreg2;
5412 signed int temp;
5413
5414 PC = cia;
5415 srcreg1 = translate_rreg (SD_, RM1);
5416 dstreg1 = translate_rreg (SD_, RN1);
5417 dstreg2 = translate_rreg (SD_, RN2);
5418
5419 State.regs[dstreg1] = State.regs[srcreg1];
5420 State.regs[dstreg2] >>= IMM4;
5421 }
5422
5423
5424 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5425 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5426 "mov_asl"
5427 *am33
5428 {
5429 int srcreg1, srcreg2, dstreg1, dstreg2;
5430
5431 PC = cia;
5432 srcreg1 = translate_rreg (SD_, RM1);
5433 srcreg2 = translate_rreg (SD_, RM2);
5434 dstreg1 = translate_rreg (SD_, RN1);
5435 dstreg2 = translate_rreg (SD_, RN2);
5436
5437 State.regs[dstreg1] = State.regs[srcreg1];
5438 State.regs[dstreg2] <<= State.regs[srcreg2];
5439 }
5440
5441 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5442 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5443 "mov_asl"
5444 *am33
5445 {
5446 int srcreg1, dstreg1, dstreg2;
5447 signed int temp;
5448
5449 PC = cia;
5450 srcreg1 = translate_rreg (SD_, RM1);
5451 dstreg1 = translate_rreg (SD_, RN1);
5452 dstreg2 = translate_rreg (SD_, RN2);
5453
5454 State.regs[dstreg1] = State.regs[srcreg1];
5455 State.regs[dstreg2] <<= IMM4;
5456 }
5457
5458 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5459 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5460 "add_add"
5461 *am33
5462 {
5463 int srcreg2, dstreg1, dstreg2;
5464
5465 PC = cia;
5466 srcreg2 = translate_rreg (SD_, RM2);
5467 dstreg1 = translate_rreg (SD_, RN1);
5468 dstreg2 = translate_rreg (SD_, RN2);
5469
5470 State.regs[dstreg1] += EXTEND4 (IMM4A);
5471 State.regs[dstreg2] += State.regs[srcreg2];
5472 }
5473
5474 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5475 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5476 "add_add"
5477 *am33
5478 {
5479 int dstreg1, dstreg2;
5480
5481 PC = cia;
5482 dstreg1 = translate_rreg (SD_, RN1);
5483 dstreg2 = translate_rreg (SD_, RN2);
5484
5485 State.regs[dstreg1] += EXTEND4 (IMM4A);
5486 State.regs[dstreg2] += EXTEND4 (IMM4);
5487 }
5488
5489 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5490 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5491 "add_sub"
5492 *am33
5493 {
5494 int srcreg2, dstreg1, dstreg2;
5495
5496 PC = cia;
5497 srcreg2 = translate_rreg (SD_, RM2);
5498 dstreg1 = translate_rreg (SD_, RN1);
5499 dstreg2 = translate_rreg (SD_, RN2);
5500
5501 State.regs[dstreg1] += EXTEND4 (IMM4A);
5502 State.regs[dstreg2] -= State.regs[srcreg2];
5503 }
5504
5505 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5506 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5507 "add_sub"
5508 *am33
5509 {
5510 int dstreg1, dstreg2;
5511
5512 PC = cia;
5513 dstreg1 = translate_rreg (SD_, RN1);
5514 dstreg2 = translate_rreg (SD_, RN2);
5515
5516 State.regs[dstreg1] += EXTEND4 (IMM4A);
5517 State.regs[dstreg2] -= EXTEND4 (IMM4);
5518 }
5519
5520 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5521 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5522 "add_cmp"
5523 *am33
5524 {
5525 int srcreg2, dstreg1, dstreg2;
5526
5527 PC = cia;
5528 srcreg2 = translate_rreg (SD_, RM2);
5529 dstreg1 = translate_rreg (SD_, RN1);
5530 dstreg2 = translate_rreg (SD_, RN2);
5531
5532 State.regs[dstreg1] += EXTEND4 (IMM4A);
5533 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5534 }
5535
5536 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5537 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5538 "add_cmp"
5539 *am33
5540 {
5541 int dstreg1, dstreg2;
5542
5543 PC = cia;
5544 dstreg1 = translate_rreg (SD_, RN1);
5545 dstreg2 = translate_rreg (SD_, RN2);
5546
5547 State.regs[dstreg1] += EXTEND4 (IMM4A);
5548 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5549 }
5550
5551 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5552 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5553 "add_mov"
5554 *am33
5555 {
5556 int srcreg2, dstreg1, dstreg2;
5557
5558 PC = cia;
5559 srcreg2 = translate_rreg (SD_, RM2);
5560 dstreg1 = translate_rreg (SD_, RN1);
5561 dstreg2 = translate_rreg (SD_, RN2);
5562
5563 State.regs[dstreg1] += EXTEND4 (IMM4A);
5564 State.regs[dstreg2] = State.regs[srcreg2];
5565 }
5566
5567 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5568 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5569 "add_mov"
5570 *am33
5571 {
5572 int dstreg1, dstreg2;
5573
5574 PC = cia;
5575 dstreg1 = translate_rreg (SD_, RN1);
5576 dstreg2 = translate_rreg (SD_, RN2);
5577
5578 State.regs[dstreg1] += EXTEND4 (IMM4A);
5579 State.regs[dstreg2] = EXTEND4 (IMM4);
5580 }
5581
5582 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5583 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5584 "add_asr"
5585 *am33
5586 {
5587 int srcreg2, dstreg1, dstreg2;
5588 signed int temp;
5589
5590 PC = cia;
5591 srcreg2 = translate_rreg (SD_, RM2);
5592 dstreg1 = translate_rreg (SD_, RN1);
5593 dstreg2 = translate_rreg (SD_, RN2);
5594
5595 State.regs[dstreg1] += EXTEND4 (IMM4A);
5596 temp = State.regs[dstreg2];
5597 temp >>= State.regs[srcreg2];
5598 State.regs[dstreg2] = temp;
5599 }
5600
5601 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5602 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5603 "add_asr"
5604 *am33
5605 {
5606 int dstreg1, dstreg2;
5607 signed int temp;
5608
5609 PC = cia;
5610 dstreg1 = translate_rreg (SD_, RN1);
5611 dstreg2 = translate_rreg (SD_, RN2);
5612
5613 State.regs[dstreg1] += EXTEND4 (IMM4A);
5614 temp = State.regs[dstreg2];
5615 temp >>= IMM4;
5616 State.regs[dstreg2] = temp;
5617 }
5618
5619 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5620 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5621 "add_lsr"
5622 *am33
5623 {
5624 int srcreg2, dstreg1, dstreg2;
5625
5626 PC = cia;
5627 srcreg2 = translate_rreg (SD_, RM2);
5628 dstreg1 = translate_rreg (SD_, RN1);
5629 dstreg2 = translate_rreg (SD_, RN2);
5630
5631 State.regs[dstreg1] += EXTEND4 (IMM4A);
5632 State.regs[dstreg2] >>= State.regs[srcreg2];
5633 }
5634
5635 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5636 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5637 "add_lsr"
5638 *am33
5639 {
5640 int dstreg1, dstreg2;
5641 signed int temp;
5642
5643 PC = cia;
5644 dstreg1 = translate_rreg (SD_, RN1);
5645 dstreg2 = translate_rreg (SD_, RN2);
5646
5647 State.regs[dstreg1] += EXTEND4 (IMM4A);
5648 State.regs[dstreg2] >>= IMM4;
5649 }
5650
5651
5652 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5653 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5654 "add_asl"
5655 *am33
5656 {
5657 int srcreg2, dstreg1, dstreg2;
5658
5659 PC = cia;
5660 srcreg2 = translate_rreg (SD_, RM2);
5661 dstreg1 = translate_rreg (SD_, RN1);
5662 dstreg2 = translate_rreg (SD_, RN2);
5663
5664 State.regs[dstreg1] += EXTEND4 (IMM4A);
5665 State.regs[dstreg2] <<= State.regs[srcreg2];
5666 }
5667
5668 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
5669 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5670 "add_asl"
5671 *am33
5672 {
5673 int dstreg1, dstreg2;
5674 signed int temp;
5675
5676 PC = cia;
5677 dstreg1 = translate_rreg (SD_, RN1);
5678 dstreg2 = translate_rreg (SD_, RN2);
5679
5680 State.regs[dstreg1] += EXTEND4 (IMM4A);
5681 State.regs[dstreg2] <<= IMM4;
5682 }
5683
5684 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
5685 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5686 "cmp_add"
5687 *am33
5688 {
5689 int srcreg2, dstreg1, dstreg2;
5690
5691 PC = cia;
5692 srcreg2 = translate_rreg (SD_, RM2);
5693 dstreg1 = translate_rreg (SD_, RN1);
5694 dstreg2 = translate_rreg (SD_, RN2);
5695
5696 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5697 State.regs[dstreg2] += State.regs[srcreg2];
5698 }
5699
5700 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
5701 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5702 "cmp_add"
5703 *am33
5704 {
5705 int dstreg1, dstreg2;
5706
5707 PC = cia;
5708 dstreg1 = translate_rreg (SD_, RN1);
5709 dstreg2 = translate_rreg (SD_, RN2);
5710
5711 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5712 State.regs[dstreg2] += EXTEND4 (IMM4);
5713 }
5714
5715 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
5716 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5717 "cmp_sub"
5718 *am33
5719 {
5720 int srcreg2, dstreg1, dstreg2;
5721
5722 PC = cia;
5723 srcreg2 = translate_rreg (SD_, RM2);
5724 dstreg1 = translate_rreg (SD_, RN1);
5725 dstreg2 = translate_rreg (SD_, RN2);
5726
5727 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5728 State.regs[dstreg2] -= State.regs[srcreg2];
5729 }
5730
5731 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
5732 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5733 "cmp_sub"
5734 *am33
5735 {
5736 int dstreg1, dstreg2;
5737
5738 PC = cia;
5739 dstreg1 = translate_rreg (SD_, RN1);
5740 dstreg2 = translate_rreg (SD_, RN2);
5741
5742 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5743 State.regs[dstreg2] -= EXTEND4 (IMM4);
5744 }
5745
5746 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
5747 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5748 "cmp_mov"
5749 *am33
5750 {
5751 int srcreg2, dstreg1, dstreg2;
5752
5753 PC = cia;
5754 srcreg2 = translate_rreg (SD_, RM2);
5755 dstreg1 = translate_rreg (SD_, RN1);
5756 dstreg2 = translate_rreg (SD_, RN2);
5757
5758 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5759 State.regs[dstreg2] = State.regs[srcreg2];
5760 }
5761
5762 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
5763 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5764 "cmp_mov"
5765 *am33
5766 {
5767 int dstreg1, dstreg2;
5768
5769 PC = cia;
5770 dstreg1 = translate_rreg (SD_, RN1);
5771 dstreg2 = translate_rreg (SD_, RN2);
5772
5773 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5774 State.regs[dstreg2] = EXTEND4 (IMM4);
5775 }
5776
5777 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
5778 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
5779 "cmp_asr"
5780 *am33
5781 {
5782 int srcreg2, dstreg1, dstreg2;
5783 signed int temp;
5784
5785 PC = cia;
5786 srcreg2 = translate_rreg (SD_, RM2);
5787 dstreg1 = translate_rreg (SD_, RN1);
5788 dstreg2 = translate_rreg (SD_, RN2);
5789
5790 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5791 temp = State.regs[dstreg2];
5792 temp >>= State.regs[srcreg2];
5793 State.regs[dstreg2] = temp;
5794 }
5795
5796 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
5797 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
5798 "cmp_asr"
5799 *am33
5800 {
5801 int dstreg1, dstreg2;
5802 signed int temp;
5803
5804 PC = cia;
5805 dstreg1 = translate_rreg (SD_, RN1);
5806 dstreg2 = translate_rreg (SD_, RN2);
5807
5808 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5809 temp = State.regs[dstreg2];
5810 temp >>= IMM4;
5811 State.regs[dstreg2] = temp;
5812 }
5813
5814 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
5815 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
5816 "cmp_lsr"
5817 *am33
5818 {
5819 int srcreg2, dstreg1, dstreg2;
5820
5821 PC = cia;
5822 srcreg2 = translate_rreg (SD_, RM2);
5823 dstreg1 = translate_rreg (SD_, RN1);
5824 dstreg2 = translate_rreg (SD_, RN2);
5825
5826 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5827 State.regs[dstreg2] >>= State.regs[srcreg2];
5828 }
5829
5830 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
5831 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
5832 "cmp_lsr"
5833 *am33
5834 {
5835 int dstreg1, dstreg2;
5836 signed int temp;
5837
5838 PC = cia;
5839 dstreg1 = translate_rreg (SD_, RN1);
5840 dstreg2 = translate_rreg (SD_, RN2);
5841
5842 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5843 State.regs[dstreg2] >>= IMM4;
5844 }
5845
5846
5847 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
5848 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
5849 "cmp_asl"
5850 *am33
5851 {
5852 int srcreg2, dstreg1, dstreg2;
5853
5854 PC = cia;
5855 srcreg2 = translate_rreg (SD_, RM2);
5856 dstreg1 = translate_rreg (SD_, RN1);
5857 dstreg2 = translate_rreg (SD_, RN2);
5858
5859 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5860 State.regs[dstreg2] <<= State.regs[srcreg2];
5861 }
5862
5863 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
5864 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
5865 "cmp_asl"
5866 *am33
5867 {
5868 int dstreg1, dstreg2;
5869 signed int temp;
5870
5871 PC = cia;
5872 dstreg1 = translate_rreg (SD_, RN1);
5873 dstreg2 = translate_rreg (SD_, RN2);
5874
5875 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5876 State.regs[dstreg2] <<= IMM4;
5877 }
5878
5879 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
5880 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
5881 "sub_add"
5882 *am33
5883 {
5884 int srcreg2, dstreg1, dstreg2;
5885
5886 PC = cia;
5887 srcreg2 = translate_rreg (SD_, RM2);
5888 dstreg1 = translate_rreg (SD_, RN1);
5889 dstreg2 = translate_rreg (SD_, RN2);
5890
5891 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5892 State.regs[dstreg2] += State.regs[srcreg2];
5893 }
5894
5895 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
5896 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
5897 "sub_add"
5898 *am33
5899 {
5900 int dstreg1, dstreg2;
5901
5902 PC = cia;
5903 dstreg1 = translate_rreg (SD_, RN1);
5904 dstreg2 = translate_rreg (SD_, RN2);
5905
5906 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5907 State.regs[dstreg2] += EXTEND4 (IMM4);
5908 }
5909
5910 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
5911 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
5912 "sub_sub"
5913 *am33
5914 {
5915 int srcreg2, dstreg1, dstreg2;
5916
5917 PC = cia;
5918 srcreg2 = translate_rreg (SD_, RM2);
5919 dstreg1 = translate_rreg (SD_, RN1);
5920 dstreg2 = translate_rreg (SD_, RN2);
5921
5922 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5923 State.regs[dstreg2] -= State.regs[srcreg2];
5924 }
5925
5926 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
5927 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
5928 "sub_sub"
5929 *am33
5930 {
5931 int dstreg1, dstreg2;
5932
5933 PC = cia;
5934 dstreg1 = translate_rreg (SD_, RN1);
5935 dstreg2 = translate_rreg (SD_, RN2);
5936
5937 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5938 State.regs[dstreg2] -= EXTEND4 (IMM4);
5939 }
5940
5941 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
5942 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
5943 "sub_cmp"
5944 *am33
5945 {
5946 int srcreg2, dstreg1, dstreg2;
5947
5948 PC = cia;
5949 srcreg2 = translate_rreg (SD_, RM2);
5950 dstreg1 = translate_rreg (SD_, RN1);
5951 dstreg2 = translate_rreg (SD_, RN2);
5952
5953 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5954 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5955 }
5956
5957 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
5958 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
5959 "sub_cmp"
5960 *am33
5961 {
5962 int dstreg1, dstreg2;
5963
5964 PC = cia;
5965 dstreg1 = translate_rreg (SD_, RN1);
5966 dstreg2 = translate_rreg (SD_, RN2);
5967
5968 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5969 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5970 }
5971
5972 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
5973 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
5974 "sub_mov"
5975 *am33
5976 {
5977 int srcreg2, dstreg1, dstreg2;
5978
5979 PC = cia;
5980 srcreg2 = translate_rreg (SD_, RM2);
5981 dstreg1 = translate_rreg (SD_, RN1);
5982 dstreg2 = translate_rreg (SD_, RN2);
5983
5984 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5985 State.regs[dstreg2] = State.regs[srcreg2];
5986 }
5987
5988 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
5989 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
5990 "sub_mov"
5991 *am33
5992 {
5993 int dstreg1, dstreg2;
5994
5995 PC = cia;
5996 dstreg1 = translate_rreg (SD_, RN1);
5997 dstreg2 = translate_rreg (SD_, RN2);
5998
5999 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6000 State.regs[dstreg2] = EXTEND4 (IMM4);
6001 }
6002
6003 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6004 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
6005 "sub_asr"
6006 *am33
6007 {
6008 int srcreg2, dstreg1, dstreg2;
6009 signed int temp;
6010
6011 PC = cia;
6012 srcreg2 = translate_rreg (SD_, RM2);
6013 dstreg1 = translate_rreg (SD_, RN1);
6014 dstreg2 = translate_rreg (SD_, RN2);
6015
6016 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6017 temp = State.regs[dstreg2];
6018 temp >>= State.regs[srcreg2];
6019 State.regs[dstreg2] = temp;
6020 }
6021
6022 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6023 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6024 "sub_asr"
6025 *am33
6026 {
6027 int dstreg1, dstreg2;
6028 signed int temp;
6029
6030 PC = cia;
6031 dstreg1 = translate_rreg (SD_, RN1);
6032 dstreg2 = translate_rreg (SD_, RN2);
6033
6034 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6035 temp = State.regs[dstreg2];
6036 temp >>= IMM4;
6037 State.regs[dstreg2] = temp;
6038 }
6039
6040 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6041 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6042 "sub_lsr"
6043 *am33
6044 {
6045 int srcreg2, dstreg1, dstreg2;
6046
6047 PC = cia;
6048 srcreg2 = translate_rreg (SD_, RM2);
6049 dstreg1 = translate_rreg (SD_, RN1);
6050 dstreg2 = translate_rreg (SD_, RN2);
6051
6052 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6053 State.regs[dstreg2] >>= State.regs[srcreg2];
6054 }
6055
6056 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6057 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6058 "sub_lsr"
6059 *am33
6060 {
6061 int dstreg1, dstreg2;
6062 signed int temp;
6063
6064 PC = cia;
6065 dstreg1 = translate_rreg (SD_, RN1);
6066 dstreg2 = translate_rreg (SD_, RN2);
6067
6068 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6069 State.regs[dstreg2] >>= IMM4;
6070 }
6071
6072
6073 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6074 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6075 "sub_asl"
6076 *am33
6077 {
6078 int srcreg2, dstreg1, dstreg2;
6079
6080 PC = cia;
6081 srcreg2 = translate_rreg (SD_, RM2);
6082 dstreg1 = translate_rreg (SD_, RN1);
6083 dstreg2 = translate_rreg (SD_, RN2);
6084
6085 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6086 State.regs[dstreg2] <<= State.regs[srcreg2];
6087 }
6088
6089 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6090 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6091 "sub_asl"
6092 *am33
6093 {
6094 int dstreg1, dstreg2;
6095 signed int temp;
6096
6097 PC = cia;
6098 dstreg1 = translate_rreg (SD_, RN1);
6099 dstreg2 = translate_rreg (SD_, RN2);
6100
6101 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6102 State.regs[dstreg2] <<= IMM4;
6103 }
6104
6105 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6106 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6107 "mov_add"
6108 *am33
6109 {
6110 int srcreg2, dstreg1, dstreg2;
6111
6112 PC = cia;
6113 srcreg2 = translate_rreg (SD_, RM2);
6114 dstreg1 = translate_rreg (SD_, RN1);
6115 dstreg2 = translate_rreg (SD_, RN2);
6116
6117 State.regs[dstreg1] = EXTEND4 (IMM4A);
6118 State.regs[dstreg2] += State.regs[srcreg2];
6119 }
6120
6121 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6122 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6123 "mov_add"
6124 *am33
6125 {
6126 int dstreg1, dstreg2;
6127
6128 PC = cia;
6129 dstreg1 = translate_rreg (SD_, RN1);
6130 dstreg2 = translate_rreg (SD_, RN2);
6131
6132 State.regs[dstreg1] = EXTEND4 (IMM4A);
6133 State.regs[dstreg2] += EXTEND4 (IMM4);
6134 }
6135
6136 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6137 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6138 "mov_sub"
6139 *am33
6140 {
6141 int srcreg2, dstreg1, dstreg2;
6142
6143 PC = cia;
6144 srcreg2 = translate_rreg (SD_, RM2);
6145 dstreg1 = translate_rreg (SD_, RN1);
6146 dstreg2 = translate_rreg (SD_, RN2);
6147
6148 State.regs[dstreg1] = EXTEND4 (IMM4A);
6149 State.regs[dstreg2] -= State.regs[srcreg2];
6150 }
6151
6152 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6153 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6154 "mov_sub"
6155 *am33
6156 {
6157 int dstreg1, dstreg2;
6158
6159 PC = cia;
6160 dstreg1 = translate_rreg (SD_, RN1);
6161 dstreg2 = translate_rreg (SD_, RN2);
6162
6163 State.regs[dstreg1] = EXTEND4 (IMM4A);
6164 State.regs[dstreg2] -= EXTEND4 (IMM4);
6165 }
6166
6167 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6168 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6169 "mov_cmp"
6170 *am33
6171 {
6172 int srcreg2, dstreg1, dstreg2;
6173
6174 PC = cia;
6175 srcreg2 = translate_rreg (SD_, RM2);
6176 dstreg1 = translate_rreg (SD_, RN1);
6177 dstreg2 = translate_rreg (SD_, RN2);
6178
6179 State.regs[dstreg1] = EXTEND4 (IMM4A);
6180 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6181 }
6182
6183 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6184 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6185 "mov_cmp"
6186 *am33
6187 {
6188 int dstreg1, dstreg2;
6189
6190 PC = cia;
6191 dstreg1 = translate_rreg (SD_, RN1);
6192 dstreg2 = translate_rreg (SD_, RN2);
6193
6194 State.regs[dstreg1] = EXTEND4 (IMM4A);
6195 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6196 }
6197
6198 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6199 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6200 "mov_mov"
6201 *am33
6202 {
6203 int srcreg2, dstreg1, dstreg2;
6204
6205 PC = cia;
6206 srcreg2 = translate_rreg (SD_, RM2);
6207 dstreg1 = translate_rreg (SD_, RN1);
6208 dstreg2 = translate_rreg (SD_, RN2);
6209
6210 State.regs[dstreg1] = EXTEND4 (IMM4A);
6211 State.regs[dstreg2] = State.regs[srcreg2];
6212 }
6213
6214 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6215 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6216 "mov_mov"
6217 *am33
6218 {
6219 int dstreg1, dstreg2;
6220
6221 PC = cia;
6222 dstreg1 = translate_rreg (SD_, RN1);
6223 dstreg2 = translate_rreg (SD_, RN2);
6224
6225 State.regs[dstreg1] = EXTEND4 (IMM4A);
6226 State.regs[dstreg2] = EXTEND4 (IMM4);
6227 }
6228
6229 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6230 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6231 "mov_asr"
6232 *am33
6233 {
6234 int srcreg2, dstreg1, dstreg2;
6235 signed int temp;
6236
6237 PC = cia;
6238 srcreg2 = translate_rreg (SD_, RM2);
6239 dstreg1 = translate_rreg (SD_, RN1);
6240 dstreg2 = translate_rreg (SD_, RN2);
6241
6242 State.regs[dstreg1] = EXTEND4 (IMM4A);
6243 temp = State.regs[dstreg2];
6244 temp >>= State.regs[srcreg2];
6245 State.regs[dstreg2] = temp;
6246 }
6247
6248 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6249 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6250 "mov_asr"
6251 *am33
6252 {
6253 int dstreg1, dstreg2;
6254 signed int temp;
6255
6256 PC = cia;
6257 dstreg1 = translate_rreg (SD_, RN1);
6258 dstreg2 = translate_rreg (SD_, RN2);
6259
6260 State.regs[dstreg1] = EXTEND4 (IMM4A);
6261 temp = State.regs[dstreg2];
6262 temp >>= IMM4;
6263 State.regs[dstreg2] = temp;
6264 }
6265
6266 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6267 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6268 "mov_lsr"
6269 *am33
6270 {
6271 int srcreg2, dstreg1, dstreg2;
6272
6273 PC = cia;
6274 srcreg2 = translate_rreg (SD_, RM2);
6275 dstreg1 = translate_rreg (SD_, RN1);
6276 dstreg2 = translate_rreg (SD_, RN2);
6277
6278 State.regs[dstreg1] = EXTEND4 (IMM4A);
6279 State.regs[dstreg2] >>= State.regs[srcreg2];
6280 }
6281
6282 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6283 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6284 "mov_lsr"
6285 *am33
6286 {
6287 int dstreg1, dstreg2;
6288 signed int temp;
6289
6290 PC = cia;
6291 dstreg1 = translate_rreg (SD_, RN1);
6292 dstreg2 = translate_rreg (SD_, RN2);
6293
6294 State.regs[dstreg1] = EXTEND4 (IMM4A);
6295 State.regs[dstreg2] >>= IMM4;
6296 }
6297
6298
6299 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6300 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6301 "mov_asl"
6302 *am33
6303 {
6304 int srcreg2, dstreg1, dstreg2;
6305
6306 PC = cia;
6307 srcreg2 = translate_rreg (SD_, RM2);
6308 dstreg1 = translate_rreg (SD_, RN1);
6309 dstreg2 = translate_rreg (SD_, RN2);
6310
6311 State.regs[dstreg1] = EXTEND4 (IMM4A);
6312 State.regs[dstreg2] <<= State.regs[srcreg2];
6313 }
6314
6315 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6316 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6317 "mov_asl"
6318 *am33
6319 {
6320 int dstreg1, dstreg2;
6321 signed int temp;
6322
6323 PC = cia;
6324 dstreg1 = translate_rreg (SD_, RN1);
6325 dstreg2 = translate_rreg (SD_, RN2);
6326
6327 State.regs[dstreg1] = EXTEND4 (IMM4A);
6328 State.regs[dstreg2] <<= IMM4;
6329 }
6330
6331 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6332 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6333 "and_add"
6334 *am33
6335 {
6336 int srcreg1, srcreg2, dstreg1, dstreg2;
6337
6338 PC = cia;
6339 srcreg1 = translate_rreg (SD_, RM1);
6340 srcreg2 = translate_rreg (SD_, RM2);
6341 dstreg1 = translate_rreg (SD_, RN1);
6342 dstreg2 = translate_rreg (SD_, RN2);
6343
6344 State.regs[dstreg1] &= State.regs[srcreg1];
6345 State.regs[dstreg2] += State.regs[srcreg2];
6346 }
6347
6348 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6349 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6350 "and_add"
6351 *am33
6352 {
6353 int srcreg1, dstreg1, dstreg2;
6354
6355 PC = cia;
6356 srcreg1 = translate_rreg (SD_, RM1);
6357 dstreg1 = translate_rreg (SD_, RN1);
6358 dstreg2 = translate_rreg (SD_, RN2);
6359
6360 State.regs[dstreg1] &= State.regs[srcreg1];
6361 State.regs[dstreg2] += EXTEND4 (IMM4);
6362 }
6363
6364 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6365 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6366 "and_sub"
6367 *am33
6368 {
6369 int srcreg1, srcreg2, dstreg1, dstreg2;
6370
6371 PC = cia;
6372 srcreg1 = translate_rreg (SD_, RM1);
6373 srcreg2 = translate_rreg (SD_, RM2);
6374 dstreg1 = translate_rreg (SD_, RN1);
6375 dstreg2 = translate_rreg (SD_, RN2);
6376
6377 State.regs[dstreg1] &= State.regs[srcreg1];
6378 State.regs[dstreg2] -= State.regs[srcreg2];
6379 }
6380
6381 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6382 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6383 "and_sub"
6384 *am33
6385 {
6386 int srcreg1, dstreg1, dstreg2;
6387
6388 PC = cia;
6389 srcreg1 = translate_rreg (SD_, RM1);
6390 dstreg1 = translate_rreg (SD_, RN1);
6391 dstreg2 = translate_rreg (SD_, RN2);
6392
6393 State.regs[dstreg1] &= State.regs[srcreg1];
6394 State.regs[dstreg2] -= EXTEND4 (IMM4);
6395 }
6396
6397 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6398 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6399 "and_cmp"
6400 *am33
6401 {
6402 int srcreg1, srcreg2, dstreg1, dstreg2;
6403
6404 PC = cia;
6405 srcreg1 = translate_rreg (SD_, RM1);
6406 srcreg2 = translate_rreg (SD_, RM2);
6407 dstreg1 = translate_rreg (SD_, RN1);
6408 dstreg2 = translate_rreg (SD_, RN2);
6409
6410 State.regs[dstreg1] &= State.regs[srcreg1];
6411 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6412 }
6413
6414 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6415 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6416 "and_cmp"
6417 *am33
6418 {
6419 int srcreg1, dstreg1, dstreg2;
6420
6421 PC = cia;
6422 srcreg1 = translate_rreg (SD_, RM1);
6423 dstreg1 = translate_rreg (SD_, RN1);
6424 dstreg2 = translate_rreg (SD_, RN2);
6425
6426 State.regs[dstreg1] &= State.regs[srcreg1];
6427 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6428 }
6429
6430 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6431 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6432 "and_mov"
6433 *am33
6434 {
6435 int srcreg1, srcreg2, dstreg1, dstreg2;
6436
6437 PC = cia;
6438 srcreg1 = translate_rreg (SD_, RM1);
6439 srcreg2 = translate_rreg (SD_, RM2);
6440 dstreg1 = translate_rreg (SD_, RN1);
6441 dstreg2 = translate_rreg (SD_, RN2);
6442
6443 State.regs[dstreg1] &= State.regs[srcreg1];
6444 State.regs[dstreg2] = State.regs[srcreg2];
6445 }
6446
6447 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6448 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6449 "and_mov"
6450 *am33
6451 {
6452 int srcreg1, dstreg1, dstreg2;
6453
6454 PC = cia;
6455 srcreg1 = translate_rreg (SD_, RM1);
6456 dstreg1 = translate_rreg (SD_, RN1);
6457 dstreg2 = translate_rreg (SD_, RN2);
6458
6459 State.regs[dstreg1] &= State.regs[srcreg1];
6460 State.regs[dstreg2] = EXTEND4 (IMM4);
6461 }
6462
6463 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6464 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6465 "and_asr"
6466 *am33
6467 {
6468 int srcreg1, srcreg2, dstreg1, dstreg2;
6469 signed int temp;
6470
6471 PC = cia;
6472 srcreg1 = translate_rreg (SD_, RM1);
6473 srcreg2 = translate_rreg (SD_, RM2);
6474 dstreg1 = translate_rreg (SD_, RN1);
6475 dstreg2 = translate_rreg (SD_, RN2);
6476
6477 State.regs[dstreg1] &= State.regs[srcreg1];
6478 temp = State.regs[dstreg2];
6479 temp >>= State.regs[srcreg2];
6480 State.regs[dstreg2] = temp;
6481 }
6482
6483 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6484 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6485 "and_asr"
6486 *am33
6487 {
6488 int srcreg1, dstreg1, dstreg2;
6489 signed int temp;
6490
6491 PC = cia;
6492 srcreg1 = translate_rreg (SD_, RM1);
6493 dstreg1 = translate_rreg (SD_, RN1);
6494 dstreg2 = translate_rreg (SD_, RN2);
6495
6496 State.regs[dstreg1] &= State.regs[srcreg1];
6497 temp = State.regs[dstreg2];
6498 temp >>= IMM4;
6499 State.regs[dstreg2] = temp;
6500 }
6501
6502 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6503 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6504 "and_lsr"
6505 *am33
6506 {
6507 int srcreg1, srcreg2, dstreg1, dstreg2;
6508
6509 PC = cia;
6510 srcreg1 = translate_rreg (SD_, RM1);
6511 srcreg2 = translate_rreg (SD_, RM2);
6512 dstreg1 = translate_rreg (SD_, RN1);
6513 dstreg2 = translate_rreg (SD_, RN2);
6514
6515 State.regs[dstreg1] &= State.regs[srcreg1];
6516 State.regs[dstreg2] >>= State.regs[srcreg2];
6517 }
6518
6519 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6520 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6521 "and_lsr"
6522 *am33
6523 {
6524 int srcreg1, dstreg1, dstreg2;
6525 signed int temp;
6526
6527 PC = cia;
6528 srcreg1 = translate_rreg (SD_, RM1);
6529 dstreg1 = translate_rreg (SD_, RN1);
6530 dstreg2 = translate_rreg (SD_, RN2);
6531
6532 State.regs[dstreg1] &= State.regs[srcreg1];
6533 State.regs[dstreg2] >>= IMM4;
6534 }
6535
6536
6537 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6538 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6539 "and_asl"
6540 *am33
6541 {
6542 int srcreg1, srcreg2, dstreg1, dstreg2;
6543
6544 PC = cia;
6545 srcreg1 = translate_rreg (SD_, RM1);
6546 srcreg2 = translate_rreg (SD_, RM2);
6547 dstreg1 = translate_rreg (SD_, RN1);
6548 dstreg2 = translate_rreg (SD_, RN2);
6549
6550 State.regs[dstreg1] &= State.regs[srcreg1];
6551 State.regs[dstreg2] <<= State.regs[srcreg2];
6552 }
6553
6554 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6555 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6556 "and_asl"
6557 *am33
6558 {
6559 int srcreg1, dstreg1, dstreg2;
6560 signed int temp;
6561
6562 PC = cia;
6563 srcreg1 = translate_rreg (SD_, RM1);
6564 dstreg1 = translate_rreg (SD_, RN1);
6565 dstreg2 = translate_rreg (SD_, RN2);
6566
6567 State.regs[dstreg1] &= State.regs[srcreg1];
6568 State.regs[dstreg2] <<= IMM4;
6569 }
6570
6571 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6572 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6573 "dmach_add"
6574 *am33
6575 {
6576 int srcreg1, srcreg2, dstreg1, dstreg2;
6577 long temp, temp2, sum;
6578
6579 PC = cia;
6580 srcreg1 = translate_rreg (SD_, RM1);
6581 srcreg2 = translate_rreg (SD_, RM2);
6582 dstreg1 = translate_rreg (SD_, RN1);
6583 dstreg2 = translate_rreg (SD_, RN2);
6584
6585 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6586 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6587 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6588 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6589 sum = temp + temp2 + State.regs[REG_MCRL];
6590
6591 State.regs[dstreg1] = sum;
6592 State.regs[dstreg2] += State.regs[srcreg2];
6593 }
6594
6595 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6596 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6597 "dmach_add"
6598 *am33
6599 {
6600 int srcreg1, dstreg1, dstreg2;
6601 long temp, temp2, sum;
6602
6603 PC = cia;
6604 srcreg1 = translate_rreg (SD_, RM1);
6605 dstreg1 = translate_rreg (SD_, RN1);
6606 dstreg2 = translate_rreg (SD_, RN2);
6607
6608 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6609 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6610 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6611 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6612 sum = temp + temp2 + State.regs[REG_MCRL];
6613
6614 State.regs[dstreg1] = sum;
6615 State.regs[dstreg2] += EXTEND4 (IMM4);
6616 }
6617
6618 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
6619 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6620 "dmach_sub"
6621 *am33
6622 {
6623 int srcreg1, srcreg2, dstreg1, dstreg2;
6624 long temp, temp2, sum;
6625
6626 PC = cia;
6627 srcreg1 = translate_rreg (SD_, RM1);
6628 srcreg2 = translate_rreg (SD_, RM2);
6629 dstreg1 = translate_rreg (SD_, RN1);
6630 dstreg2 = translate_rreg (SD_, RN2);
6631
6632 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6633 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6634 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6635 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6636 sum = temp + temp2 + State.regs[REG_MCRL];
6637
6638 State.regs[dstreg1] = sum;
6639 State.regs[dstreg2] -= State.regs[srcreg2];
6640 }
6641
6642 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
6643 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6644 "dmach_sub"
6645 *am33
6646 {
6647 int srcreg1, dstreg1, dstreg2;
6648 long temp, temp2, sum;
6649
6650 PC = cia;
6651 srcreg1 = translate_rreg (SD_, RM1);
6652 dstreg1 = translate_rreg (SD_, RN1);
6653 dstreg2 = translate_rreg (SD_, RN2);
6654
6655 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6656 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6657 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6658 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6659 sum = temp + temp2 + State.regs[REG_MCRL];
6660
6661 State.regs[dstreg1] = sum;
6662 State.regs[dstreg2] -= EXTEND4 (IMM4);
6663 }
6664
6665 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
6666 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6667 "dmach_cmp"
6668 *am33
6669 {
6670 int srcreg1, srcreg2, dstreg1, dstreg2;
6671 long temp, temp2, sum;
6672
6673 PC = cia;
6674 srcreg1 = translate_rreg (SD_, RM1);
6675 srcreg2 = translate_rreg (SD_, RM2);
6676 dstreg1 = translate_rreg (SD_, RN1);
6677 dstreg2 = translate_rreg (SD_, RN2);
6678
6679 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6680 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6681 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6682 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6683 sum = temp + temp2 + State.regs[REG_MCRL];
6684
6685 State.regs[dstreg1] = sum;
6686 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6687 }
6688
6689 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
6690 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6691 "dmach_cmp"
6692 *am33
6693 {
6694 int srcreg1, dstreg1, dstreg2;
6695 long temp, temp2, sum;
6696
6697 PC = cia;
6698 srcreg1 = translate_rreg (SD_, RM1);
6699 dstreg1 = translate_rreg (SD_, RN1);
6700 dstreg2 = translate_rreg (SD_, RN2);
6701
6702 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6703 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6704 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6705 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6706 sum = temp + temp2 + State.regs[REG_MCRL];
6707
6708 State.regs[dstreg1] = sum;
6709 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6710 }
6711
6712 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
6713 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6714 "dmach_mov"
6715 *am33
6716 {
6717 int srcreg1, srcreg2, dstreg1, dstreg2;
6718 long temp, temp2, sum;
6719
6720 PC = cia;
6721 srcreg1 = translate_rreg (SD_, RM1);
6722 srcreg2 = translate_rreg (SD_, RM2);
6723 dstreg1 = translate_rreg (SD_, RN1);
6724 dstreg2 = translate_rreg (SD_, RN2);
6725
6726 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6727 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6728 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6729 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6730 sum = temp + temp2 + State.regs[REG_MCRL];
6731
6732 State.regs[dstreg1] = sum;
6733 State.regs[dstreg2] = State.regs[srcreg2];
6734 }
6735
6736 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
6737 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6738 "dmach_mov"
6739 *am33
6740 {
6741 int srcreg1, dstreg1, dstreg2;
6742 long temp, temp2, sum;
6743
6744 PC = cia;
6745 srcreg1 = translate_rreg (SD_, RM1);
6746 dstreg1 = translate_rreg (SD_, RN1);
6747 dstreg2 = translate_rreg (SD_, RN2);
6748
6749 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6750 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6751 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6752 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6753 sum = temp + temp2 + State.regs[REG_MCRL];
6754
6755 State.regs[dstreg1] = sum;
6756 State.regs[dstreg2] = EXTEND4 (IMM4);
6757 }
6758
6759 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
6760 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6761 "dmach_asr"
6762 *am33
6763 {
6764 int srcreg1, srcreg2, dstreg1, dstreg2;
6765 long temp, temp2, sum;
6766
6767 PC = cia;
6768 srcreg1 = translate_rreg (SD_, RM1);
6769 srcreg2 = translate_rreg (SD_, RM2);
6770 dstreg1 = translate_rreg (SD_, RN1);
6771 dstreg2 = translate_rreg (SD_, RN2);
6772
6773 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6774 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6775 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6776 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6777 sum = temp + temp2 + State.regs[REG_MCRL];
6778
6779 State.regs[dstreg1] = sum;
6780 temp = State.regs[dstreg2];
6781 temp >>= State.regs[srcreg2];
6782 State.regs[dstreg2] = temp;
6783 }
6784
6785 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
6786 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
6787 "dmach_asr"
6788 *am33
6789 {
6790 int srcreg1, dstreg1, dstreg2;
6791 long temp, temp2, sum;
6792
6793 PC = cia;
6794 srcreg1 = translate_rreg (SD_, RM1);
6795 dstreg1 = translate_rreg (SD_, RN1);
6796 dstreg2 = translate_rreg (SD_, RN2);
6797
6798 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6799 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6800 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6801 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6802 sum = temp + temp2 + State.regs[REG_MCRL];
6803
6804 State.regs[dstreg1] = sum;
6805 temp = State.regs[dstreg2];
6806 temp >>= IMM4;
6807 State.regs[dstreg2] = temp;
6808 }
6809
6810 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
6811 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
6812 "dmach_lsr"
6813 *am33
6814 {
6815 int srcreg1, srcreg2, dstreg1, dstreg2;
6816 long temp, temp2, sum;
6817
6818 PC = cia;
6819 srcreg1 = translate_rreg (SD_, RM1);
6820 srcreg2 = translate_rreg (SD_, RM2);
6821 dstreg1 = translate_rreg (SD_, RN1);
6822 dstreg2 = translate_rreg (SD_, RN2);
6823
6824 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6825 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6826 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6827 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6828 sum = temp + temp2 + State.regs[REG_MCRL];
6829
6830 State.regs[dstreg1] = sum;
6831 State.regs[dstreg2] >>= State.regs[srcreg2];
6832 }
6833
6834 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
6835 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
6836 "dmach_lsr"
6837 *am33
6838 {
6839 int srcreg1, dstreg1, dstreg2;
6840 long temp, temp2, sum;
6841
6842 PC = cia;
6843 srcreg1 = translate_rreg (SD_, RM1);
6844 dstreg1 = translate_rreg (SD_, RN1);
6845 dstreg2 = translate_rreg (SD_, RN2);
6846
6847 State.regs[dstreg2] >>= IMM4;
6848 }
6849
6850
6851 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
6852 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
6853 "dmach_asl"
6854 *am33
6855 {
6856 int srcreg1, srcreg2, dstreg1, dstreg2;
6857 long temp, temp2, sum;
6858
6859 PC = cia;
6860 srcreg1 = translate_rreg (SD_, RM1);
6861 srcreg2 = translate_rreg (SD_, RM2);
6862 dstreg1 = translate_rreg (SD_, RN1);
6863 dstreg2 = translate_rreg (SD_, RN2);
6864
6865 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6866 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6867 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6868 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6869 sum = temp + temp2 + State.regs[REG_MCRL];
6870
6871 State.regs[dstreg1] = sum;
6872 State.regs[dstreg2] <<= State.regs[srcreg2];
6873 }
6874
6875 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
6876 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
6877 "dmach_asl"
6878 *am33
6879 {
6880 int srcreg1, dstreg1, dstreg2;
6881 long temp, temp2, sum;
6882
6883 PC = cia;
6884 srcreg1 = translate_rreg (SD_, RM1);
6885 dstreg1 = translate_rreg (SD_, RN1);
6886 dstreg2 = translate_rreg (SD_, RN2);
6887
6888 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6889 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6890 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6891 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6892 sum = temp + temp2 + State.regs[REG_MCRL];
6893
6894 State.regs[dstreg1] = sum;
6895 State.regs[dstreg2] <<= IMM4;
6896 }
6897
6898 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
6899 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
6900 "xor_add"
6901 *am33
6902 {
6903 int srcreg1, srcreg2, dstreg1, dstreg2;
6904
6905 PC = cia;
6906 srcreg1 = translate_rreg (SD_, RM1);
6907 srcreg2 = translate_rreg (SD_, RM2);
6908 dstreg1 = translate_rreg (SD_, RN1);
6909 dstreg2 = translate_rreg (SD_, RN2);
6910
6911 State.regs[dstreg1] ^= State.regs[srcreg1];
6912 State.regs[dstreg2] += State.regs[srcreg2];
6913 }
6914
6915 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
6916 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
6917 "xor_add"
6918 *am33
6919 {
6920 int srcreg1, dstreg1, dstreg2;
6921
6922 PC = cia;
6923 srcreg1 = translate_rreg (SD_, RM1);
6924 dstreg1 = translate_rreg (SD_, RN1);
6925 dstreg2 = translate_rreg (SD_, RN2);
6926
6927 State.regs[dstreg1] ^= State.regs[srcreg1];
6928 State.regs[dstreg2] += EXTEND4 (IMM4);
6929 }
6930
6931 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
6932 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
6933 "xor_sub"
6934 *am33
6935 {
6936 int srcreg1, srcreg2, dstreg1, dstreg2;
6937
6938 PC = cia;
6939 srcreg1 = translate_rreg (SD_, RM1);
6940 srcreg2 = translate_rreg (SD_, RM2);
6941 dstreg1 = translate_rreg (SD_, RN1);
6942 dstreg2 = translate_rreg (SD_, RN2);
6943
6944 State.regs[dstreg1] ^= State.regs[srcreg1];
6945 State.regs[dstreg2] -= State.regs[srcreg2];
6946 }
6947
6948 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
6949 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
6950 "xor_sub"
6951 *am33
6952 {
6953 int srcreg1, dstreg1, dstreg2;
6954
6955 PC = cia;
6956 srcreg1 = translate_rreg (SD_, RM1);
6957 dstreg1 = translate_rreg (SD_, RN1);
6958 dstreg2 = translate_rreg (SD_, RN2);
6959
6960 State.regs[dstreg1] ^= State.regs[srcreg1];
6961 State.regs[dstreg2] -= EXTEND4 (IMM4);
6962 }
6963
6964 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
6965 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
6966 "xor_cmp"
6967 *am33
6968 {
6969 int srcreg1, srcreg2, dstreg1, dstreg2;
6970
6971 PC = cia;
6972 srcreg1 = translate_rreg (SD_, RM1);
6973 srcreg2 = translate_rreg (SD_, RM2);
6974 dstreg1 = translate_rreg (SD_, RN1);
6975 dstreg2 = translate_rreg (SD_, RN2);
6976
6977 State.regs[dstreg1] ^= State.regs[srcreg1];
6978 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6979 }
6980
6981 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
6982 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
6983 "xor_cmp"
6984 *am33
6985 {
6986 int srcreg1, dstreg1, dstreg2;
6987
6988 PC = cia;
6989 srcreg1 = translate_rreg (SD_, RM1);
6990 dstreg1 = translate_rreg (SD_, RN1);
6991 dstreg2 = translate_rreg (SD_, RN2);
6992
6993 State.regs[dstreg1] ^= State.regs[srcreg1];
6994 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6995 }
6996
6997 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
6998 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
6999 "xor_mov"
7000 *am33
7001 {
7002 int srcreg1, srcreg2, dstreg1, dstreg2;
7003
7004 PC = cia;
7005 srcreg1 = translate_rreg (SD_, RM1);
7006 srcreg2 = translate_rreg (SD_, RM2);
7007 dstreg1 = translate_rreg (SD_, RN1);
7008 dstreg2 = translate_rreg (SD_, RN2);
7009
7010 State.regs[dstreg1] ^= State.regs[srcreg1];
7011 State.regs[dstreg2] = State.regs[srcreg2];
7012 }
7013
7014 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7015 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7016 "xor_mov"
7017 *am33
7018 {
7019 int srcreg1, dstreg1, dstreg2;
7020
7021 PC = cia;
7022 srcreg1 = translate_rreg (SD_, RM1);
7023 dstreg1 = translate_rreg (SD_, RN1);
7024 dstreg2 = translate_rreg (SD_, RN2);
7025
7026 State.regs[dstreg1] ^= State.regs[srcreg1];
7027 State.regs[dstreg2] = EXTEND4 (IMM4);
7028 }
7029
7030 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7031 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7032 "xor_asr"
7033 *am33
7034 {
7035 int srcreg1, srcreg2, dstreg1, dstreg2;
7036 signed int temp;
7037
7038 PC = cia;
7039 srcreg1 = translate_rreg (SD_, RM1);
7040 srcreg2 = translate_rreg (SD_, RM2);
7041 dstreg1 = translate_rreg (SD_, RN1);
7042 dstreg2 = translate_rreg (SD_, RN2);
7043
7044 State.regs[dstreg1] ^= State.regs[srcreg1];
7045 temp = State.regs[dstreg2];
7046 temp >>= State.regs[srcreg2];
7047 State.regs[dstreg2] = temp;
7048 }
7049
7050 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7051 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7052 "xor_asr"
7053 *am33
7054 {
7055 int srcreg1, dstreg1, dstreg2;
7056 signed int temp;
7057
7058 PC = cia;
7059 srcreg1 = translate_rreg (SD_, RM1);
7060 dstreg1 = translate_rreg (SD_, RN1);
7061 dstreg2 = translate_rreg (SD_, RN2);
7062
7063 State.regs[dstreg1] ^= State.regs[srcreg1];
7064 temp = State.regs[dstreg2];
7065 temp >>= IMM4;
7066 State.regs[dstreg2] = temp;
7067 }
7068
7069 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7070 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7071 "xor_lsr"
7072 *am33
7073 {
7074 int srcreg1, srcreg2, dstreg1, dstreg2;
7075
7076 PC = cia;
7077 srcreg1 = translate_rreg (SD_, RM1);
7078 srcreg2 = translate_rreg (SD_, RM2);
7079 dstreg1 = translate_rreg (SD_, RN1);
7080 dstreg2 = translate_rreg (SD_, RN2);
7081
7082 State.regs[dstreg1] ^= State.regs[srcreg1];
7083 State.regs[dstreg2] >>= State.regs[srcreg2];
7084 }
7085
7086 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7087 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7088 "xor_lsr"
7089 *am33
7090 {
7091 int srcreg1, dstreg1, dstreg2;
7092 signed int temp;
7093
7094 PC = cia;
7095 srcreg1 = translate_rreg (SD_, RM1);
7096 dstreg1 = translate_rreg (SD_, RN1);
7097 dstreg2 = translate_rreg (SD_, RN2);
7098
7099 State.regs[dstreg1] ^= State.regs[srcreg1];
7100 State.regs[dstreg2] >>= IMM4;
7101 }
7102
7103
7104 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7105 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7106 "xor_asl"
7107 *am33
7108 {
7109 int srcreg1, srcreg2, dstreg1, dstreg2;
7110
7111 PC = cia;
7112 srcreg1 = translate_rreg (SD_, RM1);
7113 srcreg2 = translate_rreg (SD_, RM2);
7114 dstreg1 = translate_rreg (SD_, RN1);
7115 dstreg2 = translate_rreg (SD_, RN2);
7116
7117 State.regs[dstreg1] ^= State.regs[srcreg1];
7118 State.regs[dstreg2] <<= State.regs[srcreg2];
7119 }
7120
7121 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7122 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7123 "xor_asl"
7124 *am33
7125 {
7126 int srcreg1, dstreg1, dstreg2;
7127 signed int temp;
7128
7129 PC = cia;
7130 srcreg1 = translate_rreg (SD_, RM1);
7131 dstreg1 = translate_rreg (SD_, RN1);
7132 dstreg2 = translate_rreg (SD_, RN2);
7133
7134 State.regs[dstreg1] ^= State.regs[srcreg1];
7135 State.regs[dstreg2] <<= IMM4;
7136 }
7137
7138 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7139 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7140 "swhw_add"
7141 *am33
7142 {
7143 int srcreg1, srcreg2, dstreg1, dstreg2;
7144
7145 PC = cia;
7146 srcreg1 = translate_rreg (SD_, RM1);
7147 srcreg2 = translate_rreg (SD_, RM2);
7148 dstreg1 = translate_rreg (SD_, RN1);
7149 dstreg2 = translate_rreg (SD_, RN2);
7150
7151 State.regs[dstreg1] ^= State.regs[srcreg1];
7152 State.regs[dstreg2] += State.regs[srcreg2];
7153 }
7154
7155 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7156 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7157 "swhw_add"
7158 *am33
7159 {
7160 int srcreg1, dstreg1, dstreg2;
7161
7162 PC = cia;
7163 srcreg1 = translate_rreg (SD_, RM1);
7164 dstreg1 = translate_rreg (SD_, RN1);
7165 dstreg2 = translate_rreg (SD_, RN2);
7166
7167 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7168 | ((State.regs[srcreg1] >> 16) & 0xffff));
7169 State.regs[dstreg2] += EXTEND4 (IMM4);
7170 }
7171
7172 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7173 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7174 "swhw_sub"
7175 *am33
7176 {
7177 int srcreg1, srcreg2, dstreg1, dstreg2;
7178
7179 PC = cia;
7180 srcreg1 = translate_rreg (SD_, RM1);
7181 srcreg2 = translate_rreg (SD_, RM2);
7182 dstreg1 = translate_rreg (SD_, RN1);
7183 dstreg2 = translate_rreg (SD_, RN2);
7184
7185 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7186 | ((State.regs[srcreg1] >> 16) & 0xffff));
7187 State.regs[dstreg2] -= State.regs[srcreg2];
7188 }
7189
7190 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7191 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7192 "swhw_sub"
7193 *am33
7194 {
7195 int srcreg1, dstreg1, dstreg2;
7196
7197 PC = cia;
7198 srcreg1 = translate_rreg (SD_, RM1);
7199 dstreg1 = translate_rreg (SD_, RN1);
7200 dstreg2 = translate_rreg (SD_, RN2);
7201
7202 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7203 | ((State.regs[srcreg1] >> 16) & 0xffff));
7204 State.regs[dstreg2] -= EXTEND4 (IMM4);
7205 }
7206
7207 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7208 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7209 "swhw_cmp"
7210 *am33
7211 {
7212 int srcreg1, srcreg2, dstreg1, dstreg2;
7213
7214 PC = cia;
7215 srcreg1 = translate_rreg (SD_, RM1);
7216 srcreg2 = translate_rreg (SD_, RM2);
7217 dstreg1 = translate_rreg (SD_, RN1);
7218 dstreg2 = translate_rreg (SD_, RN2);
7219
7220 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7221 | ((State.regs[srcreg1] >> 16) & 0xffff));
7222 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7223 }
7224
7225 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7226 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7227 "swhw_cmp"
7228 *am33
7229 {
7230 int srcreg1, dstreg1, dstreg2;
7231
7232 PC = cia;
7233 srcreg1 = translate_rreg (SD_, RM1);
7234 dstreg1 = translate_rreg (SD_, RN1);
7235 dstreg2 = translate_rreg (SD_, RN2);
7236
7237 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7238 | ((State.regs[srcreg1] >> 16) & 0xffff));
7239 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7240 }
7241
7242 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7243 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7244 "swhw_mov"
7245 *am33
7246 {
7247 int srcreg1, srcreg2, dstreg1, dstreg2;
7248
7249 PC = cia;
7250 srcreg1 = translate_rreg (SD_, RM1);
7251 srcreg2 = translate_rreg (SD_, RM2);
7252 dstreg1 = translate_rreg (SD_, RN1);
7253 dstreg2 = translate_rreg (SD_, RN2);
7254
7255 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7256 | ((State.regs[srcreg1] >> 16) & 0xffff));
7257 State.regs[dstreg2] = State.regs[srcreg2];
7258 }
7259
7260 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7261 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7262 "swhw_mov"
7263 *am33
7264 {
7265 int srcreg1, dstreg1, dstreg2;
7266
7267 PC = cia;
7268 srcreg1 = translate_rreg (SD_, RM1);
7269 dstreg1 = translate_rreg (SD_, RN1);
7270 dstreg2 = translate_rreg (SD_, RN2);
7271
7272 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7273 | ((State.regs[srcreg1] >> 16) & 0xffff));
7274 State.regs[dstreg2] = EXTEND4 (IMM4);
7275 }
7276
7277 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7278 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7279 "swhw_asr"
7280 *am33
7281 {
7282 int srcreg1, srcreg2, dstreg1, dstreg2;
7283 signed int temp;
7284
7285 PC = cia;
7286 srcreg1 = translate_rreg (SD_, RM1);
7287 srcreg2 = translate_rreg (SD_, RM2);
7288 dstreg1 = translate_rreg (SD_, RN1);
7289 dstreg2 = translate_rreg (SD_, RN2);
7290
7291 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7292 | ((State.regs[srcreg1] >> 16) & 0xffff));
7293 temp = State.regs[dstreg2];
7294 temp >>= State.regs[srcreg2];
7295 State.regs[dstreg2] = temp;
7296 }
7297
7298 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7299 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7300 "swhw_asr"
7301 *am33
7302 {
7303 int srcreg1, dstreg1, dstreg2;
7304 signed int temp;
7305
7306 PC = cia;
7307 srcreg1 = translate_rreg (SD_, RM1);
7308 dstreg1 = translate_rreg (SD_, RN1);
7309 dstreg2 = translate_rreg (SD_, RN2);
7310
7311 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7312 | ((State.regs[srcreg1] >> 16) & 0xffff));
7313 temp = State.regs[dstreg2];
7314 temp >>= IMM4;
7315 State.regs[dstreg2] = temp;
7316 }
7317
7318 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7319 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7320 "swhw_lsr"
7321 *am33
7322 {
7323 int srcreg1, srcreg2, dstreg1, dstreg2;
7324
7325 PC = cia;
7326 srcreg1 = translate_rreg (SD_, RM1);
7327 srcreg2 = translate_rreg (SD_, RM2);
7328 dstreg1 = translate_rreg (SD_, RN1);
7329 dstreg2 = translate_rreg (SD_, RN2);
7330
7331 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7332 | ((State.regs[srcreg1] >> 16) & 0xffff));
7333 State.regs[dstreg2] >>= State.regs[srcreg2];
7334 }
7335
7336 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7337 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7338 "swhw_lsr"
7339 *am33
7340 {
7341 int srcreg1, dstreg1, dstreg2;
7342 signed int temp;
7343
7344 PC = cia;
7345 srcreg1 = translate_rreg (SD_, RM1);
7346 dstreg1 = translate_rreg (SD_, RN1);
7347 dstreg2 = translate_rreg (SD_, RN2);
7348
7349 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7350 | ((State.regs[srcreg1] >> 16) & 0xffff));
7351 State.regs[dstreg2] >>= IMM4;
7352 }
7353
7354
7355 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7356 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7357 "swhw_asl"
7358 *am33
7359 {
7360 int srcreg1, srcreg2, dstreg1, dstreg2;
7361
7362 PC = cia;
7363 srcreg1 = translate_rreg (SD_, RM1);
7364 srcreg2 = translate_rreg (SD_, RM2);
7365 dstreg1 = translate_rreg (SD_, RN1);
7366 dstreg2 = translate_rreg (SD_, RN2);
7367
7368 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7369 | ((State.regs[srcreg1] >> 16) & 0xffff));
7370 State.regs[dstreg2] <<= State.regs[srcreg2];
7371 }
7372
7373 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7374 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7375 "swhw_asl"
7376 *am33
7377 {
7378 int srcreg1, dstreg1, dstreg2;
7379 signed int temp;
7380
7381 PC = cia;
7382 srcreg1 = translate_rreg (SD_, RM1);
7383 dstreg1 = translate_rreg (SD_, RN1);
7384 dstreg2 = translate_rreg (SD_, RN2);
7385
7386 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7387 | ((State.regs[srcreg1] >> 16) & 0xffff));
7388 State.regs[dstreg2] <<= IMM4;
7389 }
7390
7391 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7392 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7393 "or_add"
7394 *am33
7395 {
7396 int srcreg1, srcreg2, dstreg1, dstreg2;
7397
7398 PC = cia;
7399 srcreg1 = translate_rreg (SD_, RM1);
7400 srcreg2 = translate_rreg (SD_, RM2);
7401 dstreg1 = translate_rreg (SD_, RN1);
7402 dstreg2 = translate_rreg (SD_, RN2);
7403
7404 State.regs[dstreg1] |= State.regs[srcreg1];
7405 State.regs[dstreg2] += State.regs[srcreg2];
7406 }
7407
7408 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7409 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7410 "or_add"
7411 *am33
7412 {
7413 int srcreg1, dstreg1, dstreg2;
7414
7415 PC = cia;
7416 srcreg1 = translate_rreg (SD_, RM1);
7417 dstreg1 = translate_rreg (SD_, RN1);
7418 dstreg2 = translate_rreg (SD_, RN2);
7419
7420 State.regs[dstreg1] |= State.regs[srcreg1];
7421 State.regs[dstreg2] += EXTEND4 (IMM4);
7422 }
7423
7424 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7425 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7426 "or_sub"
7427 *am33
7428 {
7429 int srcreg1, srcreg2, dstreg1, dstreg2;
7430
7431 PC = cia;
7432 srcreg1 = translate_rreg (SD_, RM1);
7433 srcreg2 = translate_rreg (SD_, RM2);
7434 dstreg1 = translate_rreg (SD_, RN1);
7435 dstreg2 = translate_rreg (SD_, RN2);
7436
7437 State.regs[dstreg1] |= State.regs[srcreg1];
7438 State.regs[dstreg2] -= State.regs[srcreg2];
7439 }
7440
7441 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7442 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7443 "or_sub"
7444 *am33
7445 {
7446 int srcreg1, dstreg1, dstreg2;
7447
7448 PC = cia;
7449 srcreg1 = translate_rreg (SD_, RM1);
7450 dstreg1 = translate_rreg (SD_, RN1);
7451 dstreg2 = translate_rreg (SD_, RN2);
7452
7453 State.regs[dstreg1] |= State.regs[srcreg1];
7454 State.regs[dstreg2] -= EXTEND4 (IMM4);
7455 }
7456
7457 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7458 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7459 "or_cmp"
7460 *am33
7461 {
7462 int srcreg1, srcreg2, dstreg1, dstreg2;
7463
7464 PC = cia;
7465 srcreg1 = translate_rreg (SD_, RM1);
7466 srcreg2 = translate_rreg (SD_, RM2);
7467 dstreg1 = translate_rreg (SD_, RN1);
7468 dstreg2 = translate_rreg (SD_, RN2);
7469
7470 State.regs[dstreg1] |= State.regs[srcreg1];
7471 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7472 }
7473
7474 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7475 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7476 "or_cmp"
7477 *am33
7478 {
7479 int srcreg1, dstreg1, dstreg2;
7480
7481 PC = cia;
7482 srcreg1 = translate_rreg (SD_, RM1);
7483 dstreg1 = translate_rreg (SD_, RN1);
7484 dstreg2 = translate_rreg (SD_, RN2);
7485
7486 State.regs[dstreg1] |= State.regs[srcreg1];
7487 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7488 }
7489
7490 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7491 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7492 "or_mov"
7493 *am33
7494 {
7495 int srcreg1, srcreg2, dstreg1, dstreg2;
7496
7497 PC = cia;
7498 srcreg1 = translate_rreg (SD_, RM1);
7499 srcreg2 = translate_rreg (SD_, RM2);
7500 dstreg1 = translate_rreg (SD_, RN1);
7501 dstreg2 = translate_rreg (SD_, RN2);
7502
7503 State.regs[dstreg1] |= State.regs[srcreg1];
7504 State.regs[dstreg2] = State.regs[srcreg2];
7505 }
7506
7507 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7508 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7509 "or_mov"
7510 *am33
7511 {
7512 int srcreg1, dstreg1, dstreg2;
7513
7514 PC = cia;
7515 srcreg1 = translate_rreg (SD_, RM1);
7516 dstreg1 = translate_rreg (SD_, RN1);
7517 dstreg2 = translate_rreg (SD_, RN2);
7518
7519 State.regs[dstreg1] |= State.regs[srcreg1];
7520 State.regs[dstreg2] = EXTEND4 (IMM4);
7521 }
7522
7523 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7524 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7525 "or_asr"
7526 *am33
7527 {
7528 int srcreg1, srcreg2, dstreg1, dstreg2;
7529 signed int temp;
7530
7531 PC = cia;
7532 srcreg1 = translate_rreg (SD_, RM1);
7533 srcreg2 = translate_rreg (SD_, RM2);
7534 dstreg1 = translate_rreg (SD_, RN1);
7535 dstreg2 = translate_rreg (SD_, RN2);
7536
7537 State.regs[dstreg1] |= State.regs[srcreg1];
7538 temp = State.regs[dstreg2];
7539 temp >>= State.regs[srcreg2];
7540 State.regs[dstreg2] = temp;
7541 }
7542
7543 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
7544 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7545 "or_asr"
7546 *am33
7547 {
7548 int srcreg1, dstreg1, dstreg2;
7549 signed int temp;
7550
7551 PC = cia;
7552 srcreg1 = translate_rreg (SD_, RM1);
7553 dstreg1 = translate_rreg (SD_, RN1);
7554 dstreg2 = translate_rreg (SD_, RN2);
7555
7556 State.regs[dstreg1] |= State.regs[srcreg1];
7557 temp = State.regs[dstreg2];
7558 temp >>= IMM4;
7559 State.regs[dstreg2] = temp;
7560 }
7561
7562 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
7563 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7564 "or_lsr"
7565 *am33
7566 {
7567 int srcreg1, srcreg2, dstreg1, dstreg2;
7568
7569 PC = cia;
7570 srcreg1 = translate_rreg (SD_, RM1);
7571 srcreg2 = translate_rreg (SD_, RM2);
7572 dstreg1 = translate_rreg (SD_, RN1);
7573 dstreg2 = translate_rreg (SD_, RN2);
7574
7575 State.regs[dstreg1] |= State.regs[srcreg1];
7576 State.regs[dstreg2] >>= State.regs[srcreg2];
7577 }
7578
7579 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
7580 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7581 "or_lsr"
7582 *am33
7583 {
7584 int srcreg1, dstreg1, dstreg2;
7585 signed int temp;
7586
7587 PC = cia;
7588 srcreg1 = translate_rreg (SD_, RM1);
7589 dstreg1 = translate_rreg (SD_, RN1);
7590 dstreg2 = translate_rreg (SD_, RN2);
7591
7592 State.regs[dstreg1] |= State.regs[srcreg1];
7593 State.regs[dstreg2] >>= IMM4;
7594 }
7595
7596
7597 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
7598 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7599 "or_asl"
7600 *am33
7601 {
7602 int srcreg1, srcreg2, dstreg1, dstreg2;
7603
7604 PC = cia;
7605 srcreg1 = translate_rreg (SD_, RM1);
7606 srcreg2 = translate_rreg (SD_, RM2);
7607 dstreg1 = translate_rreg (SD_, RN1);
7608 dstreg2 = translate_rreg (SD_, RN2);
7609
7610 State.regs[dstreg1] |= State.regs[srcreg1];
7611 State.regs[dstreg2] <<= State.regs[srcreg2];
7612 }
7613
7614 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
7615 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7616 "or_asl"
7617 *am33
7618 {
7619 int srcreg1, dstreg1, dstreg2;
7620 signed int temp;
7621
7622 PC = cia;
7623 srcreg1 = translate_rreg (SD_, RM1);
7624 dstreg1 = translate_rreg (SD_, RN1);
7625 dstreg2 = translate_rreg (SD_, RN2);
7626
7627 State.regs[dstreg1] |= State.regs[srcreg1];
7628 State.regs[dstreg2] <<= IMM4;
7629 }
7630
7631 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
7632 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7633 "sat16_add"
7634 *am33
7635 {
7636 int srcreg1, srcreg2, dstreg1, dstreg2;
7637
7638 PC = cia;
7639 srcreg1 = translate_rreg (SD_, RM1);
7640 srcreg2 = translate_rreg (SD_, RM2);
7641 dstreg1 = translate_rreg (SD_, RN1);
7642 dstreg2 = translate_rreg (SD_, RN2);
7643
7644 if (State.regs[srcreg1] >= 0x7fff)
7645 State.regs[dstreg1] = 0x7fff;
7646 else if (State.regs[srcreg1] <= 0xffff8000)
7647 State.regs[dstreg1] = 0xffff8000;
7648 else
7649 State.regs[dstreg1] = State.regs[srcreg1];
7650
7651 State.regs[dstreg2] += State.regs[srcreg2];
7652 }
7653
7654 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
7655 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7656 "sat16_add"
7657 *am33
7658 {
7659 int srcreg1, dstreg1, dstreg2;
7660
7661 PC = cia;
7662 srcreg1 = translate_rreg (SD_, RM1);
7663 dstreg1 = translate_rreg (SD_, RN1);
7664 dstreg2 = translate_rreg (SD_, RN2);
7665
7666 if (State.regs[srcreg1] >= 0x7fff)
7667 State.regs[dstreg1] = 0x7fff;
7668 else if (State.regs[srcreg1] <= 0xffff8000)
7669 State.regs[dstreg1] = 0xffff8000;
7670 else
7671 State.regs[dstreg1] = State.regs[srcreg1];
7672
7673 State.regs[dstreg2] += EXTEND4 (IMM4);
7674 }
7675
7676 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
7677 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7678 "sat16_sub"
7679 *am33
7680 {
7681 int srcreg1, srcreg2, dstreg1, dstreg2;
7682
7683 PC = cia;
7684 srcreg1 = translate_rreg (SD_, RM1);
7685 srcreg2 = translate_rreg (SD_, RM2);
7686 dstreg1 = translate_rreg (SD_, RN1);
7687 dstreg2 = translate_rreg (SD_, RN2);
7688
7689 if (State.regs[srcreg1] >= 0x7fff)
7690 State.regs[dstreg1] = 0x7fff;
7691 else if (State.regs[srcreg1] <= 0xffff8000)
7692 State.regs[dstreg1] = 0xffff8000;
7693 else
7694 State.regs[dstreg1] = State.regs[srcreg1];
7695
7696 State.regs[dstreg2] -= State.regs[srcreg2];
7697 }
7698
7699 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
7700 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7701 "sat16_sub"
7702 *am33
7703 {
7704 int srcreg1, dstreg1, dstreg2;
7705
7706 PC = cia;
7707 srcreg1 = translate_rreg (SD_, RM1);
7708 dstreg1 = translate_rreg (SD_, RN1);
7709 dstreg2 = translate_rreg (SD_, RN2);
7710
7711 if (State.regs[srcreg1] >= 0x7fff)
7712 State.regs[dstreg1] = 0x7fff;
7713 else if (State.regs[srcreg1] <= 0xffff8000)
7714 State.regs[dstreg1] = 0xffff8000;
7715 else
7716 State.regs[dstreg1] = State.regs[srcreg1];
7717
7718 State.regs[dstreg2] -= EXTEND4 (IMM4);
7719 }
7720
7721 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
7722 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7723 "sat16_cmp"
7724 *am33
7725 {
7726 int srcreg1, srcreg2, dstreg1, dstreg2;
7727
7728 PC = cia;
7729 srcreg1 = translate_rreg (SD_, RM1);
7730 srcreg2 = translate_rreg (SD_, RM2);
7731 dstreg1 = translate_rreg (SD_, RN1);
7732 dstreg2 = translate_rreg (SD_, RN2);
7733
7734 if (State.regs[srcreg1] >= 0x7fff)
7735 State.regs[dstreg1] = 0x7fff;
7736 else if (State.regs[srcreg1] <= 0xffff8000)
7737 State.regs[dstreg1] = 0xffff8000;
7738 else
7739 State.regs[dstreg1] = State.regs[srcreg1];
7740
7741 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7742 }
7743
7744 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
7745 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7746 "sat16_cmp"
7747 *am33
7748 {
7749 int srcreg1, dstreg1, dstreg2;
7750
7751 PC = cia;
7752 srcreg1 = translate_rreg (SD_, RM1);
7753 dstreg1 = translate_rreg (SD_, RN1);
7754 dstreg2 = translate_rreg (SD_, RN2);
7755
7756 if (State.regs[srcreg1] >= 0x7fff)
7757 State.regs[dstreg1] = 0x7fff;
7758 else if (State.regs[srcreg1] <= 0xffff8000)
7759 State.regs[dstreg1] = 0xffff8000;
7760 else
7761 State.regs[dstreg1] = State.regs[srcreg1];
7762
7763 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7764 }
7765
7766 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
7767 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7768 "sat16_mov"
7769 *am33
7770 {
7771 int srcreg1, srcreg2, dstreg1, dstreg2;
7772
7773 PC = cia;
7774 srcreg1 = translate_rreg (SD_, RM1);
7775 srcreg2 = translate_rreg (SD_, RM2);
7776 dstreg1 = translate_rreg (SD_, RN1);
7777 dstreg2 = translate_rreg (SD_, RN2);
7778
7779 if (State.regs[srcreg1] >= 0x7fff)
7780 State.regs[dstreg1] = 0x7fff;
7781 else if (State.regs[srcreg1] <= 0xffff8000)
7782 State.regs[dstreg1] = 0xffff8000;
7783 else
7784 State.regs[dstreg1] = State.regs[srcreg1];
7785
7786 State.regs[dstreg2] = State.regs[srcreg2];
7787 }
7788
7789 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
7790 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
7791 "sat16_mov"
7792 *am33
7793 {
7794 int srcreg1, dstreg1, dstreg2;
7795
7796 PC = cia;
7797 srcreg1 = translate_rreg (SD_, RM1);
7798 dstreg1 = translate_rreg (SD_, RN1);
7799 dstreg2 = translate_rreg (SD_, RN2);
7800
7801 if (State.regs[srcreg1] >= 0x7fff)
7802 State.regs[dstreg1] = 0x7fff;
7803 else if (State.regs[srcreg1] <= 0xffff8000)
7804 State.regs[dstreg1] = 0xffff8000;
7805 else
7806 State.regs[dstreg1] = State.regs[srcreg1];
7807
7808 State.regs[dstreg2] = EXTEND4 (IMM4);
7809 }
7810
7811 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
7812 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
7813 "sat16_asr"
7814 *am33
7815 {
7816 int srcreg1, srcreg2, dstreg1, dstreg2;
7817 signed int temp;
7818
7819 PC = cia;
7820 srcreg1 = translate_rreg (SD_, RM1);
7821 srcreg2 = translate_rreg (SD_, RM2);
7822 dstreg1 = translate_rreg (SD_, RN1);
7823 dstreg2 = translate_rreg (SD_, RN2);
7824
7825 if (State.regs[srcreg1] >= 0x7fff)
7826 State.regs[dstreg1] = 0x7fff;
7827 else if (State.regs[srcreg1] <= 0xffff8000)
7828 State.regs[dstreg1] = 0xffff8000;
7829 else
7830 State.regs[dstreg1] = State.regs[srcreg1];
7831
7832 temp = State.regs[dstreg2];
7833 temp >>= State.regs[srcreg2];
7834 State.regs[dstreg2] = temp;
7835 }
7836
7837 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
7838 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
7839 "sat16_asr"
7840 *am33
7841 {
7842 int srcreg1, dstreg1, dstreg2;
7843 signed int temp;
7844
7845 PC = cia;
7846 srcreg1 = translate_rreg (SD_, RM1);
7847 dstreg1 = translate_rreg (SD_, RN1);
7848 dstreg2 = translate_rreg (SD_, RN2);
7849
7850 if (State.regs[srcreg1] >= 0x7fff)
7851 State.regs[dstreg1] = 0x7fff;
7852 else if (State.regs[srcreg1] <= 0xffff8000)
7853 State.regs[dstreg1] = 0xffff8000;
7854 else
7855 State.regs[dstreg1] = State.regs[srcreg1];
7856
7857 temp = State.regs[dstreg2];
7858 temp >>= IMM4;
7859 State.regs[dstreg2] = temp;
7860 }
7861
7862 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
7863 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
7864 "sat16_lsr"
7865 *am33
7866 {
7867 int srcreg1, srcreg2, dstreg1, dstreg2;
7868
7869 PC = cia;
7870 srcreg1 = translate_rreg (SD_, RM1);
7871 srcreg2 = translate_rreg (SD_, RM2);
7872 dstreg1 = translate_rreg (SD_, RN1);
7873 dstreg2 = translate_rreg (SD_, RN2);
7874
7875 if (State.regs[srcreg1] >= 0x7fff)
7876 State.regs[dstreg1] = 0x7fff;
7877 else if (State.regs[srcreg1] <= 0xffff8000)
7878 State.regs[dstreg1] = 0xffff8000;
7879 else
7880 State.regs[dstreg1] = State.regs[srcreg1];
7881
7882 State.regs[dstreg2] >>= State.regs[srcreg2];
7883 }
7884
7885 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
7886 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
7887 "sat16_lsr"
7888 *am33
7889 {
7890 int srcreg1, dstreg1, dstreg2;
7891 signed int temp;
7892
7893 PC = cia;
7894 srcreg1 = translate_rreg (SD_, RM1);
7895 dstreg1 = translate_rreg (SD_, RN1);
7896 dstreg2 = translate_rreg (SD_, RN2);
7897
7898 if (State.regs[srcreg1] >= 0x7fff)
7899 State.regs[dstreg1] = 0x7fff;
7900 else if (State.regs[srcreg1] <= 0xffff8000)
7901 State.regs[dstreg1] = 0xffff8000;
7902 else
7903 State.regs[dstreg1] = State.regs[srcreg1];
7904
7905 State.regs[dstreg2] >>= IMM4;
7906 }
7907
7908
7909 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
7910 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
7911 "sat16_asl"
7912 *am33
7913 {
7914 int srcreg1, srcreg2, dstreg1, dstreg2;
7915
7916 PC = cia;
7917 srcreg1 = translate_rreg (SD_, RM1);
7918 srcreg2 = translate_rreg (SD_, RM2);
7919 dstreg1 = translate_rreg (SD_, RN1);
7920 dstreg2 = translate_rreg (SD_, RN2);
7921
7922 if (State.regs[srcreg1] >= 0x7fff)
7923 State.regs[dstreg1] = 0x7fff;
7924 else if (State.regs[srcreg1] <= 0xffff8000)
7925 State.regs[dstreg1] = 0xffff8000;
7926 else
7927 State.regs[dstreg1] = State.regs[srcreg1];
7928
7929 State.regs[dstreg2] <<= State.regs[srcreg2];
7930 }
7931
7932 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
7933 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
7934 "sat16_asl"
7935 *am33
7936 {
7937 int srcreg1, dstreg1, dstreg2;
7938 signed int temp;
7939
7940 PC = cia;
7941 srcreg1 = translate_rreg (SD_, RM1);
7942 dstreg1 = translate_rreg (SD_, RN1);
7943 dstreg2 = translate_rreg (SD_, RN2);
7944
7945 if (State.regs[srcreg1] >= 0x7fff)
7946 State.regs[dstreg1] = 0x7fff;
7947 else if (State.regs[srcreg1] <= 0xffff8000)
7948 State.regs[dstreg1] = 0xffff8000;
7949 else
7950 State.regs[dstreg1] = State.regs[srcreg1];
7951
7952 State.regs[dstreg2] <<= IMM4;
7953 }
7954
GDB Binutils - Deliverables
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