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* am33.igen: Add remaining non-DSP instructions.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // Helper:
2 //
3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
6 //
7 //
8
9 :function:::int:translate_rreg:int rreg
10 {
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20 }
21
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
24 "mov"
25 *am33
26 {
27 PC = cia;
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
29 }
30
31
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
34 "mov"
35 *am33
36 {
37 PC = cia;
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
39 }
40
41
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
44 "mov"
45 *am33
46 {
47 PC = cia;
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
49 }
50
51
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
54 "mov"
55 *am33
56 {
57 PC = cia;
58 State.regs[REG_A0 + AN0] = PC;
59 }
60
61
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
64 "mov"
65 *am33
66 {
67 PC = cia;
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
69 }
70
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
73 "mov"
74 *am33
75 {
76 PC = cia;
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
78 }
79
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
82 "mov"
83 *am33
84 {
85 PC = cia;
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
87 }
88
89
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
92 "syscall"
93 *am33
94 {
95 unsigned int sp, next_pc;
96
97 PC = cia;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
103 nia = PC;
104 }
105
106
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
109 "mov"
110 *am33
111 {
112 PC = cia;
113 State.regs[REG_D0 + DN0] = PSW;
114 }
115
116
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
119 "mov"
120 *am33
121 {
122 PC = cia;
123 PSW = State.regs[REG_D0 + DM1];
124 }
125
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
128 "mov"
129 *am33
130 {
131 int destreg = translate_rreg (SD_, RN0);
132
133 PC = cia;
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
135 }
136
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
139 "mov"
140 *am33
141 {
142 int destreg = translate_rreg (SD_, RN0);
143
144 PC = cia;
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
146 }
147
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
150 "mov"
151 *am33
152 {
153 int destreg = translate_rreg (SD_, RM1);
154
155 PC = cia;
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
157 }
158
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
161 "mov"
162 *am33
163 {
164 int destreg = translate_rreg (SD_, RM1);
165
166 PC = cia;
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
168 }
169
170
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
173 "movm"
174 *am33
175 {
176 unsigned long usp = State.regs[REG_USP];
177 unsigned long mask;
178
179 PC = cia;
180 mask = REGS;
181
182 if (mask & 0x8)
183 {
184 usp += 4;
185 State.regs[REG_LAR] = load_word (usp);
186 usp += 4;
187 State.regs[REG_LIR] = load_word (usp);
188 usp += 4;
189 State.regs[REG_MDR] = load_word (usp);
190 usp += 4;
191 State.regs[REG_A0 + 1] = load_word (usp);
192 usp += 4;
193 State.regs[REG_A0] = load_word (usp);
194 usp += 4;
195 State.regs[REG_D0 + 1] = load_word (usp);
196 usp += 4;
197 State.regs[REG_D0] = load_word (usp);
198 usp += 4;
199 }
200
201 if (mask & 0x10)
202 {
203 State.regs[REG_A0 + 3] = load_word (usp);
204 usp += 4;
205 }
206
207 if (mask & 0x20)
208 {
209 State.regs[REG_A0 + 2] = load_word (usp);
210 usp += 4;
211 }
212
213 if (mask & 0x40)
214 {
215 State.regs[REG_D0 + 3] = load_word (usp);
216 usp += 4;
217 }
218
219 if (mask & 0x80)
220 {
221 State.regs[REG_D0 + 2] = load_word (usp);
222 usp += 4;
223 }
224
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
227 {
228 if (mask & 0x1)
229 {
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 usp += 16;
232 State.regs[REG_E0 + 1] = load_word (usp);
233 usp += 4;
234 State.regs[REG_E0 + 0] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x2)
239 {
240 State.regs[REG_E0 + 7] = load_word (usp);
241 usp += 4;
242 State.regs[REG_E0 + 6] = load_word (usp);
243 usp += 4;
244 State.regs[REG_E0 + 5] = load_word (usp);
245 usp += 4;
246 State.regs[REG_E0 + 4] = load_word (usp);
247 usp += 4;
248 }
249
250 if (mask & 0x4)
251 {
252 State.regs[REG_E0 + 3] = load_word (usp);
253 usp += 4;
254 State.regs[REG_E0 + 2] = load_word (usp);
255 usp += 4;
256 }
257 }
258 /* end-sanitize-am33 */
259
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
262 }
263
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
266 "movm"
267 *am33
268 {
269 unsigned long usp = State.regs[REG_USP];
270 unsigned long mask;
271
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
273 {
274 if (mask & 0x4)
275 {
276 usp -= 4;
277 store_word (usp, State.regs[REG_E0 + 2]);
278 usp -= 4;
279 store_word (usp, State.regs[REG_E0 + 3]);
280 }
281
282 if (mask & 0x2)
283 {
284 usp -= 4;
285 store_word (usp, State.regs[REG_E0 + 4]);
286 usp -= 4;
287 store_word (usp, State.regs[REG_E0 + 5]);
288 usp -= 4;
289 store_word (usp, State.regs[REG_E0 + 6]);
290 usp -= 4;
291 store_word (usp, State.regs[REG_E0 + 7]);
292 }
293
294 if (mask & 0x1)
295 {
296 usp -= 4;
297 store_word (usp, State.regs[REG_E0 + 0]);
298 usp -= 4;
299 store_word (usp, State.regs[REG_E0 + 1]);
300 usp -= 16;
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
302 }
303 }
304 /* end-sanitize-am33 */
305
306 if (mask & 0x80)
307 {
308 usp -= 4;
309 store_word (usp, State.regs[REG_D0 + 2]);
310 }
311
312 if (mask & 0x40)
313 {
314 usp -= 4;
315 store_word (usp, State.regs[REG_D0 + 3]);
316 }
317
318 if (mask & 0x20)
319 {
320 usp -= 4;
321 store_word (usp, State.regs[REG_A0 + 2]);
322 }
323
324 if (mask & 0x10)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_A0 + 3]);
328 }
329
330 if (mask & 0x8)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0]);
334 usp -= 4;
335 store_word (usp, State.regs[REG_D0 + 1]);
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0]);
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 1]);
340 usp -= 4;
341 store_word (usp, State.regs[REG_MDR]);
342 usp -= 4;
343 store_word (usp, State.regs[REG_LIR]);
344 usp -= 4;
345 store_word (usp, State.regs[REG_LAR]);
346 usp -= 4;
347 }
348
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
351 }
352
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
355 "and"
356 *am33
357 {
358 PC = cia;
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
360 }
361
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
364 "or"
365 *am33
366 {
367 PC = cia;
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
369 }
370
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
373 "mov"
374 *am33
375 {
376 int srcreg, dstreg;
377
378 PC = cia;
379
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
383 }
384
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
387 "mov"
388 *am33
389 {
390 int srcreg;
391
392 PC = cia;
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
396 else
397 State.regs[REG_MDR] = 0;
398 }
399
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
402 "extb"
403 *am33
404 {
405 int srcreg, dstreg;
406
407 PC = cia;
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
411 }
412
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
415 "extbu"
416 *am33
417 {
418 int srcreg, dstreg;
419
420 PC = cia;
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
424 }
425
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
428 "exth"
429 *am33
430 {
431 int srcreg, dstreg;
432
433 PC = cia;
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
437 }
438
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
441 "exthu"
442 *am33
443 {
444 int srcreg, dstreg;
445
446 PC = cia;
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
450 }
451
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
454 "clr"
455 *am33
456 {
457 int dstreg;
458
459 PC = cia;
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
462 PSW |= PSW_Z;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
464 }
465
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
468 "add"
469 *am33
470 {
471 int srcreg, dstreg;
472
473 PC = cia;
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
477 }
478
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
481 "addc"
482 *am33
483 {
484 int srcreg, dstreg;
485 int z, c, n, v;
486 unsigned long reg1, reg2, sum;
487
488 PC = cia;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
491
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
496
497 z = (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
502
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
506 }
507
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
510 "sub"
511 *am33
512 {
513 int srcreg, dstreg;
514
515 PC = cia;
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
519 }
520
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
523 "subc"
524 *am33
525 {
526 int srcreg, dstreg;
527 int z, c, n, v;
528 unsigned long reg1, reg2, difference;
529
530 PC = cia;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
533
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
538
539 z = (difference == 0);
540 n = (difference & 0x80000000);
541 c = (reg1 > reg2);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
544
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
548 }
549
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
552 "inc"
553 *am33
554 {
555 int dstreg;
556
557 PC = cia;
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
560 }
561
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
564 "inc4"
565 *am33
566 {
567 int dstreg;
568
569 PC = cia;
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
572 }
573
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
576 "cmp"
577 *am33
578 {
579 int srcreg1, srcreg2;
580
581 PC = cia;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
585 }
586
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
589 "mov"
590 *am33
591 {
592 int dstreg;
593
594 PC = cia;
595 dstreg = translate_rreg (SD_, RN0);
596
597 if (XRM2 == 0)
598 {
599 State.regs[dstreg] = State.regs[REG_SP];
600 }
601 else
602 abort ();
603 }
604
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
607 "mov"
608 *am33
609 {
610 int srcreg;
611
612 PC = cia;
613 srcreg = translate_rreg (SD_, RM2);
614
615 if (XRN0 == 0)
616 {
617 State.regs[REG_SP] = State.regs[srcreg];
618 }
619 else
620 abort ();
621 }
622
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
625 "and"
626 *am33
627 {
628 int srcreg, dstreg;
629 int z, n;
630
631 PC = cia;
632
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
635
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
641 }
642
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
645 "or"
646 *am33
647 {
648 int srcreg, dstreg;
649 int z, n;
650
651 PC = cia;
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
654
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
660 }
661
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
664 "xor"
665 *am33
666 {
667 int srcreg, dstreg;
668 int z, n;
669
670 PC = cia;
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
673
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
679 }
680
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
683 "not"
684 *am33
685 {
686 int dstreg;
687 int z, n;
688
689 PC = cia;
690 dstreg = translate_rreg (SD_, RN0);
691
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
697 }
698
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
701 "asr"
702 *am33
703 {
704 int srcreg, dstreg;
705 long temp;
706 int c, z, n;
707
708 PC = cia;
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
711
712 temp = State.regs[dstreg];
713 c = temp & 1;
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
720 }
721
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
724 "lsr"
725 *am33
726 {
727 int srcreg, dstreg;
728 int z, n, c;
729
730 PC = cia;
731
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
734
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
741 }
742
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
745 "asl"
746 *am33
747 {
748 int srcreg, dstreg;
749 int z, n;
750
751 PC = cia;
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
754
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
760 }
761
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
764 "asl2"
765 *am33
766 {
767 int dstreg;
768 int n, z;
769
770 PC = cia;
771 dstreg = translate_rreg (SD_, RN0);
772
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
778 }
779
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
782 "ror"
783 *am33
784 {
785 int dstreg;
786 int c, n, z;
787 unsigned long value;
788
789 PC = cia;
790 dstreg = translate_rreg (SD_, RN0);
791
792 value = State.regs[dstreg];
793 c = (value & 0x1);
794
795 value >>= 1;
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
798 z = (value == 0);
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
802 }
803
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
806 "rol"
807 *am33
808 {
809 int dstreg;
810 int c, n, z;
811 unsigned long value;
812
813 PC = cia;
814 dstreg = translate_rreg (SD_, RN0);
815
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
818
819 value <<= 1;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
822 z = (value == 0);
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
826 }
827
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
830 "mul"
831 *am33
832 {
833 int srcreg, dstreg;
834 unsigned long long temp;
835 int n, z;
836
837 PC = cia;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
840
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849 }
850
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
853 "mulu"
854 *am33
855 {
856 int srcreg, dstreg;
857 unsigned long long temp;
858 int n, z;
859
860 PC = cia;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
863
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
872 }
873
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
876 "div"
877 *am33
878 {
879 int srcreg, dstreg;
880 long long temp;
881 int n, z;
882
883 PC = cia;
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
886
887 temp = State.regs[REG_MDR];
888 temp <<= 32;
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (long)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
897 }
898
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
901 "divu"
902 *am33
903 {
904 int srcreg, dstreg;
905 unsigned long long temp;
906 int n, z;
907
908 PC = cia;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
911
912 temp = State.regs[REG_MDR];
913 temp <<= 32;
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
922 }
923
924
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
927 "mov"
928 *am33
929 {
930 int srcreg, dstreg;
931
932 PC = cia;
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
936 }
937
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
940 "mov"
941 *am33
942 {
943 int srcreg, dstreg;
944
945 PC = cia;
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
949 }
950
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
953 "movbu"
954 *am33
955 {
956 int srcreg, dstreg;
957
958 PC = cia;
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
962 }
963
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
966 "movbu"
967 *am33
968 {
969 int srcreg, dstreg;
970
971 PC = cia;
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
975 }
976
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
979 "movhu"
980 *am33
981 {
982 int srcreg, dstreg;
983
984 PC = cia;
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
988 }
989
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
992 "movhu"
993 *am33
994 {
995 int srcreg, dstreg;
996
997 PC = cia;
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1001 }
1002
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1005 "mov"
1006 *am33
1007 {
1008 int srcreg, dstreg;
1009
1010 PC = cia;
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1015 }
1016
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1019 "mov"
1020 *am33
1021 {
1022 int srcreg, dstreg;
1023
1024 PC = cia;
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1029 }
1030
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1033 "mov"
1034 *am33
1035 {
1036 int dstreg;
1037
1038 PC = cia;
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1041 }
1042
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1045 "mov"
1046 *am33
1047 {
1048 int srcreg;
1049
1050 PC = cia;
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1053 }
1054
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1057 "movbu"
1058 *am33
1059 {
1060 int dstreg;
1061
1062 PC = cia;
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1065 }
1066
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1069 "movbu"
1070 *am33
1071 {
1072 int srcreg;
1073
1074 PC = cia;
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1077 }
1078
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1081 "movhu"
1082 *am33
1083 {
1084 int dstreg;
1085
1086 PC = cia;
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1089 }
1090
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1093 "movhu"
1094 *am33
1095 {
1096 int srcreg;
1097
1098 PC = cia;
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1101 }
1102
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1105 "movhu"
1106 *am33
1107 {
1108 int srcreg, dstreg;
1109
1110 PC = cia;
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1115 }
1116
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1119 "movhu"
1120 *am33
1121 {
1122 int srcreg, dstreg;
1123
1124 PC = cia;
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1129 }
1130
1131
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1134 "mac"
1135 *am33
1136 {
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1139 int c, v;
1140
1141 PC = cia;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1144
1145 temp = ((signed64)State.regs[srcreg2]
1146 * (signed64)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1150 temp >>= 32;
1151 temp &= 0xffffffff;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1156 if (v)
1157 State.regs[REG_MCVF] = 1;
1158 }
1159
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1162 "macu"
1163 *am33
1164 {
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1167 int c, v;
1168
1169 PC = cia;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1172
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1178 temp >>= 32;
1179 temp &= 0xffffffff;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1184 if (v)
1185 State.regs[REG_MCVF] = 1;
1186 }
1187
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1190 "macb"
1191 *am33
1192 {
1193 int srcreg1, srcreg2;
1194 long temp, sum;
1195 int v;
1196
1197 PC = cia;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1200
1201 temp = ((signed32)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1207 if (v)
1208 State.regs[REG_MCVF] = 1;
1209 }
1210
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1213 "macbu"
1214 *am33
1215 {
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1218 int v;
1219
1220 PC = cia;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1223
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1230 if (v)
1231 State.regs[REG_MCVF] = 1;
1232 }
1233
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1236 "mach"
1237 *am33
1238 {
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1241 int c, v;
1242
1243 PC = cia;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1246
1247 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1252 temp >>= 32;
1253 temp &= 0xffffffff;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1258 if (v)
1259 State.regs[REG_MCVF] = 1;
1260 }
1261
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1264 "machu"
1265 *am33
1266 {
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1269 int c, v;
1270
1271 PC = cia;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1274
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1280 temp >>= 32;
1281 temp &= 0xffffffff;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1286 if (v)
1287 State.regs[REG_MCVF] = 1;
1288 }
1289
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1292 "dmach"
1293 *am33
1294 {
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1297 int v;
1298
1299 PC = cia;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1302
1303 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1311 if (v)
1312 State.regs[REG_MCVF] = 1;
1313 }
1314
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1317 "dmachu"
1318 *am33
1319 {
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1322 int v;
1323
1324 PC = cia;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1327
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1336 if (v)
1337 State.regs[REG_MCVF] = 1;
1338 }
1339
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1342 "dmulh"
1343 *am33
1344 {
1345 int srcreg, dstreg;
1346 long temp;
1347
1348 PC = cia;
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1351
1352 temp = ((signed32)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1358 }
1359
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1362 "dmachu"
1363 *am33
1364 {
1365 int srcreg, dstreg;
1366 unsigned long temp;
1367
1368 PC = cia;
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1371
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1378 }
1379
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1382 "sat16"
1383 *am33
1384 {
1385 int srcreg, dstreg;
1386 int value;
1387
1388 PC = cia;
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1391
1392 value = State.regs[srcreg];
1393
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1398 else
1399 State.regs[dstreg] = value;
1400 }
1401
1402 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1403 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1404 "mcste"
1405 *am33
1406 {
1407 int srcreg, dstreg;
1408
1409 PC = cia;
1410 srcreg = translate_rreg (SD_, RM2);
1411 dstreg = translate_rreg (SD_, RN0);
1412
1413 PSW &= ~(PSW_V | PSW_C);
1414 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1415
1416 /* 32bit saturation. */
1417 if (State.regs[srcreg] == 0x20)
1418 {
1419 long long tmp;
1420
1421 tmp = State.regs[REG_MCRH];
1422 tmp <<= 32;
1423 tmp += State.regs[REG_MCRL];
1424
1425 if (tmp > 0x7fffffff)
1426 State.regs[dstreg] = 0x7fffffff;
1427 else if (tmp < 0xffffffff80000000LL)
1428 State.regs[dstreg] = 0x80000000;
1429 else
1430 State.regs[dstreg] = tmp;
1431 }
1432 /* 16bit saturation */
1433 else if (State.regs[srcreg] == 0x10)
1434 {
1435 long long tmp;
1436
1437 tmp = State.regs[REG_MCRH];
1438 tmp <<= 32;
1439 tmp += State.regs[REG_MCRL];
1440
1441 if (tmp > 0x7fff)
1442 State.regs[dstreg] = 0x7fff;
1443 else if (tmp < 0xffffffffffff8000LL)
1444 State.regs[dstreg] = 0x8000;
1445 else
1446 State.regs[dstreg] = tmp;
1447 }
1448 /* 8 bit saturation */
1449 else if (State.regs[srcreg] == 0x8)
1450 {
1451 long long tmp;
1452
1453 tmp = State.regs[REG_MCRH];
1454 tmp <<= 32;
1455 tmp += State.regs[REG_MCRL];
1456
1457 if (tmp > 0x7f)
1458 State.regs[dstreg] = 0x7f;
1459 else if (tmp < 0xffffffffffffff80LL)
1460 State.regs[dstreg] = 0x80;
1461 else
1462 State.regs[dstreg] = tmp;
1463 }
1464 /* 9 bit saturation */
1465 else if (State.regs[srcreg] == 0x9)
1466 {
1467 long long tmp;
1468
1469 tmp = State.regs[REG_MCRH];
1470 tmp <<= 32;
1471 tmp += State.regs[REG_MCRL];
1472
1473 if (tmp > 0x80)
1474 State.regs[dstreg] = 0x80;
1475 else if (tmp < 0xffffffffffffff81LL)
1476 State.regs[dstreg] = 0x81;
1477 else
1478 State.regs[dstreg] = tmp;
1479 }
1480 /* 9 bit saturation */
1481 else if (State.regs[srcreg] == 0x30)
1482 {
1483 long long tmp;
1484
1485 tmp = State.regs[REG_MCRH];
1486 tmp <<= 32;
1487 tmp += State.regs[REG_MCRL];
1488
1489 if (tmp > 0x7fffffffffffLL)
1490 tmp = 0x7fffffffffffLL;
1491 else if (tmp < 0xffff800000000000LL)
1492 tmp = 0xffff800000000000LL;
1493
1494 tmp >>= 16;
1495 State.regs[dstreg] = tmp;
1496 }
1497 }
1498
1499 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1500 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1501 "swap"
1502 *am33
1503 {
1504 int srcreg, dstreg;
1505
1506 PC = cia;
1507 srcreg = translate_rreg (SD_, RM2);
1508 dstreg = translate_rreg (SD_, RN0);
1509
1510 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1511 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1512 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1513 | ((State.regs[srcreg] >> 24) & 0xff));
1514 }
1515
1516 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1517 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1518 "swaph"
1519 *am33
1520 {
1521 int srcreg, dstreg;
1522
1523 PC = cia;
1524 srcreg = translate_rreg (SD_, RM2);
1525 dstreg = translate_rreg (SD_, RN0);
1526
1527 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1528 | ((State.regs[srcreg] >> 8) & 0xff)
1529 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1530 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1531 }
1532
1533 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1534 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1535 "swhw"
1536 *am33
1537 {
1538 int srcreg, dstreg;
1539
1540 PC = cia;
1541 srcreg = translate_rreg (SD_, RM2);
1542 dstreg = translate_rreg (SD_, RN0);
1543
1544 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1545 | ((State.regs[srcreg] >> 16) & 0xffff));
1546 }
1547
1548 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1549 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1550 "bsch"
1551 *am33
1552 {
1553 int temp, c, i;
1554 int srcreg, dstreg;
1555 int start;
1556
1557 PC = cia;
1558 srcreg = translate_rreg (SD_, RM2);
1559 dstreg = translate_rreg (SD_, RN0);
1560
1561 temp = State.regs[srcreg];
1562 start = (State.regs[dstreg] & 0x1f) - 1;
1563 if (start == -1)
1564 start = 31;
1565
1566 for (i = start; i >= 0; i--)
1567 {
1568 if (temp & (1 << i))
1569 {
1570 c = 1;
1571 State.regs[dstreg] = i;
1572 break;
1573 }
1574 }
1575
1576 if (i < 0)
1577 {
1578 c = 0;
1579 State.regs[dstreg] = 0;
1580 }
1581 PSW &= ~(PSW_C);
1582 PSW |= (c ? PSW_C : 0);
1583 }
1584
1585
1586 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1587 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1588 "mov"
1589 *am33
1590 {
1591 int dstreg;
1592
1593 PC = cia;
1594 dstreg = translate_rreg (SD_, RN0);
1595 State.regs[dstreg] = EXTEND8 (IMM8);
1596 }
1597
1598 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1599 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1600 "movu"
1601 *am33
1602 {
1603 int dstreg;
1604
1605 PC = cia;
1606 dstreg = translate_rreg (SD_, RN0);
1607 State.regs[dstreg] = IMM8 & 0xff;
1608 }
1609
1610 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1611 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1612 "add"
1613 *am33
1614 {
1615 int dstreg;
1616
1617 PC = cia;
1618 dstreg = translate_rreg (SD_, RN0);
1619 genericAdd (EXTEND8 (IMM8), dstreg);
1620 }
1621
1622 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1623 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1624 "addc"
1625 *am33
1626 {
1627 int dstreg, imm;
1628 int z, c, n, v;
1629 unsigned long reg1, reg2, sum;
1630
1631 PC = cia;
1632 dstreg = translate_rreg (SD_, RN0);
1633
1634 imm = EXTEND8 (IMM8);
1635 reg2 = State.regs[dstreg];
1636 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1637 State.regs[dstreg] = sum;
1638
1639 z = (sum == 0);
1640 n = (sum & 0x80000000);
1641 c = (sum < imm) || (sum < reg2);
1642 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1643 && (reg2 & 0x80000000) != (sum & 0x80000000));
1644
1645 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1646 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1647 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1648 }
1649
1650 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1651 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1652 "sub"
1653 *am33
1654 {
1655 int dstreg;
1656
1657 PC = cia;
1658 dstreg = translate_rreg (SD_, RN0);
1659
1660 genericSub (EXTEND8 (IMM8), dstreg);
1661 }
1662
1663 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1664 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1665 "subc"
1666 *am33
1667 {
1668 int imm, dstreg;
1669 int z, c, n, v;
1670 unsigned long reg1, reg2, difference;
1671
1672 PC = cia;
1673 dstreg = translate_rreg (SD_, RN0);
1674
1675 imm = EXTEND8 (IMM8);
1676 reg2 = State.regs[dstreg];
1677 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1678 State.regs[dstreg] = difference;
1679
1680 z = (difference == 0);
1681 n = (difference & 0x80000000);
1682 c = (imm > reg2);
1683 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1684 && (reg2 & 0x80000000) != (difference & 0x80000000));
1685
1686 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1687 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1688 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1689 }
1690
1691 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1692 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1693 "cmp"
1694 *am33
1695 {
1696 int srcreg;
1697
1698 PC = cia;
1699 srcreg = translate_rreg (SD_, RN0);
1700 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1701 }
1702
1703 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1704 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1705 "mov"
1706 *am33
1707 {
1708 int dstreg;
1709
1710 PC = cia;
1711
1712 if (XRN0 == 0)
1713 State.regs[REG_SP] = EXTEND8 (IMM8);
1714 else
1715 abort ();
1716 }
1717
1718 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1719 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1720 "and"
1721 *am33
1722 {
1723 int dstreg;
1724 int z, n;
1725
1726 PC = cia;
1727 dstreg = translate_rreg (SD_, RN0);
1728
1729 State.regs[dstreg] &= (IMM8 & 0xff);
1730 z = (State.regs[dstreg] == 0);
1731 n = (State.regs[dstreg] & 0x80000000) != 0;
1732 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1733 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1734 }
1735
1736 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1737 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1738 "or"
1739 *am33
1740 {
1741 int dstreg;
1742 int z, n;
1743
1744 PC = cia;
1745 dstreg = translate_rreg (SD_, RN0);
1746
1747 State.regs[dstreg] |= (IMM8 & 0xff);
1748 z = (State.regs[dstreg] == 0);
1749 n = (State.regs[dstreg] & 0x80000000) != 0;
1750 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1752 }
1753
1754 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1755 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1756 "xor"
1757 *am33
1758 {
1759 int dstreg;
1760 int z, n;
1761
1762 PC = cia;
1763 dstreg = translate_rreg (SD_, RN0);
1764
1765 State.regs[dstreg] ^= (IMM8 & 0xff);
1766 z = (State.regs[dstreg] == 0);
1767 n = (State.regs[dstreg] & 0x80000000) != 0;
1768 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1769 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1770 }
1771
1772 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1773 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1774 "asr"
1775 *am33
1776 {
1777 int dstreg;
1778 long temp;
1779 int c, z, n;
1780
1781 PC = cia;
1782 dstreg = translate_rreg (SD_, RN0);
1783
1784 temp = State.regs[dstreg];
1785 c = temp & 1;
1786 temp >>= (IMM8 & 0xff);
1787 State.regs[dstreg] = temp;
1788 z = (State.regs[dstreg] == 0);
1789 n = (State.regs[dstreg] & 0x80000000) != 0;
1790 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1791 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1792 }
1793
1794 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1795 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1796 "lsr"
1797 *am33
1798 {
1799 int dstreg;
1800 int z, n, c;
1801
1802 PC = cia;
1803 dstreg = translate_rreg (SD_, RN0);
1804
1805 c = State.regs[dstreg] & 1;
1806 State.regs[dstreg] >>= (IMM8 & 0xff);
1807 z = (State.regs[dstreg] == 0);
1808 n = (State.regs[dstreg] & 0x80000000) != 0;
1809 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1810 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1811 }
1812
1813 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1814 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1815 "asl"
1816 *am33
1817 {
1818 int srcreg, dstreg;
1819 int z, n;
1820
1821 PC = cia;
1822 dstreg = translate_rreg (SD_, RN0);
1823
1824 State.regs[dstreg] <<= (IMM8 & 0xff);
1825 z = (State.regs[dstreg] == 0);
1826 n = (State.regs[dstreg] & 0x80000000) != 0;
1827 PSW &= ~(PSW_Z | PSW_N);
1828 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1829 }
1830
1831 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1832 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1833 "mul"
1834 *am33
1835 {
1836 int dstreg;
1837 unsigned long long temp;
1838 int z, n;
1839
1840 PC = cia;
1841 dstreg = translate_rreg (SD_, RN0);
1842
1843 temp = ((signed64)(signed32)State.regs[dstreg]
1844 * (signed64)(signed32)EXTEND8 (IMM8));
1845 State.regs[dstreg] = temp & 0xffffffff;
1846 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1847 z = (State.regs[dstreg] == 0);
1848 n = (State.regs[dstreg] & 0x80000000) != 0;
1849 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1850 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1851 }
1852
1853 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1854 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1855 "mulu"
1856 *am33
1857 {
1858 int dstreg;
1859 unsigned long long temp;
1860 int z, n;
1861
1862 PC = cia;
1863 dstreg = translate_rreg (SD_, RN0);
1864
1865 temp = ((unsigned64)State.regs[dstreg]
1866 * (unsigned64)(IMM8 & 0xff));
1867 State.regs[dstreg] = temp & 0xffffffff;
1868 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1869 z = (State.regs[dstreg] == 0);
1870 n = (State.regs[dstreg] & 0x80000000) != 0;
1871 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1872 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1873 }
1874
1875 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1876 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1877 "btst"
1878 *am33
1879 {
1880 int srcreg;
1881
1882 PC = cia;
1883 srcreg = translate_rreg (SD_, RM0);
1884 genericBtst(IMM8, State.regs[srcreg]);
1885 }
1886
1887
1888 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1889 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1890 "mov"
1891 *am33
1892 {
1893 int srcreg, dstreg;
1894
1895 PC = cia;
1896 srcreg = translate_rreg (SD_, RM0);
1897 dstreg = translate_rreg (SD_, RN2);
1898 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1899 }
1900
1901 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1902 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1903 "mov"
1904 {
1905 int srcreg, dstreg;
1906
1907 PC = cia;
1908 srcreg = translate_rreg (SD_, RM2);
1909 dstreg = translate_rreg (SD_, RN0);
1910 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1911 }
1912
1913 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1914 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1915 "movbu"
1916 {
1917 int srcreg, dstreg;
1918
1919 PC = cia;
1920 srcreg = translate_rreg (SD_, RM0);
1921 dstreg = translate_rreg (SD_, RN2);
1922 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1923 }
1924
1925 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1926 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1927 "movbu"
1928 {
1929 int srcreg, dstreg;
1930
1931 PC = cia;
1932 srcreg = translate_rreg (SD_, RM2);
1933 dstreg = translate_rreg (SD_, RN0);
1934 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1935 }
1936
1937 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1938 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1939 "movhu"
1940 {
1941 int srcreg, dstreg;
1942
1943 PC = cia;
1944 srcreg = translate_rreg (SD_, RM0);
1945 dstreg = translate_rreg (SD_, RN2);
1946 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1947 }
1948
1949 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1950 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1951 "movhu"
1952 {
1953 int srcreg, dstreg;
1954
1955 PC = cia;
1956 srcreg = translate_rreg (SD_, RM2);
1957 dstreg = translate_rreg (SD_, RN0);
1958 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1959 }
1960
1961 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1962 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1963 "mov"
1964 *am33
1965 {
1966 int srcreg, dstreg;
1967
1968 PC = cia;
1969 srcreg = translate_rreg (SD_, RM0);
1970 dstreg = translate_rreg (SD_, RN2);
1971 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1972 State.regs[srcreg] += 4;
1973 }
1974
1975 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1976 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1977 "mov"
1978 {
1979 int srcreg, dstreg;
1980
1981 PC = cia;
1982 srcreg = translate_rreg (SD_, RM2);
1983 dstreg = translate_rreg (SD_, RN0);
1984 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1985 State.regs[dstreg] += 4;
1986 }
1987
1988
1989 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1990 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1991 "mov"
1992 {
1993 int dstreg;
1994
1995 PC = cia;
1996 dstreg = translate_rreg (SD_, RN2);
1997 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
1998 }
1999
2000 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2001 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2002 "mov"
2003 {
2004 int srcreg;
2005
2006 PC = cia;
2007 srcreg = translate_rreg (SD_, RM2);
2008 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2009 }
2010
2011 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2012 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2013 "movbu"
2014 {
2015 int dstreg;
2016
2017 PC = cia;
2018 dstreg = translate_rreg (SD_, RN2);
2019 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2020 }
2021
2022 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2023 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2024 "movbu"
2025 {
2026 int srcreg;
2027
2028 PC = cia;
2029 srcreg = translate_rreg (SD_, RM2);
2030 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2031 }
2032
2033 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2034 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2035 "movhu"
2036 {
2037 int dstreg;
2038
2039 PC = cia;
2040 dstreg = translate_rreg (SD_, RN2);
2041 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2042 }
2043
2044 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2045 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2046 "movhu"
2047 {
2048 int srcreg;
2049
2050 PC = cia;
2051 srcreg = translate_rreg (SD_, RM2);
2052 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2053 }
2054
2055 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2056 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2057 "movhu"
2058 *am33
2059 {
2060 int srcreg, dstreg;
2061
2062 PC = cia;
2063 srcreg = translate_rreg (SD_, RM0);
2064 dstreg = translate_rreg (SD_, RN2);
2065 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2066 State.regs[srcreg] += 2;
2067 }
2068
2069 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2070 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2071 "movhu"
2072 {
2073 int srcreg, dstreg;
2074
2075 PC = cia;
2076 srcreg = translate_rreg (SD_, RM2);
2077 dstreg = translate_rreg (SD_, RN0);
2078 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2079 State.regs[dstreg] += 2;
2080 }
2081
2082
2083 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2084 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2085 "mac"
2086 {
2087 int srcreg;
2088 long long temp, sum;
2089 int c, v;
2090
2091 PC = cia;
2092 srcreg = translate_rreg (SD_, RN2);
2093
2094 temp = ((signed64)EXTEND8 (IMM8)
2095 * (signed64)State.regs[srcreg]);
2096 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2097 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2098 State.regs[REG_MCRL] = sum;
2099 temp >>= 32;
2100 temp &= 0xffffffff;
2101 sum = State.regs[REG_MCRH] + temp + c;
2102 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2103 && (temp & 0x80000000) != (sum & 0x80000000));
2104 State.regs[REG_MCRH] = sum;
2105 if (v)
2106 State.regs[REG_MCVF] = 1;
2107 }
2108
2109 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2110 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2111 "macu"
2112 {
2113 int srcreg;
2114 long long temp, sum;
2115 int c, v;
2116
2117 PC = cia;
2118 srcreg = translate_rreg (SD_, RN2);
2119
2120 temp = ((unsigned64) (IMM8)
2121 * (unsigned64)State.regs[srcreg]);
2122 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2123 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2124 State.regs[REG_MCRL] = sum;
2125 temp >>= 32;
2126 temp &= 0xffffffff;
2127 sum = State.regs[REG_MCRH] + temp + c;
2128 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2129 && (temp & 0x80000000) != (sum & 0x80000000));
2130 State.regs[REG_MCRH] = sum;
2131 if (v)
2132 State.regs[REG_MCVF] = 1;
2133 }
2134
2135 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2136 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2137 "macb"
2138 {
2139 int srcreg;
2140 long long temp, sum;
2141 int c, v;
2142
2143 PC = cia;
2144 srcreg = translate_rreg (SD_, RN2);
2145
2146 temp = ((signed64)EXTEND8 (IMM8)
2147 * (signed64)State.regs[srcreg] & 0xff);
2148 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2149 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2150 State.regs[REG_MCRL] = sum;
2151 temp >>= 32;
2152 temp &= 0xffffffff;
2153 sum = State.regs[REG_MCRH] + temp + c;
2154 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2155 && (temp & 0x80000000) != (sum & 0x80000000));
2156 State.regs[REG_MCRH] = sum;
2157 if (v)
2158 State.regs[REG_MCVF] = 1;
2159 }
2160
2161 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2162 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2163 "macbu"
2164 {
2165 int srcreg;
2166 long long temp, sum;
2167 int c, v;
2168
2169 PC = cia;
2170 srcreg = translate_rreg (SD_, RN2);
2171
2172 temp = ((unsigned64) (IMM8)
2173 * (unsigned64)State.regs[srcreg] & 0xff);
2174 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2175 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2176 State.regs[REG_MCRL] = sum;
2177 temp >>= 32;
2178 temp &= 0xffffffff;
2179 sum = State.regs[REG_MCRH] + temp + c;
2180 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2181 && (temp & 0x80000000) != (sum & 0x80000000));
2182 State.regs[REG_MCRH] = sum;
2183 if (v)
2184 State.regs[REG_MCVF] = 1;
2185 }
2186
2187 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2188 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2189 "mach"
2190 {
2191 int srcreg;
2192 long long temp, sum;
2193 int c, v;
2194
2195 PC = cia;
2196 srcreg = translate_rreg (SD_, RN2);
2197
2198 temp = ((signed64)EXTEND8 (IMM8)
2199 * (signed64)State.regs[srcreg] & 0xffff);
2200 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2201 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2202 State.regs[REG_MCRL] = sum;
2203 temp >>= 32;
2204 temp &= 0xffffffff;
2205 sum = State.regs[REG_MCRH] + temp + c;
2206 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2207 && (temp & 0x80000000) != (sum & 0x80000000));
2208 State.regs[REG_MCRH] = sum;
2209 if (v)
2210 State.regs[REG_MCVF] = 1;
2211 }
2212
2213 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2214 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2215 "machu"
2216 {
2217 int srcreg;
2218 long long temp, sum;
2219 int c, v;
2220
2221 PC = cia;
2222 srcreg = translate_rreg (SD_, RN2);
2223
2224 temp = ((unsigned64) (IMM8)
2225 * (unsigned64)State.regs[srcreg] & 0xffff);
2226 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2227 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2228 State.regs[REG_MCRL] = sum;
2229 temp >>= 32;
2230 temp &= 0xffffffff;
2231 sum = State.regs[REG_MCRH] + temp + c;
2232 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2233 && (temp & 0x80000000) != (sum & 0x80000000));
2234 State.regs[REG_MCRH] = sum;
2235 if (v)
2236 State.regs[REG_MCVF] = 1;
2237 }
2238
2239 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2240 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2241 "mcste"
2242 {
2243 int dstreg;
2244
2245 PC = cia;
2246 dstreg = translate_rreg (SD_, RN0);
2247
2248 PSW &= ~(PSW_V | PSW_C);
2249 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2250
2251 /* 32bit saturation. */
2252 if (IMM8 == 0x20)
2253 {
2254 long long tmp;
2255
2256 tmp = State.regs[REG_MCRH];
2257 tmp <<= 32;
2258 tmp += State.regs[REG_MCRL];
2259
2260 if (tmp > 0x7fffffff)
2261 State.regs[dstreg] = 0x7fffffff;
2262 else if (tmp < 0xffffffff80000000LL)
2263 State.regs[dstreg] = 0x80000000;
2264 else
2265 State.regs[dstreg] = tmp;
2266 }
2267 /* 16bit saturation */
2268 else if (IMM8 == 0x10)
2269 {
2270 long long tmp;
2271
2272 tmp = State.regs[REG_MCRH];
2273 tmp <<= 32;
2274 tmp += State.regs[REG_MCRL];
2275
2276 if (tmp > 0x7fff)
2277 State.regs[dstreg] = 0x7fff;
2278 else if (tmp < 0xffffffffffff8000LL)
2279 State.regs[dstreg] = 0x8000;
2280 else
2281 State.regs[dstreg] = tmp;
2282 }
2283 /* 8 bit saturation */
2284 else if (IMM8 == 0x8)
2285 {
2286 long long tmp;
2287
2288 tmp = State.regs[REG_MCRH];
2289 tmp <<= 32;
2290 tmp += State.regs[REG_MCRL];
2291
2292 if (tmp > 0x7f)
2293 State.regs[dstreg] = 0x7f;
2294 else if (tmp < 0xffffffffffffff80LL)
2295 State.regs[dstreg] = 0x80;
2296 else
2297 State.regs[dstreg] = tmp;
2298 }
2299 /* 9 bit saturation */
2300 else if (IMM8 == 0x9)
2301 {
2302 long long tmp;
2303
2304 tmp = State.regs[REG_MCRH];
2305 tmp <<= 32;
2306 tmp += State.regs[REG_MCRL];
2307
2308 if (tmp > 0x80)
2309 State.regs[dstreg] = 0x80;
2310 else if (tmp < 0xffffffffffffff81LL)
2311 State.regs[dstreg] = 0x81;
2312 else
2313 State.regs[dstreg] = tmp;
2314 }
2315 /* 9 bit saturation */
2316 else if (IMM8 == 0x30)
2317 {
2318 long long tmp;
2319
2320 tmp = State.regs[REG_MCRH];
2321 tmp <<= 32;
2322 tmp += State.regs[REG_MCRL];
2323
2324 if (tmp > 0x7fffffffffffLL)
2325 tmp = 0x7fffffffffffLL;
2326 else if (tmp < 0xffff800000000000LL)
2327 tmp = 0xffff800000000000LL;
2328
2329 tmp >>= 16;
2330 State.regs[dstreg] = tmp;
2331 }
2332 }
2333
2334 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2335 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2336 "add"
2337 *am33
2338 {
2339 int z, c, n, v;
2340 unsigned long sum, source1, source2;
2341 int srcreg1, srcreg2, dstreg;
2342
2343 PC = cia;
2344 srcreg1 = translate_rreg (SD_, RM2);
2345 srcreg2 = translate_rreg (SD_, RN0);
2346 dstreg = translate_rreg (SD_, RD0);
2347
2348 source1 = State.regs[srcreg1];
2349 source2 = State.regs[srcreg2];
2350 sum = source1 + source2;
2351 State.regs[dstreg] = sum;
2352
2353 z = (sum == 0);
2354 n = (sum & 0x80000000);
2355 c = (sum < source1) || (sum < source2);
2356 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2357 && (source1 & 0x80000000) != (sum & 0x80000000));
2358
2359 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2360 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2361 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2362 }
2363
2364 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2365 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2366 "addc"
2367 *am33
2368 {
2369 int z, c, n, v;
2370 unsigned long sum, source1, source2;
2371 int srcreg1, srcreg2, dstreg;
2372
2373 PC = cia;
2374 srcreg1 = translate_rreg (SD_, RM2);
2375 srcreg2 = translate_rreg (SD_, RN0);
2376 dstreg = translate_rreg (SD_, RD0);
2377
2378 source1 = State.regs[srcreg1];
2379 source2 = State.regs[srcreg2];
2380 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2381 State.regs[dstreg] = sum;
2382
2383 z = (sum == 0);
2384 n = (sum & 0x80000000);
2385 c = (sum < source1) || (sum < source2);
2386 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2387 && (source1 & 0x80000000) != (sum & 0x80000000));
2388
2389 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2390 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2391 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2392 }
2393
2394 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2395 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2396 "sub"
2397 *am33
2398 {
2399 int z, c, n, v;
2400 unsigned long difference, source1, source2;
2401 int srcreg1, srcreg2, dstreg;
2402
2403 PC = cia;
2404 srcreg1 = translate_rreg (SD_, RM2);
2405 srcreg2 = translate_rreg (SD_, RN0);
2406 dstreg = translate_rreg (SD_, RD0);
2407
2408 source1 = State.regs[srcreg1];
2409 source2 = State.regs[srcreg2];
2410 difference = source2 - source1;
2411 State.regs[dstreg] = difference;
2412
2413 z = (difference == 0);
2414 n = (difference & 0x80000000);
2415 c = (source1 > source1);
2416 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2417 && (source1 & 0x80000000) != (difference & 0x80000000));
2418
2419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2420 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2421 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2422 }
2423
2424 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2425 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2426 "subc"
2427 *am33
2428 {
2429 int z, c, n, v;
2430 unsigned long difference, source1, source2;
2431 int srcreg1, srcreg2, dstreg;
2432
2433 PC = cia;
2434 srcreg1 = translate_rreg (SD_, RM2);
2435 srcreg2 = translate_rreg (SD_, RN0);
2436 dstreg = translate_rreg (SD_, RD0);
2437
2438 source1 = State.regs[srcreg1];
2439 source2 = State.regs[srcreg2];
2440 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2441 State.regs[dstreg] = difference;
2442
2443 z = (difference == 0);
2444 n = (difference & 0x80000000);
2445 c = (source1 > source2);
2446 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2447 && (source1 & 0x80000000) != (difference & 0x80000000));
2448
2449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2450 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2451 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2452 }
2453
2454 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2455 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2456 "and"
2457 *am33
2458 {
2459 int z, c, n, v;
2460 int srcreg1, srcreg2, dstreg;
2461
2462 PC = cia;
2463 srcreg1 = translate_rreg (SD_, RM2);
2464 srcreg2 = translate_rreg (SD_, RN0);
2465 dstreg = translate_rreg (SD_, RD0);
2466
2467 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2468
2469 z = (State.regs[dstreg] == 0);
2470 n = (State.regs[dstreg] & 0x80000000);
2471
2472 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2473 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2474 }
2475
2476 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2477 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2478 "or"
2479 *am33
2480 {
2481 int z, c, n, v;
2482 int srcreg1, srcreg2, dstreg;
2483
2484 PC = cia;
2485 srcreg1 = translate_rreg (SD_, RM2);
2486 srcreg2 = translate_rreg (SD_, RN0);
2487 dstreg = translate_rreg (SD_, RD0);
2488
2489 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2490
2491 z = (State.regs[dstreg] == 0);
2492 n = (State.regs[dstreg] & 0x80000000);
2493
2494 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2495 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2496 }
2497
2498 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2499 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2500 "xor"
2501 *am33
2502 {
2503 int z, c, n, v;
2504 int srcreg1, srcreg2, dstreg;
2505
2506 PC = cia;
2507 srcreg1 = translate_rreg (SD_, RM2);
2508 srcreg2 = translate_rreg (SD_, RN0);
2509 dstreg = translate_rreg (SD_, RD0);
2510
2511 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2512
2513 z = (State.regs[dstreg] == 0);
2514 n = (State.regs[dstreg] & 0x80000000);
2515
2516 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2517 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2518 }
2519
2520 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2521 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2522 "asr"
2523 *am33
2524 {
2525 int z, c, n, v;
2526 long temp;
2527 int srcreg1, srcreg2, dstreg;
2528
2529 PC = cia;
2530 srcreg1 = translate_rreg (SD_, RM2);
2531 srcreg2 = translate_rreg (SD_, RN0);
2532 dstreg = translate_rreg (SD_, RD0);
2533
2534 temp = State.regs[srcreg2];
2535 c = temp & 1;
2536 temp >>= State.regs[srcreg1];
2537 State.regs[dstreg] = temp;
2538
2539 z = (State.regs[dstreg] == 0);
2540 n = (State.regs[dstreg] & 0x80000000);
2541
2542 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2543 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2544 }
2545
2546 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2547 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2548 "lsr"
2549 *am33
2550 {
2551 int z, c, n, v;
2552 int srcreg1, srcreg2, dstreg;
2553
2554 PC = cia;
2555 srcreg1 = translate_rreg (SD_, RM2);
2556 srcreg2 = translate_rreg (SD_, RN0);
2557 dstreg = translate_rreg (SD_, RD0);
2558
2559 c = State.regs[srcreg2] & 1;
2560 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2561
2562 z = (State.regs[dstreg] == 0);
2563 n = (State.regs[dstreg] & 0x80000000);
2564
2565 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2566 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2567 }
2568
2569 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2570 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2571 "asl"
2572 *am33
2573 {
2574 int z, c, n, v;
2575 int srcreg1, srcreg2, dstreg;
2576
2577 PC = cia;
2578 srcreg1 = translate_rreg (SD_, RM2);
2579 srcreg2 = translate_rreg (SD_, RN0);
2580 dstreg = translate_rreg (SD_, RD0);
2581
2582 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2583
2584 z = (State.regs[dstreg] == 0);
2585 n = (State.regs[dstreg] & 0x80000000);
2586
2587 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2588 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2589 }
2590
2591 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2592 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2593 "mul"
2594 *am33
2595 {
2596 int srcreg1, srcreg2, dstreg1, dstreg2;
2597 signed long long temp;
2598
2599 PC = cia;
2600 srcreg1 = translate_rreg (SD_, RM2);
2601 srcreg2 = translate_rreg (SD_, RN0);
2602 dstreg1 = translate_rreg (SD_, RD0);
2603 dstreg2 = translate_rreg (SD_, RD2);
2604
2605 temp = ((signed64)(signed32)State.regs[srcreg1]
2606 * (signed64)(signed32)State.regs[srcreg2]);
2607 State.regs[dstreg1] = temp & 0xffffffff;
2608 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2609 }
2610
2611 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2612 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2613 "mulu"
2614 *am33
2615 {
2616 int srcreg1, srcreg2, dstreg1, dstreg2;
2617 signed long long temp;
2618
2619 PC = cia;
2620 srcreg1 = translate_rreg (SD_, RM2);
2621 srcreg2 = translate_rreg (SD_, RN0);
2622 dstreg1 = translate_rreg (SD_, RD0);
2623 dstreg2 = translate_rreg (SD_, RD2);
2624
2625 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
2626 * (unsigned64)(unsigned32)State.regs[srcreg2]);
2627 State.regs[dstreg1] = temp & 0xffffffff;
2628 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2629 }
2630
2631 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2632 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2633 "mov"
2634 *am33
2635 {
2636 int dstreg;
2637
2638 PC = cia;
2639 dstreg = translate_rreg (SD_, RN2);
2640 State.regs[dstreg] = load_word (IMM8);
2641 }
2642
2643 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2644 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2645 "mov"
2646 *am33
2647 {
2648 int srcreg;
2649
2650 PC = cia;
2651 srcreg = translate_rreg (SD_, RM2);
2652 store_word (IMM8, State.regs[srcreg]);
2653 }
2654
2655 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2656 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2657 "movbu"
2658 *am33
2659 {
2660 int dstreg;
2661
2662 PC = cia;
2663 dstreg = translate_rreg (SD_, RN2);
2664 State.regs[dstreg] = load_byte (IMM8);
2665 }
2666
2667 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2668 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2669 "movbu"
2670 *am33
2671 {
2672 int srcreg;
2673
2674 PC = cia;
2675 srcreg = translate_rreg (SD_, RM2);
2676 store_byte (IMM8, State.regs[srcreg]);
2677 }
2678
2679 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2680 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2681 "movhu"
2682 *am33
2683 {
2684 int dstreg;
2685
2686 PC = cia;
2687 dstreg = translate_rreg (SD_, RN2);
2688 State.regs[dstreg] = load_half (IMM8);
2689 }
2690
2691 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2692 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2693 "movhu"
2694 *am33
2695 {
2696 int srcreg;
2697
2698 PC = cia;
2699 srcreg = translate_rreg (SD_, RM2);
2700 store_half (IMM8, State.regs[srcreg]);
2701 }
2702
2703 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2704 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2705 "mov"
2706 *am33
2707 {
2708 int srcreg1, srcreg2, dstreg;
2709
2710 PC = cia;
2711 srcreg1 = translate_rreg (SD_, RM0);
2712 srcreg1 = translate_rreg (SD_, RI0);
2713 dstreg = translate_rreg (SD_, RN0);
2714 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2715 }
2716
2717 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2718 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2719 "mov"
2720 *am33
2721 {
2722 int srcreg, dstreg1, dstreg2;
2723
2724 PC = cia;
2725 srcreg = translate_rreg (SD_, RM0);
2726 dstreg1 = translate_rreg (SD_, RI0);
2727 dstreg2 = translate_rreg (SD_, RN0);
2728 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2729 }
2730
2731 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2732 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2733 "movbu"
2734 *am33
2735 {
2736 int srcreg1, srcreg2, dstreg;
2737
2738 PC = cia;
2739 srcreg1 = translate_rreg (SD_, RM0);
2740 srcreg1 = translate_rreg (SD_, RI0);
2741 dstreg = translate_rreg (SD_, RN0);
2742 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2743 }
2744
2745 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2746 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2747 "movbu"
2748 *am33
2749 {
2750 int srcreg, dstreg1, dstreg2;
2751
2752 PC = cia;
2753 srcreg = translate_rreg (SD_, RM0);
2754 dstreg1 = translate_rreg (SD_, RI0);
2755 dstreg2 = translate_rreg (SD_, RN0);
2756 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2757 }
2758
2759 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2760 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2761 "movhu"
2762 *am33
2763 {
2764 int srcreg1, srcreg2, dstreg;
2765
2766 PC = cia;
2767 srcreg1 = translate_rreg (SD_, RM0);
2768 srcreg1 = translate_rreg (SD_, RI0);
2769 dstreg = translate_rreg (SD_, RN0);
2770 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2771 }
2772
2773 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2774 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2775 "movhu"
2776 *am33
2777 {
2778 int srcreg, dstreg1, dstreg2;
2779
2780 PC = cia;
2781 srcreg = translate_rreg (SD_, RM0);
2782 dstreg1 = translate_rreg (SD_, RI0);
2783 dstreg2 = translate_rreg (SD_, RN0);
2784 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2785 }
2786
2787 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2788 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2789 "mac"
2790 *am33
2791 {
2792 int srcreg1, srcreg2, dstreg1, dstreg2;
2793 signed long long temp;
2794 unsigned long sum;
2795 int c, v;
2796
2797 PC = cia;
2798 srcreg1 = translate_rreg (SD_, RM2);
2799 srcreg2 = translate_rreg (SD_, RN0);
2800 dstreg1 = translate_rreg (SD_, RD0);
2801 dstreg2 = translate_rreg (SD_, RD2);
2802
2803 temp = ((signed64)(signed32)State.regs[srcreg1]
2804 * (signed64)(signed32)State.regs[srcreg2]);
2805
2806 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2807 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2808 State.regs[dstreg2] = sum;
2809 temp >>= 32;
2810 temp &= 0xffffffff;
2811 sum = State.regs[dstreg1] + temp + c;
2812 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2813 && (temp & 0x80000000) != (sum & 0x80000000));
2814 State.regs[dstreg1] = sum;
2815 if (v)
2816 State.regs[REG_MCVF] = 1;
2817 }
2818
2819 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2820 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2821 "macu"
2822 *am33
2823 {
2824 int srcreg1, srcreg2, dstreg1, dstreg2;
2825 signed long long temp;
2826 unsigned long sum;
2827 int c, v;
2828
2829 PC = cia;
2830 srcreg1 = translate_rreg (SD_, RM2);
2831 srcreg2 = translate_rreg (SD_, RN0);
2832 dstreg1 = translate_rreg (SD_, RD0);
2833 dstreg2 = translate_rreg (SD_, RD2);
2834
2835 temp = ((unsigned64)State.regs[srcreg1]
2836 * (unsigned64)State.regs[srcreg2]);
2837
2838 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2839 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2840 State.regs[dstreg2] = sum;
2841 temp >>= 32;
2842 temp &= 0xffffffff;
2843 sum = State.regs[dstreg1] + temp + c;
2844 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2845 && (temp & 0x80000000) != (sum & 0x80000000));
2846 State.regs[dstreg1] = sum;
2847 if (v)
2848 State.regs[REG_MCVF] = 1;
2849 }
2850
2851 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2852 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2853 "macb"
2854 *am33
2855 {
2856 int srcreg1, srcreg2, dstreg;
2857 long temp, sum;
2858 int v;
2859
2860 PC = cia;
2861 srcreg1 = translate_rreg (SD_, RM2);
2862 srcreg2 = translate_rreg (SD_, RN0);
2863 dstreg = translate_rreg (SD_, RD0);
2864
2865 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2866 * (signed32)(State.regs[srcreg1] & 0xff));
2867 sum = State.regs[dstreg] + temp;
2868 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2869 && (temp & 0x80000000) != (sum & 0x80000000));
2870 State.regs[dstreg] = sum;
2871 if (v)
2872 State.regs[REG_MCVF] = 1;
2873 }
2874
2875 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2876 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2877 "macbu"
2878 *am33
2879 {
2880 int srcreg1, srcreg2, dstreg;
2881 long temp, sum;
2882 int v;
2883
2884 PC = cia;
2885 srcreg1 = translate_rreg (SD_, RM2);
2886 srcreg2 = translate_rreg (SD_, RN0);
2887 dstreg = translate_rreg (SD_, RD0);
2888
2889 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2890 * (unsigned32)(State.regs[srcreg1] & 0xff));
2891 sum = State.regs[dstreg] + temp;
2892 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2893 && (temp & 0x80000000) != (sum & 0x80000000));
2894 State.regs[dstreg] = sum;
2895 if (v)
2896 State.regs[REG_MCVF] = 1;
2897 }
2898
2899 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2900 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2901 "mach"
2902 *am33
2903 {
2904 int srcreg1, srcreg2, dstreg;
2905 long temp, sum;
2906 int v;
2907
2908 PC = cia;
2909 srcreg1 = translate_rreg (SD_, RM2);
2910 srcreg2 = translate_rreg (SD_, RN0);
2911 dstreg = translate_rreg (SD_, RD0);
2912
2913 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2914 * (signed32)(State.regs[srcreg1] & 0xffff));
2915 sum = State.regs[dstreg] + temp;
2916 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2917 && (temp & 0x80000000) != (sum & 0x80000000));
2918 State.regs[dstreg] = sum;
2919 if (v)
2920 State.regs[REG_MCVF] = 1;
2921 }
2922
2923 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2924 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2925 "machu"
2926 *am33
2927 {
2928 int srcreg1, srcreg2, dstreg;
2929 long temp, sum;
2930 int v;
2931
2932 PC = cia;
2933 srcreg1 = translate_rreg (SD_, RM2);
2934 srcreg2 = translate_rreg (SD_, RN0);
2935 dstreg = translate_rreg (SD_, RD0);
2936
2937 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2938 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2939 sum = State.regs[dstreg] + temp;
2940 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2941 && (temp & 0x80000000) != (sum & 0x80000000));
2942 State.regs[dstreg] = sum;
2943 if (v)
2944 State.regs[REG_MCVF] = 1;
2945 }
2946
2947 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2948 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2949 "dmach"
2950 *am33
2951 {
2952 int srcreg1, srcreg2, dstreg;
2953 long temp, temp2, sum;
2954 int v;
2955
2956 PC = cia;
2957 srcreg1 = translate_rreg (SD_, RM2);
2958 srcreg2 = translate_rreg (SD_, RN0);
2959 dstreg = translate_rreg (SD_, RD0);
2960
2961 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2962 * (signed32)(State.regs[srcreg1] & 0xffff));
2963 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
2964 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
2965 sum = temp + temp2 + State.regs[dstreg];
2966 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2967 && (temp & 0x80000000) != (sum & 0x80000000));
2968 State.regs[dstreg] = sum;
2969 if (v)
2970 State.regs[REG_MCVF] = 1;
2971 }
2972
2973 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
2974 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
2975 "dmachu"
2976 *am33
2977 {
2978 int srcreg1, srcreg2, dstreg;
2979 long temp, temp2, sum;
2980 int v;
2981
2982 PC = cia;
2983 srcreg1 = translate_rreg (SD_, RM2);
2984 srcreg2 = translate_rreg (SD_, RN0);
2985 dstreg = translate_rreg (SD_, RD0);
2986
2987 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2988 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2989 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
2990 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
2991 sum = temp + temp2 + State.regs[dstreg];
2992 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2993 && (temp & 0x80000000) != (sum & 0x80000000));
2994 State.regs[dstreg] = sum;
2995 if (v)
2996 State.regs[REG_MCVF] = 1;
2997 }
2998
2999 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3000 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3001 "dmulh"
3002 *am33
3003 {
3004 int srcreg1, srcreg2, dstreg1, dstreg2;
3005 signed long long temp;
3006
3007 PC = cia;
3008 srcreg1 = translate_rreg (SD_, RM2);
3009 srcreg2 = translate_rreg (SD_, RN0);
3010 dstreg1 = translate_rreg (SD_, RD0);
3011 dstreg2 = translate_rreg (SD_, RD2);
3012
3013 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3014 * (signed32)(State.regs[srcreg1] & 0xffff));
3015 State.regs[dstreg2] = temp;
3016 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3017 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3018 State.regs[dstreg1] = temp;
3019 }
3020
3021 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3022 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3023 "dmulhu"
3024 *am33
3025 {
3026 int srcreg1, srcreg2, dstreg1, dstreg2;
3027 signed long long temp;
3028
3029 PC = cia;
3030 srcreg1 = translate_rreg (SD_, RM2);
3031 srcreg2 = translate_rreg (SD_, RN0);
3032 dstreg1 = translate_rreg (SD_, RD0);
3033 dstreg2 = translate_rreg (SD_, RD2);
3034
3035 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3036 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3037 State.regs[dstreg2] = temp;
3038 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3039 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3040 State.regs[dstreg1] = temp;
3041 }
3042
3043 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3044 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3045 "sat24"
3046 *am33
3047 {
3048 int srcreg, dstreg;
3049 int value;
3050
3051 PC = cia;
3052 srcreg = translate_rreg (SD_, RM2);
3053 dstreg = translate_rreg (SD_, RN0);
3054
3055 value = State.regs[srcreg];
3056
3057 if (value >= 0x7fffff)
3058 State.regs[dstreg] = 0x7fffff;
3059 else if (value <= 0xff800000)
3060 State.regs[dstreg] = 0xff800000;
3061 else
3062 State.regs[dstreg] = value;
3063 }
3064
3065 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3066 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3067 "bsch"
3068 *am33
3069 {
3070 int temp, c, i;
3071 int srcreg1, srcreg2, dstreg;
3072 int start;
3073
3074 PC = cia;
3075 srcreg1 = translate_rreg (SD_, RM2);
3076 srcreg2 = translate_rreg (SD_, RN0);
3077 dstreg = translate_rreg (SD_, RD0);
3078
3079 temp = State.regs[srcreg1];
3080 start = (State.regs[srcreg2] & 0x1f) - 1;
3081 if (start == -1)
3082 start = 31;
3083
3084 for (i = start; i >= 0; i--)
3085 {
3086 if (temp & (1 << i))
3087 {
3088 c = 1;
3089 State.regs[dstreg] = i;
3090 break;
3091 }
3092 }
3093
3094 if (i < 0)
3095 {
3096 c = 0;
3097 State.regs[dstreg] = 0;
3098 }
3099 PSW &= ~(PSW_C);
3100 PSW |= (c ? PSW_C : 0);
3101 }
3102
3103 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3104 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3105 "mov"
3106 *am33
3107 {
3108 int dstreg;
3109
3110 PC = cia;
3111 dstreg = translate_rreg (SD_, RN0);
3112 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3113 }
3114
3115 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3116 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3117 "movu"
3118 *am33
3119 {
3120 int dstreg;
3121
3122 PC = cia;
3123 dstreg = translate_rreg (SD_, RN0);
3124 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3125 }
3126
3127 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3128 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3129 "add"
3130 *am33
3131 {
3132 int dstreg;
3133
3134 PC = cia;
3135 dstreg = translate_rreg (SD_, RN0);
3136 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
3137 }
3138
3139 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3140 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3141 "addc"
3142 *am33
3143 {
3144 int dstreg, z, n, c, v;
3145 unsigned long sum, imm, reg2;
3146
3147 PC = cia;
3148 dstreg = translate_rreg (SD_, RN0);
3149
3150 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3151 reg2 = State.regs[dstreg];
3152 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3153 State.regs[dstreg] = sum;
3154
3155 z = (sum == 0);
3156 n = (sum & 0x80000000);
3157 c = (sum < imm) || (sum < reg2);
3158 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3159 && (reg2 & 0x80000000) != (sum & 0x80000000));
3160
3161 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3162 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3163 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3164 }
3165
3166 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3167 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3168 "sub"
3169 *am33
3170 {
3171 int dstreg;
3172
3173 PC = cia;
3174 dstreg = translate_rreg (SD_, RN0);
3175 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
3176 }
3177
3178 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3179 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3180 "subc"
3181 *am33
3182 {
3183 int dstreg, z, n, c, v;
3184 unsigned long difference, imm, reg2;
3185
3186 PC = cia;
3187 dstreg = translate_rreg (SD_, RN0);
3188
3189 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3190 reg2 = State.regs[dstreg];
3191 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3192 State.regs[dstreg] = difference;
3193
3194 z = (difference == 0);
3195 n = (difference & 0x80000000);
3196 c = (imm > reg2);
3197 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3198 && (reg2 & 0x80000000) != (difference & 0x80000000));
3199
3200 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3201 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3202 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3203 }
3204
3205 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3206 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3207 "cmp"
3208 *am33
3209 {
3210 int srcreg;
3211
3212 PC = cia;
3213 srcreg = translate_rreg (SD_, RN0);
3214 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3215 }
3216
3217 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3218 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3219 "mov"
3220 *am33
3221 {
3222 PC = cia;
3223
3224 if (XRN0 == 0)
3225 {
3226 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3227 }
3228 else
3229 abort ();
3230 }
3231
3232 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3233 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3234 "and"
3235 *am33
3236 {
3237 int dstreg;
3238 int z,n;
3239
3240 PC = cia;
3241 dstreg = translate_rreg (SD_, RN0);
3242
3243 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3244 z = (State.regs[dstreg] == 0);
3245 n = (State.regs[dstreg] & 0x80000000) != 0;
3246 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3247 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3248 }
3249
3250 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3251 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3252 "or"
3253 *am33
3254 {
3255 int dstreg;
3256 int z,n;
3257
3258 PC = cia;
3259 dstreg = translate_rreg (SD_, RN0);
3260
3261 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3262 z = (State.regs[dstreg] == 0);
3263 n = (State.regs[dstreg] & 0x80000000) != 0;
3264 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3265 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3266 }
3267
3268 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3269 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3270 "xor"
3271 *am33
3272 {
3273 int dstreg;
3274 int z,n;
3275
3276 PC = cia;
3277 dstreg = translate_rreg (SD_, RN0);
3278
3279 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3280 z = (State.regs[dstreg] == 0);
3281 n = (State.regs[dstreg] & 0x80000000) != 0;
3282 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3283 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3284 }
3285
3286 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3287 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3288 "asr"
3289 *am33
3290 {
3291 int dstreg;
3292 long temp;
3293 int c, z, n;
3294
3295 PC = cia;
3296 dstreg = translate_rreg (SD_, RN0);
3297
3298 temp = State.regs[dstreg];
3299 c = temp & 1;
3300 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3301 State.regs[dstreg] = temp;
3302 z = (State.regs[dstreg] == 0);
3303 n = (State.regs[dstreg] & 0x80000000) != 0;
3304 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3305 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3306 }
3307
3308
3309 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3310 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3311 "lsr"
3312 *am33
3313 {
3314 int dstreg;
3315 int z, n, c;
3316
3317 PC = cia;
3318 dstreg = translate_rreg (SD_, RN0);
3319
3320 c = State.regs[dstreg] & 1;
3321 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3322 z = (State.regs[dstreg] == 0);
3323 n = (State.regs[dstreg] & 0x80000000) != 0;
3324 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3325 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3326 }
3327
3328 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3329 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3330 "asl"
3331 *am33
3332 {
3333 int srcreg, dstreg;
3334 int z, n;
3335
3336 PC = cia;
3337 dstreg = translate_rreg (SD_, RN0);
3338
3339 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3340 z = (State.regs[dstreg] == 0);
3341 n = (State.regs[dstreg] & 0x80000000) != 0;
3342 PSW &= ~(PSW_Z | PSW_N);
3343 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3344 }
3345
3346 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3347 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3348 "mul"
3349 *am33
3350 {
3351 int dstreg;
3352 unsigned long long temp;
3353 int z, n;
3354
3355 PC = cia;
3356 dstreg = translate_rreg (SD_, RN0);
3357
3358 temp = ((signed64)(signed32)State.regs[dstreg]
3359 * (signed64)(signed32)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3360 State.regs[dstreg] = temp & 0xffffffff;
3361 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3362 z = (State.regs[dstreg] == 0);
3363 n = (State.regs[dstreg] & 0x80000000) != 0;
3364 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3365 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3366 }
3367
3368 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3369 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3370 "mulu"
3371 *am33
3372 {
3373 int dstreg;
3374 unsigned long long temp;
3375 int z, n;
3376
3377 PC = cia;
3378 dstreg = translate_rreg (SD_, RN0);
3379
3380 temp = ((unsigned64)State.regs[dstreg]
3381 * (unsigned64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3382 State.regs[dstreg] = temp & 0xffffffff;
3383 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3384 z = (State.regs[dstreg] == 0);
3385 n = (State.regs[dstreg] & 0x80000000) != 0;
3386 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3387 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3388 }
3389
3390 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3391 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3392 "btst"
3393 *am33
3394 {
3395 int srcreg;
3396
3397 PC = cia;
3398 srcreg = translate_rreg (SD_, RN0);
3399 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3400 }
3401
3402 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3403 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3404 "mov"
3405 *am33
3406 {
3407 int srcreg, dstreg;
3408
3409 PC = cia;
3410 srcreg = translate_rreg (SD_, RM0);
3411 dstreg = translate_rreg (SD_, RN2);
3412 State.regs[dstreg] = load_word (State.regs[srcreg]
3413 + FETCH24 (IMM24A, IMM24B, IMM24C));
3414 }
3415
3416 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3417 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3418 "mov"
3419 *am33
3420 {
3421 int srcreg, dstreg;
3422
3423 PC = cia;
3424 srcreg = translate_rreg (SD_, RM2);
3425 dstreg = translate_rreg (SD_, RN0);
3426 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3427 State.regs[srcreg]);
3428 }
3429
3430 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3431 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3432 "movbu"
3433 *am33
3434 {
3435 int srcreg, dstreg;
3436
3437 PC = cia;
3438 srcreg = translate_rreg (SD_, RM0);
3439 dstreg = translate_rreg (SD_, RN2);
3440 State.regs[dstreg] = load_byte (State.regs[srcreg]
3441 + FETCH24 (IMM24A, IMM24B, IMM24C));
3442 }
3443
3444 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3445 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3446 "movbu"
3447 *am33
3448 {
3449 int srcreg, dstreg;
3450
3451 PC = cia;
3452 srcreg = translate_rreg (SD_, RM2);
3453 dstreg = translate_rreg (SD_, RN0);
3454 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3455 State.regs[srcreg]);
3456 }
3457
3458 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3459 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3460 "movhu"
3461 *am33
3462 {
3463 int srcreg, dstreg;
3464
3465 PC = cia;
3466 srcreg = translate_rreg (SD_, RM0);
3467 dstreg = translate_rreg (SD_, RN2);
3468 State.regs[dstreg] = load_half (State.regs[srcreg]
3469 + FETCH24 (IMM24A, IMM24B, IMM24C));
3470 }
3471
3472 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3473 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3474 "movhu"
3475 *am33
3476 {
3477 int srcreg, dstreg;
3478
3479 PC = cia;
3480 srcreg = translate_rreg (SD_, RM2);
3481 dstreg = translate_rreg (SD_, RN0);
3482 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3483 State.regs[srcreg]);
3484 }
3485
3486 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3487 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3488 "mov"
3489 *am33
3490 {
3491 int srcreg, dstreg;
3492
3493 PC = cia;
3494 srcreg = translate_rreg (SD_, RM0);
3495 dstreg = translate_rreg (SD_, RN2);
3496 State.regs[dstreg] = load_word (State.regs[srcreg]
3497 + FETCH24 (IMM24A, IMM24B, IMM24C));
3498 State.regs[srcreg] += 4;
3499 }
3500
3501 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3502 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3503 "mov"
3504 *am33
3505 {
3506 int srcreg, dstreg;
3507
3508 PC = cia;
3509 srcreg = translate_rreg (SD_, RM2);
3510 dstreg = translate_rreg (SD_, RN0);
3511 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3512 State.regs[srcreg]);
3513 State.regs[dstreg] += 4;
3514 }
3515
3516
3517 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3518 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3519 "mov"
3520 *am33
3521 {
3522 int dstreg;
3523
3524 PC = cia;
3525 dstreg = translate_rreg (SD_, RN2);
3526 State.regs[dstreg] = load_word (State.regs[REG_SP]
3527 + FETCH24 (IMM24A, IMM24B, IMM24C));
3528 }
3529
3530 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3531 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3532 "mov"
3533 *am33
3534 {
3535 int srcreg;
3536
3537 PC = cia;
3538 srcreg = translate_rreg (SD_, RM2);
3539 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3540 State.regs[srcreg]);
3541 }
3542
3543 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3544 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3545 "movbu"
3546 *am33
3547 {
3548 int dstreg;
3549
3550 PC = cia;
3551 dstreg = translate_rreg (SD_, RN2);
3552 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3553 + FETCH24 (IMM24A, IMM24B, IMM24C));
3554 }
3555
3556 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3557 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3558 "movbu"
3559 *am33
3560 {
3561 int srcreg;
3562
3563 PC = cia;
3564 srcreg = translate_rreg (SD_, RM2);
3565 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3566 State.regs[srcreg]);
3567 }
3568
3569 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3570 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3571 "movhu"
3572 *am33
3573 {
3574 int dstreg;
3575
3576 PC = cia;
3577 dstreg = translate_rreg (SD_, RN2);
3578 State.regs[dstreg] = load_half (State.regs[REG_SP]
3579 + FETCH24 (IMM24A, IMM24B, IMM24C));
3580 }
3581
3582 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3583 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3584 "movhu"
3585 *am33
3586 {
3587 int srcreg;
3588
3589 PC = cia;
3590 srcreg = translate_rreg (SD_, RM2);
3591 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3592 State.regs[srcreg]);
3593 }
3594
3595 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3596 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3597 "movhu"
3598 *am33
3599 {
3600 int srcreg, dstreg;
3601
3602 PC = cia;
3603 srcreg = translate_rreg (SD_, RM0);
3604 dstreg = translate_rreg (SD_, RN2);
3605 State.regs[dstreg] = load_half (State.regs[srcreg]
3606 + FETCH24 (IMM24A, IMM24B, IMM24C));
3607 State.regs[dstreg] += 2;
3608 }
3609
3610 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3611 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3612 "movhu"
3613 *am33
3614 {
3615 int srcreg, dstreg;
3616
3617 PC = cia;
3618 srcreg = translate_rreg (SD_, RM2);
3619 dstreg = translate_rreg (SD_, RN0);
3620 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3621 State.regs[srcreg]);
3622 State.regs[srcreg] += 2;
3623 }
3624
3625 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3626 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3627 "mac"
3628 *am33
3629 {
3630 int srcreg;
3631 long long temp, sum;
3632 int c, v;
3633
3634 PC = cia;
3635 srcreg = translate_rreg (SD_, RN2);
3636
3637 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3638 * (signed64)State.regs[srcreg]);
3639 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3640 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3641 State.regs[REG_MCRL] = sum;
3642 temp >>= 32;
3643 temp &= 0xffffffff;
3644 sum = State.regs[REG_MCRH] + temp + c;
3645 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3646 && (temp & 0x80000000) != (sum & 0x80000000));
3647 State.regs[REG_MCRH] = sum;
3648 if (v)
3649 State.regs[REG_MCVF] = 1;
3650 }
3651
3652 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3653 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3654 "macu"
3655 *am33
3656 {
3657 int srcreg;
3658 long long temp, sum;
3659 int c, v;
3660
3661 PC = cia;
3662 srcreg = translate_rreg (SD_, RN2);
3663
3664 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3665 * (unsigned64)State.regs[srcreg]);
3666 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3667 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3668 State.regs[REG_MCRL] = sum;
3669 temp >>= 32;
3670 temp &= 0xffffffff;
3671 sum = State.regs[REG_MCRH] + temp + c;
3672 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3673 && (temp & 0x80000000) != (sum & 0x80000000));
3674 State.regs[REG_MCRH] = sum;
3675 if (v)
3676 State.regs[REG_MCVF] = 1;
3677 }
3678
3679 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3680 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3681 "macb"
3682 *am33
3683 {
3684 int srcreg;
3685 long long temp, sum;
3686 int c, v;
3687
3688 PC = cia;
3689 srcreg = translate_rreg (SD_, RN2);
3690
3691 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3692 * (signed64)State.regs[srcreg] & 0xff);
3693 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3694 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3695 State.regs[REG_MCRL] = sum;
3696 temp >>= 32;
3697 temp &= 0xffffffff;
3698 sum = State.regs[REG_MCRH] + temp + c;
3699 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3700 && (temp & 0x80000000) != (sum & 0x80000000));
3701 State.regs[REG_MCRH] = sum;
3702 if (v)
3703 State.regs[REG_MCVF] = 1;
3704 }
3705
3706 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3707 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3708 "macbu"
3709 *am33
3710 {
3711 int srcreg;
3712 long long temp, sum;
3713 int c, v;
3714
3715 PC = cia;
3716 srcreg = translate_rreg (SD_, RN2);
3717
3718 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3719 * (unsigned64)State.regs[srcreg] & 0xff);
3720 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3721 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3722 State.regs[REG_MCRL] = sum;
3723 temp >>= 32;
3724 temp &= 0xffffffff;
3725 sum = State.regs[REG_MCRH] + temp + c;
3726 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3727 && (temp & 0x80000000) != (sum & 0x80000000));
3728 State.regs[REG_MCRH] = sum;
3729 if (v)
3730 State.regs[REG_MCVF] = 1;
3731 }
3732
3733 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3734 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3735 "mach"
3736 *am33
3737 {
3738 int srcreg;
3739 long long temp, sum;
3740 int c, v;
3741
3742 PC = cia;
3743 srcreg = translate_rreg (SD_, RN2);
3744
3745 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3746 * (signed64)State.regs[srcreg] & 0xffff);
3747 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3748 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3749 State.regs[REG_MCRL] = sum;
3750 temp >>= 32;
3751 temp &= 0xffffffff;
3752 sum = State.regs[REG_MCRH] + temp + c;
3753 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3754 && (temp & 0x80000000) != (sum & 0x80000000));
3755 State.regs[REG_MCRH] = sum;
3756 if (v)
3757 State.regs[REG_MCVF] = 1;
3758 }
3759
3760 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3761 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3762 "machu"
3763 *am33
3764 {
3765 int srcreg;
3766 long long temp, sum;
3767 int c, v;
3768
3769 PC = cia;
3770 srcreg = translate_rreg (SD_, RN2);
3771
3772 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3773 * (unsigned64)State.regs[srcreg] & 0xffff);
3774 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3775 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3776 State.regs[REG_MCRL] = sum;
3777 temp >>= 32;
3778 temp &= 0xffffffff;
3779 sum = State.regs[REG_MCRH] + temp + c;
3780 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3781 && (temp & 0x80000000) != (sum & 0x80000000));
3782 State.regs[REG_MCRH] = sum;
3783 if (v)
3784 State.regs[REG_MCVF] = 1;
3785 }
3786
3787 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3788 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3789 "mov"
3790 *am33
3791 {
3792 int dstreg;
3793
3794 PC = cia;
3795 dstreg = translate_rreg (SD_, RN2);
3796 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3797 }
3798
3799 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3800 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3801 "mov"
3802 *am33
3803 {
3804 int srcreg;
3805
3806 PC = cia;
3807 srcreg = translate_rreg (SD_, RM2);
3808 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3809 }
3810
3811
3812 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3813 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3814 "movbu"
3815 *am33
3816 {
3817 int dstreg;
3818
3819 PC = cia;
3820 dstreg = translate_rreg (SD_, RN2);
3821 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3822 }
3823
3824 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3825 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3826 "movbu"
3827 *am33
3828 {
3829 int srcreg;
3830
3831 PC = cia;
3832 srcreg = translate_rreg (SD_, RM2);
3833 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3834 }
3835
3836
3837 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3838 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3839 "movhu"
3840 *am33
3841 {
3842 int dstreg;
3843
3844 PC = cia;
3845 dstreg = translate_rreg (SD_, RN2);
3846 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3847 }
3848
3849 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3850 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3851 "movhu"
3852 *am33
3853 {
3854 int srcreg;
3855
3856 PC = cia;
3857 srcreg = translate_rreg (SD_, RM2);
3858 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3859 }
3860
3861
3862 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3863 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3864 "mov"
3865 *am33
3866 {
3867 int dstreg;
3868
3869 PC = cia;
3870 dstreg = translate_rreg (SD_, RN0);
3871 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3872 }
3873
3874 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3875 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3876 "movu"
3877 *am33
3878 {
3879 int dstreg;
3880
3881 PC = cia;
3882 dstreg = translate_rreg (SD_, RN0);
3883 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3884 }
3885
3886 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3887 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3888 "add"
3889 *am33
3890 {
3891 int dstreg;
3892
3893 PC = cia;
3894 dstreg = translate_rreg (SD_, RN0);
3895 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3896 }
3897
3898 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3899 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3900 "addc"
3901 *am33
3902 {
3903 int dstreg;
3904 unsigned int imm, reg2, sum;
3905 int z, n, c, v;
3906
3907 PC = cia;
3908 dstreg = translate_rreg (SD_, RN0);
3909
3910 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3911 reg2 = State.regs[dstreg];
3912 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3913 State.regs[dstreg] = sum;
3914
3915 z = (sum == 0);
3916 n = (sum & 0x80000000);
3917 c = (sum < imm) || (sum < reg2);
3918 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3919 && (reg2 & 0x80000000) != (sum & 0x80000000));
3920
3921 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3922 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3923 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3924 }
3925
3926 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3927 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3928 "sub"
3929 *am33
3930 {
3931 int dstreg;
3932
3933 PC = cia;
3934 dstreg = translate_rreg (SD_, RN0);
3935 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3936 }
3937
3938 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3939 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3940 "subc"
3941 *am33
3942 {
3943 int dstreg;
3944 unsigned int imm, reg2, difference;
3945 int z, n, c, v;
3946
3947 PC = cia;
3948 dstreg = translate_rreg (SD_, RN0);
3949
3950 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3951 reg2 = State.regs[dstreg];
3952 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3953 State.regs[dstreg] = difference;
3954
3955 z = (difference == 0);
3956 n = (difference & 0x80000000);
3957 c = (imm > reg2);
3958 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3959 && (reg2 & 0x80000000) != (difference & 0x80000000));
3960
3961 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3962 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3963 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3964 }
3965
3966 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3967 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3968 "cmp"
3969 *am33
3970 {
3971 int srcreg;
3972
3973 PC = cia;
3974 srcreg = translate_rreg (SD_, RN0);
3975 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3976 }
3977
3978 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3979 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3980 "mov"
3981 *am33
3982 {
3983 PC = cia;
3984
3985 if (XRN0 == 0)
3986 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3987 else
3988 abort ();
3989 }
3990
3991 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3992 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
3993 "and"
3994 *am33
3995 {
3996 int dstreg;
3997 int z,n;
3998
3999 PC = cia;
4000 dstreg = translate_rreg (SD_, RN0);
4001
4002 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4003 z = (State.regs[dstreg] == 0);
4004 n = (State.regs[dstreg] & 0x80000000) != 0;
4005 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4006 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4007 }
4008
4009 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4010 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4011 "or"
4012 *am33
4013 {
4014 int dstreg;
4015 int z,n;
4016
4017 PC = cia;
4018 dstreg = translate_rreg (SD_, RN0);
4019
4020 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4021 z = (State.regs[dstreg] == 0);
4022 n = (State.regs[dstreg] & 0x80000000) != 0;
4023 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4024 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4025 }
4026
4027 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4028 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4029 "xor"
4030 *am33
4031 {
4032 int dstreg;
4033 int z,n;
4034
4035 PC = cia;
4036 dstreg = translate_rreg (SD_, RN0);
4037
4038 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4039 z = (State.regs[dstreg] == 0);
4040 n = (State.regs[dstreg] & 0x80000000) != 0;
4041 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4042 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4043 }
4044
4045 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4046 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4047 "asr"
4048 *am33
4049 {
4050 int dstreg;
4051 long temp;
4052 int c, z, n;
4053
4054 PC = cia;
4055 dstreg = translate_rreg (SD_, RN0);
4056
4057 temp = State.regs[dstreg];
4058 c = temp & 1;
4059 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4060 State.regs[dstreg] = temp;
4061 z = (State.regs[dstreg] == 0);
4062 n = (State.regs[dstreg] & 0x80000000) != 0;
4063 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4064 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4065 }
4066
4067 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4068 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4069 "lsr"
4070 *am33
4071 {
4072 int dstreg;
4073 int z, n, c;
4074
4075 PC = cia;
4076 dstreg = translate_rreg (SD_, RN0);
4077
4078 c = State.regs[dstreg] & 1;
4079 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4080 z = (State.regs[dstreg] == 0);
4081 n = (State.regs[dstreg] & 0x80000000) != 0;
4082 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4083 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4084 }
4085
4086 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4087 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4088 "asl"
4089 *am33
4090 {
4091 int srcreg, dstreg;
4092 int z, n;
4093
4094 PC = cia;
4095 dstreg = translate_rreg (SD_, RN0);
4096
4097 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4098 z = (State.regs[dstreg] == 0);
4099 n = (State.regs[dstreg] & 0x80000000) != 0;
4100 PSW &= ~(PSW_Z | PSW_N);
4101 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4102 }
4103
4104 // ??? mul
4105 // ??? mulu
4106
4107 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4108 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4109 "btst"
4110 *am33
4111 {
4112 int srcreg;
4113
4114 PC = cia;
4115 srcreg = translate_rreg (SD_, RN0);
4116 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4117 }
4118
4119 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4120 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4121 "mov"
4122 *am33
4123 {
4124 int srcreg, dstreg;
4125
4126 PC = cia;
4127 srcreg = translate_rreg (SD_, RM0);
4128 dstreg = translate_rreg (SD_, RN2);
4129 State.regs[dstreg] = load_word (State.regs[srcreg]
4130 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4131 }
4132
4133 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4134 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4135 "mov"
4136 *am33
4137 {
4138 int srcreg, dstreg;
4139
4140 PC = cia;
4141 srcreg = translate_rreg (SD_, RM2);
4142 dstreg = translate_rreg (SD_, RN0);
4143 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4144 State.regs[srcreg]);
4145 }
4146
4147 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4148 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4149 "movbu"
4150 *am33
4151 {
4152 int srcreg, dstreg;
4153
4154 PC = cia;
4155 srcreg = translate_rreg (SD_, RM0);
4156 dstreg = translate_rreg (SD_, RN2);
4157 State.regs[dstreg] = load_byte (State.regs[srcreg]
4158 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4159 }
4160
4161 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4162 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4163 "movbu"
4164 *am33
4165 {
4166 int srcreg, dstreg;
4167
4168 PC = cia;
4169 srcreg = translate_rreg (SD_, RM2);
4170 dstreg = translate_rreg (SD_, RN0);
4171 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4172 State.regs[srcreg]);
4173 }
4174
4175 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4176 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4177 "movhu"
4178 *am33
4179 {
4180 int srcreg, dstreg;
4181
4182 PC = cia;
4183 srcreg = translate_rreg (SD_, RM0);
4184 dstreg = translate_rreg (SD_, RN2);
4185 State.regs[dstreg] = load_half (State.regs[srcreg]
4186 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4187 }
4188
4189 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4190 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4191 "movhu"
4192 *am33
4193 {
4194 int srcreg, dstreg;
4195
4196 PC = cia;
4197 srcreg = translate_rreg (SD_, RM2);
4198 dstreg = translate_rreg (SD_, RN0);
4199 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4200 State.regs[srcreg]);
4201 }
4202
4203 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4204 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4205 "mov"
4206 *am33
4207 {
4208 int srcreg, dstreg;
4209
4210 PC = cia;
4211 srcreg = translate_rreg (SD_, RM0);
4212 dstreg = translate_rreg (SD_, RN2);
4213 State.regs[dstreg] = load_word (State.regs[srcreg]
4214 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4215 State.regs[srcreg] += 4;
4216 }
4217
4218 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4219 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4220 "mov"
4221 *am33
4222 {
4223 int srcreg, dstreg;
4224
4225 PC = cia;
4226 srcreg = translate_rreg (SD_, RM2);
4227 dstreg = translate_rreg (SD_, RN0);
4228 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4229 State.regs[srcreg]);
4230 State.regs[dstreg] += 4;
4231 }
4232
4233
4234 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4235 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4236 "mov"
4237 *am33
4238 {
4239 int dstreg;
4240
4241 PC = cia;
4242 dstreg = translate_rreg (SD_, RN2);
4243 State.regs[dstreg] = load_word (State.regs[REG_SP]
4244 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4245 }
4246
4247 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4248 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4249 "mov"
4250 *am33
4251 {
4252 int srcreg;
4253
4254 PC = cia;
4255 srcreg = translate_rreg (SD_, RM2);
4256 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4257 State.regs[srcreg]);
4258 }
4259
4260 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4261 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4262 "movbu"
4263 *am33
4264 {
4265 int dstreg;
4266
4267 PC = cia;
4268 dstreg = translate_rreg (SD_, RN2);
4269 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4270 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4271 }
4272
4273 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4274 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4275 "movbu"
4276 *am33
4277 {
4278 int srcreg;
4279
4280 PC = cia;
4281 srcreg = translate_rreg (SD_, RM2);
4282 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4283 State.regs[srcreg]);
4284 }
4285
4286 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4287 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4288 "movhu"
4289 *am33
4290 {
4291 int dstreg;
4292
4293 PC = cia;
4294 dstreg = translate_rreg (SD_, RN2);
4295 State.regs[dstreg] = load_half (State.regs[REG_SP]
4296 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4297 }
4298
4299 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4300 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4301 "movhu"
4302 *am33
4303 {
4304 int srcreg;
4305
4306 PC = cia;
4307 srcreg = translate_rreg (SD_, RM2);
4308 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4309 State.regs[srcreg]);
4310 }
4311
4312
4313 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4314 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4315 "movhu"
4316 *am33
4317 {
4318 int srcreg, dstreg;
4319
4320 PC = cia;
4321 srcreg = translate_rreg (SD_, RM0);
4322 dstreg = translate_rreg (SD_, RN2);
4323 State.regs[dstreg] = load_half (State.regs[srcreg]
4324 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4325 State.regs[srcreg] += 2;
4326 }
4327
4328 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4329 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4330 "movhu"
4331 *am33
4332 {
4333 int srcreg, dstreg;
4334
4335 PC = cia;
4336 srcreg = translate_rreg (SD_, RM2);
4337 dstreg = translate_rreg (SD_, RN0);
4338 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4339 State.regs[srcreg]);
4340 State.regs[dstreg] += 2;
4341 }
4342
4343
4344 // ??? mac
4345 // ??? macu
4346 // ??? macb
4347 // ??? macbu
4348 // ??? mach
4349 // ??? machu
4350 // ??? dmach
4351 // ??? dmachu
4352 // ??? dmulh
4353 // ??? dmulhu
4354
4355 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4356 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4357 "mov"
4358 *am33
4359 {
4360 int dstreg;
4361
4362 PC = cia;
4363 dstreg = translate_rreg (SD_, RN2);
4364 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4365 }
4366
4367 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4368 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4369 "mov"
4370 *am33
4371 {
4372 int srcreg;
4373
4374 PC = cia;
4375 srcreg = translate_rreg (SD_, RM2);
4376 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4377 }
4378
4379 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4380 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4381 "movbu"
4382 *am33
4383 {
4384 int dstreg;
4385
4386 PC = cia;
4387 dstreg = translate_rreg (SD_, RN2);
4388 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4389 }
4390
4391 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4392 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4393 "movbu"
4394 *am33
4395 {
4396 int srcreg;
4397
4398 PC = cia;
4399 srcreg = translate_rreg (SD_, RM2);
4400 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4401 }
4402
4403 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4404 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4405 "movhu"
4406 *am33
4407 {
4408 int dstreg;
4409
4410 PC = cia;
4411 dstreg = translate_rreg (SD_, RN2);
4412 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4413 }
4414
4415 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4416 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4417 "movhu"
4418 *am33
4419 {
4420 int srcreg;
4421
4422 PC = cia;
4423 srcreg = translate_rreg (SD_, RM2);
4424 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4425 }
4426
4427 // ??? DSP
GDB Binutils - Deliverables
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