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* am33.igen: More am33 instructions. Fix "div".
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // 1111 0000 0010 00An; mov USP,An
2 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
3 "mov"
4 *am33
5 {
6 PC = cia;
7 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
8 }
9
10
11 // 1111 0000 0010 01An; mov SSP,An
12 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
13 "mov"
14 *am33
15 {
16 PC = cia;
17 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
18 }
19
20
21 // 1111 0000 0010 10An; mov MSP,An
22 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
23 "mov"
24 *am33
25 {
26 PC = cia;
27 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
28 }
29
30
31 // 1111 0000 0010 11An; mov PC,An
32 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
33 "mov"
34 *am33
35 {
36 PC = cia;
37 State.regs[REG_A0 + AN0] = PC;
38 }
39
40
41 // 1111 0000 0011 Am00; mov Am,USP
42 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
43 "mov"
44 *am33
45 {
46 PC = cia;
47 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
48 }
49
50 // 1111 0000 0011 Am01; mov Am,SSP
51 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
52 "mov"
53 *am33
54 {
55 PC = cia;
56 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
57 }
58
59 // 1111 0000 0011 Am10; mov Am,MSP
60 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
61 "mov"
62 *am33
63 {
64 PC = cia;
65 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
66 }
67
68
69 // 1111 0000 1110 imm4; syscall
70 8.0xf0+4.0xe,IMM4:D0t:::syscall
71 "syscall"
72 *am33
73 {
74 unsigned int sp, next_pc;
75
76 PC = cia;
77 sp = State.regs[REG_SP];
78 next_pc = State.regs[REG_PC] + 2;
79 store_word (sp - 4, next_pc);
80 store_word (sp - 8, PSW);
81 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
82 nia = PC;
83 }
84
85
86 // 1111 0010 1110 11Dn; mov EPSW,Dn
87 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
88 "mov"
89 *am33
90 {
91 PC = cia;
92 State.regs[REG_D0 + DN0] = PSW;
93 }
94
95
96 // 1111 0010 1111 Dm01; mov Dm,EPSW
97 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
98 "mov"
99 *am33
100 {
101 PC = cia;
102 PSW = State.regs[REG_D0 + DM1];
103 }
104
105 // 1111 0101 00Am Rn; mov Am,Rn
106 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
107 "mov"
108 *am33
109 {
110 PC = cia;
111 /* The higher register numbers actually correspond to the
112 basic machine's address and data registers. */
113 if (RN0 > 7 && RN0 < 12)
114 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_A0 + AM1];
115 else if (RN0 > 11 && RN0 < 16)
116 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_A0 + AM1];
117 else
118 State.regs[REG_E0 + RN0] = State.regs[REG_A0 + AM1] ;
119 }
120
121 // 1111 0101 01Dm Rn; mov Dm,Rn
122 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
123 "mov"
124 *am33
125 {
126 PC = cia;
127 /* The higher register numbers actually correspond to the
128 basic machine's address and data registers. */
129 if (RN0 > 7 && RN0 < 12)
130 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_D0 + DM1];
131 else if (RN0 > 11 && RN0 < 16)
132 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_D0 + DM1];
133 else
134 State.regs[REG_E0 + RN0] = State.regs[REG_D0 + DM1] ;
135 }
136
137 // 1111 0101 10Rm An; mov Rm,An
138 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
139 "mov"
140 *am33
141 {
142 PC = cia;
143 /* The higher register numbers actually correspond to the
144 basic machine's address and data registers. */
145 if (RM1 > 7 && RM1 < 12)
146 State.regs[REG_A0 + AN0] = State.regs[REG_A0 + RM1 - 8];
147 else if (RM1 > 11 && RM1 < 16)
148 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + RM1 - 12];
149 else
150 State.regs[REG_A0 + AN0] = State.regs[REG_E0 + RM1];
151 }
152
153 // 1111 0101 11Rm Dn; mov Rm,Dn
154 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
155 "mov"
156 *am33
157 {
158 PC = cia;
159 /* The higher register numbers actually correspond to the
160 basic machine's address and data registers. */
161 if (RM1 > 7 && RM1 < 12)
162 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + RM1 - 8];
163 else if (RM1 > 11 && RM1 < 16)
164 State.regs[REG_D0 + DN0] = State.regs[REG_D0 + RM1 - 12];
165 else
166 State.regs[REG_D0 + DN0] = State.regs[REG_E0 + RM1];
167 }
168
169
170 // 1111 1000 1100 1110 regs....; movm (USP),regs
171 8.0xf8+8.0xce+8.REGS:D1a:::movm
172 "movm"
173 *am33
174 {
175 unsigned long usp = State.regs[REG_USP];
176 unsigned long mask;
177
178 PC = cia;
179 mask = REGS;
180
181 if (mask & 0x8)
182 {
183 usp += 4;
184 State.regs[REG_LAR] = load_word (usp);
185 usp += 4;
186 State.regs[REG_LIR] = load_word (usp);
187 usp += 4;
188 State.regs[REG_MDR] = load_word (usp);
189 usp += 4;
190 State.regs[REG_A0 + 1] = load_word (usp);
191 usp += 4;
192 State.regs[REG_A0] = load_word (usp);
193 usp += 4;
194 State.regs[REG_D0 + 1] = load_word (usp);
195 usp += 4;
196 State.regs[REG_D0] = load_word (usp);
197 usp += 4;
198 }
199
200 if (mask & 0x10)
201 {
202 State.regs[REG_A0 + 3] = load_word (usp);
203 usp += 4;
204 }
205
206 if (mask & 0x20)
207 {
208 State.regs[REG_A0 + 2] = load_word (usp);
209 usp += 4;
210 }
211
212 if (mask & 0x40)
213 {
214 State.regs[REG_D0 + 3] = load_word (usp);
215 usp += 4;
216 }
217
218 if (mask & 0x80)
219 {
220 State.regs[REG_D0 + 2] = load_word (usp);
221 usp += 4;
222 }
223
224 /* start-sanitize-am33 */
225 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
226 {
227 if (mask & 0x1)
228 {
229 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
230 usp += 16;
231 State.regs[REG_E0 + 1] = load_word (usp);
232 usp += 4;
233 State.regs[REG_E0 + 0] = load_word (usp);
234 usp += 4;
235 }
236
237 if (mask & 0x2)
238 {
239 State.regs[REG_E0 + 7] = load_word (usp);
240 usp += 4;
241 State.regs[REG_E0 + 6] = load_word (usp);
242 usp += 4;
243 State.regs[REG_E0 + 5] = load_word (usp);
244 usp += 4;
245 State.regs[REG_E0 + 4] = load_word (usp);
246 usp += 4;
247 }
248
249 if (mask & 0x4)
250 {
251 State.regs[REG_E0 + 3] = load_word (usp);
252 usp += 4;
253 State.regs[REG_E0 + 2] = load_word (usp);
254 usp += 4;
255 }
256 }
257 /* end-sanitize-am33 */
258
259 /* And make sure to update the stack pointer. */
260 State.regs[REG_USP] = usp;
261 }
262
263 // 1111 1000 1100 1111 regs....; movm (USP),regs
264 8.0xf8+8.0xcf+8.REGS:D1b:::movm
265 "movm"
266 *am33
267 {
268 unsigned long usp = State.regs[REG_USP];
269 unsigned long mask;
270
271 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
272 {
273 if (mask & 0x4)
274 {
275 usp -= 4;
276 store_word (usp, State.regs[REG_E0 + 2]);
277 usp -= 4;
278 store_word (usp, State.regs[REG_E0 + 3]);
279 }
280
281 if (mask & 0x2)
282 {
283 usp -= 4;
284 store_word (usp, State.regs[REG_E0 + 4]);
285 usp -= 4;
286 store_word (usp, State.regs[REG_E0 + 5]);
287 usp -= 4;
288 store_word (usp, State.regs[REG_E0 + 6]);
289 usp -= 4;
290 store_word (usp, State.regs[REG_E0 + 7]);
291 }
292
293 if (mask & 0x1)
294 {
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 0]);
297 usp -= 4;
298 store_word (usp, State.regs[REG_E0 + 1]);
299 usp -= 16;
300 /* Need to save MDQR, MCRH, MCRL, and MCVF */
301 }
302 }
303 /* end-sanitize-am33 */
304
305 if (mask & 0x80)
306 {
307 usp -= 4;
308 store_word (usp, State.regs[REG_D0 + 2]);
309 }
310
311 if (mask & 0x40)
312 {
313 usp -= 4;
314 store_word (usp, State.regs[REG_D0 + 3]);
315 }
316
317 if (mask & 0x20)
318 {
319 usp -= 4;
320 store_word (usp, State.regs[REG_A0 + 2]);
321 }
322
323 if (mask & 0x10)
324 {
325 usp -= 4;
326 store_word (usp, State.regs[REG_A0 + 3]);
327 }
328
329 if (mask & 0x8)
330 {
331 usp -= 4;
332 store_word (usp, State.regs[REG_D0]);
333 usp -= 4;
334 store_word (usp, State.regs[REG_D0 + 1]);
335 usp -= 4;
336 store_word (usp, State.regs[REG_A0]);
337 usp -= 4;
338 store_word (usp, State.regs[REG_A0 + 1]);
339 usp -= 4;
340 store_word (usp, State.regs[REG_MDR]);
341 usp -= 4;
342 store_word (usp, State.regs[REG_LIR]);
343 usp -= 4;
344 store_word (usp, State.regs[REG_LAR]);
345 usp -= 4;
346 }
347
348 /* And make sure to update the stack pointer. */
349 State.regs[REG_USP] = usp;
350 }
351
352 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
353 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
354 "and"
355 *am33
356 {
357 PC = cia;
358 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
359 }
360
361 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
362 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
363 "or"
364 *am33
365 {
366 PC = cia;
367 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
368 }
369
370 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
371 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
372 "mov"
373 *am33
374 {
375 int srcreg, dstreg;
376
377 PC = cia;
378
379 if (RM2 > 7 && RM2 < 12)
380 srcreg = REG_A0 + RM2 - 8;
381 else if (RM2 > 11 && RM2 < 16)
382 srcreg = REG_D0 + RM2 - 12;
383 else
384 srcreg = REG_E0 + RM2;
385
386 if (RN0 > 7 && RN0 < 12)
387 dstreg = REG_A0 + RN0 - 8;
388 else if (RN0 > 11 && RN0 < 16)
389 dstreg = REG_D0 + RN0 - 12;
390 else
391 dstreg = REG_E0 + RN0;
392
393 State.regs[dstreg] = State.regs[srcreg];
394 }
395
396 // 1111 1001 0001 1000 Rn Rn; ext Rn
397 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
398 "mov"
399 *am33
400 {
401 int srcreg, dstreg;
402
403 PC = cia;
404
405 if (RN0 > 7 && RN0 < 12)
406 srcreg = REG_A0 + RN0 - 8;
407 else if (RN0 > 11 && RN0 < 16)
408 srcreg = REG_D0 + RN0 - 12;
409 else
410 srcreg = REG_E0 + RN0;
411
412 if (State.regs[srcreg] & 0x80000000)
413 State.regs[REG_MDR] = -1;
414 else
415 State.regs[REG_MDR] = 0;
416 }
417
418 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
419 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
420 "extb"
421 *am33
422 {
423 int srcreg, dstreg;
424
425 PC = cia;
426
427 if (RM2 > 7 && RM2 < 12)
428 srcreg = REG_A0 + RM2 - 8;
429 else if (RM2 > 11 && RM2 < 16)
430 srcreg = REG_D0 + RM2 - 12;
431 else
432 srcreg = REG_E0 + RM2;
433
434 if (RN0 > 7 && RN0 < 12)
435 dstreg = REG_A0 + RN0 - 8;
436 else if (RN0 > 11 && RN0 < 16)
437 dstreg = REG_D0 + RN0 - 12;
438 else
439 dstreg = REG_E0 + RN0;
440
441 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
442 }
443
444 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
445 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
446 "extbu"
447 *am33
448 {
449 int srcreg, dstreg;
450
451 PC = cia;
452
453 if (RM2 > 7 && RM2 < 12)
454 srcreg = REG_A0 + RM2 - 8;
455 else if (RM2 > 11 && RM2 < 16)
456 srcreg = REG_D0 + RM2 - 12;
457 else
458 srcreg = REG_E0 + RM2;
459
460 if (RN0 > 7 && RN0 < 12)
461 dstreg = REG_A0 + RN0 - 8;
462 else if (RN0 > 11 && RN0 < 16)
463 dstreg = REG_D0 + RN0 - 12;
464 else
465 dstreg = REG_E0 + RN0;
466
467 State.regs[dstreg] = State.regs[srcreg] & 0xff;
468 }
469
470 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
471 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
472 "exth"
473 *am33
474 {
475 int srcreg, dstreg;
476
477 PC = cia;
478
479 if (RM2 > 7 && RM2 < 12)
480 srcreg = REG_A0 + RM2 - 8;
481 else if (RM2 > 11 && RM2 < 16)
482 srcreg = REG_D0 + RM2 - 12;
483 else
484 srcreg = REG_E0 + RM2;
485
486 if (RN0 > 7 && RN0 < 12)
487 dstreg = REG_A0 + RN0 - 8;
488 else if (RN0 > 11 && RN0 < 16)
489 dstreg = REG_D0 + RN0 - 12;
490 else
491 dstreg = REG_E0 + RN0;
492
493 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
494 }
495
496 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
497 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
498 "exthu"
499 *am33
500 {
501 int srcreg, dstreg;
502
503 PC = cia;
504
505 if (RM2 > 7 && RM2 < 12)
506 srcreg = REG_A0 + RM2 - 8;
507 else if (RM2 > 11 && RM2 < 16)
508 srcreg = REG_D0 + RM2 - 12;
509 else
510 srcreg = REG_E0 + RM2;
511
512 if (RN0 > 7 && RN0 < 12)
513 dstreg = REG_A0 + RN0 - 8;
514 else if (RN0 > 11 && RN0 < 16)
515 dstreg = REG_D0 + RN0 - 12;
516 else
517 dstreg = REG_E0 + RN0;
518
519 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
520 }
521
522 // 1111 1001 0110 1000 Rn Rn; clr Rn
523 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
524 "clr"
525 *am33
526 {
527 int srcreg, dstreg;
528
529 PC = cia;
530
531 if (RN0 > 7 && RN0 < 12)
532 dstreg = REG_A0 + RN0 - 8;
533 else if (RN0 > 11 && RN0 < 16)
534 dstreg = REG_D0 + RN0 - 12;
535 else
536 dstreg = REG_E0 + RN0;
537
538 State.regs[dstreg] = 0;
539
540 PSW |= PSW_Z;
541 PSW &= ~(PSW_V | PSW_C | PSW_N);
542 }
543
544 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
545 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
546 "add"
547 *am33
548 {
549 int srcreg, dstreg;
550
551 PC = cia;
552
553 if (RM2 > 7 && RM2 < 12)
554 srcreg = REG_A0 + RM2 - 8;
555 else if (RM2 > 11 && RM2 < 16)
556 srcreg = REG_D0 + RM2 - 12;
557 else
558 srcreg = REG_E0 + RM2;
559
560 if (RN0 > 7 && RN0 < 12)
561 dstreg = REG_A0 + RN0 - 8;
562 else if (RN0 > 11 && RN0 < 16)
563 dstreg = REG_D0 + RN0 - 12;
564 else
565 dstreg = REG_E0 + RN0;
566
567 genericAdd (State.regs[srcreg], dstreg);
568 }
569
570 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
571 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
572 "addc"
573 *am33
574 {
575 int srcreg, dstreg;
576 int z, c, n, v;
577 unsigned long reg1, reg2, sum;
578
579 PC = cia;
580
581 if (RM2 > 7 && RM2 < 12)
582 srcreg = REG_A0 + RM2 - 8;
583 else if (RM2 > 11 && RM2 < 16)
584 srcreg = REG_D0 + RM2 - 12;
585 else
586 srcreg = REG_E0 + RM2;
587
588 if (RN0 > 7 && RN0 < 12)
589 dstreg = REG_A0 + RN0 - 8;
590 else if (RN0 > 11 && RN0 < 16)
591 dstreg = REG_D0 + RN0 - 12;
592 else
593 dstreg = REG_E0 + RN0;
594
595 reg1 = State.regs[srcreg];
596 reg2 = State.regs[dstreg];
597 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
598 State.regs[dstreg] = sum;
599
600 z = (sum == 0);
601 n = (sum & 0x80000000);
602 c = (sum < reg1) || (sum < reg2);
603 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
604 && (reg2 & 0x80000000) != (sum & 0x80000000));
605
606 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
607 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
608 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
609 }
610
611 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
612 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
613 "sub"
614 *am33
615 {
616 int srcreg, dstreg;
617
618 PC = cia;
619
620 if (RM2 > 7 && RM2 < 12)
621 srcreg = REG_A0 + RM2 - 8;
622 else if (RM2 > 11 && RM2 < 16)
623 srcreg = REG_D0 + RM2 - 12;
624 else
625 srcreg = REG_E0 + RM2;
626
627 if (RN0 > 7 && RN0 < 12)
628 dstreg = REG_A0 + RN0 - 8;
629 else if (RN0 > 11 && RN0 < 16)
630 dstreg = REG_D0 + RN0 - 12;
631 else
632 dstreg = REG_E0 + RN0;
633
634 genericSub (State.regs[srcreg], dstreg);
635 }
636
637 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
638 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
639 "subc"
640 *am33
641 {
642 int srcreg, dstreg;
643 int z, c, n, v;
644 unsigned long reg1, reg2, difference;
645
646 PC = cia;
647
648 if (RM2 > 7 && RM2 < 12)
649 srcreg = REG_A0 + RM2 - 8;
650 else if (RM2 > 11 && RM2 < 16)
651 srcreg = REG_D0 + RM2 - 12;
652 else
653 srcreg = REG_E0 + RM2;
654
655 if (RN0 > 7 && RN0 < 12)
656 dstreg = REG_A0 + RN0 - 8;
657 else if (RN0 > 11 && RN0 < 16)
658 dstreg = REG_D0 + RN0 - 12;
659 else
660 dstreg = REG_E0 + RN0;
661
662 reg1 = State.regs[srcreg];
663 reg2 = State.regs[dstreg];
664 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
665 State.regs[dstreg] = difference;
666
667 z = (difference == 0);
668 n = (difference & 0x80000000);
669 c = (reg1 > reg2);
670 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
671 && (reg2 & 0x80000000) != (difference & 0x80000000));
672
673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
675 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
676 }
677
678 // 1111 1001 1011 1000 Rn Rn; inc Rn
679 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
680 "inc"
681 *am33
682 {
683 int dstreg;
684
685 PC = cia;
686
687 if (RN0 > 7 && RN0 < 12)
688 dstreg = REG_A0 + RN0 - 8;
689 else if (RN0 > 11 && RN0 < 16)
690 dstreg = REG_D0 + RN0 - 12;
691 else
692 dstreg = REG_E0 + RN0;
693
694 genericAdd (1, dstreg);
695 }
696
697 // 1111 1001 1101 1000 Rn Rn; inc Rn
698 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
699 "inc4"
700 *am33
701 {
702 int dstreg;
703
704 PC = cia;
705
706 if (RN0 > 7 && RN0 < 12)
707 dstreg = REG_A0 + RN0 - 8;
708 else if (RN0 > 11 && RN0 < 16)
709 dstreg = REG_D0 + RN0 - 12;
710 else
711 dstreg = REG_E0 + RN0;
712 State.regs[dstreg] += 4;
713 }
714
715 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
716 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
717 "cmp"
718 *am33
719 {
720 int srcreg1, srcreg2;
721
722 PC = cia;
723
724 if (RN0 > 7 && RN0 < 12)
725 srcreg1 = REG_A0 + RN0 - 8;
726 else if (RN0 > 11 && RN0 < 16)
727 srcreg1 = REG_D0 + RN0 - 12;
728 else
729 srcreg1 = REG_E0 + RN0;
730
731 if (RM2 > 7 && RM2 < 12)
732 srcreg2 = REG_A0 + RM2 - 8;
733 else if (RM2 > 11 && RM2 < 16)
734 srcreg2 = REG_D0 + RM2 - 12;
735 else
736 srcreg2 = REG_E0 + RM2;
737 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
738 }
739
740 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
741 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
742 "mov"
743 *am33
744 {
745 int srcreg, dstreg;
746
747 PC = cia;
748 if (RN0 > 7 && RN0 < 12)
749 dstreg = REG_A0 + RN0 - 8;
750 else if (RN0 > 11 && RN0 < 16)
751 dstreg = REG_D0 + RN0 - 12;
752 else
753 dstreg = REG_E0 + RN0;
754
755 if (XRM2 == 0)
756 {
757 State.regs[dstreg] = State.regs[REG_SP];
758 }
759 else
760 abort ();
761 }
762
763 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
764 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
765 "mov"
766 *am33
767 {
768 int srcreg;
769
770 PC = cia;
771
772 if (RM2 > 7 && RM2 < 12)
773 srcreg = REG_A0 + RM2 - 8;
774 else if (RM2 > 11 && RM2 < 16)
775 srcreg = REG_D0 + RM2 - 12;
776 else
777 srcreg = REG_E0 + RM2;
778
779 if (XRN0 == 0)
780 {
781 State.regs[REG_SP] = State.regs[srcreg];
782 }
783 else
784 abort ();
785 }
786
787 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
788 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
789 "and"
790 *am33
791 {
792 int srcreg, dstreg;
793 int z, n;
794
795 PC = cia;
796
797 if (RM2 > 7 && RM2 < 12)
798 srcreg = REG_A0 + RM2 - 8;
799 else if (RM2 > 11 && RM2 < 16)
800 srcreg = REG_D0 + RM2 - 12;
801 else
802 srcreg = REG_E0 + RM2;
803
804 if (RN0 > 7 && RN0 < 12)
805 dstreg = REG_A0 + RN0 - 8;
806 else if (RN0 > 11 && RN0 < 16)
807 dstreg = REG_D0 + RN0 - 12;
808 else
809 dstreg = REG_E0 + RN0;
810
811 State.regs[dstreg] &= State.regs[srcreg];
812 z = (State.regs[dstreg] == 0);
813 n = (State.regs[dstreg] & 0x80000000) != 0;
814 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
816 }
817
818 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
819 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
820 "or"
821 *am33
822 {
823 int srcreg, dstreg;
824 int z, n;
825
826 PC = cia;
827
828 if (RM2 > 7 && RM2 < 12)
829 srcreg = REG_A0 + RM2 - 8;
830 else if (RM2 > 11 && RM2 < 16)
831 srcreg = REG_D0 + RM2 - 12;
832 else
833 srcreg = REG_E0 + RM2;
834
835 if (RN0 > 7 && RN0 < 12)
836 dstreg = REG_A0 + RN0 - 8;
837 else if (RN0 > 11 && RN0 < 16)
838 dstreg = REG_D0 + RN0 - 12;
839 else
840 dstreg = REG_E0 + RN0;
841
842 State.regs[dstreg] |= State.regs[srcreg];
843 z = (State.regs[dstreg] == 0);
844 n = (State.regs[dstreg] & 0x80000000) != 0;
845 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
846 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
847 }
848
849 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
850 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
851 "xor"
852 *am33
853 {
854 int srcreg, dstreg;
855 int z, n;
856
857 PC = cia;
858
859 if (RM2 > 7 && RM2 < 12)
860 srcreg = REG_A0 + RM2 - 8;
861 else if (RM2 > 11 && RM2 < 16)
862 srcreg = REG_D0 + RM2 - 12;
863 else
864 srcreg = REG_E0 + RM2;
865
866 if (RN0 > 7 && RN0 < 12)
867 dstreg = REG_A0 + RN0 - 8;
868 else if (RN0 > 11 && RN0 < 16)
869 dstreg = REG_D0 + RN0 - 12;
870 else
871 dstreg = REG_E0 + RN0;
872
873 State.regs[dstreg] ^= State.regs[srcreg];
874 z = (State.regs[dstreg] == 0);
875 n = (State.regs[dstreg] & 0x80000000) != 0;
876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
878 }
879
880 // 1111 1001 0011 1001 Rn Rn; not Rn
881 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
882 "not"
883 *am33
884 {
885 int dstreg;
886 int z, n;
887
888 PC = cia;
889
890 if (RN0 > 7 && RN0 < 12)
891 dstreg = REG_A0 + RN0 - 8;
892 else if (RN0 > 11 && RN0 < 16)
893 dstreg = REG_D0 + RN0 - 12;
894 else
895 dstreg = REG_E0 + RN0;
896
897 State.regs[dstreg] = ~State.regs[dstreg];
898 z = (State.regs[dstreg] == 0);
899 n = (State.regs[dstreg] & 0x80000000) != 0;
900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
902 }
903
904 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
905 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
906 "asr"
907 *am33
908 {
909 int srcreg, dstreg;
910 long temp;
911 int c, z, n;
912
913 PC = cia;
914
915 if (RM2 > 7 && RM2 < 12)
916 srcreg = REG_A0 + RM2 - 8;
917 else if (RM2 > 11 && RM2 < 16)
918 srcreg = REG_D0 + RM2 - 12;
919 else
920 srcreg = REG_E0 + RM2;
921
922 if (RN0 > 7 && RN0 < 12)
923 dstreg = REG_A0 + RN0 - 8;
924 else if (RN0 > 11 && RN0 < 16)
925 dstreg = REG_D0 + RN0 - 12;
926 else
927 dstreg = REG_E0 + RN0;
928
929 temp = State.regs[dstreg];
930 c = temp & 1;
931 temp >>= State.regs[srcreg];
932 State.regs[dstreg] = temp;
933 z = (State.regs[dstreg] == 0);
934 n = (State.regs[dstreg] & 0x80000000) != 0;
935 PSW &= ~(PSW_Z | PSW_N | PSW_C);
936 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
937 }
938
939 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
940 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
941 "lsr"
942 *am33
943 {
944 int srcreg, dstreg;
945 int z, n, c;
946
947 PC = cia;
948
949 if (RM2 > 7 && RM2 < 12)
950 srcreg = REG_A0 + RM2 - 8;
951 else if (RM2 > 11 && RM2 < 16)
952 srcreg = REG_D0 + RM2 - 12;
953 else
954 srcreg = REG_E0 + RM2;
955
956 if (RN0 > 7 && RN0 < 12)
957 dstreg = REG_A0 + RN0 - 8;
958 else if (RN0 > 11 && RN0 < 16)
959 dstreg = REG_D0 + RN0 - 12;
960 else
961 dstreg = REG_E0 + RN0;
962
963 c = State.regs[dstreg] & 1;
964 State.regs[dstreg] >>= State.regs[srcreg];
965 z = (State.regs[dstreg] == 0);
966 n = (State.regs[dstreg] & 0x80000000) != 0;
967 PSW &= ~(PSW_Z | PSW_N | PSW_C);
968 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
969 }
970
971 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
972 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
973 "asl"
974 *am33
975 {
976 int srcreg, dstreg;
977 int z, n;
978
979 PC = cia;
980
981 if (RM2 > 7 && RM2 < 12)
982 srcreg = REG_A0 + RM2 - 8;
983 else if (RM2 > 11 && RM2 < 16)
984 srcreg = REG_D0 + RM2 - 12;
985 else
986 srcreg = REG_E0 + RM2;
987
988 if (RN0 > 7 && RN0 < 12)
989 dstreg = REG_A0 + RN0 - 8;
990 else if (RN0 > 11 && RN0 < 16)
991 dstreg = REG_D0 + RN0 - 12;
992 else
993 dstreg = REG_E0 + RN0;
994
995 State.regs[dstreg] <<= State.regs[srcreg];
996 z = (State.regs[dstreg] == 0);
997 n = (State.regs[dstreg] & 0x80000000) != 0;
998 PSW &= ~(PSW_Z | PSW_N);
999 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1000 }
1001
1002 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
1003 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
1004 "asl2"
1005 *am33
1006 {
1007 int dstreg;
1008 int n, z;
1009
1010 PC = cia;
1011
1012 if (RN0 > 7 && RN0 < 12)
1013 dstreg = REG_A0 + RN0 - 8;
1014 else if (RN0 > 11 && RN0 < 16)
1015 dstreg = REG_D0 + RN0 - 12;
1016 else
1017 dstreg = REG_E0 + RN0;
1018
1019 State.regs[dstreg] <<= 2;
1020 z = (State.regs[dstreg] == 0);
1021 n = (State.regs[dstreg] & 0x80000000) != 0;
1022 PSW &= ~(PSW_Z | PSW_N);
1023 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1024 }
1025
1026 // 1111 1001 1000 1001 Rn Rn; ror Rn
1027 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
1028 "ror"
1029 *am33
1030 {
1031 int dstreg;
1032 int c, n, z;
1033 unsigned long value;
1034
1035 PC = cia;
1036
1037 if (RN0 > 7 && RN0 < 12)
1038 dstreg = REG_A0 + RN0 - 8;
1039 else if (RN0 > 11 && RN0 < 16)
1040 dstreg = REG_D0 + RN0 - 12;
1041 else
1042 dstreg = REG_E0 + RN0;
1043
1044 value = State.regs[dstreg];
1045 c = (value & 0x1);
1046
1047 value >>= 1;
1048 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1049 State.regs[dstreg] = value;
1050 z = (value == 0);
1051 n = (value & 0x80000000) != 0;
1052 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1053 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1054 }
1055
1056 // 1111 1001 1001 1001 Rn Rn; rol Rn
1057 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
1058 "rol"
1059 *am33
1060 {
1061 int dstreg;
1062 int c, n, z;
1063 unsigned long value;
1064
1065 PC = cia;
1066
1067 if (RN0 > 7 && RN0 < 12)
1068 dstreg = REG_A0 + RN0 - 8;
1069 else if (RN0 > 11 && RN0 < 16)
1070 dstreg = REG_D0 + RN0 - 12;
1071 else
1072 dstreg = REG_E0 + RN0;
1073
1074 value = State.regs[dstreg];
1075 c = (value & 0x80000000) ? 1 : 0;
1076
1077 value <<= 1;
1078 value |= ((PSW & PSW_C) != 0);
1079 State.regs[dstreg] = value;
1080 z = (value == 0);
1081 n = (value & 0x80000000) != 0;
1082 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1083 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1084 }
1085
1086 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
1087 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
1088 "mul"
1089 *am33
1090 {
1091 int srcreg, dstreg;
1092 unsigned long long temp;
1093 int n, z;
1094
1095 PC = cia;
1096
1097 if (RM2 > 7 && RM2 < 12)
1098 srcreg = REG_A0 + RM2 - 8;
1099 else if (RM2 > 11 && RM2 < 16)
1100 srcreg = REG_D0 + RM2 - 12;
1101 else
1102 srcreg = REG_E0 + RM2;
1103
1104 if (RN0 > 7 && RN0 < 12)
1105 dstreg = REG_A0 + RN0 - 8;
1106 else if (RN0 > 11 && RN0 < 16)
1107 dstreg = REG_D0 + RN0 - 12;
1108 else
1109 dstreg = REG_E0 + RN0;
1110
1111 temp = ((signed64)(signed32)State.regs[dstreg]
1112 * (signed64)(signed32)State.regs[srcreg]);
1113 State.regs[dstreg] = temp & 0xffffffff;
1114 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1115 z = (State.regs[dstreg] == 0);
1116 n = (State.regs[dstreg] & 0x80000000) != 0;
1117 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1118 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1119 }
1120
1121 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
1122 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
1123 "mulu"
1124 *am33
1125 {
1126 int srcreg, dstreg;
1127 unsigned long long temp;
1128 int n, z;
1129
1130 PC = cia;
1131
1132 if (RM2 > 7 && RM2 < 12)
1133 srcreg = REG_A0 + RM2 - 8;
1134 else if (RM2 > 11 && RM2 < 16)
1135 srcreg = REG_D0 + RM2 - 12;
1136 else
1137 srcreg = REG_E0 + RM2;
1138
1139 if (RN0 > 7 && RN0 < 12)
1140 dstreg = REG_A0 + RN0 - 8;
1141 else if (RN0 > 11 && RN0 < 16)
1142 dstreg = REG_D0 + RN0 - 12;
1143 else
1144 dstreg = REG_E0 + RN0;
1145
1146 temp = ((unsigned64)State.regs[dstreg]
1147 * (unsigned64)State.regs[srcreg]);
1148 State.regs[dstreg] = temp & 0xffffffff;
1149 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1150 z = (State.regs[dstreg] == 0);
1151 n = (State.regs[dstreg] & 0x80000000) != 0;
1152 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1154 }
1155
1156 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
1157 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
1158 "div"
1159 *am33
1160 {
1161 int srcreg, dstreg;
1162 long long temp;
1163 int n, z;
1164
1165 PC = cia;
1166
1167 if (RM2 > 7 && RM2 < 12)
1168 srcreg = REG_A0 + RM2 - 8;
1169 else if (RM2 > 11 && RM2 < 16)
1170 srcreg = REG_D0 + RM2 - 12;
1171 else
1172 srcreg = REG_E0 + RM2;
1173
1174 if (RN0 > 7 && RN0 < 12)
1175 dstreg = REG_A0 + RN0 - 8;
1176 else if (RN0 > 11 && RN0 < 16)
1177 dstreg = REG_D0 + RN0 - 12;
1178 else
1179 dstreg = REG_E0 + RN0;
1180
1181 temp = State.regs[REG_MDR];
1182 temp <<= 32;
1183 temp |= State.regs[dstreg];
1184 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
1185 temp /= (long)State.regs[srcreg];
1186 State.regs[dstreg] = temp & 0xffffffff;
1187 z = (State.regs[dstreg] == 0);
1188 n = (State.regs[dstreg] & 0x80000000) != 0;
1189 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1190 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1191 }
1192
1193 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
1194 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
1195 "divu"
1196 *am33
1197 {
1198 int srcreg, dstreg;
1199 unsigned long long temp;
1200 int n, z;
1201
1202 PC = cia;
1203
1204 if (RM2 > 7 && RM2 < 12)
1205 srcreg = REG_A0 + RM2 - 8;
1206 else if (RM2 > 11 && RM2 < 16)
1207 srcreg = REG_D0 + RM2 - 12;
1208 else
1209 srcreg = REG_E0 + RM2;
1210
1211 if (RN0 > 7 && RN0 < 12)
1212 dstreg = REG_A0 + RN0 - 8;
1213 else if (RN0 > 11 && RN0 < 16)
1214 dstreg = REG_D0 + RN0 - 12;
1215 else
1216 dstreg = REG_E0 + RN0;
1217
1218 temp = State.regs[REG_MDR];
1219 temp <<= 32;
1220 temp |= State.regs[dstreg];
1221 State.regs[REG_MDR] = temp % State.regs[srcreg];
1222 temp /= State.regs[srcreg];
1223 State.regs[dstreg] = temp & 0xffffffff;
1224 z = (State.regs[dstreg] == 0);
1225 n = (State.regs[dstreg] & 0x80000000) != 0;
1226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1227 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1228 }
1229
1230
1231 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
1232 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
1233 "mov"
1234 *am33
1235 {
1236 int srcreg, dstreg;
1237
1238 PC = cia;
1239
1240 if (RM0 > 7 && RM0 < 12)
1241 srcreg = REG_A0 + RM0 - 8;
1242 else if (RM0 > 11 && RM0 < 16)
1243 srcreg = REG_D0 + RM0 - 12;
1244 else
1245 srcreg = REG_E0 + RM0;
1246
1247 if (RN2 > 7 && RN2 < 12)
1248 dstreg = REG_A0 + RN2 - 8;
1249 else if (RN2 > 11 && RN2 < 16)
1250 dstreg = REG_D0 + RN2 - 12;
1251 else
1252 dstreg = REG_E0 + RN2;
1253
1254 State.regs[dstreg] = load_word (State.regs[srcreg]);
1255 }
1256
1257 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
1258 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
1259 "mov"
1260 *am33
1261 {
1262 int srcreg, dstreg;
1263
1264 PC = cia;
1265
1266 if (RM2 > 7 && RM2 < 12)
1267 srcreg = REG_A0 + RM2 - 8;
1268 else if (RM2 > 11 && RM2 < 16)
1269 srcreg = REG_D0 + RM2 - 12;
1270 else
1271 srcreg = REG_E0 + RM2;
1272
1273 if (RN0 > 7 && RN0 < 12)
1274 dstreg = REG_A0 + RN0 - 8;
1275 else if (RN0 > 11 && RN0 < 16)
1276 dstreg = REG_D0 + RN0 - 12;
1277 else
1278 dstreg = REG_E0 + RN0;
1279
1280 store_word (State.regs[dstreg], State.regs[srcreg]);
1281 }
1282
1283 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
1284 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
1285 "movbu"
1286 *am33
1287 {
1288 int srcreg, dstreg;
1289
1290 PC = cia;
1291
1292 if (RM0 > 7 && RM0 < 12)
1293 srcreg = REG_A0 + RM0 - 8;
1294 else if (RM0 > 11 && RM0 < 16)
1295 srcreg = REG_D0 + RM0 - 12;
1296 else
1297 srcreg = REG_E0 + RM0;
1298
1299 if (RN2 > 7 && RN2 < 12)
1300 dstreg = REG_A0 + RN2 - 8;
1301 else if (RN2 > 11 && RN2 < 16)
1302 dstreg = REG_D0 + RN2 - 12;
1303 else
1304 dstreg = REG_E0 + RN2;
1305
1306 State.regs[dstreg] = load_byte (State.regs[srcreg]);
1307 }
1308
1309 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
1310 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
1311 "movbu"
1312 *am33
1313 {
1314 int srcreg, dstreg;
1315
1316 PC = cia;
1317
1318 if (RM2 > 7 && RM2 < 12)
1319 srcreg = REG_A0 + RM2 - 8;
1320 else if (RM2 > 11 && RM2 < 16)
1321 srcreg = REG_D0 + RM2 - 12;
1322 else
1323 srcreg = REG_E0 + RM2;
1324
1325 if (RN0 > 7 && RN0 < 12)
1326 dstreg = REG_A0 + RN0 - 8;
1327 else if (RN0 > 11 && RN0 < 16)
1328 dstreg = REG_D0 + RN0 - 12;
1329 else
1330 dstreg = REG_E0 + RN0;
1331
1332 store_byte (State.regs[dstreg], State.regs[srcreg]);
1333 }
1334
1335 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
1336 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
1337 "movhu"
1338 *am33
1339 {
1340 int srcreg, dstreg;
1341
1342 PC = cia;
1343
1344 if (RM0 > 7 && RM0 < 12)
1345 srcreg = REG_A0 + RM0 - 8;
1346 else if (RM0 > 11 && RM0 < 16)
1347 srcreg = REG_D0 + RM0 - 12;
1348 else
1349 srcreg = REG_E0 + RM0;
1350
1351 if (RN2 > 7 && RN2 < 12)
1352 dstreg = REG_A0 + RN2 - 8;
1353 else if (RN2 > 11 && RN2 < 16)
1354 dstreg = REG_D0 + RN2 - 12;
1355 else
1356 dstreg = REG_E0 + RN2;
1357
1358 State.regs[dstreg] = load_half (State.regs[srcreg]);
1359 }
1360
1361 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1362 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1363 "movhu"
1364 *am33
1365 {
1366 int srcreg, dstreg;
1367
1368 PC = cia;
1369
1370 if (RM2 > 7 && RM2 < 12)
1371 srcreg = REG_A0 + RM2 - 8;
1372 else if (RM2 > 11 && RM2 < 16)
1373 srcreg = REG_D0 + RM2 - 12;
1374 else
1375 srcreg = REG_E0 + RM2;
1376
1377 if (RN0 > 7 && RN0 < 12)
1378 dstreg = REG_A0 + RN0 - 8;
1379 else if (RN0 > 11 && RN0 < 16)
1380 dstreg = REG_D0 + RN0 - 12;
1381 else
1382 dstreg = REG_E0 + RN0;
1383
1384 store_half (State.regs[dstreg], State.regs[srcreg]);
1385 }
1386
1387 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1388 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1389 "mov"
1390 *am33
1391 {
1392 int srcreg, dstreg;
1393
1394 PC = cia;
1395
1396 if (RM0 > 7 && RM0 < 12)
1397 srcreg = REG_A0 + RM0 - 8;
1398 else if (RM0 > 11 && RM0 < 16)
1399 srcreg = REG_D0 + RM0 - 12;
1400 else
1401 srcreg = REG_E0 + RM0;
1402
1403 if (RN2 > 7 && RN2 < 12)
1404 dstreg = REG_A0 + RN2 - 8;
1405 else if (RN2 > 11 && RN2 < 16)
1406 dstreg = REG_D0 + RN2 - 12;
1407 else
1408 dstreg = REG_E0 + RN2;
1409
1410 State.regs[dstreg] = load_word (State.regs[srcreg]);
1411 State.regs[srcreg] += 4;
1412 }
1413
1414 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1415 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1416 "mov"
1417 *am33
1418 {
1419 int srcreg, dstreg;
1420
1421 PC = cia;
1422
1423 if (RM2 > 7 && RM2 < 12)
1424 srcreg = REG_A0 + RM2 - 8;
1425 else if (RM2 > 11 && RM2 < 16)
1426 srcreg = REG_D0 + RM2 - 12;
1427 else
1428 srcreg = REG_E0 + RM2;
1429
1430 if (RN0 > 7 && RN0 < 12)
1431 dstreg = REG_A0 + RN0 - 8;
1432 else if (RN0 > 11 && RN0 < 16)
1433 dstreg = REG_D0 + RN0 - 12;
1434 else
1435 dstreg = REG_E0 + RN0;
1436
1437 store_word (State.regs[dstreg], State.regs[srcreg]);
1438 State.regs[dstreg] += 4;
1439 }
1440
1441 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1442 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1443 "mov"
1444 *am33
1445 {
1446 int srcreg, dstreg;
1447
1448 PC = cia;
1449
1450 if (RN2 > 7 && RN2 < 12)
1451 dstreg = REG_A0 + RN2 - 8;
1452 else if (RN2 > 11 && RN2 < 16)
1453 dstreg = REG_D0 + RN2 - 12;
1454 else
1455 dstreg = REG_E0 + RN2;
1456
1457 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1458 }
1459
1460 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1461 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1462 "mov"
1463 *am33
1464 {
1465 int srcreg, dstreg;
1466
1467 PC = cia;
1468
1469 if (RM2 > 7 && RM2 < 12)
1470 dstreg = REG_A0 + RM2 - 8;
1471 else if (RM2 > 11 && RM2 < 16)
1472 dstreg = REG_D0 + RM2 - 12;
1473 else
1474 dstreg = REG_E0 + RM2;
1475
1476 store_word (State.regs[REG_SP], State.regs[dstreg]);
1477 }
1478
1479 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1480 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1481 "movbu"
1482 *am33
1483 {
1484 int srcreg, dstreg;
1485
1486 PC = cia;
1487
1488 if (RN2 > 7 && RN2 < 12)
1489 dstreg = REG_A0 + RN2 - 8;
1490 else if (RN2 > 11 && RN2 < 16)
1491 dstreg = REG_D0 + RN2 - 12;
1492 else
1493 dstreg = REG_E0 + RN2;
1494
1495 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1496 }
1497
1498 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1499 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1500 "movbu"
1501 *am33
1502 {
1503 int srcreg, dstreg;
1504
1505 PC = cia;
1506
1507 if (RM2 > 7 && RM2 < 12)
1508 dstreg = REG_A0 + RM2 - 8;
1509 else if (RM2 > 11 && RM2 < 16)
1510 dstreg = REG_D0 + RM2 - 12;
1511 else
1512 dstreg = REG_E0 + RM2;
1513
1514 store_byte (State.regs[REG_SP], State.regs[dstreg]);
1515 }
1516
1517 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1518 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1519 "movhu"
1520 *am33
1521 {
1522 int srcreg, dstreg;
1523
1524 PC = cia;
1525
1526 if (RN2 > 7 && RN2 < 12)
1527 dstreg = REG_A0 + RN2 - 8;
1528 else if (RN2 > 11 && RN2 < 16)
1529 dstreg = REG_D0 + RN2 - 12;
1530 else
1531 dstreg = REG_E0 + RN2;
1532
1533 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1534 }
1535
1536 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1537 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1538 "movhu"
1539 *am33
1540 {
1541 int srcreg, dstreg;
1542
1543 PC = cia;
1544
1545 if (RM2 > 7 && RM2 < 12)
1546 dstreg = REG_A0 + RM2 - 8;
1547 else if (RM2 > 11 && RM2 < 16)
1548 dstreg = REG_D0 + RM2 - 12;
1549 else
1550 dstreg = REG_E0 + RM2;
1551
1552 store_half (State.regs[REG_SP], State.regs[dstreg]);
1553 }
1554
1555 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1556 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1557 "movhu"
1558 *am33
1559 {
1560 int srcreg, dstreg;
1561
1562 PC = cia;
1563
1564 if (RM0 > 7 && RM0 < 12)
1565 srcreg = REG_A0 + RM0 - 8;
1566 else if (RM0 > 11 && RM0 < 16)
1567 srcreg = REG_D0 + RM0 - 12;
1568 else
1569 srcreg = REG_E0 + RM0;
1570
1571 if (RN2 > 7 && RN2 < 12)
1572 dstreg = REG_A0 + RN2 - 8;
1573 else if (RN2 > 11 && RN2 < 16)
1574 dstreg = REG_D0 + RN2 - 12;
1575 else
1576 dstreg = REG_E0 + RN2;
1577
1578 State.regs[dstreg] = load_half (State.regs[srcreg]);
1579 State.regs[srcreg] += 2;
1580 }
1581
1582 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1583 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1584 "movhu"
1585 *am33
1586 {
1587 int srcreg, dstreg;
1588
1589 PC = cia;
1590
1591 if (RM2 > 7 && RM2 < 12)
1592 srcreg = REG_A0 + RM2 - 8;
1593 else if (RM2 > 11 && RM2 < 16)
1594 srcreg = REG_D0 + RM2 - 12;
1595 else
1596 srcreg = REG_E0 + RM2;
1597
1598 if (RN0 > 7 && RN0 < 12)
1599 dstreg = REG_A0 + RN0 - 8;
1600 else if (RN0 > 11 && RN0 < 16)
1601 dstreg = REG_D0 + RN0 - 12;
1602 else
1603 dstreg = REG_E0 + RN0;
1604
1605 store_half (State.regs[dstreg], State.regs[srcreg]);
1606 State.regs[dstreg] += 2;
1607 }
1608
1609
1610 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1611 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1612 "mac"
1613 *am33
1614 {
1615 int srcreg1, srcreg2;
1616 long long temp, sum;
1617 int c, v;
1618
1619 PC = cia;
1620
1621 if (RM2 > 7 && RM2 < 12)
1622 srcreg1 = REG_A0 + RM2 - 8;
1623 else if (RM2 > 11 && RM2 < 16)
1624 srcreg1 = REG_D0 + RM2 - 12;
1625 else
1626 srcreg1 = REG_E0 + RM2;
1627
1628 if (RN0 > 7 && RN0 < 12)
1629 srcreg2 = REG_A0 + RN0 - 8;
1630 else if (RN0 > 11 && RN0 < 16)
1631 srcreg2 = REG_D0 + RN0 - 12;
1632 else
1633 srcreg2 = REG_E0 + RN0;
1634
1635 temp = ((signed64)State.regs[srcreg2]
1636 * (signed64)State.regs[srcreg1]);
1637 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1638 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1639 State.regs[REG_MCRL] = sum;
1640 temp >>= 32;
1641 temp &= 0xffffffff;
1642 sum = State.regs[REG_MCRH] + temp + c;
1643 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1644 && (temp & 0x80000000) != (sum & 0x80000000));
1645 State.regs[REG_MCRH] = sum;
1646 if (v)
1647 State.regs[REG_MCVF] = 1;
1648 }
1649
1650 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1651 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1652 "macu"
1653 *am33
1654 {
1655 int srcreg1, srcreg2;
1656 unsigned long long temp, sum;
1657 int c, v;
1658
1659 PC = cia;
1660
1661 if (RM2 > 7 && RM2 < 12)
1662 srcreg1 = REG_A0 + RM2 - 8;
1663 else if (RM2 > 11 && RM2 < 16)
1664 srcreg1 = REG_D0 + RM2 - 12;
1665 else
1666 srcreg1 = REG_E0 + RM2;
1667
1668 if (RN0 > 7 && RN0 < 12)
1669 srcreg2 = REG_A0 + RN0 - 8;
1670 else if (RN0 > 11 && RN0 < 16)
1671 srcreg2 = REG_D0 + RN0 - 12;
1672 else
1673 srcreg2 = REG_E0 + RN0;
1674
1675 temp = ((unsigned64)State.regs[srcreg2]
1676 * (unsigned64)State.regs[srcreg1]);
1677 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1678 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1679 State.regs[REG_MCRL] = sum;
1680 temp >>= 32;
1681 temp &= 0xffffffff;
1682 sum = State.regs[REG_MCRH] + temp + c;
1683 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1684 && (temp & 0x80000000) != (sum & 0x80000000));
1685 State.regs[REG_MCRH] = sum;
1686 if (v)
1687 State.regs[REG_MCVF] = 1;
1688 }
1689
1690 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1691 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1692 "macb"
1693 *am33
1694 {
1695 int srcreg1, srcreg2;
1696 long temp, sum;
1697 int v;
1698
1699 PC = cia;
1700
1701 if (RM2 > 7 && RM2 < 12)
1702 srcreg1 = REG_A0 + RM2 - 8;
1703 else if (RM2 > 11 && RM2 < 16)
1704 srcreg1 = REG_D0 + RM2 - 12;
1705 else
1706 srcreg1 = REG_E0 + RM2;
1707
1708 if (RN0 > 7 && RN0 < 12)
1709 srcreg2 = REG_A0 + RN0 - 8;
1710 else if (RN0 > 11 && RN0 < 16)
1711 srcreg2 = REG_D0 + RN0 - 12;
1712 else
1713 srcreg2 = REG_E0 + RN0;
1714
1715 temp = ((signed32)(State.regs[srcreg2] & 0xff)
1716 * (signed32)(State.regs[srcreg1] & 0xff));
1717 sum = State.regs[REG_MCRL] + temp;
1718 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1719 && (temp & 0x80000000) != (sum & 0x80000000));
1720 State.regs[REG_MCRL] = sum;
1721 if (v)
1722 State.regs[REG_MCVF] = 1;
1723 }
1724
1725 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1726 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1727 "macbu"
1728 *am33
1729 {
1730 int srcreg1, srcreg2;
1731 long long temp, sum;
1732 int v;
1733
1734 PC = cia;
1735
1736 if (RM2 > 7 && RM2 < 12)
1737 srcreg1 = REG_A0 + RM2 - 8;
1738 else if (RM2 > 11 && RM2 < 16)
1739 srcreg1 = REG_D0 + RM2 - 12;
1740 else
1741 srcreg1 = REG_E0 + RM2;
1742
1743 if (RN0 > 7 && RN0 < 12)
1744 srcreg2 = REG_A0 + RN0 - 8;
1745 else if (RN0 > 11 && RN0 < 16)
1746 srcreg2 = REG_D0 + RN0 - 12;
1747 else
1748 srcreg2 = REG_E0 + RN0;
1749
1750 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1751 * (unsigned32)(State.regs[srcreg1] & 0xff));
1752 sum = State.regs[REG_MCRL] + temp;
1753 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1754 && (temp & 0x80000000) != (sum & 0x80000000));
1755 State.regs[REG_MCRL] = sum;
1756 if (v)
1757 State.regs[REG_MCVF] = 1;
1758 }
1759
1760 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1761 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1762 "mach"
1763 *am33
1764 {
1765 int srcreg1, srcreg2;
1766 long long temp, sum;
1767 int c, v;
1768
1769 PC = cia;
1770
1771 if (RM2 > 7 && RM2 < 12)
1772 srcreg1 = REG_A0 + RM2 - 8;
1773 else if (RM2 > 11 && RM2 < 16)
1774 srcreg1 = REG_D0 + RM2 - 12;
1775 else
1776 srcreg1 = REG_E0 + RM2;
1777
1778 if (RN0 > 7 && RN0 < 12)
1779 srcreg2 = REG_A0 + RN0 - 8;
1780 else if (RN0 > 11 && RN0 < 16)
1781 srcreg2 = REG_D0 + RN0 - 12;
1782 else
1783 srcreg2 = REG_E0 + RN0;
1784
1785 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1786 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1787 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1788 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1789 State.regs[REG_MCRL] = sum;
1790 temp >>= 32;
1791 temp &= 0xffffffff;
1792 sum = State.regs[REG_MCRH] + temp + c;
1793 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1794 && (temp & 0x80000000) != (sum & 0x80000000));
1795 State.regs[REG_MCRH] = sum;
1796 if (v)
1797 State.regs[REG_MCVF] = 1;
1798 }
1799
1800 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1801 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1802 "machu"
1803 *am33
1804 {
1805 int srcreg1, srcreg2;
1806 long long temp, sum;
1807 int c, v;
1808
1809 PC = cia;
1810
1811 if (RM2 > 7 && RM2 < 12)
1812 srcreg1 = REG_A0 + RM2 - 8;
1813 else if (RM2 > 11 && RM2 < 16)
1814 srcreg1 = REG_D0 + RM2 - 12;
1815 else
1816 srcreg1 = REG_E0 + RM2;
1817
1818 if (RN0 > 7 && RN0 < 12)
1819 srcreg2 = REG_A0 + RN0 - 8;
1820 else if (RN0 > 11 && RN0 < 16)
1821 srcreg2 = REG_D0 + RN0 - 12;
1822 else
1823 srcreg2 = REG_E0 + RN0;
1824
1825 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1826 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1827 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1828 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1829 State.regs[REG_MCRL] = sum;
1830 temp >>= 32;
1831 temp &= 0xffffffff;
1832 sum = State.regs[REG_MCRH] + temp + c;
1833 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1834 && (temp & 0x80000000) != (sum & 0x80000000));
1835 State.regs[REG_MCRH] = sum;
1836 if (v)
1837 State.regs[REG_MCVF] = 1;
1838 }
1839
1840 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1841 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1842 "dmach"
1843 *am33
1844 {
1845 int srcreg1, srcreg2;
1846 long temp, temp2, sum;
1847 int v;
1848
1849 PC = cia;
1850
1851 if (RM2 > 7 && RM2 < 12)
1852 srcreg1 = REG_A0 + RM2 - 8;
1853 else if (RM2 > 11 && RM2 < 16)
1854 srcreg1 = REG_D0 + RM2 - 12;
1855 else
1856 srcreg1 = REG_E0 + RM2;
1857
1858 if (RN0 > 7 && RN0 < 12)
1859 srcreg2 = REG_A0 + RN0 - 8;
1860 else if (RN0 > 11 && RN0 < 16)
1861 srcreg2 = REG_D0 + RN0 - 12;
1862 else
1863 srcreg2 = REG_E0 + RN0;
1864
1865 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
1866 * (signed32)(State.regs[srcreg1] & 0xffff));
1867 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
1868 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
1869 sum = temp + temp2 + State.regs[REG_MCRL];
1870 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1871 && (temp & 0x80000000) != (sum & 0x80000000));
1872 State.regs[REG_MCRL] = sum;
1873 if (v)
1874 State.regs[REG_MCVF] = 1;
1875 }
1876
1877 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1878 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1879 "dmachu"
1880 *am33
1881 {
1882 int srcreg1, srcreg2;
1883 unsigned long temp, temp2, sum;
1884 int v;
1885
1886 PC = cia;
1887
1888 if (RM2 > 7 && RM2 < 12)
1889 srcreg1 = REG_A0 + RM2 - 8;
1890 else if (RM2 > 11 && RM2 < 16)
1891 srcreg1 = REG_D0 + RM2 - 12;
1892 else
1893 srcreg1 = REG_E0 + RM2;
1894
1895 if (RN0 > 7 && RN0 < 12)
1896 srcreg2 = REG_A0 + RN0 - 8;
1897 else if (RN0 > 11 && RN0 < 16)
1898 srcreg2 = REG_D0 + RN0 - 12;
1899 else
1900 srcreg2 = REG_E0 + RN0;
1901
1902 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1903 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1904 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1905 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1906 sum = temp + temp2 + State.regs[REG_MCRL];
1907 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1908 && (temp & 0x80000000) != (sum & 0x80000000));
1909 State.regs[REG_MCRL] = sum;
1910 if (v)
1911 State.regs[REG_MCVF] = 1;
1912 }
1913
1914 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1915 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1916 "dmulh"
1917 *am33
1918 {
1919 int srcreg, dstreg;
1920 long temp;
1921
1922 PC = cia;
1923
1924 if (RM2 > 7 && RM2 < 12)
1925 srcreg = REG_A0 + RM2 - 8;
1926 else if (RM2 > 11 && RM2 < 16)
1927 srcreg = REG_D0 + RM2 - 12;
1928 else
1929 srcreg = REG_E0 + RM2;
1930
1931 if (RN0 > 7 && RN0 < 12)
1932 dstreg = REG_A0 + RN0 - 8;
1933 else if (RN0 > 11 && RN0 < 16)
1934 dstreg = REG_D0 + RN0 - 12;
1935 else
1936 dstreg = REG_E0 + RN0;
1937
1938 temp = ((signed32)(State.regs[dstreg] & 0xffff)
1939 * (signed32)(State.regs[srcreg] & 0xffff));
1940 State.regs[REG_MDRQ] = temp;
1941 temp = ((signed32)((State.regs[dstreg] >> 16) & 0xffff)
1942 * (signed32)((State.regs[srcreg] >>16) & 0xffff));
1943 State.regs[dstreg] = temp;
1944 }
1945
1946 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1947 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1948 "dmachu"
1949 *am33
1950 {
1951 int srcreg, dstreg;
1952 unsigned long temp;
1953
1954 PC = cia;
1955
1956 if (RM2 > 7 && RM2 < 12)
1957 srcreg = REG_A0 + RM2 - 8;
1958 else if (RM2 > 11 && RM2 < 16)
1959 srcreg = REG_D0 + RM2 - 12;
1960 else
1961 srcreg = REG_E0 + RM2;
1962
1963 if (RN0 > 7 && RN0 < 12)
1964 dstreg = REG_A0 + RN0 - 8;
1965 else if (RN0 > 11 && RN0 < 16)
1966 dstreg = REG_D0 + RN0 - 12;
1967 else
1968 dstreg = REG_E0 + RN0;
1969
1970 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1971 * (unsigned32)(State.regs[srcreg] & 0xffff));
1972 State.regs[REG_MDRQ] = temp;
1973 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1974 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1975 State.regs[dstreg] = temp;
1976 }
1977
1978 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1979 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1980 "sat16"
1981 *am33
1982 {
1983 int srcreg, dstreg;
1984 int value;
1985
1986 PC = cia;
1987
1988 if (RM2 > 7 && RM2 < 12)
1989 srcreg = REG_A0 + RM2 - 8;
1990 else if (RM2 > 11 && RM2 < 16)
1991 srcreg = REG_D0 + RM2 - 12;
1992 else
1993 srcreg = REG_E0 + RM2;
1994
1995 if (RN0 > 7 && RN0 < 12)
1996 dstreg = REG_A0 + RN0 - 8;
1997 else if (RN0 > 11 && RN0 < 16)
1998 dstreg = REG_D0 + RN0 - 12;
1999 else
2000 dstreg = REG_E0 + RN0;
2001
2002 value = State.regs[srcreg];
2003
2004 if (value >= 0x7fff)
2005 State.regs[dstreg] = 0x7fff;
2006 else if (value <= 0xffff8000)
2007 State.regs[dstreg] = 0xffff8000;
2008 else
2009 State.regs[dstreg] = value;
2010 }
2011
2012 // ??? mcste
2013
2014 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
2015 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
2016 "swap"
2017 *am33
2018 {
2019 int srcreg, dstreg;
2020
2021 if (RM2 > 7 && RM2 < 12)
2022 srcreg = REG_A0 + RM2 - 8;
2023 else if (RM2 > 11 && RM2 < 16)
2024 srcreg = REG_D0 + RM2 - 12;
2025 else
2026 srcreg = REG_E0 + RM2;
2027
2028 if (RN0 > 7 && RN0 < 12)
2029 dstreg = REG_A0 + RN0 - 8;
2030 else if (RN0 > 11 && RN0 < 16)
2031 dstreg = REG_D0 + RN0 - 12;
2032 else
2033 dstreg = REG_E0 + RN0;
2034
2035 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
2036 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
2037 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
2038 | ((State.regs[srcreg] >> 24) & 0xff));
2039 }
2040
2041 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
2042 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
2043 "swaph"
2044 *am33
2045 {
2046 int srcreg, dstreg;
2047
2048 if (RM2 > 7 && RM2 < 12)
2049 srcreg = REG_A0 + RM2 - 8;
2050 else if (RM2 > 11 && RM2 < 16)
2051 srcreg = REG_D0 + RM2 - 12;
2052 else
2053 srcreg = REG_E0 + RM2;
2054
2055 if (RN0 > 7 && RN0 < 12)
2056 dstreg = REG_A0 + RN0 - 8;
2057 else if (RN0 > 11 && RN0 < 16)
2058 dstreg = REG_D0 + RN0 - 12;
2059 else
2060 dstreg = REG_E0 + RN0;
2061
2062 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
2063 | ((State.regs[srcreg] >> 8) & 0xff)
2064 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
2065 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
2066 }
2067
2068 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
2069 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
2070 "swhw"
2071 *am33
2072 {
2073 int srcreg, dstreg;
2074
2075 if (RM2 > 7 && RM2 < 12)
2076 srcreg = REG_A0 + RM2 - 8;
2077 else if (RM2 > 11 && RM2 < 16)
2078 srcreg = REG_D0 + RM2 - 12;
2079 else
2080 srcreg = REG_E0 + RM2;
2081
2082 if (RN0 > 7 && RN0 < 12)
2083 dstreg = REG_A0 + RN0 - 8;
2084 else if (RN0 > 11 && RN0 < 16)
2085 dstreg = REG_D0 + RN0 - 12;
2086 else
2087 dstreg = REG_E0 + RN0;
2088
2089 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
2090 | ((State.regs[srcreg] >> 16) & 0xffff));
2091 }
2092
2093 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
2094 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
2095 "bsch"
2096 *am33
2097 {
2098 int temp, c, i;
2099 int srcreg, dstreg;
2100 int start;
2101
2102 PC = cia;
2103
2104 if (RM2 > 7 && RM2 < 12)
2105 srcreg = REG_A0 + RM2 - 8;
2106 else if (RM2 > 11 && RM2 < 16)
2107 srcreg = REG_D0 + RM2 - 12;
2108 else
2109 srcreg = REG_E0 + RM2;
2110
2111 if (RN0 > 7 && RN0 < 12)
2112 dstreg = REG_A0 + RN0 - 8;
2113 else if (RN0 > 11 && RN0 < 16)
2114 dstreg = REG_D0 + RN0 - 12;
2115 else
2116 dstreg = REG_E0 + RN0;
2117
2118 temp = State.regs[srcreg];
2119 start = (State.regs[dstreg] & 0x1f) - 1;
2120 if (start == -1)
2121 start = 31;
2122
2123 for (i = start; i >= 0; i--)
2124 {
2125 if (temp & (1 << i))
2126 {
2127 c = 1;
2128 State.regs[dstreg] = i;
2129 break;
2130 }
2131 }
2132
2133 if (i < 0)
2134 {
2135 c = 0;
2136 State.regs[dstreg] = 0;
2137 }
2138 PSW &= ~(PSW_C);
2139 PSW |= (c ? PSW_C : 0);
2140 }
2141
2142
2143 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
2144 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
2145 "mov"
2146 *am33
2147 {
2148 int dstreg;
2149
2150 PC = cia;
2151
2152 if (RN0 > 7 && RN0 < 12)
2153 dstreg = REG_A0 + RN0 - 8;
2154 else if (RN0 > 11 && RN0 < 16)
2155 dstreg = REG_D0 + RN0 - 12;
2156 else
2157 dstreg = REG_E0 + RN0;
2158
2159 State.regs[dstreg] = EXTEND8 (IMM8);
2160 }
2161
2162 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
2163 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
2164 "movu"
2165 *am33
2166 {
2167 int dstreg;
2168
2169 PC = cia;
2170
2171 if (RN0 > 7 && RN0 < 12)
2172 dstreg = REG_A0 + RN0 - 8;
2173 else if (RN0 > 11 && RN0 < 16)
2174 dstreg = REG_D0 + RN0 - 12;
2175 else
2176 dstreg = REG_E0 + RN0;
2177
2178 State.regs[dstreg] = IMM8 & 0xff;
2179 }
2180
2181 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
2182 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
2183 "add"
2184 *am33
2185 {
2186 int dstreg;
2187
2188 PC = cia;
2189
2190 if (RN0 > 7 && RN0 < 12)
2191 dstreg = REG_A0 + RN0 - 8;
2192 else if (RN0 > 11 && RN0 < 16)
2193 dstreg = REG_D0 + RN0 - 12;
2194 else
2195 dstreg = REG_E0 + RN0;
2196
2197 genericAdd (EXTEND8 (IMM8), dstreg);
2198 }
2199
2200 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
2201 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
2202 "addc"
2203 *am33
2204 {
2205 int dstreg, imm;
2206 int z, c, n, v;
2207 unsigned long reg1, reg2, sum;
2208
2209 PC = cia;
2210
2211 if (RN0 > 7 && RN0 < 12)
2212 dstreg = REG_A0 + RN0 - 8;
2213 else if (RN0 > 11 && RN0 < 16)
2214 dstreg = REG_D0 + RN0 - 12;
2215 else
2216 dstreg = REG_E0 + RN0;
2217
2218 imm = EXTEND8 (IMM8);
2219 reg2 = State.regs[dstreg];
2220 sum = imm + reg2 + ((PSW & PSW_C) != 0);
2221 State.regs[dstreg] = sum;
2222
2223 z = (sum == 0);
2224 n = (sum & 0x80000000);
2225 c = (sum < imm) || (sum < reg2);
2226 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2227 && (reg2 & 0x80000000) != (sum & 0x80000000));
2228
2229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2230 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2231 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2232 }
2233
2234 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
2235 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
2236 "sub"
2237 *am33
2238 {
2239 int dstreg;
2240
2241 PC = cia;
2242
2243 if (RN0 > 7 && RN0 < 12)
2244 dstreg = REG_A0 + RN0 - 8;
2245 else if (RN0 > 11 && RN0 < 16)
2246 dstreg = REG_D0 + RN0 - 12;
2247 else
2248 dstreg = REG_E0 + RN0;
2249
2250 genericSub (EXTEND8 (IMM8), dstreg);
2251 }
2252
2253 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
2254 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
2255 "subc"
2256 *am33
2257 {
2258 int imm, dstreg;
2259 int z, c, n, v;
2260 unsigned long reg1, reg2, difference;
2261
2262 PC = cia;
2263
2264 if (RN0 > 7 && RN0 < 12)
2265 dstreg = REG_A0 + RN0 - 8;
2266 else if (RN0 > 11 && RN0 < 16)
2267 dstreg = REG_D0 + RN0 - 12;
2268 else
2269 dstreg = REG_E0 + RN0;
2270
2271 imm = EXTEND8 (IMM8);
2272 reg2 = State.regs[dstreg];
2273 difference = reg2 - imm - ((PSW & PSW_C) != 0);
2274 State.regs[dstreg] = difference;
2275
2276 z = (difference == 0);
2277 n = (difference & 0x80000000);
2278 c = (imm > reg2);
2279 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2280 && (reg2 & 0x80000000) != (difference & 0x80000000));
2281
2282 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2283 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2284 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2285 }
2286
2287 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
2288 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
2289 "cmp"
2290 *am33
2291 {
2292 int srcreg;
2293
2294 PC = cia;
2295
2296 if (RN0 > 7 && RN0 < 12)
2297 srcreg = REG_A0 + RN0 - 8;
2298 else if (RN0 > 11 && RN0 < 16)
2299 srcreg = REG_D0 + RN0 - 12;
2300 else
2301 srcreg = REG_E0 + RN0;
2302
2303 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
2304 }
2305
2306 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
2307 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
2308 "mov"
2309 *am33
2310 {
2311 int dstreg;
2312
2313 PC = cia;
2314
2315 if (XRN0 == 0)
2316 State.regs[REG_SP] = EXTEND8 (IMM8);
2317 else
2318 abort ();
2319 }
2320
2321 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
2322 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
2323 "and"
2324 *am33
2325 {
2326 int dstreg;
2327 int z, n;
2328
2329 PC = cia;
2330
2331 if (RN0 > 7 && RN0 < 12)
2332 dstreg = REG_A0 + RN0 - 8;
2333 else if (RN0 > 11 && RN0 < 16)
2334 dstreg = REG_D0 + RN0 - 12;
2335 else
2336 dstreg = REG_E0 + RN0;
2337
2338 State.regs[dstreg] &= (IMM8 & 0xff);
2339 z = (State.regs[dstreg] == 0);
2340 n = (State.regs[dstreg] & 0x80000000) != 0;
2341 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2342 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2343 }
2344
2345 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
2346 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
2347 "or"
2348 *am33
2349 {
2350 int dstreg;
2351 int z, n;
2352
2353 PC = cia;
2354
2355 if (RN0 > 7 && RN0 < 12)
2356 dstreg = REG_A0 + RN0 - 8;
2357 else if (RN0 > 11 && RN0 < 16)
2358 dstreg = REG_D0 + RN0 - 12;
2359 else
2360 dstreg = REG_E0 + RN0;
2361
2362 State.regs[dstreg] |= (IMM8 & 0xff);
2363 z = (State.regs[dstreg] == 0);
2364 n = (State.regs[dstreg] & 0x80000000) != 0;
2365 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2366 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2367 }
2368
2369 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
2370 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
2371 "xor"
2372 *am33
2373 {
2374 int dstreg;
2375 int z, n;
2376
2377 PC = cia;
2378
2379 if (RN0 > 7 && RN0 < 12)
2380 dstreg = REG_A0 + RN0 - 8;
2381 else if (RN0 > 11 && RN0 < 16)
2382 dstreg = REG_D0 + RN0 - 12;
2383 else
2384 dstreg = REG_E0 + RN0;
2385
2386 State.regs[dstreg] ^= (IMM8 & 0xff);
2387 z = (State.regs[dstreg] == 0);
2388 n = (State.regs[dstreg] & 0x80000000) != 0;
2389 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2390 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2391 }
2392
2393 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
2394 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
2395 "asr"
2396 *am33
2397 {
2398 int dstreg;
2399 long temp;
2400 int c, z, n;
2401
2402 PC = cia;
2403
2404 if (RN0 > 7 && RN0 < 12)
2405 dstreg = REG_A0 + RN0 - 8;
2406 else if (RN0 > 11 && RN0 < 16)
2407 dstreg = REG_D0 + RN0 - 12;
2408 else
2409 dstreg = REG_E0 + RN0;
2410
2411 temp = State.regs[dstreg];
2412 c = temp & 1;
2413 temp >>= (IMM8 & 0xff);
2414 State.regs[dstreg] = temp;
2415 z = (State.regs[dstreg] == 0);
2416 n = (State.regs[dstreg] & 0x80000000) != 0;
2417 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2418 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2419 }
2420
2421 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
2422 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
2423 "lsr"
2424 *am33
2425 {
2426 int dstreg;
2427 int z, n, c;
2428
2429 PC = cia;
2430
2431 if (RN0 > 7 && RN0 < 12)
2432 dstreg = REG_A0 + RN0 - 8;
2433 else if (RN0 > 11 && RN0 < 16)
2434 dstreg = REG_D0 + RN0 - 12;
2435 else
2436 dstreg = REG_E0 + RN0;
2437
2438 c = State.regs[dstreg] & 1;
2439 State.regs[dstreg] >>= (IMM8 & 0xff);
2440 z = (State.regs[dstreg] == 0);
2441 n = (State.regs[dstreg] & 0x80000000) != 0;
2442 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2443 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2444 }
2445
2446 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
2447 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
2448 "asl"
2449 *am33
2450 {
2451 int srcreg, dstreg;
2452 int z, n;
2453
2454 PC = cia;
2455
2456 if (RN0 > 7 && RN0 < 12)
2457 dstreg = REG_A0 + RN0 - 8;
2458 else if (RN0 > 11 && RN0 < 16)
2459 dstreg = REG_D0 + RN0 - 12;
2460 else
2461 dstreg = REG_E0 + RN0;
2462
2463 State.regs[dstreg] <<= (IMM8 & 0xff);
2464 z = (State.regs[dstreg] == 0);
2465 n = (State.regs[dstreg] & 0x80000000) != 0;
2466 PSW &= ~(PSW_Z | PSW_N);
2467 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2468 }
2469
2470 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
2471 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
2472 "mul"
2473 *am33
2474 {
2475 int dstreg;
2476 unsigned long long temp;
2477 int z, n;
2478
2479 PC = cia;
2480
2481 if (RN0 > 7 && RN0 < 12)
2482 dstreg = REG_A0 + RN0 - 8;
2483 else if (RN0 > 11 && RN0 < 16)
2484 dstreg = REG_D0 + RN0 - 12;
2485 else
2486 dstreg = REG_E0 + RN0;
2487
2488 temp = ((signed64)(signed32)State.regs[dstreg]
2489 * (signed64)(signed32)EXTEND8 (IMM8));
2490 State.regs[dstreg] = temp & 0xffffffff;
2491 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
2492 z = (State.regs[dstreg] == 0);
2493 n = (State.regs[dstreg] & 0x80000000) != 0;
2494 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2495 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2496 }
2497
2498 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
2499 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
2500 "mulu"
2501 *am33
2502 {
2503 int dstreg;
2504 unsigned long long temp;
2505 int z, n;
2506
2507 PC = cia;
2508
2509 if (RN0 > 7 && RN0 < 12)
2510 dstreg = REG_A0 + RN0 - 8;
2511 else if (RN0 > 11 && RN0 < 16)
2512 dstreg = REG_D0 + RN0 - 12;
2513 else
2514 dstreg = REG_E0 + RN0;
2515
2516 temp = ((unsigned64)State.regs[dstreg]
2517 * (unsigned64)(IMM8 & 0xff));
2518 State.regs[dstreg] = temp & 0xffffffff;
2519 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
2520 z = (State.regs[dstreg] == 0);
2521 n = (State.regs[dstreg] & 0x80000000) != 0;
2522 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2523 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2524 }
2525
2526 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
2527 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
2528 "btst"
2529 *am33
2530 {
2531 int srcreg;
2532
2533 PC = cia;
2534
2535 if (RM0 > 7 && RM0 < 12)
2536 srcreg = REG_A0 + RM0 - 8;
2537 else if (RM0 > 11 && RM0 < 16)
2538 srcreg = REG_D0 + RM0 - 12;
2539 else
2540 srcreg = REG_E0 + RM0;
2541
2542 genericBtst(IMM8, State.regs[srcreg]);
2543
2544 }
2545
2546
2547 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
2548 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
2549 "mov"
2550 *am33
2551 {
2552 int srcreg, dstreg;
2553
2554 PC = cia;
2555
2556 if (RM0 > 7 && RM0 < 12)
2557 srcreg = REG_A0 + RM0 - 8;
2558 else if (RM0 > 11 && RM0 < 16)
2559 srcreg = REG_D0 + RM0 - 12;
2560 else
2561 srcreg = REG_E0 + RM0;
2562
2563 if (RN2 > 7 && RN2 < 12)
2564 dstreg = REG_A0 + RN2 - 8;
2565 else if (RN2 > 11 && RN2 < 16)
2566 dstreg = REG_D0 + RN2 - 12;
2567 else
2568 dstreg = REG_E0 + RN2;
2569
2570 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
2571 }
2572
2573 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
2574 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
2575 "mov"
2576 {
2577 int srcreg, dstreg;
2578
2579 PC = cia;
2580
2581 if (RM2 > 7 && RM2 < 12)
2582 srcreg = REG_A0 + RM2 - 8;
2583 else if (RM2 > 11 && RM2 < 16)
2584 srcreg = REG_D0 + RM2 - 12;
2585 else
2586 srcreg = REG_E0 + RM2;
2587
2588 if (RN0 > 7 && RN0 < 12)
2589 dstreg = REG_A0 + RN0 - 8;
2590 else if (RN0 > 11 && RN0 < 16)
2591 dstreg = REG_D0 + RN0 - 12;
2592 else
2593 dstreg = REG_E0 + RN0;
2594
2595 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2596 }
2597
2598 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
2599 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
2600 "movbu"
2601 {
2602 int srcreg, dstreg;
2603
2604 PC = cia;
2605
2606 if (RM0 > 7 && RM0 < 12)
2607 srcreg = REG_A0 + RM0 - 8;
2608 else if (RM0 > 11 && RM0 < 16)
2609 srcreg = REG_D0 + RM0 - 12;
2610 else
2611 srcreg = REG_E0 + RM0;
2612
2613 if (RN2 > 7 && RN2 < 12)
2614 dstreg = REG_A0 + RN2 - 8;
2615 else if (RN2 > 11 && RN2 < 16)
2616 dstreg = REG_D0 + RN2 - 12;
2617 else
2618 dstreg = REG_E0 + RN2;
2619
2620 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
2621 }
2622
2623 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
2624 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
2625 "movbu"
2626 {
2627 int srcreg, dstreg;
2628
2629 PC = cia;
2630
2631 if (RM2 > 7 && RM2 < 12)
2632 srcreg = REG_A0 + RM2 - 8;
2633 else if (RM2 > 11 && RM2 < 16)
2634 srcreg = REG_D0 + RM2 - 12;
2635 else
2636 srcreg = REG_E0 + RM2;
2637
2638 if (RN0 > 7 && RN0 < 12)
2639 dstreg = REG_A0 + RN0 - 8;
2640 else if (RN0 > 11 && RN0 < 16)
2641 dstreg = REG_D0 + RN0 - 12;
2642 else
2643 dstreg = REG_E0 + RN0;
2644
2645 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2646 }
2647
2648 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
2649 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
2650 "movhu"
2651 {
2652 int srcreg, dstreg;
2653
2654 PC = cia;
2655
2656 if (RM0 > 7 && RM0 < 12)
2657 srcreg = REG_A0 + RM0 - 8;
2658 else if (RM0 > 11 && RM0 < 16)
2659 srcreg = REG_D0 + RM0 - 12;
2660 else
2661 srcreg = REG_E0 + RM0;
2662
2663 if (RN2 > 7 && RN2 < 12)
2664 dstreg = REG_A0 + RN2 - 8;
2665 else if (RN2 > 11 && RN2 < 16)
2666 dstreg = REG_D0 + RN2 - 12;
2667 else
2668 dstreg = REG_E0 + RN2;
2669
2670 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2671 }
2672
2673 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
2674 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
2675 "movhu"
2676 {
2677 int srcreg, dstreg;
2678
2679 PC = cia;
2680
2681 if (RM2 > 7 && RM2 < 12)
2682 srcreg = REG_A0 + RM2 - 8;
2683 else if (RM2 > 11 && RM2 < 16)
2684 srcreg = REG_D0 + RM2 - 12;
2685 else
2686 srcreg = REG_E0 + RM2;
2687
2688 if (RN0 > 7 && RN0 < 12)
2689 dstreg = REG_A0 + RN0 - 8;
2690 else if (RN0 > 11 && RN0 < 16)
2691 dstreg = REG_D0 + RN0 - 12;
2692 else
2693 dstreg = REG_E0 + RN0;
2694
2695 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2696 }
2697
2698 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
2699 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
2700 "mov"
2701 *am33
2702 {
2703 int srcreg, dstreg;
2704
2705 PC = cia;
2706
2707 if (RM0 > 7 && RM0 < 12)
2708 srcreg = REG_A0 + RM0 - 8;
2709 else if (RM0 > 11 && RM0 < 16)
2710 srcreg = REG_D0 + RM0 - 12;
2711 else
2712 srcreg = REG_E0 + RM0;
2713
2714 if (RN2 > 7 && RN2 < 12)
2715 dstreg = REG_A0 + RN2 - 8;
2716 else if (RN2 > 11 && RN2 < 16)
2717 dstreg = REG_D0 + RN2 - 12;
2718 else
2719 dstreg = REG_E0 + RN2;
2720
2721 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
2722 State.regs[srcreg] += 4;
2723 }
2724
2725 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
2726 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
2727 "mov"
2728 {
2729 int srcreg, dstreg;
2730
2731 PC = cia;
2732
2733 if (RM2 > 7 && RM2 < 12)
2734 srcreg = REG_A0 + RM2 - 8;
2735 else if (RM2 > 11 && RM2 < 16)
2736 srcreg = REG_D0 + RM2 - 12;
2737 else
2738 srcreg = REG_E0 + RM2;
2739
2740 if (RN0 > 7 && RN0 < 12)
2741 dstreg = REG_A0 + RN0 - 8;
2742 else if (RN0 > 11 && RN0 < 16)
2743 dstreg = REG_D0 + RN0 - 12;
2744 else
2745 dstreg = REG_E0 + RN0;
2746
2747 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2748 State.regs[dstreg] += 4;
2749 }
2750
2751
2752 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2753 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2754 "mov"
2755 {
2756 int dstreg;
2757
2758 PC = cia;
2759
2760 if (RN2 > 7 && RN2 < 12)
2761 dstreg = REG_A0 + RN2 - 8;
2762 else if (RN2 > 11 && RN2 < 16)
2763 dstreg = REG_D0 + RN2 - 12;
2764 else
2765 dstreg = REG_E0 + RN2;
2766
2767 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2768 }
2769
2770 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2771 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2772 "mov"
2773 {
2774 int srcreg;
2775
2776 PC = cia;
2777
2778 if (RM2 > 7 && RM2 < 12)
2779 srcreg = REG_A0 + RM2 - 8;
2780 else if (RM2 > 11 && RM2 < 16)
2781 srcreg = REG_D0 + RM2 - 12;
2782 else
2783 srcreg = REG_E0 + RM2;
2784
2785 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2786 }
2787
2788 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2789 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2790 "movbu"
2791 {
2792 int dstreg;
2793
2794 PC = cia;
2795
2796 if (RN2 > 7 && RN2 < 12)
2797 dstreg = REG_A0 + RN2 - 8;
2798 else if (RN2 > 11 && RN2 < 16)
2799 dstreg = REG_D0 + RN2 - 12;
2800 else
2801 dstreg = REG_E0 + RN2;
2802
2803 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2804 }
2805
2806 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2807 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2808 "movbu"
2809 {
2810 int srcreg;
2811
2812 PC = cia;
2813
2814 if (RM2 > 7 && RM2 < 12)
2815 srcreg = REG_A0 + RM2 - 8;
2816 else if (RM2 > 11 && RM2 < 16)
2817 srcreg = REG_D0 + RM2 - 12;
2818 else
2819 srcreg = REG_E0 + RM2;
2820
2821 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2822 }
2823
2824 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2825 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2826 "movhu"
2827 {
2828 int dstreg;
2829
2830 PC = cia;
2831
2832 if (RN2 > 7 && RN2 < 12)
2833 dstreg = REG_A0 + RN2 - 8;
2834 else if (RN2 > 11 && RN2 < 16)
2835 dstreg = REG_D0 + RN2 - 12;
2836 else
2837 dstreg = REG_E0 + RN2;
2838
2839 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2840 }
2841
2842 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2843 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2844 "movhu"
2845 {
2846 int srcreg;
2847
2848 PC = cia;
2849
2850 if (RM2 > 7 && RM2 < 12)
2851 srcreg = REG_A0 + RM2 - 8;
2852 else if (RM2 > 11 && RM2 < 16)
2853 srcreg = REG_D0 + RM2 - 12;
2854 else
2855 srcreg = REG_E0 + RM2;
2856
2857 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2858 }
2859
2860 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2861 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2862 "movhu"
2863 *am33
2864 {
2865 int srcreg, dstreg;
2866
2867 PC = cia;
2868
2869 if (RM0 > 7 && RM0 < 12)
2870 srcreg = REG_A0 + RM0 - 8;
2871 else if (RM0 > 11 && RM0 < 16)
2872 srcreg = REG_D0 + RM0 - 12;
2873 else
2874 srcreg = REG_E0 + RM0;
2875
2876 if (RN2 > 7 && RN2 < 12)
2877 dstreg = REG_A0 + RN2 - 8;
2878 else if (RN2 > 11 && RN2 < 16)
2879 dstreg = REG_D0 + RN2 - 12;
2880 else
2881 dstreg = REG_E0 + RN2;
2882
2883 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2884 State.regs[srcreg] += 2;
2885 }
2886
2887 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2888 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2889 "movhu"
2890 {
2891 int srcreg, dstreg;
2892
2893 PC = cia;
2894
2895 if (RM2 > 7 && RM2 < 12)
2896 srcreg = REG_A0 + RM2 - 8;
2897 else if (RM2 > 11 && RM2 < 16)
2898 srcreg = REG_D0 + RM2 - 12;
2899 else
2900 srcreg = REG_E0 + RM2;
2901
2902 if (RN0 > 7 && RN0 < 12)
2903 dstreg = REG_A0 + RN0 - 8;
2904 else if (RN0 > 11 && RN0 < 16)
2905 dstreg = REG_D0 + RN0 - 12;
2906 else
2907 dstreg = REG_E0 + RN0;
2908
2909 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2910 State.regs[dstreg] += 2;
2911 }
2912
2913
2914 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2915 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2916 "mac"
2917 {
2918 int srcreg1, srcreg2;
2919 long long temp, sum;
2920 int c, v;
2921
2922 PC = cia;
2923
2924 if (RN2 > 7 && RN2 < 12)
2925 srcreg1 = REG_A0 + RN2 - 8;
2926 else if (RN2 > 11 && RN2 < 16)
2927 srcreg1 = REG_D0 + RN2 - 12;
2928 else
2929 srcreg1 = REG_E0 + RN2;
2930
2931 temp = ((signed64)EXTEND8 (IMM8)
2932 * (signed64)State.regs[srcreg1]);
2933 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2934 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2935 State.regs[REG_MCRL] = sum;
2936 temp >>= 32;
2937 temp &= 0xffffffff;
2938 sum = State.regs[REG_MCRH] + temp + c;
2939 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2940 && (temp & 0x80000000) != (sum & 0x80000000));
2941 State.regs[REG_MCRH] = sum;
2942 if (v)
2943 State.regs[REG_MCVF] = 1;
2944 }
2945
2946 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2947 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2948 "macu"
2949 {
2950 int srcreg1, srcreg2;
2951 long long temp, sum;
2952 int c, v;
2953
2954 PC = cia;
2955
2956 if (RN2 > 7 && RN2 < 12)
2957 srcreg1 = REG_A0 + RN2 - 8;
2958 else if (RN2 > 11 && RN2 < 16)
2959 srcreg1 = REG_D0 + RN2 - 12;
2960 else
2961 srcreg1 = REG_E0 + RN2;
2962
2963 temp = ((unsigned64) (IMM8)
2964 * (unsigned64)State.regs[srcreg1]);
2965 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2966 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2967 State.regs[REG_MCRL] = sum;
2968 temp >>= 32;
2969 temp &= 0xffffffff;
2970 sum = State.regs[REG_MCRH] + temp + c;
2971 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2972 && (temp & 0x80000000) != (sum & 0x80000000));
2973 State.regs[REG_MCRH] = sum;
2974 if (v)
2975 State.regs[REG_MCVF] = 1;
2976 }
2977
2978 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2979 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2980 "macb"
2981 {
2982 int srcreg1, srcreg2;
2983 long long temp, sum;
2984 int c, v;
2985
2986 PC = cia;
2987
2988 if (RN2 > 7 && RN2 < 12)
2989 srcreg1 = REG_A0 + RN2 - 8;
2990 else if (RN2 > 11 && RN2 < 16)
2991 srcreg1 = REG_D0 + RN2 - 12;
2992 else
2993 srcreg1 = REG_E0 + RN2;
2994
2995 temp = ((signed64)EXTEND8 (IMM8)
2996 * (signed64)State.regs[srcreg1] & 0xff);
2997 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2998 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2999 State.regs[REG_MCRL] = sum;
3000 temp >>= 32;
3001 temp &= 0xffffffff;
3002 sum = State.regs[REG_MCRH] + temp + c;
3003 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3004 && (temp & 0x80000000) != (sum & 0x80000000));
3005 State.regs[REG_MCRH] = sum;
3006 if (v)
3007 State.regs[REG_MCVF] = 1;
3008 }
3009
3010 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
3011 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
3012 "macbu"
3013 {
3014 int srcreg1, srcreg2;
3015 long long temp, sum;
3016 int c, v;
3017
3018 PC = cia;
3019
3020 if (RN2 > 7 && RN2 < 12)
3021 srcreg1 = REG_A0 + RN2 - 8;
3022 else if (RN2 > 11 && RN2 < 16)
3023 srcreg1 = REG_D0 + RN2 - 12;
3024 else
3025 srcreg1 = REG_E0 + RN2;
3026
3027 temp = ((unsigned64) (IMM8)
3028 * (unsigned64)State.regs[srcreg1] & 0xff);
3029 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3030 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3031 State.regs[REG_MCRL] = sum;
3032 temp >>= 32;
3033 temp &= 0xffffffff;
3034 sum = State.regs[REG_MCRH] + temp + c;
3035 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3036 && (temp & 0x80000000) != (sum & 0x80000000));
3037 State.regs[REG_MCRH] = sum;
3038 if (v)
3039 State.regs[REG_MCVF] = 1;
3040 }
3041
3042 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
3043 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
3044 "mach"
3045 {
3046 int srcreg1, srcreg2;
3047 long long temp, sum;
3048 int c, v;
3049
3050 PC = cia;
3051
3052 if (RN2 > 7 && RN2 < 12)
3053 srcreg1 = REG_A0 + RN2 - 8;
3054 else if (RN2 > 11 && RN2 < 16)
3055 srcreg1 = REG_D0 + RN2 - 12;
3056 else
3057 srcreg1 = REG_E0 + RN2;
3058
3059 temp = ((signed64)EXTEND8 (IMM8)
3060 * (signed64)State.regs[srcreg1] & 0xffff);
3061 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3062 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3063 State.regs[REG_MCRL] = sum;
3064 temp >>= 32;
3065 temp &= 0xffffffff;
3066 sum = State.regs[REG_MCRH] + temp + c;
3067 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3068 && (temp & 0x80000000) != (sum & 0x80000000));
3069 State.regs[REG_MCRH] = sum;
3070 if (v)
3071 State.regs[REG_MCVF] = 1;
3072 }
3073
3074 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
3075 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
3076 "machu"
3077 {
3078 int srcreg1, srcreg2;
3079 long long temp, sum;
3080 int c, v;
3081
3082 PC = cia;
3083
3084 if (RN2 > 7 && RN2 < 12)
3085 srcreg1 = REG_A0 + RN2 - 8;
3086 else if (RN2 > 11 && RN2 < 16)
3087 srcreg1 = REG_D0 + RN2 - 12;
3088 else
3089 srcreg1 = REG_E0 + RN2;
3090
3091 temp = ((unsigned64) (IMM8)
3092 * (unsigned64)State.regs[srcreg1] & 0xffff);
3093 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3094 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3095 State.regs[REG_MCRL] = sum;
3096 temp >>= 32;
3097 temp &= 0xffffffff;
3098 sum = State.regs[REG_MCRH] + temp + c;
3099 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3100 && (temp & 0x80000000) != (sum & 0x80000000));
3101 State.regs[REG_MCRH] = sum;
3102 if (v)
3103 State.regs[REG_MCVF] = 1;
3104 }
3105
3106 // ??? mcste
3107
3108 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
3109 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
3110 "add"
3111 *am33
3112 {
3113 int z, c, n, v;
3114 unsigned long sum, source1, source2;
3115 int srcreg1, srcreg2, dstreg;
3116
3117 PC = cia;
3118
3119 if (RM2 > 7 && RM2 < 12)
3120 srcreg1 = REG_A0 + RM2 - 8;
3121 else if (RM2 > 11 && RM2 < 16)
3122 srcreg1 = REG_D0 + RM2 - 12;
3123 else
3124 srcreg1 = REG_E0 + RM2;
3125
3126 if (RN0 > 7 && RN0 < 12)
3127 srcreg2 = REG_A0 + RN0 - 8;
3128 else if (RN0 > 11 && RN0 < 16)
3129 srcreg2 = REG_D0 + RN0 - 12;
3130 else
3131 srcreg2 = REG_E0 + RN0;
3132
3133 if (RD0 > 7 && RD0 < 12)
3134 dstreg = REG_A0 + RD0 - 8;
3135 else if (RD0 > 11 && RD0 < 16)
3136 dstreg = REG_D0 + RD0 - 12;
3137 else
3138 dstreg = REG_E0 + RD0;
3139
3140 source1 = State.regs[srcreg1];
3141 source2 = State.regs[srcreg2];
3142 sum = source1 + source2;
3143 State.regs[dstreg] = sum;
3144
3145 z = (sum == 0);
3146 n = (sum & 0x80000000);
3147 c = (sum < source1) || (sum < source2);
3148 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
3149 && (source1 & 0x80000000) != (sum & 0x80000000));
3150
3151 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3152 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3153 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3154 }
3155
3156 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
3157 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
3158 "addc"
3159 *am33
3160 {
3161 int z, c, n, v;
3162 unsigned long sum, source1, source2;
3163 int srcreg1, srcreg2, dstreg;
3164
3165 PC = cia;
3166
3167 if (RM2 > 7 && RM2 < 12)
3168 srcreg1 = REG_A0 + RM2 - 8;
3169 else if (RM2 > 11 && RM2 < 16)
3170 srcreg1 = REG_D0 + RM2 - 12;
3171 else
3172 srcreg1 = REG_E0 + RM2;
3173
3174 if (RN0 > 7 && RN0 < 12)
3175 srcreg2 = REG_A0 + RN0 - 8;
3176 else if (RN0 > 11 && RN0 < 16)
3177 srcreg2 = REG_D0 + RN0 - 12;
3178 else
3179 srcreg2 = REG_E0 + RN0;
3180
3181 if (RD0 > 7 && RD0 < 12)
3182 dstreg = REG_A0 + RD0 - 8;
3183 else if (RD0 > 11 && RD0 < 16)
3184 dstreg = REG_D0 + RD0 - 12;
3185 else
3186 dstreg = REG_E0 + RD0;
3187
3188 source1 = State.regs[srcreg1];
3189 source2 = State.regs[srcreg2];
3190 sum = source1 + source2 + ((PSW & PSW_C) != 0);
3191 State.regs[dstreg] = sum;
3192
3193 z = (sum == 0);
3194 n = (sum & 0x80000000);
3195 c = (sum < source1) || (sum < source2);
3196 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
3197 && (source1 & 0x80000000) != (sum & 0x80000000));
3198
3199 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3200 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3201 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3202 }
3203
3204 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
3205 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
3206 "sub"
3207 *am33
3208 {
3209 int z, c, n, v;
3210 unsigned long difference, source1, source2;
3211 int srcreg1, srcreg2, dstreg;
3212
3213 PC = cia;
3214
3215 if (RM2 > 7 && RM2 < 12)
3216 srcreg1 = REG_A0 + RM2 - 8;
3217 else if (RM2 > 11 && RM2 < 16)
3218 srcreg1 = REG_D0 + RM2 - 12;
3219 else
3220 srcreg1 = REG_E0 + RM2;
3221
3222 if (RN0 > 7 && RN0 < 12)
3223 srcreg2 = REG_A0 + RN0 - 8;
3224 else if (RN0 > 11 && RN0 < 16)
3225 srcreg2 = REG_D0 + RN0 - 12;
3226 else
3227 srcreg2 = REG_E0 + RN0;
3228
3229 if (RD0 > 7 && RD0 < 12)
3230 dstreg = REG_A0 + RD0 - 8;
3231 else if (RD0 > 11 && RD0 < 16)
3232 dstreg = REG_D0 + RD0 - 12;
3233 else
3234 dstreg = REG_E0 + RD0;
3235
3236 source1 = State.regs[srcreg1];
3237 source2 = State.regs[srcreg2];
3238 difference = source2 - source1;
3239 State.regs[dstreg] = difference;
3240
3241 z = (difference == 0);
3242 n = (difference & 0x80000000);
3243 c = (source1 > source1);
3244 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
3245 && (source1 & 0x80000000) != (difference & 0x80000000));
3246
3247 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3248 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3249 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3250 }
3251
3252 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
3253 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
3254 "subc"
3255 *am33
3256 {
3257 int z, c, n, v;
3258 unsigned long difference, source1, source2;
3259 int srcreg1, srcreg2, dstreg;
3260
3261 PC = cia;
3262
3263 if (RM2 > 7 && RM2 < 12)
3264 srcreg1 = REG_A0 + RM2 - 8;
3265 else if (RM2 > 11 && RM2 < 16)
3266 srcreg1 = REG_D0 + RM2 - 12;
3267 else
3268 srcreg1 = REG_E0 + RM2;
3269
3270 if (RN0 > 7 && RN0 < 12)
3271 srcreg2 = REG_A0 + RN0 - 8;
3272 else if (RN0 > 11 && RN0 < 16)
3273 srcreg2 = REG_D0 + RN0 - 12;
3274 else
3275 srcreg2 = REG_E0 + RN0;
3276
3277 if (RD0 > 7 && RD0 < 12)
3278 dstreg = REG_A0 + RD0 - 8;
3279 else if (RD0 > 11 && RD0 < 16)
3280 dstreg = REG_D0 + RD0 - 12;
3281 else
3282 dstreg = REG_E0 + RD0;
3283
3284 source1 = State.regs[srcreg1];
3285 source2 = State.regs[srcreg2];
3286 difference = source2 - source1 - ((PSW & PSW_C) != 0);
3287 State.regs[dstreg] = difference;
3288
3289 z = (difference == 0);
3290 n = (difference & 0x80000000);
3291 c = (source1 > source2);
3292 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
3293 && (source1 & 0x80000000) != (difference & 0x80000000));
3294
3295 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3296 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3297 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3298 }
3299
3300 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
3301 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
3302 "and"
3303 *am33
3304 {
3305 int z, c, n, v;
3306 int srcreg1, srcreg2, dstreg;
3307
3308 PC = cia;
3309
3310 if (RM2 > 7 && RM2 < 12)
3311 srcreg1 = REG_A0 + RM2 - 8;
3312 else if (RM2 > 11 && RM2 < 16)
3313 srcreg1 = REG_D0 + RM2 - 12;
3314 else
3315 srcreg1 = REG_E0 + RM2;
3316
3317 if (RN0 > 7 && RN0 < 12)
3318 srcreg2 = REG_A0 + RN0 - 8;
3319 else if (RN0 > 11 && RN0 < 16)
3320 srcreg2 = REG_D0 + RN0 - 12;
3321 else
3322 srcreg2 = REG_E0 + RN0;
3323
3324 if (RD0 > 7 && RD0 < 12)
3325 dstreg = REG_A0 + RD0 - 8;
3326 else if (RD0 > 11 && RD0 < 16)
3327 dstreg = REG_D0 + RD0 - 12;
3328 else
3329 dstreg = REG_E0 + RD0;
3330
3331 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
3332
3333 z = (State.regs[dstreg] == 0);
3334 n = (State.regs[dstreg] & 0x80000000);
3335
3336 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3337 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3338 }
3339
3340 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
3341 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
3342 "or"
3343 *am33
3344 {
3345 int z, c, n, v;
3346 int srcreg1, srcreg2, dstreg;
3347
3348 PC = cia;
3349
3350 if (RM2 > 7 && RM2 < 12)
3351 srcreg1 = REG_A0 + RM2 - 8;
3352 else if (RM2 > 11 && RM2 < 16)
3353 srcreg1 = REG_D0 + RM2 - 12;
3354 else
3355 srcreg1 = REG_E0 + RM2;
3356
3357 if (RN0 > 7 && RN0 < 12)
3358 srcreg2 = REG_A0 + RN0 - 8;
3359 else if (RN0 > 11 && RN0 < 16)
3360 srcreg2 = REG_D0 + RN0 - 12;
3361 else
3362 srcreg2 = REG_E0 + RN0;
3363
3364 if (RD0 > 7 && RD0 < 12)
3365 dstreg = REG_A0 + RD0 - 8;
3366 else if (RD0 > 11 && RD0 < 16)
3367 dstreg = REG_D0 + RD0 - 12;
3368 else
3369 dstreg = REG_E0 + RD0;
3370
3371 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
3372
3373 z = (State.regs[dstreg] == 0);
3374 n = (State.regs[dstreg] & 0x80000000);
3375
3376 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3377 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3378 }
3379
3380 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
3381 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
3382 "xor"
3383 *am33
3384 {
3385 int z, c, n, v;
3386 int srcreg1, srcreg2, dstreg;
3387
3388 PC = cia;
3389
3390 if (RM2 > 7 && RM2 < 12)
3391 srcreg1 = REG_A0 + RM2 - 8;
3392 else if (RM2 > 11 && RM2 < 16)
3393 srcreg1 = REG_D0 + RM2 - 12;
3394 else
3395 srcreg1 = REG_E0 + RM2;
3396
3397 if (RN0 > 7 && RN0 < 12)
3398 srcreg2 = REG_A0 + RN0 - 8;
3399 else if (RN0 > 11 && RN0 < 16)
3400 srcreg2 = REG_D0 + RN0 - 12;
3401 else
3402 srcreg2 = REG_E0 + RN0;
3403
3404 if (RD0 > 7 && RD0 < 12)
3405 dstreg = REG_A0 + RD0 - 8;
3406 else if (RD0 > 11 && RD0 < 16)
3407 dstreg = REG_D0 + RD0 - 12;
3408 else
3409 dstreg = REG_E0 + RD0;
3410
3411 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
3412
3413 z = (State.regs[dstreg] == 0);
3414 n = (State.regs[dstreg] & 0x80000000);
3415
3416 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3417 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3418 }
3419
3420 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
3421 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
3422 "asr"
3423 *am33
3424 {
3425 int z, c, n, v;
3426 long temp;
3427 int srcreg1, srcreg2, dstreg;
3428
3429 PC = cia;
3430
3431 if (RM2 > 7 && RM2 < 12)
3432 srcreg1 = REG_A0 + RM2 - 8;
3433 else if (RM2 > 11 && RM2 < 16)
3434 srcreg1 = REG_D0 + RM2 - 12;
3435 else
3436 srcreg1 = REG_E0 + RM2;
3437
3438 if (RN0 > 7 && RN0 < 12)
3439 srcreg2 = REG_A0 + RN0 - 8;
3440 else if (RN0 > 11 && RN0 < 16)
3441 srcreg2 = REG_D0 + RN0 - 12;
3442 else
3443 srcreg2 = REG_E0 + RN0;
3444
3445 if (RD0 > 7 && RD0 < 12)
3446 dstreg = REG_A0 + RD0 - 8;
3447 else if (RD0 > 11 && RD0 < 16)
3448 dstreg = REG_D0 + RD0 - 12;
3449 else
3450 dstreg = REG_E0 + RD0;
3451
3452 temp = State.regs[srcreg2];
3453 c = temp & 1;
3454 temp >>= State.regs[srcreg1];
3455 State.regs[dstreg] = temp;
3456
3457 z = (State.regs[dstreg] == 0);
3458 n = (State.regs[dstreg] & 0x80000000);
3459
3460 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3461 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3462 }
3463
3464 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
3465 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
3466 "lsr"
3467 *am33
3468 {
3469 int z, c, n, v;
3470 int srcreg1, srcreg2, dstreg;
3471
3472 PC = cia;
3473
3474 if (RM2 > 7 && RM2 < 12)
3475 srcreg1 = REG_A0 + RM2 - 8;
3476 else if (RM2 > 11 && RM2 < 16)
3477 srcreg1 = REG_D0 + RM2 - 12;
3478 else
3479 srcreg1 = REG_E0 + RM2;
3480
3481 if (RN0 > 7 && RN0 < 12)
3482 srcreg2 = REG_A0 + RN0 - 8;
3483 else if (RN0 > 11 && RN0 < 16)
3484 srcreg2 = REG_D0 + RN0 - 12;
3485 else
3486 srcreg2 = REG_E0 + RN0;
3487
3488 if (RD0 > 7 && RD0 < 12)
3489 dstreg = REG_A0 + RD0 - 8;
3490 else if (RD0 > 11 && RD0 < 16)
3491 dstreg = REG_D0 + RD0 - 12;
3492 else
3493 dstreg = REG_E0 + RD0;
3494
3495 c = State.regs[srcreg2] & 1;
3496 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
3497
3498 z = (State.regs[dstreg] == 0);
3499 n = (State.regs[dstreg] & 0x80000000);
3500
3501 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3502 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3503 }
3504
3505 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
3506 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
3507 "asl"
3508 *am33
3509 {
3510 int z, c, n, v;
3511 int srcreg1, srcreg2, dstreg;
3512
3513 PC = cia;
3514
3515 if (RM2 > 7 && RM2 < 12)
3516 srcreg1 = REG_A0 + RM2 - 8;
3517 else if (RM2 > 11 && RM2 < 16)
3518 srcreg1 = REG_D0 + RM2 - 12;
3519 else
3520 srcreg1 = REG_E0 + RM2;
3521
3522 if (RN0 > 7 && RN0 < 12)
3523 srcreg2 = REG_A0 + RN0 - 8;
3524 else if (RN0 > 11 && RN0 < 16)
3525 srcreg2 = REG_D0 + RN0 - 12;
3526 else
3527 srcreg2 = REG_E0 + RN0;
3528
3529 if (RD0 > 7 && RD0 < 12)
3530 dstreg = REG_A0 + RD0 - 8;
3531 else if (RD0 > 11 && RD0 < 16)
3532 dstreg = REG_D0 + RD0 - 12;
3533 else
3534 dstreg = REG_E0 + RD0;
3535
3536 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
3537
3538 z = (State.regs[dstreg] == 0);
3539 n = (State.regs[dstreg] & 0x80000000);
3540
3541 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3542 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
3543 }
3544
3545 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
3546 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
3547 "mul"
3548 *am33
3549 {
3550 int srcreg1, srcreg2, dstreg1, dstreg2;
3551 signed long long temp;
3552
3553 PC = cia;
3554
3555 if (RM2 > 7 && RM2 < 12)
3556 srcreg1 = REG_A0 + RM2 - 8;
3557 else if (RM2 > 11 && RM2 < 16)
3558 srcreg1 = REG_D0 + RM2 - 12;
3559 else
3560 srcreg1 = REG_E0 + RM2;
3561
3562 if (RN0 > 7 && RN0 < 12)
3563 srcreg2 = REG_A0 + RN0 - 8;
3564 else if (RN0 > 11 && RN0 < 16)
3565 srcreg2 = REG_D0 + RN0 - 12;
3566 else
3567 srcreg2 = REG_E0 + RN0;
3568
3569 if (RD0 > 7 && RD0 < 12)
3570 dstreg1 = REG_A0 + RD0 - 8;
3571 else if (RD0 > 11 && RD0 < 16)
3572 dstreg1 = REG_D0 + RD0 - 12;
3573 else
3574 dstreg1 = REG_E0 + RD0;
3575
3576 if (RD2 > 7 && RD2 < 12)
3577 dstreg2 = REG_A0 + RD2 - 8;
3578 else if (RD2 > 11 && RD2 < 16)
3579 dstreg2 = REG_D0 + RD2 - 12;
3580 else
3581 dstreg2 = REG_E0 + RD2;
3582
3583 temp = ((signed64)(signed32)State.regs[srcreg1]
3584 * (signed64)(signed32)State.regs[srcreg2]);
3585 State.regs[dstreg1] = temp & 0xffffffff;
3586 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
3587 }
3588
3589 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
3590 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
3591 "mulu"
3592 *am33
3593 {
3594 int srcreg1, srcreg2, dstreg1, dstreg2;
3595 signed long long temp;
3596
3597 PC = cia;
3598
3599 if (RM2 > 7 && RM2 < 12)
3600 srcreg1 = REG_A0 + RM2 - 8;
3601 else if (RM2 > 11 && RM2 < 16)
3602 srcreg1 = REG_D0 + RM2 - 12;
3603 else
3604 srcreg1 = REG_E0 + RM2;
3605
3606 if (RN0 > 7 && RN0 < 12)
3607 srcreg2 = REG_A0 + RN0 - 8;
3608 else if (RN0 > 11 && RN0 < 16)
3609 srcreg2 = REG_D0 + RN0 - 12;
3610 else
3611 srcreg2 = REG_E0 + RN0;
3612
3613 if (RD0 > 7 && RD0 < 12)
3614 dstreg1 = REG_A0 + RD0 - 8;
3615 else if (RD0 > 11 && RD0 < 16)
3616 dstreg1 = REG_D0 + RD0 - 12;
3617 else
3618 dstreg1 = REG_E0 + RD0;
3619
3620 if (RD2 > 7 && RD2 < 12)
3621 dstreg2 = REG_A0 + RD2 - 8;
3622 else if (RD2 > 11 && RD2 < 16)
3623 dstreg2 = REG_D0 + RD2 - 12;
3624 else
3625 dstreg2 = REG_E0 + RD2;
3626
3627 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
3628 * (unsigned64)(unsigned32)State.regs[srcreg2]);
3629 State.regs[dstreg1] = temp & 0xffffffff;
3630 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
3631 }
3632
3633 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
3634 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
3635 "mov"
3636 *am33
3637 {
3638 int dstreg;
3639
3640 PC = cia;
3641 if (RN2 > 7 && RN2 < 12)
3642 dstreg = REG_A0 + RN2 - 8;
3643 else if (RN2 > 11 && RN2 < 16)
3644 dstreg = REG_D0 + RN2 - 12;
3645 else
3646 dstreg = REG_E0 + RN2;
3647
3648 State.regs[dstreg] = load_word (IMM8);
3649 }
3650
3651 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
3652 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
3653 "mov"
3654 *am33
3655 {
3656 int srcreg;
3657
3658 if (RM2 > 7 && RM2 < 12)
3659 srcreg = REG_A0 + RM2 - 8;
3660 else if (RM2 > 11 && RM2 < 16)
3661 srcreg = REG_D0 + RM2 - 12;
3662 else
3663 srcreg = REG_E0 + RM2;
3664
3665 store_word (IMM8, State.regs[srcreg]);
3666 }
3667
3668 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
3669 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
3670 "movbu"
3671 *am33
3672 {
3673 int dstreg;
3674
3675 PC = cia;
3676 if (RN2 > 7 && RN2 < 12)
3677 dstreg = REG_A0 + RN2 - 8;
3678 else if (RN2 > 11 && RN2 < 16)
3679 dstreg = REG_D0 + RN2 - 12;
3680 else
3681 dstreg = REG_E0 + RN2;
3682
3683 State.regs[dstreg] = load_byte (IMM8);
3684 }
3685
3686 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
3687 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
3688 "movbu"
3689 *am33
3690 {
3691 int srcreg;
3692
3693 PC = cia;
3694 if (RM2 > 7 && RM2 < 12)
3695 srcreg = REG_A0 + RM2 - 8;
3696 else if (RM2 > 11 && RM2 < 16)
3697 srcreg = REG_D0 + RM2 - 12;
3698 else
3699 srcreg = REG_E0 + RM2;
3700
3701 store_byte (IMM8, State.regs[srcreg]);
3702 }
3703
3704 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
3705 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
3706 "movhu"
3707 *am33
3708 {
3709 int dstreg;
3710
3711 PC = cia;
3712 if (RN2 > 7 && RN2 < 12)
3713 dstreg = REG_A0 + RN2 - 8;
3714 else if (RN2 > 11 && RN2 < 16)
3715 dstreg = REG_D0 + RN2 - 12;
3716 else
3717 dstreg = REG_E0 + RN2;
3718
3719 State.regs[dstreg] = load_half (IMM8);
3720 }
3721
3722 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
3723 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
3724 "movhu"
3725 *am33
3726 {
3727 int srcreg;
3728
3729 PC = cia;
3730 if (RM2 > 7 && RM2 < 12)
3731 srcreg = REG_A0 + RM2 - 8;
3732 else if (RM2 > 11 && RM2 < 16)
3733 srcreg = REG_D0 + RM2 - 12;
3734 else
3735 srcreg = REG_E0 + RM2;
3736
3737 store_half (IMM8, State.regs[srcreg]);
3738 }
3739
3740 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
3741 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
3742 "mov"
3743 *am33
3744 {
3745 int srcreg1, srcreg2, dstreg;
3746
3747 PC = cia;
3748
3749 if (RM0 > 7 && RM0 < 12)
3750 srcreg1 = REG_A0 + RM0 - 8;
3751 else if (RM0 > 11 && RM0 < 16)
3752 srcreg1 = REG_D0 + RM0 - 12;
3753 else
3754 srcreg1 = REG_E0 + RM0;
3755
3756 if (RI0 > 7 && RI0 < 12)
3757 srcreg2 = REG_A0 + RI0 - 8;
3758 else if (RI0 > 11 && RI0 < 16)
3759 srcreg2 = REG_D0 + RI0 - 12;
3760 else
3761 srcreg2 = REG_E0 + RI0;
3762
3763 if (RN0 > 7 && RN0 < 12)
3764 dstreg = REG_A0 + RN0 - 8;
3765 else if (RN0 > 11 && RN0 < 16)
3766 dstreg = REG_D0 + RN0 - 12;
3767 else
3768 dstreg = REG_E0 + RN0;
3769
3770 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
3771 }
3772
3773 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
3774 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
3775 "mov"
3776 *am33
3777 {
3778 int srcreg, dstreg1, dstreg2;
3779
3780 PC = cia;
3781
3782 if (RM0 > 7 && RM0 < 12)
3783 srcreg = REG_A0 + RM0 - 8;
3784 else if (RM0 > 11 && RM0 < 16)
3785 srcreg = REG_D0 + RM0 - 12;
3786 else
3787 srcreg = REG_E0 + RM0;
3788
3789 if (RI0 > 7 && RI0 < 12)
3790 dstreg1 = REG_A0 + RI0 - 8;
3791 else if (RI0 > 11 && RI0 < 16)
3792 dstreg1 = REG_D0 + RI0 - 12;
3793 else
3794 dstreg1 = REG_E0 + RI0;
3795
3796 if (RN0 > 7 && RN0 < 12)
3797 dstreg2 = REG_A0 + RN0 - 8;
3798 else if (RN0 > 11 && RN0 < 16)
3799 dstreg2 = REG_D0 + RN0 - 12;
3800 else
3801 dstreg2 = REG_E0 + RN0;
3802
3803 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3804 }
3805
3806 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
3807 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
3808 "movbu"
3809 *am33
3810 {
3811 int srcreg1, srcreg2, dstreg;
3812
3813 PC = cia;
3814
3815 if (RM0 > 7 && RM0 < 12)
3816 srcreg1 = REG_A0 + RM0 - 8;
3817 else if (RM0 > 11 && RM0 < 16)
3818 srcreg1 = REG_D0 + RM0 - 12;
3819 else
3820 srcreg1 = REG_E0 + RM0;
3821
3822 if (RI0 > 7 && RI0 < 12)
3823 srcreg2 = REG_A0 + RI0 - 8;
3824 else if (RI0 > 11 && RI0 < 16)
3825 srcreg2 = REG_D0 + RI0 - 12;
3826 else
3827 srcreg2 = REG_E0 + RI0;
3828
3829 if (RN0 > 7 && RN0 < 12)
3830 dstreg = REG_A0 + RN0 - 8;
3831 else if (RN0 > 11 && RN0 < 16)
3832 dstreg = REG_D0 + RN0 - 12;
3833 else
3834 dstreg = REG_E0 + RN0;
3835
3836 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
3837 }
3838
3839 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
3840 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
3841 "movbu"
3842 *am33
3843 {
3844 int srcreg, dstreg1, dstreg2;
3845
3846 PC = cia;
3847
3848 if (RM0 > 7 && RM0 < 12)
3849 srcreg = REG_A0 + RM0 - 8;
3850 else if (RM0 > 11 && RM0 < 16)
3851 srcreg = REG_D0 + RM0 - 12;
3852 else
3853 srcreg = REG_E0 + RM0;
3854
3855 if (RI0 > 7 && RI0 < 12)
3856 dstreg1 = REG_A0 + RI0 - 8;
3857 else if (RI0 > 11 && RI0 < 16)
3858 dstreg1 = REG_D0 + RI0 - 12;
3859 else
3860 dstreg1 = REG_E0 + RI0;
3861
3862 if (RN0 > 7 && RN0 < 12)
3863 dstreg2 = REG_A0 + RN0 - 8;
3864 else if (RN0 > 11 && RN0 < 16)
3865 dstreg2 = REG_D0 + RN0 - 12;
3866 else
3867 dstreg2 = REG_E0 + RN0;
3868
3869 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3870 }
3871
3872 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
3873 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
3874 "movhu"
3875 *am33
3876 {
3877 int srcreg1, srcreg2, dstreg;
3878
3879 PC = cia;
3880
3881 if (RM0 > 7 && RM0 < 12)
3882 srcreg1 = REG_A0 + RM0 - 8;
3883 else if (RM0 > 11 && RM0 < 16)
3884 srcreg1 = REG_D0 + RM0 - 12;
3885 else
3886 srcreg1 = REG_E0 + RM0;
3887
3888 if (RI0 > 7 && RI0 < 12)
3889 srcreg2 = REG_A0 + RI0 - 8;
3890 else if (RI0 > 11 && RI0 < 16)
3891 srcreg2 = REG_D0 + RI0 - 12;
3892 else
3893 srcreg2 = REG_E0 + RI0;
3894
3895 if (RN0 > 7 && RN0 < 12)
3896 dstreg = REG_A0 + RN0 - 8;
3897 else if (RN0 > 11 && RN0 < 16)
3898 dstreg = REG_D0 + RN0 - 12;
3899 else
3900 dstreg = REG_E0 + RN0;
3901
3902 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
3903 }
3904
3905 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
3906 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
3907 "movhu"
3908 *am33
3909 {
3910 int srcreg, dstreg1, dstreg2;
3911
3912 PC = cia;
3913
3914 if (RM0 > 7 && RM0 < 12)
3915 srcreg = REG_A0 + RM0 - 8;
3916 else if (RM0 > 11 && RM0 < 16)
3917 srcreg = REG_D0 + RM0 - 12;
3918 else
3919 srcreg = REG_E0 + RM0;
3920
3921 if (RI0 > 7 && RI0 < 12)
3922 dstreg1 = REG_A0 + RI0 - 8;
3923 else if (RI0 > 11 && RI0 < 16)
3924 dstreg1 = REG_D0 + RI0 - 12;
3925 else
3926 dstreg1 = REG_E0 + RI0;
3927
3928 if (RN0 > 7 && RN0 < 12)
3929 dstreg2 = REG_A0 + RN0 - 8;
3930 else if (RN0 > 11 && RN0 < 16)
3931 dstreg2 = REG_D0 + RN0 - 12;
3932 else
3933 dstreg2 = REG_E0 + RN0;
3934
3935 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3936 }
3937
3938 // ??? mac
3939 // ??? macu
3940 // ??? macb
3941 // ??? macbu
3942 // ??? mach
3943 // ??? machu
3944 // ??? dmach
3945 // ??? dmachu
3946 // ??? dmulh
3947 // ??? dmulhu
3948
3949 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3950 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3951 "sat24"
3952 *am33
3953 {
3954 int srcreg, dstreg;
3955 int value;
3956
3957 PC = cia;
3958
3959 if (RM2 > 7 && RM2 < 12)
3960 srcreg = REG_A0 + RM2 - 8;
3961 else if (RM2 > 11 && RM2 < 16)
3962 srcreg = REG_D0 + RM2 - 12;
3963 else
3964 srcreg = REG_E0 + RM2;
3965
3966 if (RN0 > 7 && RN0 < 12)
3967 dstreg = REG_A0 + RN0 - 8;
3968 else if (RN0 > 11 && RN0 < 16)
3969 dstreg = REG_D0 + RN0 - 12;
3970 else
3971 dstreg = REG_E0 + RN0;
3972
3973 value = State.regs[srcreg];
3974
3975 if (value >= 0x7fffff)
3976 State.regs[dstreg] = 0x7fffff;
3977 else if (value <= 0xff800000)
3978 State.regs[dstreg] = 0xff800000;
3979 else
3980 State.regs[dstreg] = value;
3981 }
3982
3983 // ??? bsch
3984
3985 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3986 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3987 "mov"
3988 *am33
3989 {
3990 int dstreg;
3991
3992 PC = cia;
3993
3994 if (RN0 > 7 && RN0 < 12)
3995 dstreg = REG_A0 + RN0 - 8;
3996 else if (RN0 > 11 && RN0 < 16)
3997 dstreg = REG_D0 + RN0 - 12;
3998 else
3999 dstreg = REG_E0 + RN0;
4000
4001 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
4002 }
4003
4004 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
4005 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
4006 "movu"
4007 *am33
4008 {
4009 int dstreg;
4010
4011 PC = cia;
4012
4013 if (RN0 > 7 && RN0 < 12)
4014 dstreg = REG_A0 + RN0 - 8;
4015 else if (RN0 > 11 && RN0 < 16)
4016 dstreg = REG_D0 + RN0 - 12;
4017 else
4018 dstreg = REG_E0 + RN0;
4019
4020 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
4021 }
4022
4023 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
4024 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
4025 "add"
4026 *am33
4027 {
4028 int dstreg;
4029
4030 PC = cia;
4031
4032 if (RN0 > 7 && RN0 < 12)
4033 dstreg = REG_A0 + RN0 - 8;
4034 else if (RN0 > 11 && RN0 < 16)
4035 dstreg = REG_D0 + RN0 - 12;
4036 else
4037 dstreg = REG_E0 + RN0;
4038
4039 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
4040 }
4041
4042 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
4043 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
4044 "addc"
4045 *am33
4046 {
4047 int dstreg, z, n, c, v;
4048 unsigned long sum, imm, reg2;
4049
4050 PC = cia;
4051
4052 if (RN0 > 7 && RN0 < 12)
4053 dstreg = REG_A0 + RN0 - 8;
4054 else if (RN0 > 11 && RN0 < 16)
4055 dstreg = REG_D0 + RN0 - 12;
4056 else
4057 dstreg = REG_E0 + RN0;
4058
4059 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
4060 reg2 = State.regs[dstreg];
4061 sum = imm + reg2 + ((PSW & PSW_C) != 0);
4062 State.regs[dstreg] = sum;
4063
4064 z = (sum == 0);
4065 n = (sum & 0x80000000);
4066 c = (sum < imm) || (sum < reg2);
4067 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4068 && (reg2 & 0x80000000) != (sum & 0x80000000));
4069
4070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4071 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4072 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4073 }
4074
4075 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
4076 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
4077 "sub"
4078 *am33
4079 {
4080 int dstreg;
4081
4082 PC = cia;
4083
4084 if (RN0 > 7 && RN0 < 12)
4085 dstreg = REG_A0 + RN0 - 8;
4086 else if (RN0 > 11 && RN0 < 16)
4087 dstreg = REG_D0 + RN0 - 12;
4088 else
4089 dstreg = REG_E0 + RN0;
4090
4091 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
4092 }
4093
4094 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
4095 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
4096 "subc"
4097 *am33
4098 {
4099 int dstreg, z, n, c, v;
4100 unsigned long difference, imm, reg2;
4101
4102 PC = cia;
4103
4104 if (RN0 > 7 && RN0 < 12)
4105 dstreg = REG_A0 + RN0 - 8;
4106 else if (RN0 > 11 && RN0 < 16)
4107 dstreg = REG_D0 + RN0 - 12;
4108 else
4109 dstreg = REG_E0 + RN0;
4110
4111 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
4112 reg2 = State.regs[dstreg];
4113 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4114 State.regs[dstreg] = difference;
4115
4116 z = (difference == 0);
4117 n = (difference & 0x80000000);
4118 c = (imm > reg2);
4119 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4120 && (reg2 & 0x80000000) != (difference & 0x80000000));
4121
4122 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4123 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4124 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4125 }
4126
4127 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
4128 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
4129 "cmp"
4130 *am33
4131 {
4132 int srcreg;
4133
4134 PC = cia;
4135
4136 if (RN0 > 7 && RN0 < 12)
4137 srcreg = REG_A0 + RN0 - 8;
4138 else if (RN0 > 11 && RN0 < 16)
4139 srcreg = REG_D0 + RN0 - 12;
4140 else
4141 srcreg = REG_E0 + RN0;
4142
4143 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
4144 }
4145
4146 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
4147 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
4148 "mov"
4149 *am33
4150 {
4151 int dstreg;
4152
4153 PC = cia;
4154
4155 if (XRN0 == 0)
4156 {
4157 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
4158 }
4159 else
4160 abort ();
4161 }
4162
4163 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
4164 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
4165 "and"
4166 *am33
4167 {
4168 int dstreg;
4169 int z,n;
4170
4171 PC = cia;
4172
4173 if (RN0 > 7 && RN0 < 12)
4174 dstreg = REG_A0 + RN0 - 8;
4175 else if (RN0 > 11 && RN0 < 16)
4176 dstreg = REG_D0 + RN0 - 12;
4177 else
4178 dstreg = REG_E0 + RN0;
4179
4180 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
4181 z = (State.regs[dstreg] == 0);
4182 n = (State.regs[dstreg] & 0x80000000) != 0;
4183 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4184 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4185 }
4186
4187 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
4188 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
4189 "or"
4190 *am33
4191 {
4192 int dstreg;
4193 int z,n;
4194
4195 PC = cia;
4196
4197 if (RN0 > 7 && RN0 < 12)
4198 dstreg = REG_A0 + RN0 - 8;
4199 else if (RN0 > 11 && RN0 < 16)
4200 dstreg = REG_D0 + RN0 - 12;
4201 else
4202 dstreg = REG_E0 + RN0;
4203
4204 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
4205 z = (State.regs[dstreg] == 0);
4206 n = (State.regs[dstreg] & 0x80000000) != 0;
4207 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4208 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4209 }
4210
4211 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
4212 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
4213 "xor"
4214 *am33
4215 {
4216 int dstreg;
4217 int z,n;
4218
4219 PC = cia;
4220
4221 if (RN0 > 7 && RN0 < 12)
4222 dstreg = REG_A0 + RN0 - 8;
4223 else if (RN0 > 11 && RN0 < 16)
4224 dstreg = REG_D0 + RN0 - 12;
4225 else
4226 dstreg = REG_E0 + RN0;
4227
4228 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
4229 z = (State.regs[dstreg] == 0);
4230 n = (State.regs[dstreg] & 0x80000000) != 0;
4231 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4232 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4233 }
4234
4235 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
4236 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
4237 "asr"
4238 *am33
4239 {
4240 int dstreg;
4241 long temp;
4242 int c, z, n;
4243
4244 PC = cia;
4245
4246 if (RN0 > 7 && RN0 < 12)
4247 dstreg = REG_A0 + RN0 - 8;
4248 else if (RN0 > 11 && RN0 < 16)
4249 dstreg = REG_D0 + RN0 - 12;
4250 else
4251 dstreg = REG_E0 + RN0;
4252
4253 temp = State.regs[dstreg];
4254 c = temp & 1;
4255 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
4256 State.regs[dstreg] = temp;
4257 z = (State.regs[dstreg] == 0);
4258 n = (State.regs[dstreg] & 0x80000000) != 0;
4259 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4260 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4261 }
4262
4263
4264 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
4265 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
4266 "lsr"
4267 *am33
4268 {
4269 int dstreg;
4270 int z, n, c;
4271
4272 PC = cia;
4273
4274 if (RN0 > 7 && RN0 < 12)
4275 dstreg = REG_A0 + RN0 - 8;
4276 else if (RN0 > 11 && RN0 < 16)
4277 dstreg = REG_D0 + RN0 - 12;
4278 else
4279 dstreg = REG_E0 + RN0;
4280
4281 c = State.regs[dstreg] & 1;
4282 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
4283 z = (State.regs[dstreg] == 0);
4284 n = (State.regs[dstreg] & 0x80000000) != 0;
4285 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4286 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4287 }
4288
4289 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
4290 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
4291 "asl"
4292 *am33
4293 {
4294 int srcreg, dstreg;
4295 int z, n;
4296
4297 PC = cia;
4298
4299 if (RN0 > 7 && RN0 < 12)
4300 dstreg = REG_A0 + RN0 - 8;
4301 else if (RN0 > 11 && RN0 < 16)
4302 dstreg = REG_D0 + RN0 - 12;
4303 else
4304 dstreg = REG_E0 + RN0;
4305
4306 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
4307 z = (State.regs[dstreg] == 0);
4308 n = (State.regs[dstreg] & 0x80000000) != 0;
4309 PSW &= ~(PSW_Z | PSW_N);
4310 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4311 }
4312
4313 // ??? mul
4314 // ??? mulu
4315
4316 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
4317 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
4318 "btst"
4319 *am33
4320 {
4321 int srcreg;
4322
4323 PC = cia;
4324
4325 if (RN0 > 7 && RN0 < 12)
4326 srcreg = REG_A0 + RN0 - 8;
4327 else if (RN0 > 11 && RN0 < 16)
4328 srcreg = REG_D0 + RN0 - 12;
4329 else
4330 srcreg = REG_E0 + RN0;
4331
4332 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
4333 }
4334
4335 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
4336 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
4337 "mov"
4338 *am33
4339 {
4340 int srcreg, dstreg;
4341
4342 PC = cia;
4343
4344 if (RM0 > 7 && RM0 < 12)
4345 srcreg = REG_A0 + RM0 - 8;
4346 else if (RM0 > 11 && RM0 < 16)
4347 srcreg = REG_D0 + RM0 - 12;
4348 else
4349 srcreg = REG_E0 + RM0;
4350
4351 if (RN2 > 7 && RN2 < 12)
4352 dstreg = REG_A0 + RN2 - 8;
4353 else if (RN2 > 11 && RN2 < 16)
4354 dstreg = REG_D0 + RN2 - 12;
4355 else
4356 dstreg = REG_E0 + RN2;
4357
4358 State.regs[dstreg] = load_word (State.regs[srcreg]
4359 + FETCH24 (IMM24A, IMM24B, IMM24C));
4360 }
4361
4362 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
4363 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
4364 "mov"
4365 *am33
4366 {
4367 int srcreg, dstreg;
4368
4369 PC = cia;
4370
4371 if (RM2 > 7 && RM2 < 12)
4372 srcreg = REG_A0 + RM2 - 8;
4373 else if (RM2 > 11 && RM2 < 16)
4374 srcreg = REG_D0 + RM2 - 12;
4375 else
4376 srcreg = REG_E0 + RM2;
4377
4378 if (RN0 > 7 && RN0 < 12)
4379 dstreg = REG_A0 + RN0 - 8;
4380 else if (RN0 > 11 && RN0 < 16)
4381 dstreg = REG_D0 + RN0 - 12;
4382 else
4383 dstreg = REG_E0 + RN0;
4384
4385 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
4386 State.regs[srcreg]);
4387 }
4388
4389 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
4390 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
4391 "movbu"
4392 *am33
4393 {
4394 int srcreg, dstreg;
4395
4396 PC = cia;
4397
4398 if (RM0 > 7 && RM0 < 12)
4399 srcreg = REG_A0 + RM0 - 8;
4400 else if (RM0 > 11 && RM0 < 16)
4401 srcreg = REG_D0 + RM0 - 12;
4402 else
4403 srcreg = REG_E0 + RM0;
4404
4405 if (RN2 > 7 && RN2 < 12)
4406 dstreg = REG_A0 + RN2 - 8;
4407 else if (RN2 > 11 && RN2 < 16)
4408 dstreg = REG_D0 + RN2 - 12;
4409 else
4410 dstreg = REG_E0 + RN2;
4411
4412 State.regs[dstreg] = load_byte (State.regs[srcreg]
4413 + FETCH24 (IMM24A, IMM24B, IMM24C));
4414 }
4415
4416 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
4417 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
4418 "movbu"
4419 *am33
4420 {
4421 int srcreg, dstreg;
4422
4423 PC = cia;
4424
4425 if (RM2 > 7 && RM2 < 12)
4426 srcreg = REG_A0 + RM2 - 8;
4427 else if (RM2 > 11 && RM2 < 16)
4428 srcreg = REG_D0 + RM2 - 12;
4429 else
4430 srcreg = REG_E0 + RM2;
4431
4432 if (RN0 > 7 && RN0 < 12)
4433 dstreg = REG_A0 + RN0 - 8;
4434 else if (RN0 > 11 && RN0 < 16)
4435 dstreg = REG_D0 + RN0 - 12;
4436 else
4437 dstreg = REG_E0 + RN0;
4438
4439 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
4440 State.regs[srcreg]);
4441 }
4442
4443 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
4444 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
4445 "movhu"
4446 *am33
4447 {
4448 int srcreg, dstreg;
4449
4450 PC = cia;
4451
4452 if (RM0 > 7 && RM0 < 12)
4453 srcreg = REG_A0 + RM0 - 8;
4454 else if (RM0 > 11 && RM0 < 16)
4455 srcreg = REG_D0 + RM0 - 12;
4456 else
4457 srcreg = REG_E0 + RM0;
4458
4459 if (RN2 > 7 && RN2 < 12)
4460 dstreg = REG_A0 + RN2 - 8;
4461 else if (RN2 > 11 && RN2 < 16)
4462 dstreg = REG_D0 + RN2 - 12;
4463 else
4464 dstreg = REG_E0 + RN2;
4465
4466 State.regs[dstreg] = load_half (State.regs[srcreg]
4467 + FETCH24 (IMM24A, IMM24B, IMM24C));
4468 }
4469
4470 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
4471 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
4472 "movhu"
4473 *am33
4474 {
4475 int srcreg, dstreg;
4476
4477 PC = cia;
4478
4479 if (RM2 > 7 && RM2 < 12)
4480 srcreg = REG_A0 + RM2 - 8;
4481 else if (RM2 > 11 && RM2 < 16)
4482 srcreg = REG_D0 + RM2 - 12;
4483 else
4484 srcreg = REG_E0 + RM2;
4485
4486 if (RN0 > 7 && RN0 < 12)
4487 dstreg = REG_A0 + RN0 - 8;
4488 else if (RN0 > 11 && RN0 < 16)
4489 dstreg = REG_D0 + RN0 - 12;
4490 else
4491 dstreg = REG_E0 + RN0;
4492
4493 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
4494 State.regs[srcreg]);
4495 }
4496
4497 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
4498 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
4499 "mov"
4500 *am33
4501 {
4502 int srcreg, dstreg;
4503
4504 PC = cia;
4505
4506 if (RM0 > 7 && RM0 < 12)
4507 srcreg = REG_A0 + RM0 - 8;
4508 else if (RM0 > 11 && RM0 < 16)
4509 srcreg = REG_D0 + RM0 - 12;
4510 else
4511 srcreg = REG_E0 + RM0;
4512
4513 if (RN2 > 7 && RN2 < 12)
4514 dstreg = REG_A0 + RN2 - 8;
4515 else if (RN2 > 11 && RN2 < 16)
4516 dstreg = REG_D0 + RN2 - 12;
4517 else
4518 dstreg = REG_E0 + RN2;
4519
4520 State.regs[dstreg] = load_word (State.regs[srcreg]
4521 + FETCH24 (IMM24A, IMM24B, IMM24C));
4522 State.regs[srcreg] += 4;
4523 }
4524
4525 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
4526 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
4527 "mov"
4528 *am33
4529 {
4530 int srcreg, dstreg;
4531
4532 PC = cia;
4533
4534 if (RM2 > 7 && RM2 < 12)
4535 srcreg = REG_A0 + RM2 - 8;
4536 else if (RM2 > 11 && RM2 < 16)
4537 srcreg = REG_D0 + RM2 - 12;
4538 else
4539 srcreg = REG_E0 + RM2;
4540
4541 if (RN0 > 7 && RN0 < 12)
4542 dstreg = REG_A0 + RN0 - 8;
4543 else if (RN0 > 11 && RN0 < 16)
4544 dstreg = REG_D0 + RN0 - 12;
4545 else
4546 dstreg = REG_E0 + RN0;
4547
4548 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
4549 State.regs[srcreg]);
4550 State.regs[dstreg] += 4;
4551 }
4552
4553
4554 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
4555 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
4556 "mov"
4557 *am33
4558 {
4559 int dstreg;
4560
4561 PC = cia;
4562
4563 if (RN2 > 7 && RN2 < 12)
4564 dstreg = REG_A0 + RN2 - 8;
4565 else if (RN2 > 11 && RN2 < 16)
4566 dstreg = REG_D0 + RN2 - 12;
4567 else
4568 dstreg = REG_E0 + RN2;
4569
4570 State.regs[dstreg] = load_word (State.regs[REG_SP]
4571 + FETCH24 (IMM24A, IMM24B, IMM24C));
4572 }
4573
4574 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
4575 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
4576 "mov"
4577 *am33
4578 {
4579 int srcreg;
4580
4581 PC = cia;
4582
4583 if (RM2 > 7 && RM2 < 12)
4584 srcreg = REG_A0 + RM2 - 8;
4585 else if (RM2 > 11 && RM2 < 16)
4586 srcreg = REG_D0 + RM2 - 12;
4587 else
4588 srcreg = REG_E0 + RM2;
4589
4590 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
4591 State.regs[srcreg]);
4592 }
4593
4594 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
4595 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
4596 "movbu"
4597 *am33
4598 {
4599 int dstreg;
4600
4601 PC = cia;
4602
4603 if (RN2 > 7 && RN2 < 12)
4604 dstreg = REG_A0 + RN2 - 8;
4605 else if (RN2 > 11 && RN2 < 16)
4606 dstreg = REG_D0 + RN2 - 12;
4607 else
4608 dstreg = REG_E0 + RN2;
4609
4610 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4611 + FETCH24 (IMM24A, IMM24B, IMM24C));
4612 }
4613
4614 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
4615 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
4616 "movbu"
4617 *am33
4618 {
4619 int srcreg;
4620
4621 PC = cia;
4622
4623 if (RM2 > 7 && RM2 < 12)
4624 srcreg = REG_A0 + RM2 - 8;
4625 else if (RM2 > 11 && RM2 < 16)
4626 srcreg = REG_D0 + RM2 - 12;
4627 else
4628 srcreg = REG_E0 + RM2;
4629
4630 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
4631 State.regs[srcreg]);
4632 }
4633
4634 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
4635 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
4636 "movhu"
4637 *am33
4638 {
4639 int dstreg;
4640
4641 PC = cia;
4642
4643 if (RN2 > 7 && RN2 < 12)
4644 dstreg = REG_A0 + RN2 - 8;
4645 else if (RN2 > 11 && RN2 < 16)
4646 dstreg = REG_D0 + RN2 - 12;
4647 else
4648 dstreg = REG_E0 + RN2;
4649
4650 State.regs[dstreg] = load_half (State.regs[REG_SP]
4651 + FETCH24 (IMM24A, IMM24B, IMM24C));
4652 }
4653
4654 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
4655 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
4656 "movhu"
4657 *am33
4658 {
4659 int srcreg;
4660
4661 PC = cia;
4662
4663 if (RM2 > 7 && RM2 < 12)
4664 srcreg = REG_A0 + RM2 - 8;
4665 else if (RM2 > 11 && RM2 < 16)
4666 srcreg = REG_D0 + RM2 - 12;
4667 else
4668 srcreg = REG_E0 + RM2;
4669
4670 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
4671 State.regs[srcreg]);
4672 }
4673
4674 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
4675 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
4676 "movhu"
4677 *am33
4678 {
4679 int srcreg, dstreg;
4680
4681 PC = cia;
4682
4683 if (RM0 > 7 && RM0 < 12)
4684 srcreg = REG_A0 + RM0 - 8;
4685 else if (RM0 > 11 && RM0 < 16)
4686 srcreg = REG_D0 + RM0 - 12;
4687 else
4688 srcreg = REG_E0 + RM0;
4689
4690 if (RN2 > 7 && RN2 < 12)
4691 dstreg = REG_A0 + RN2 - 8;
4692 else if (RN2 > 11 && RN2 < 16)
4693 dstreg = REG_D0 + RN2 - 12;
4694 else
4695 dstreg = REG_E0 + RN2;
4696
4697 State.regs[dstreg] = load_half (State.regs[srcreg]
4698 + FETCH24 (IMM24A, IMM24B, IMM24C));
4699 State.regs[dstreg] += 2;
4700 }
4701
4702 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
4703 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
4704 "movhu"
4705 *am33
4706 {
4707 int srcreg, dstreg;
4708
4709 PC = cia;
4710
4711 if (RM2 > 7 && RM2 < 12)
4712 srcreg = REG_A0 + RM2 - 8;
4713 else if (RM2 > 11 && RM2 < 16)
4714 srcreg = REG_D0 + RM2 - 12;
4715 else
4716 srcreg = REG_E0 + RM2;
4717
4718 if (RN0 > 7 && RN0 < 12)
4719 dstreg = REG_A0 + RN0 - 8;
4720 else if (RN0 > 11 && RN0 < 16)
4721 dstreg = REG_D0 + RN0 - 12;
4722 else
4723 dstreg = REG_E0 + RN0;
4724
4725 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
4726 State.regs[srcreg]);
4727 State.regs[srcreg] += 2;
4728 }
4729
4730 // ??? mac
4731 // ??? macb
4732 // ??? macbu
4733 // ??? mach
4734 // ??? machu
4735
4736 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
4737 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
4738 "mov"
4739 *am33
4740 {
4741 int dstreg;
4742
4743 PC = cia;
4744
4745 if (RN2 > 7 && RN2 < 12)
4746 dstreg = REG_A0 + RN2 - 8;
4747 else if (RN2 > 11 && RN2 < 16)
4748 dstreg = REG_D0 + RN2 - 12;
4749 else
4750 dstreg = REG_E0 + RN2;
4751
4752 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
4753 }
4754
4755 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
4756 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
4757 "mov"
4758 *am33
4759 {
4760 int srcreg;
4761
4762 PC = cia;
4763
4764 if (RM2 > 7 && RM2 < 12)
4765 srcreg = REG_A0 + RM2 - 8;
4766 else if (RM2 > 11 && RM2 < 16)
4767 srcreg = REG_D0 + RM2 - 12;
4768 else
4769 srcreg = REG_E0 + RM2;
4770
4771 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
4772 }
4773
4774
4775 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
4776 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
4777 "movbu"
4778 *am33
4779 {
4780 int dstreg;
4781
4782 PC = cia;
4783
4784 if (RN2 > 7 && RN2 < 12)
4785 dstreg = REG_A0 + RN2 - 8;
4786 else if (RN2 > 11 && RN2 < 16)
4787 dstreg = REG_D0 + RN2 - 12;
4788 else
4789 dstreg = REG_E0 + RN2;
4790
4791 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
4792 }
4793
4794 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
4795 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
4796 "movbu"
4797 *am33
4798 {
4799 int srcreg;
4800
4801 PC = cia;
4802
4803 if (RM2 > 7 && RM2 < 12)
4804 srcreg = REG_A0 + RM2 - 8;
4805 else if (RM2 > 11 && RM2 < 16)
4806 srcreg = REG_D0 + RM2 - 12;
4807 else
4808 srcreg = REG_E0 + RM2;
4809
4810 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
4811 }
4812
4813
4814 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
4815 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
4816 "movhu"
4817 *am33
4818 {
4819 int dstreg;
4820
4821 PC = cia;
4822
4823 if (RN2 > 7 && RN2 < 12)
4824 dstreg = REG_A0 + RN2 - 8;
4825 else if (RN2 > 11 && RN2 < 16)
4826 dstreg = REG_D0 + RN2 - 12;
4827 else
4828 dstreg = REG_E0 + RN2;
4829
4830 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
4831 }
4832
4833 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
4834 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
4835 "movhu"
4836 *am33
4837 {
4838 int srcreg;
4839
4840 PC = cia;
4841
4842 if (RM2 > 7 && RM2 < 12)
4843 srcreg = REG_A0 + RM2 - 8;
4844 else if (RM2 > 11 && RM2 < 16)
4845 srcreg = REG_D0 + RM2 - 12;
4846 else
4847 srcreg = REG_E0 + RM2;
4848
4849 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
4850 }
4851
4852
4853 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
4854 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
4855 "mov"
4856 *am33
4857 {
4858 int dstreg;
4859
4860 PC = cia;
4861
4862 if (RN0 > 7 && RN0 < 12)
4863 dstreg = REG_A0 + RN0 - 8;
4864 else if (RN0 > 11 && RN0 < 16)
4865 dstreg = REG_D0 + RN0 - 12;
4866 else
4867 dstreg = REG_E0 + RN0;
4868
4869 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4870 }
4871
4872 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
4873 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
4874 "movu"
4875 *am33
4876 {
4877 int dstreg;
4878
4879 PC = cia;
4880
4881 if (RN0 > 7 && RN0 < 12)
4882 dstreg = REG_A0 + RN0 - 8;
4883 else if (RN0 > 11 && RN0 < 16)
4884 dstreg = REG_D0 + RN0 - 12;
4885 else
4886 dstreg = REG_E0 + RN0;
4887
4888 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4889 }
4890
4891 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
4892 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
4893 "add"
4894 *am33
4895 {
4896 int dstreg;
4897
4898 PC = cia;
4899
4900 if (RN0 > 7 && RN0 < 12)
4901 dstreg = REG_A0 + RN0 - 8;
4902 else if (RN0 > 11 && RN0 < 16)
4903 dstreg = REG_D0 + RN0 - 12;
4904 else
4905 dstreg = REG_E0 + RN0;
4906
4907 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4908 }
4909
4910 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
4911 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
4912 "addc"
4913 *am33
4914 {
4915 int dstreg;
4916 unsigned int imm, reg2, sum;
4917 int z, n, c, v;
4918
4919 PC = cia;
4920
4921 if (RN0 > 7 && RN0 < 12)
4922 dstreg = REG_A0 + RN0 - 8;
4923 else if (RN0 > 11 && RN0 < 16)
4924 dstreg = REG_D0 + RN0 - 12;
4925 else
4926 dstreg = REG_E0 + RN0;
4927
4928 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4929 reg2 = State.regs[dstreg];
4930 sum = imm + reg2 + ((PSW & PSW_C) != 0);
4931 State.regs[dstreg] = sum;
4932
4933 z = (sum == 0);
4934 n = (sum & 0x80000000);
4935 c = (sum < imm) || (sum < reg2);
4936 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4937 && (reg2 & 0x80000000) != (sum & 0x80000000));
4938
4939 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4940 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4941 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4942 }
4943
4944 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
4945 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4946 "sub"
4947 *am33
4948 {
4949 int dstreg;
4950
4951 PC = cia;
4952
4953 if (RN0 > 7 && RN0 < 12)
4954 dstreg = REG_A0 + RN0 - 8;
4955 else if (RN0 > 11 && RN0 < 16)
4956 dstreg = REG_D0 + RN0 - 12;
4957 else
4958 dstreg = REG_E0 + RN0;
4959
4960 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4961 }
4962
4963 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4964 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4965 "subc"
4966 *am33
4967 {
4968 int dstreg;
4969 unsigned int imm, reg2, difference;
4970 int z, n, c, v;
4971
4972 PC = cia;
4973
4974 if (RN0 > 7 && RN0 < 12)
4975 dstreg = REG_A0 + RN0 - 8;
4976 else if (RN0 > 11 && RN0 < 16)
4977 dstreg = REG_D0 + RN0 - 12;
4978 else
4979 dstreg = REG_E0 + RN0;
4980
4981 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4982 reg2 = State.regs[dstreg];
4983 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4984 State.regs[dstreg] = difference;
4985
4986 z = (difference == 0);
4987 n = (difference & 0x80000000);
4988 c = (imm > reg2);
4989 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4990 && (reg2 & 0x80000000) != (difference & 0x80000000));
4991
4992 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4993 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4994 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4995 }
4996
4997 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4998 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4999 "cmp"
5000 *am33
5001 {
5002 int srcreg;
5003
5004 PC = cia;
5005
5006 if (RN0 > 7 && RN0 < 12)
5007 srcreg = REG_A0 + RN0 - 8;
5008 else if (RN0 > 11 && RN0 < 16)
5009 srcreg = REG_D0 + RN0 - 12;
5010 else
5011 srcreg = REG_E0 + RN0;
5012
5013 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
5014 }
5015
5016 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
5017 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
5018 "mov"
5019 *am33
5020 {
5021 int dstreg;
5022
5023 PC = cia;
5024
5025 if (XRN0 == 0)
5026 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
5027 else
5028 abort ();
5029 }
5030
5031 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
5032 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
5033 "and"
5034 *am33
5035 {
5036 int dstreg;
5037 int z,n;
5038
5039 PC = cia;
5040
5041 if (RN0 > 7 && RN0 < 12)
5042 dstreg = REG_A0 + RN0 - 8;
5043 else if (RN0 > 11 && RN0 < 16)
5044 dstreg = REG_D0 + RN0 - 12;
5045 else
5046 dstreg = REG_E0 + RN0;
5047
5048 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5049 z = (State.regs[dstreg] == 0);
5050 n = (State.regs[dstreg] & 0x80000000) != 0;
5051 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
5052 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
5053 }
5054
5055 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
5056 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
5057 "or"
5058 *am33
5059 {
5060 int dstreg;
5061 int z,n;
5062
5063 PC = cia;
5064
5065 if (RN0 > 7 && RN0 < 12)
5066 dstreg = REG_A0 + RN0 - 8;
5067 else if (RN0 > 11 && RN0 < 16)
5068 dstreg = REG_D0 + RN0 - 12;
5069 else
5070 dstreg = REG_E0 + RN0;
5071
5072 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5073 z = (State.regs[dstreg] == 0);
5074 n = (State.regs[dstreg] & 0x80000000) != 0;
5075 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
5076 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
5077 }
5078
5079 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
5080 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
5081 "xor"
5082 *am33
5083 {
5084 int dstreg;
5085 int z,n;
5086
5087 PC = cia;
5088
5089 if (RN0 > 7 && RN0 < 12)
5090 dstreg = REG_A0 + RN0 - 8;
5091 else if (RN0 > 11 && RN0 < 16)
5092 dstreg = REG_D0 + RN0 - 12;
5093 else
5094 dstreg = REG_E0 + RN0;
5095
5096 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5097 z = (State.regs[dstreg] == 0);
5098 n = (State.regs[dstreg] & 0x80000000) != 0;
5099 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
5100 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
5101 }
5102
5103 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
5104 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
5105 "asr"
5106 *am33
5107 {
5108 int dstreg;
5109 long temp;
5110 int c, z, n;
5111
5112 PC = cia;
5113
5114 if (RN0 > 7 && RN0 < 12)
5115 dstreg = REG_A0 + RN0 - 8;
5116 else if (RN0 > 11 && RN0 < 16)
5117 dstreg = REG_D0 + RN0 - 12;
5118 else
5119 dstreg = REG_E0 + RN0;
5120
5121 temp = State.regs[dstreg];
5122 c = temp & 1;
5123 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5124 State.regs[dstreg] = temp;
5125 z = (State.regs[dstreg] == 0);
5126 n = (State.regs[dstreg] & 0x80000000) != 0;
5127 PSW &= ~(PSW_Z | PSW_N | PSW_C);
5128 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
5129 }
5130
5131 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
5132 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
5133 "lsr"
5134 *am33
5135 {
5136 int dstreg;
5137 int z, n, c;
5138
5139 PC = cia;
5140
5141 if (RN0 > 7 && RN0 < 12)
5142 dstreg = REG_A0 + RN0 - 8;
5143 else if (RN0 > 11 && RN0 < 16)
5144 dstreg = REG_D0 + RN0 - 12;
5145 else
5146 dstreg = REG_E0 + RN0;
5147
5148 c = State.regs[dstreg] & 1;
5149 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5150 z = (State.regs[dstreg] == 0);
5151 n = (State.regs[dstreg] & 0x80000000) != 0;
5152 PSW &= ~(PSW_Z | PSW_N | PSW_C);
5153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
5154 }
5155
5156 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
5157 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
5158 "asl"
5159 *am33
5160 {
5161 int srcreg, dstreg;
5162 int z, n;
5163
5164 PC = cia;
5165
5166 if (RN0 > 7 && RN0 < 12)
5167 dstreg = REG_A0 + RN0 - 8;
5168 else if (RN0 > 11 && RN0 < 16)
5169 dstreg = REG_D0 + RN0 - 12;
5170 else
5171 dstreg = REG_E0 + RN0;
5172
5173 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5174 z = (State.regs[dstreg] == 0);
5175 n = (State.regs[dstreg] & 0x80000000) != 0;
5176 PSW &= ~(PSW_Z | PSW_N);
5177 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
5178 }
5179
5180 // ??? mul
5181 // ??? mulu
5182
5183 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
5184 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
5185 "btst"
5186 *am33
5187 {
5188 int srcreg;
5189
5190 PC = cia;
5191
5192 if (RN0 > 7 && RN0 < 12)
5193 srcreg = REG_A0 + RN0 - 8;
5194 else if (RN0 > 11 && RN0 < 16)
5195 srcreg = REG_D0 + RN0 - 12;
5196 else
5197 srcreg = REG_E0 + RN0;
5198
5199 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
5200 }
5201
5202 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
5203 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
5204 "mov"
5205 *am33
5206 {
5207 int srcreg, dstreg;
5208
5209 PC = cia;
5210
5211 if (RM0 > 7 && RM0 < 12)
5212 srcreg = REG_A0 + RM0 - 8;
5213 else if (RM0 > 11 && RM0 < 16)
5214 srcreg = REG_D0 + RM0 - 12;
5215 else
5216 srcreg = REG_E0 + RM0;
5217
5218 if (RN2 > 7 && RN2 < 12)
5219 dstreg = REG_A0 + RN2 - 8;
5220 else if (RN2 > 11 && RN2 < 16)
5221 dstreg = REG_D0 + RN2 - 12;
5222 else
5223 dstreg = REG_E0 + RN2;
5224
5225 State.regs[dstreg] = load_word (State.regs[srcreg]
5226 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5227 }
5228
5229 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
5230 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
5231 "mov"
5232 *am33
5233 {
5234 int srcreg, dstreg;
5235
5236 PC = cia;
5237
5238 if (RM2 > 7 && RM2 < 12)
5239 srcreg = REG_A0 + RM2 - 8;
5240 else if (RM2 > 11 && RM2 < 16)
5241 srcreg = REG_D0 + RM2 - 12;
5242 else
5243 srcreg = REG_E0 + RM2;
5244
5245 if (RN0 > 7 && RN0 < 12)
5246 dstreg = REG_A0 + RN0 - 8;
5247 else if (RN0 > 11 && RN0 < 16)
5248 dstreg = REG_D0 + RN0 - 12;
5249 else
5250 dstreg = REG_E0 + RN0;
5251
5252 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5253 State.regs[srcreg]);
5254 }
5255
5256 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
5257 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
5258 "movbu"
5259 *am33
5260 {
5261 int srcreg, dstreg;
5262
5263 PC = cia;
5264
5265 if (RM0 > 7 && RM0 < 12)
5266 srcreg = REG_A0 + RM0 - 8;
5267 else if (RM0 > 11 && RM0 < 16)
5268 srcreg = REG_D0 + RM0 - 12;
5269 else
5270 srcreg = REG_E0 + RM0;
5271
5272 if (RN2 > 7 && RN2 < 12)
5273 dstreg = REG_A0 + RN2 - 8;
5274 else if (RN2 > 11 && RN2 < 16)
5275 dstreg = REG_D0 + RN2 - 12;
5276 else
5277 dstreg = REG_E0 + RN2;
5278
5279 State.regs[dstreg] = load_byte (State.regs[srcreg]
5280 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5281 }
5282
5283 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
5284 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
5285 "movbu"
5286 *am33
5287 {
5288 int srcreg, dstreg;
5289
5290 PC = cia;
5291
5292 if (RM2 > 7 && RM2 < 12)
5293 srcreg = REG_A0 + RM2 - 8;
5294 else if (RM2 > 11 && RM2 < 16)
5295 srcreg = REG_D0 + RM2 - 12;
5296 else
5297 srcreg = REG_E0 + RM2;
5298
5299 if (RN0 > 7 && RN0 < 12)
5300 dstreg = REG_A0 + RN0 - 8;
5301 else if (RN0 > 11 && RN0 < 16)
5302 dstreg = REG_D0 + RN0 - 12;
5303 else
5304 dstreg = REG_E0 + RN0;
5305
5306 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5307 State.regs[srcreg]);
5308 }
5309
5310 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
5311 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
5312 "movhu"
5313 *am33
5314 {
5315 int srcreg, dstreg;
5316
5317 PC = cia;
5318
5319 if (RM0 > 7 && RM0 < 12)
5320 srcreg = REG_A0 + RM0 - 8;
5321 else if (RM0 > 11 && RM0 < 16)
5322 srcreg = REG_D0 + RM0 - 12;
5323 else
5324 srcreg = REG_E0 + RM0;
5325
5326 if (RN2 > 7 && RN2 < 12)
5327 dstreg = REG_A0 + RN2 - 8;
5328 else if (RN2 > 11 && RN2 < 16)
5329 dstreg = REG_D0 + RN2 - 12;
5330 else
5331 dstreg = REG_E0 + RN2;
5332
5333 State.regs[dstreg] = load_half (State.regs[srcreg]
5334 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5335 }
5336
5337 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
5338 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
5339 "movhu"
5340 *am33
5341 {
5342 int srcreg, dstreg;
5343
5344 PC = cia;
5345
5346 if (RM2 > 7 && RM2 < 12)
5347 srcreg = REG_A0 + RM2 - 8;
5348 else if (RM2 > 11 && RM2 < 16)
5349 srcreg = REG_D0 + RM2 - 12;
5350 else
5351 srcreg = REG_E0 + RM2;
5352
5353 if (RN0 > 7 && RN0 < 12)
5354 dstreg = REG_A0 + RN0 - 8;
5355 else if (RN0 > 11 && RN0 < 16)
5356 dstreg = REG_D0 + RN0 - 12;
5357 else
5358 dstreg = REG_E0 + RN0;
5359
5360 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5361 State.regs[srcreg]);
5362 }
5363
5364 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
5365 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
5366 "mov"
5367 *am33
5368 {
5369 int srcreg, dstreg;
5370
5371 PC = cia;
5372
5373 if (RM0 > 7 && RM0 < 12)
5374 srcreg = REG_A0 + RM0 - 8;
5375 else if (RM0 > 11 && RM0 < 16)
5376 srcreg = REG_D0 + RM0 - 12;
5377 else
5378 srcreg = REG_E0 + RM0;
5379
5380 if (RN2 > 7 && RN2 < 12)
5381 dstreg = REG_A0 + RN2 - 8;
5382 else if (RN2 > 11 && RN2 < 16)
5383 dstreg = REG_D0 + RN2 - 12;
5384 else
5385 dstreg = REG_E0 + RN2;
5386
5387 State.regs[dstreg] = load_word (State.regs[srcreg]
5388 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5389 State.regs[srcreg] += 4;
5390 }
5391
5392 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
5393 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
5394 "mov"
5395 *am33
5396 {
5397 int srcreg, dstreg;
5398
5399 PC = cia;
5400
5401 if (RM2 > 7 && RM2 < 12)
5402 srcreg = REG_A0 + RM2 - 8;
5403 else if (RM2 > 11 && RM2 < 16)
5404 srcreg = REG_D0 + RM2 - 12;
5405 else
5406 srcreg = REG_E0 + RM2;
5407
5408 if (RN0 > 7 && RN0 < 12)
5409 dstreg = REG_A0 + RN0 - 8;
5410 else if (RN0 > 11 && RN0 < 16)
5411 dstreg = REG_D0 + RN0 - 12;
5412 else
5413 dstreg = REG_E0 + RN0;
5414
5415 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5416 State.regs[srcreg]);
5417 State.regs[dstreg] += 4;
5418 }
5419
5420
5421 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
5422 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
5423 "mov"
5424 *am33
5425 {
5426 int dstreg;
5427
5428 PC = cia;
5429
5430 if (RN2 > 7 && RN2 < 12)
5431 dstreg = REG_A0 + RN2 - 8;
5432 else if (RN2 > 11 && RN2 < 16)
5433 dstreg = REG_D0 + RN2 - 12;
5434 else
5435 dstreg = REG_E0 + RN2;
5436
5437 State.regs[dstreg] = load_word (State.regs[REG_SP]
5438 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5439 }
5440
5441 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
5442 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
5443 "mov"
5444 *am33
5445 {
5446 int srcreg;
5447
5448 PC = cia;
5449
5450 if (RM2 > 7 && RM2 < 12)
5451 srcreg = REG_A0 + RM2 - 8;
5452 else if (RM2 > 11 && RM2 < 16)
5453 srcreg = REG_D0 + RM2 - 12;
5454 else
5455 srcreg = REG_E0 + RM2;
5456
5457 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5458 State.regs[srcreg]);
5459 }
5460
5461 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
5462 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
5463 "movbu"
5464 *am33
5465 {
5466 int dstreg;
5467
5468 PC = cia;
5469
5470 if (RN2 > 7 && RN2 < 12)
5471 dstreg = REG_A0 + RN2 - 8;
5472 else if (RN2 > 11 && RN2 < 16)
5473 dstreg = REG_D0 + RN2 - 12;
5474 else
5475 dstreg = REG_E0 + RN2;
5476
5477 State.regs[dstreg] = load_byte (State.regs[REG_SP]
5478 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5479 }
5480
5481 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
5482 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
5483 "movbu"
5484 *am33
5485 {
5486 int srcreg;
5487
5488 PC = cia;
5489
5490 if (RM2 > 7 && RM2 < 12)
5491 srcreg = REG_A0 + RM2 - 8;
5492 else if (RM2 > 11 && RM2 < 16)
5493 srcreg = REG_D0 + RM2 - 12;
5494 else
5495 srcreg = REG_E0 + RM2;
5496
5497 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5498 State.regs[srcreg]);
5499 }
5500
5501 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
5502 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
5503 "movhu"
5504 *am33
5505 {
5506 int dstreg;
5507
5508 PC = cia;
5509
5510 if (RN2 > 7 && RN2 < 12)
5511 dstreg = REG_A0 + RN2 - 8;
5512 else if (RN2 > 11 && RN2 < 16)
5513 dstreg = REG_D0 + RN2 - 12;
5514 else
5515 dstreg = REG_E0 + RN2;
5516
5517 State.regs[dstreg] = load_half (State.regs[REG_SP]
5518 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5519 }
5520
5521 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
5522 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
5523 "movhu"
5524 *am33
5525 {
5526 int srcreg;
5527
5528 PC = cia;
5529
5530 if (RM2 > 7 && RM2 < 12)
5531 srcreg = REG_A0 + RM2 - 8;
5532 else if (RM2 > 11 && RM2 < 16)
5533 srcreg = REG_D0 + RM2 - 12;
5534 else
5535 srcreg = REG_E0 + RM2;
5536
5537 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5538 State.regs[srcreg]);
5539 }
5540
5541
5542 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
5543 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
5544 "movhu"
5545 *am33
5546 {
5547 int srcreg, dstreg;
5548
5549 PC = cia;
5550
5551 if (RM0 > 7 && RM0 < 12)
5552 srcreg = REG_A0 + RM0 - 8;
5553 else if (RM0 > 11 && RM0 < 16)
5554 srcreg = REG_D0 + RM0 - 12;
5555 else
5556 srcreg = REG_E0 + RM0;
5557
5558 if (RN2 > 7 && RN2 < 12)
5559 dstreg = REG_A0 + RN2 - 8;
5560 else if (RN2 > 11 && RN2 < 16)
5561 dstreg = REG_D0 + RN2 - 12;
5562 else
5563 dstreg = REG_E0 + RN2;
5564
5565 State.regs[dstreg] = load_half (State.regs[srcreg]
5566 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5567 State.regs[srcreg] += 2;
5568 }
5569
5570 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
5571 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
5572 "movhu"
5573 *am33
5574 {
5575 int srcreg, dstreg;
5576
5577 PC = cia;
5578
5579 if (RM2 > 7 && RM2 < 12)
5580 srcreg = REG_A0 + RM2 - 8;
5581 else if (RM2 > 11 && RM2 < 16)
5582 srcreg = REG_D0 + RM2 - 12;
5583 else
5584 srcreg = REG_E0 + RM2;
5585
5586 if (RN0 > 7 && RN0 < 12)
5587 dstreg = REG_A0 + RN0 - 8;
5588 else if (RN0 > 11 && RN0 < 16)
5589 dstreg = REG_D0 + RN0 - 12;
5590 else
5591 dstreg = REG_E0 + RN0;
5592
5593 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
5594 State.regs[srcreg]);
5595 State.regs[dstreg] += 2;
5596 }
5597
5598
5599 // ??? mac
5600 // ??? macu
5601 // ??? macb
5602 // ??? macbu
5603 // ??? mach
5604 // ??? machu
5605 // ??? dmach
5606 // ??? dmachu
5607 // ??? dmulh
5608 // ??? dmulhu
5609
5610 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
5611 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
5612 "mov"
5613 *am33
5614 {
5615 int dstreg;
5616
5617 PC = cia;
5618
5619 if (RN2 > 7 && RN2 < 12)
5620 dstreg = REG_A0 + RN2 - 8;
5621 else if (RN2 > 11 && RN2 < 16)
5622 dstreg = REG_D0 + RN2 - 12;
5623 else
5624 dstreg = REG_E0 + RN2;
5625
5626 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5627 }
5628
5629 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
5630 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
5631 "mov"
5632 *am33
5633 {
5634 int srcreg;
5635
5636 PC = cia;
5637
5638 if (RM2 > 7 && RM2 < 12)
5639 srcreg = REG_A0 + RM2 - 8;
5640 else if (RM2 > 11 && RM2 < 16)
5641 srcreg = REG_D0 + RM2 - 12;
5642 else
5643 srcreg = REG_E0 + RM2;
5644
5645 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
5646 }
5647
5648 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
5649 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
5650 "movbu"
5651 *am33
5652 {
5653 int dstreg;
5654
5655 PC = cia;
5656
5657 if (RN2 > 7 && RN2 < 12)
5658 dstreg = REG_A0 + RN2 - 8;
5659 else if (RN2 > 11 && RN2 < 16)
5660 dstreg = REG_D0 + RN2 - 12;
5661 else
5662 dstreg = REG_E0 + RN2;
5663
5664 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5665 }
5666
5667 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
5668 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
5669 "movbu"
5670 *am33
5671 {
5672 int srcreg;
5673
5674 PC = cia;
5675
5676 if (RM2 > 7 && RM2 < 12)
5677 srcreg = REG_A0 + RM2 - 8;
5678 else if (RM2 > 11 && RM2 < 16)
5679 srcreg = REG_D0 + RM2 - 12;
5680 else
5681 srcreg = REG_E0 + RM2;
5682
5683 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
5684 }
5685
5686 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
5687 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
5688 "movhu"
5689 *am33
5690 {
5691 int dstreg;
5692
5693 PC = cia;
5694
5695 if (RN2 > 7 && RN2 < 12)
5696 dstreg = REG_A0 + RN2 - 8;
5697 else if (RN2 > 11 && RN2 < 16)
5698 dstreg = REG_D0 + RN2 - 12;
5699 else
5700 dstreg = REG_E0 + RN2;
5701
5702 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
5703 }
5704
5705 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
5706 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
5707 "movhu"
5708 *am33
5709 {
5710 int srcreg;
5711
5712 PC = cia;
5713
5714 if (RM2 > 7 && RM2 < 12)
5715 srcreg = REG_A0 + RM2 - 8;
5716 else if (RM2 > 11 && RM2 < 16)
5717 srcreg = REG_D0 + RM2 - 12;
5718 else
5719 srcreg = REG_E0 + RM2;
5720
5721 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
5722 }
5723
5724 // DSP
GDB Binutils - Deliverables
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