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* am33.igen: Add many more am33 instructions.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // 1111 0000 0010 00An; mov USP,An
2 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
3 "mov"
4 *am33
5 {
6 PC = cia;
7 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
8 }
9
10
11 // 1111 0000 0010 01An; mov SSP,An
12 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
13 "mov"
14 *am33
15 {
16 PC = cia;
17 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
18 }
19
20
21 // 1111 0000 0010 10An; mov MSP,An
22 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
23 "mov"
24 *am33
25 {
26 PC = cia;
27 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
28 }
29
30
31 // 1111 0000 0010 11An; mov PC,An
32 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
33 "mov"
34 *am33
35 {
36 PC = cia;
37 State.regs[REG_A0 + AN0] = PC;
38 }
39
40
41 // 1111 0000 0011 Am00; mov Am,USP
42 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
43 "mov"
44 *am33
45 {
46 PC = cia;
47 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
48 }
49
50 // 1111 0000 0011 Am01; mov Am,SSP
51 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
52 "mov"
53 *am33
54 {
55 PC = cia;
56 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
57 }
58
59 // 1111 0000 0011 Am10; mov Am,MSP
60 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
61 "mov"
62 *am33
63 {
64 PC = cia;
65 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
66 }
67
68
69 // 1111 0000 1110 imm4; syscall
70 8.0xf0+4.0xe,IMM4:D0t:::syscall
71 "syscall"
72 *am33
73 {
74 unsigned int sp, next_pc;
75
76 PC = cia;
77 sp = State.regs[REG_SP];
78 next_pc = State.regs[REG_PC] + 2;
79 store_word (sp - 4, next_pc);
80 store_word (sp - 8, PSW);
81 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
82 nia = PC;
83 }
84
85
86 // 1111 0010 1110 11Dn; mov EPSW,Dn
87 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
88 "mov"
89 *am33
90 {
91 PC = cia;
92 State.regs[REG_D0 + DN0] = PSW;
93 }
94
95
96 // 1111 0010 1111 Dm01; mov Dm,EPSW
97 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
98 "mov"
99 *am33
100 {
101 PC = cia;
102 PSW = State.regs[REG_D0 + DM1];
103 }
104
105 // 1111 0101 00Am Rn; mov Am,Rn
106 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
107 "mov"
108 *am33
109 {
110 PC = cia;
111 /* The higher register numbers actually correspond to the
112 basic machine's address and data registers. */
113 if (RN0 > 7 && RN0 < 12)
114 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_A0 + AM1];
115 else if (RN0 > 11 && RN0 < 16)
116 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_A0 + AM1];
117 else
118 State.regs[REG_E0 + RN0] = State.regs[REG_A0 + AM1] ;
119 }
120
121 // 1111 0101 01Dm Rn; mov Dm,Rn
122 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
123 "mov"
124 *am33
125 {
126 PC = cia;
127 /* The higher register numbers actually correspond to the
128 basic machine's address and data registers. */
129 if (RN0 > 7 && RN0 < 12)
130 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_D0 + DM1];
131 else if (RN0 > 11 && RN0 < 16)
132 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_D0 + DM1];
133 else
134 State.regs[REG_E0 + RN0] = State.regs[REG_D0 + DM1] ;
135 }
136
137 // 1111 0101 10Rm An; mov Rm,An
138 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
139 "mov"
140 *am33
141 {
142 PC = cia;
143 /* The higher register numbers actually correspond to the
144 basic machine's address and data registers. */
145 if (RM1 > 7 && RM1 < 12)
146 State.regs[REG_A0 + AN0] = State.regs[REG_A0 + RM1 - 8];
147 else if (RM1 > 11 && RM1 < 16)
148 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + RM1 - 12];
149 else
150 State.regs[REG_A0 + AN0] = State.regs[REG_E0 + RM1];
151 }
152
153 // 1111 0101 11Rm Dn; mov Rm,Dn
154 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
155 "mov"
156 *am33
157 {
158 PC = cia;
159 /* The higher register numbers actually correspond to the
160 basic machine's address and data registers. */
161 if (RM1 > 7 && RM1 < 12)
162 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + RM1 - 8];
163 else if (RM1 > 11 && RM1 < 16)
164 State.regs[REG_D0 + DN0] = State.regs[REG_D0 + RM1 - 12];
165 else
166 State.regs[REG_D0 + DN0] = State.regs[REG_E0 + RM1];
167 }
168
169
170 // 1111 1000 1100 1110 regs....; movm (USP),regs
171 8.0xf8+8.0xce+8.REGS:D1a:::movm
172 "movm"
173 *am33
174 {
175 unsigned long usp = State.regs[REG_USP];
176 unsigned long mask;
177
178 PC = cia;
179 mask = REGS;
180
181 if (mask & 0x8)
182 {
183 usp += 4;
184 State.regs[REG_LAR] = load_word (usp);
185 usp += 4;
186 State.regs[REG_LIR] = load_word (usp);
187 usp += 4;
188 State.regs[REG_MDR] = load_word (usp);
189 usp += 4;
190 State.regs[REG_A0 + 1] = load_word (usp);
191 usp += 4;
192 State.regs[REG_A0] = load_word (usp);
193 usp += 4;
194 State.regs[REG_D0 + 1] = load_word (usp);
195 usp += 4;
196 State.regs[REG_D0] = load_word (usp);
197 usp += 4;
198 }
199
200 if (mask & 0x10)
201 {
202 State.regs[REG_A0 + 3] = load_word (usp);
203 usp += 4;
204 }
205
206 if (mask & 0x20)
207 {
208 State.regs[REG_A0 + 2] = load_word (usp);
209 usp += 4;
210 }
211
212 if (mask & 0x40)
213 {
214 State.regs[REG_D0 + 3] = load_word (usp);
215 usp += 4;
216 }
217
218 if (mask & 0x80)
219 {
220 State.regs[REG_D0 + 2] = load_word (usp);
221 usp += 4;
222 }
223
224 /* start-sanitize-am33 */
225 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
226 {
227 if (mask & 0x1)
228 {
229 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
230 usp += 16;
231 State.regs[REG_E0 + 1] = load_word (usp);
232 usp += 4;
233 State.regs[REG_E0 + 0] = load_word (usp);
234 usp += 4;
235 }
236
237 if (mask & 0x2)
238 {
239 State.regs[REG_E0 + 7] = load_word (usp);
240 usp += 4;
241 State.regs[REG_E0 + 6] = load_word (usp);
242 usp += 4;
243 State.regs[REG_E0 + 5] = load_word (usp);
244 usp += 4;
245 State.regs[REG_E0 + 4] = load_word (usp);
246 usp += 4;
247 }
248
249 if (mask & 0x4)
250 {
251 State.regs[REG_E0 + 3] = load_word (usp);
252 usp += 4;
253 State.regs[REG_E0 + 2] = load_word (usp);
254 usp += 4;
255 }
256 }
257 /* end-sanitize-am33 */
258
259 /* And make sure to update the stack pointer. */
260 State.regs[REG_USP] = usp;
261 }
262
263 // 1111 1000 1100 1111 regs....; movm (USP),regs
264 8.0xf8+8.0xcf+8.REGS:D1b:::movm
265 "movm"
266 *am33
267 {
268 unsigned long usp = State.regs[REG_USP];
269 unsigned long mask;
270
271 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
272 {
273 if (mask & 0x4)
274 {
275 usp -= 4;
276 store_word (usp, State.regs[REG_E0 + 2]);
277 usp -= 4;
278 store_word (usp, State.regs[REG_E0 + 3]);
279 }
280
281 if (mask & 0x2)
282 {
283 usp -= 4;
284 store_word (usp, State.regs[REG_E0 + 4]);
285 usp -= 4;
286 store_word (usp, State.regs[REG_E0 + 5]);
287 usp -= 4;
288 store_word (usp, State.regs[REG_E0 + 6]);
289 usp -= 4;
290 store_word (usp, State.regs[REG_E0 + 7]);
291 }
292
293 if (mask & 0x1)
294 {
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 0]);
297 usp -= 4;
298 store_word (usp, State.regs[REG_E0 + 1]);
299 usp -= 16;
300 /* Need to save MDQR, MCRH, MCRL, and MCVF */
301 }
302 }
303 /* end-sanitize-am33 */
304
305 if (mask & 0x80)
306 {
307 usp -= 4;
308 store_word (usp, State.regs[REG_D0 + 2]);
309 }
310
311 if (mask & 0x40)
312 {
313 usp -= 4;
314 store_word (usp, State.regs[REG_D0 + 3]);
315 }
316
317 if (mask & 0x20)
318 {
319 usp -= 4;
320 store_word (usp, State.regs[REG_A0 + 2]);
321 }
322
323 if (mask & 0x10)
324 {
325 usp -= 4;
326 store_word (usp, State.regs[REG_A0 + 3]);
327 }
328
329 if (mask & 0x8)
330 {
331 usp -= 4;
332 store_word (usp, State.regs[REG_D0]);
333 usp -= 4;
334 store_word (usp, State.regs[REG_D0 + 1]);
335 usp -= 4;
336 store_word (usp, State.regs[REG_A0]);
337 usp -= 4;
338 store_word (usp, State.regs[REG_A0 + 1]);
339 usp -= 4;
340 store_word (usp, State.regs[REG_MDR]);
341 usp -= 4;
342 store_word (usp, State.regs[REG_LIR]);
343 usp -= 4;
344 store_word (usp, State.regs[REG_LAR]);
345 usp -= 4;
346 }
347
348 /* And make sure to update the stack pointer. */
349 State.regs[REG_USP] = usp;
350 }
351
352 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
353 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
354 "and"
355 *am33
356 {
357 PC = cia;
358 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
359 }
360
361 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
362 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
363 "or"
364 *am33
365 {
366 PC = cia;
367 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
368 }
369
370 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
371 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
372 "mov"
373 *am33
374 {
375 int srcreg, dstreg;
376
377 PC = cia;
378
379 if (RM2 > 7 && RM2 < 12)
380 srcreg = REG_A0 + RM2 - 8;
381 else if (RM2 > 11 && RM2 < 16)
382 srcreg = REG_D0 + RM2 - 12;
383 else
384 srcreg = REG_E0 + RM2;
385
386 if (RN0 > 7 && RN0 < 12)
387 dstreg = REG_A0 + RN0 - 8;
388 else if (RN0 > 11 && RN0 < 16)
389 dstreg = REG_D0 + RN0 - 12;
390 else
391 dstreg = REG_E0 + RN0;
392
393 State.regs[dstreg] = State.regs[srcreg];
394 }
395
396 // 1111 1001 0001 1000 Rn Rn; ext Rn
397 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
398 "mov"
399 *am33
400 {
401 int srcreg, dstreg;
402
403 PC = cia;
404
405 if (RN0 > 7 && RN0 < 12)
406 srcreg = REG_A0 + RN0 - 8;
407 else if (RN0 > 11 && RN0 < 16)
408 srcreg = REG_D0 + RN0 - 12;
409 else
410 srcreg = REG_E0 + RN0;
411
412 if (State.regs[srcreg] & 0x80000000)
413 State.regs[REG_MDR] = -1;
414 else
415 State.regs[REG_MDR] = 0;
416 }
417
418 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
419 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
420 "extb"
421 *am33
422 {
423 int srcreg, dstreg;
424
425 PC = cia;
426
427 if (RM2 > 7 && RM2 < 12)
428 srcreg = REG_A0 + RM2 - 8;
429 else if (RM2 > 11 && RM2 < 16)
430 srcreg = REG_D0 + RM2 - 12;
431 else
432 srcreg = REG_E0 + RM2;
433
434 if (RN0 > 7 && RN0 < 12)
435 dstreg = REG_A0 + RN0 - 8;
436 else if (RN0 > 11 && RN0 < 16)
437 dstreg = REG_D0 + RN0 - 12;
438 else
439 dstreg = REG_E0 + RN0;
440
441 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
442 }
443
444 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
445 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
446 "extbu"
447 *am33
448 {
449 int srcreg, dstreg;
450
451 PC = cia;
452
453 if (RM2 > 7 && RM2 < 12)
454 srcreg = REG_A0 + RM2 - 8;
455 else if (RM2 > 11 && RM2 < 16)
456 srcreg = REG_D0 + RM2 - 12;
457 else
458 srcreg = REG_E0 + RM2;
459
460 if (RN0 > 7 && RN0 < 12)
461 dstreg = REG_A0 + RN0 - 8;
462 else if (RN0 > 11 && RN0 < 16)
463 dstreg = REG_D0 + RN0 - 12;
464 else
465 dstreg = REG_E0 + RN0;
466
467 State.regs[dstreg] = State.regs[srcreg] & 0xff;
468 }
469
470 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
471 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
472 "exth"
473 *am33
474 {
475 int srcreg, dstreg;
476
477 PC = cia;
478
479 if (RM2 > 7 && RM2 < 12)
480 srcreg = REG_A0 + RM2 - 8;
481 else if (RM2 > 11 && RM2 < 16)
482 srcreg = REG_D0 + RM2 - 12;
483 else
484 srcreg = REG_E0 + RM2;
485
486 if (RN0 > 7 && RN0 < 12)
487 dstreg = REG_A0 + RN0 - 8;
488 else if (RN0 > 11 && RN0 < 16)
489 dstreg = REG_D0 + RN0 - 12;
490 else
491 dstreg = REG_E0 + RN0;
492
493 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
494 }
495
496 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
497 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
498 "exthu"
499 *am33
500 {
501 int srcreg, dstreg;
502
503 PC = cia;
504
505 if (RM2 > 7 && RM2 < 12)
506 srcreg = REG_A0 + RM2 - 8;
507 else if (RM2 > 11 && RM2 < 16)
508 srcreg = REG_D0 + RM2 - 12;
509 else
510 srcreg = REG_E0 + RM2;
511
512 if (RN0 > 7 && RN0 < 12)
513 dstreg = REG_A0 + RN0 - 8;
514 else if (RN0 > 11 && RN0 < 16)
515 dstreg = REG_D0 + RN0 - 12;
516 else
517 dstreg = REG_E0 + RN0;
518
519 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
520 }
521
522 // 1111 1001 0110 1000 Rn Rn; clr Rn
523 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
524 "clr"
525 *am33
526 {
527 int srcreg, dstreg;
528
529 PC = cia;
530
531 if (RN0 > 7 && RN0 < 12)
532 dstreg = REG_A0 + RN0 - 8;
533 else if (RN0 > 11 && RN0 < 16)
534 dstreg = REG_D0 + RN0 - 12;
535 else
536 dstreg = REG_E0 + RN0;
537
538 State.regs[dstreg] = 0;
539
540 PSW |= PSW_Z;
541 PSW &= ~(PSW_V | PSW_C | PSW_N);
542 }
543
544 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
545 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
546 "add"
547 *am33
548 {
549 int srcreg, dstreg;
550
551 PC = cia;
552
553 if (RM2 > 7 && RM2 < 12)
554 srcreg = REG_A0 + RM2 - 8;
555 else if (RM2 > 11 && RM2 < 16)
556 srcreg = REG_D0 + RM2 - 12;
557 else
558 srcreg = REG_E0 + RM2;
559
560 if (RN0 > 7 && RN0 < 12)
561 dstreg = REG_A0 + RN0 - 8;
562 else if (RN0 > 11 && RN0 < 16)
563 dstreg = REG_D0 + RN0 - 12;
564 else
565 dstreg = REG_E0 + RN0;
566
567 genericAdd (State.regs[srcreg], dstreg);
568 }
569
570 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
571 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
572 "addc"
573 *am33
574 {
575 int srcreg, dstreg;
576 int z, c, n, v;
577 unsigned long reg1, reg2, sum;
578
579 PC = cia;
580
581 if (RM2 > 7 && RM2 < 12)
582 srcreg = REG_A0 + RM2 - 8;
583 else if (RM2 > 11 && RM2 < 16)
584 srcreg = REG_D0 + RM2 - 12;
585 else
586 srcreg = REG_E0 + RM2;
587
588 if (RN0 > 7 && RN0 < 12)
589 dstreg = REG_A0 + RN0 - 8;
590 else if (RN0 > 11 && RN0 < 16)
591 dstreg = REG_D0 + RN0 - 12;
592 else
593 dstreg = REG_E0 + RN0;
594
595 reg1 = State.regs[srcreg];
596 reg2 = State.regs[dstreg];
597 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
598 State.regs[dstreg] = sum;
599
600 z = (sum == 0);
601 n = (sum & 0x80000000);
602 c = (sum < reg1) || (sum < reg2);
603 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
604 && (reg2 & 0x80000000) != (sum & 0x80000000));
605
606 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
607 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
608 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
609 }
610
611 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
612 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
613 "sub"
614 *am33
615 {
616 int srcreg, dstreg;
617
618 PC = cia;
619
620 if (RM2 > 7 && RM2 < 12)
621 srcreg = REG_A0 + RM2 - 8;
622 else if (RM2 > 11 && RM2 < 16)
623 srcreg = REG_D0 + RM2 - 12;
624 else
625 srcreg = REG_E0 + RM2;
626
627 if (RN0 > 7 && RN0 < 12)
628 dstreg = REG_A0 + RN0 - 8;
629 else if (RN0 > 11 && RN0 < 16)
630 dstreg = REG_D0 + RN0 - 12;
631 else
632 dstreg = REG_E0 + RN0;
633
634 genericSub (State.regs[srcreg], dstreg);
635 }
636
637 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
638 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
639 "subc"
640 *am33
641 {
642 int srcreg, dstreg;
643 int z, c, n, v;
644 unsigned long reg1, reg2, difference;
645
646 PC = cia;
647
648 if (RM2 > 7 && RM2 < 12)
649 srcreg = REG_A0 + RM2 - 8;
650 else if (RM2 > 11 && RM2 < 16)
651 srcreg = REG_D0 + RM2 - 12;
652 else
653 srcreg = REG_E0 + RM2;
654
655 if (RN0 > 7 && RN0 < 12)
656 dstreg = REG_A0 + RN0 - 8;
657 else if (RN0 > 11 && RN0 < 16)
658 dstreg = REG_D0 + RN0 - 12;
659 else
660 dstreg = REG_E0 + RN0;
661
662 reg1 = State.regs[srcreg];
663 reg2 = State.regs[dstreg];
664 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
665 State.regs[dstreg] = difference;
666
667 z = (difference == 0);
668 n = (difference & 0x80000000);
669 c = (reg1 > reg2);
670 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
671 && (reg2 & 0x80000000) != (difference & 0x80000000));
672
673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
675 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
676 }
677
678 // 1111 1001 1011 1000 Rn Rn; inc Rn
679 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
680 "inc"
681 *am33
682 {
683 int dstreg;
684
685 PC = cia;
686
687 if (RN0 > 7 && RN0 < 12)
688 dstreg = REG_A0 + RN0 - 8;
689 else if (RN0 > 11 && RN0 < 16)
690 dstreg = REG_D0 + RN0 - 12;
691 else
692 dstreg = REG_E0 + RN0;
693
694 genericAdd (1, dstreg);
695 }
696
697 // 1111 1001 1101 1000 Rn Rn; inc Rn
698 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
699 "inc4"
700 *am33
701 {
702 int dstreg;
703
704 PC = cia;
705
706 if (RN0 > 7 && RN0 < 12)
707 dstreg = REG_A0 + RN0 - 8;
708 else if (RN0 > 11 && RN0 < 16)
709 dstreg = REG_D0 + RN0 - 12;
710 else
711 dstreg = REG_E0 + RN0;
712 State.regs[dstreg] += 4;
713 }
714
715 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
716 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
717 "cmp"
718 *am33
719 {
720 int srcreg1, srcreg2;
721
722 PC = cia;
723
724 if (RN0 > 7 && RN0 < 12)
725 srcreg1 = REG_A0 + RN0 - 8;
726 else if (RN0 > 11 && RN0 < 16)
727 srcreg1 = REG_D0 + RN0 - 12;
728 else
729 srcreg1 = REG_E0 + RN0;
730
731 if (RM2 > 7 && RM2 < 12)
732 srcreg2 = REG_A0 + RM2 - 8;
733 else if (RM2 > 11 && RM2 < 16)
734 srcreg2 = REG_D0 + RM2 - 12;
735 else
736 srcreg2 = REG_E0 + RM2;
737 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
738 }
739
740 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
741 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
742 "mov"
743 *am33
744 {
745 int srcreg, dstreg;
746
747 PC = cia;
748 if (RN0 > 7 && RN0 < 12)
749 dstreg = REG_A0 + RN0 - 8;
750 else if (RN0 > 11 && RN0 < 16)
751 dstreg = REG_D0 + RN0 - 12;
752 else
753 dstreg = REG_E0 + RN0;
754
755 if (XRM2 == 0)
756 {
757 State.regs[dstreg] = State.regs[REG_SP];
758 }
759 else
760 abort ();
761 }
762
763 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
764 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
765 "mov"
766 *am33
767 {
768 int srcreg;
769
770 PC = cia;
771
772 if (RM2 > 7 && RM2 < 12)
773 srcreg = REG_A0 + RM2 - 8;
774 else if (RM2 > 11 && RM2 < 16)
775 srcreg = REG_D0 + RM2 - 12;
776 else
777 srcreg = REG_E0 + RM2;
778
779 if (XRN0 == 0)
780 {
781 State.regs[REG_SP] = State.regs[srcreg];
782 }
783 else
784 abort ();
785 }
786
787 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
788 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
789 "and"
790 *am33
791 {
792 int srcreg, dstreg;
793 int z, n;
794
795 PC = cia;
796
797 if (RM2 > 7 && RM2 < 12)
798 srcreg = REG_A0 + RM2 - 8;
799 else if (RM2 > 11 && RM2 < 16)
800 srcreg = REG_D0 + RM2 - 12;
801 else
802 srcreg = REG_E0 + RM2;
803
804 if (RN0 > 7 && RN0 < 12)
805 dstreg = REG_A0 + RN0 - 8;
806 else if (RN0 > 11 && RN0 < 16)
807 dstreg = REG_D0 + RN0 - 12;
808 else
809 dstreg = REG_E0 + RN0;
810
811 State.regs[dstreg] &= State.regs[srcreg];
812 z = (State.regs[dstreg] == 0);
813 n = (State.regs[dstreg] & 0x80000000) != 0;
814 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
816 }
817
818 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
819 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
820 "or"
821 *am33
822 {
823 int srcreg, dstreg;
824 int z, n;
825
826 PC = cia;
827
828 if (RM2 > 7 && RM2 < 12)
829 srcreg = REG_A0 + RM2 - 8;
830 else if (RM2 > 11 && RM2 < 16)
831 srcreg = REG_D0 + RM2 - 12;
832 else
833 srcreg = REG_E0 + RM2;
834
835 if (RN0 > 7 && RN0 < 12)
836 dstreg = REG_A0 + RN0 - 8;
837 else if (RN0 > 11 && RN0 < 16)
838 dstreg = REG_D0 + RN0 - 12;
839 else
840 dstreg = REG_E0 + RN0;
841
842 State.regs[dstreg] |= State.regs[srcreg];
843 z = (State.regs[dstreg] == 0);
844 n = (State.regs[dstreg] & 0x80000000) != 0;
845 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
846 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
847 }
848
849 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
850 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
851 "xor"
852 *am33
853 {
854 int srcreg, dstreg;
855 int z, n;
856
857 PC = cia;
858
859 if (RM2 > 7 && RM2 < 12)
860 srcreg = REG_A0 + RM2 - 8;
861 else if (RM2 > 11 && RM2 < 16)
862 srcreg = REG_D0 + RM2 - 12;
863 else
864 srcreg = REG_E0 + RM2;
865
866 if (RN0 > 7 && RN0 < 12)
867 dstreg = REG_A0 + RN0 - 8;
868 else if (RN0 > 11 && RN0 < 16)
869 dstreg = REG_D0 + RN0 - 12;
870 else
871 dstreg = REG_E0 + RN0;
872
873 State.regs[dstreg] ^= State.regs[srcreg];
874 z = (State.regs[dstreg] == 0);
875 n = (State.regs[dstreg] & 0x80000000) != 0;
876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
878 }
879
880 // 1111 1001 0011 1001 Rn Rn; not Rn
881 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
882 "not"
883 *am33
884 {
885 int dstreg;
886 int z, n;
887
888 PC = cia;
889
890 if (RN0 > 7 && RN0 < 12)
891 dstreg = REG_A0 + RN0 - 8;
892 else if (RN0 > 11 && RN0 < 16)
893 dstreg = REG_D0 + RN0 - 12;
894 else
895 dstreg = REG_E0 + RN0;
896
897 State.regs[dstreg] = ~State.regs[dstreg];
898 z = (State.regs[dstreg] == 0);
899 n = (State.regs[dstreg] & 0x80000000) != 0;
900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
902 }
903
904 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
905 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
906 "asr"
907 *am33
908 {
909 int srcreg, dstreg;
910 long temp;
911 int c, z, n;
912
913 PC = cia;
914
915 if (RM2 > 7 && RM2 < 12)
916 srcreg = REG_A0 + RM2 - 8;
917 else if (RM2 > 11 && RM2 < 16)
918 srcreg = REG_D0 + RM2 - 12;
919 else
920 srcreg = REG_E0 + RM2;
921
922 if (RN0 > 7 && RN0 < 12)
923 dstreg = REG_A0 + RN0 - 8;
924 else if (RN0 > 11 && RN0 < 16)
925 dstreg = REG_D0 + RN0 - 12;
926 else
927 dstreg = REG_E0 + RN0;
928
929 temp = State.regs[dstreg];
930 c = temp & 1;
931 temp >>= State.regs[srcreg];
932 State.regs[dstreg] = temp;
933 z = (State.regs[dstreg] == 0);
934 n = (State.regs[dstreg] & 0x80000000) != 0;
935 PSW &= ~(PSW_Z | PSW_N | PSW_C);
936 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
937 }
938
939 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
940 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
941 "lsr"
942 *am33
943 {
944 int srcreg, dstreg;
945 int z, n, c;
946
947 PC = cia;
948
949 if (RM2 > 7 && RM2 < 12)
950 srcreg = REG_A0 + RM2 - 8;
951 else if (RM2 > 11 && RM2 < 16)
952 srcreg = REG_D0 + RM2 - 12;
953 else
954 srcreg = REG_E0 + RM2;
955
956 if (RN0 > 7 && RN0 < 12)
957 dstreg = REG_A0 + RN0 - 8;
958 else if (RN0 > 11 && RN0 < 16)
959 dstreg = REG_D0 + RN0 - 12;
960 else
961 dstreg = REG_E0 + RN0;
962
963 c = State.regs[dstreg] & 1;
964 State.regs[dstreg] >>= State.regs[srcreg];
965 z = (State.regs[dstreg] == 0);
966 n = (State.regs[dstreg] & 0x80000000) != 0;
967 PSW &= ~(PSW_Z | PSW_N | PSW_C);
968 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
969 }
970
971 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
972 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
973 "asl"
974 *am33
975 {
976 int srcreg, dstreg;
977 int z, n;
978
979 PC = cia;
980
981 if (RM2 > 7 && RM2 < 12)
982 srcreg = REG_A0 + RM2 - 8;
983 else if (RM2 > 11 && RM2 < 16)
984 srcreg = REG_D0 + RM2 - 12;
985 else
986 srcreg = REG_E0 + RM2;
987
988 if (RN0 > 7 && RN0 < 12)
989 dstreg = REG_A0 + RN0 - 8;
990 else if (RN0 > 11 && RN0 < 16)
991 dstreg = REG_D0 + RN0 - 12;
992 else
993 dstreg = REG_E0 + RN0;
994
995 State.regs[dstreg] <<= State.regs[srcreg];
996 z = (State.regs[dstreg] == 0);
997 n = (State.regs[dstreg] & 0x80000000) != 0;
998 PSW &= ~(PSW_Z | PSW_N);
999 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1000 }
1001
1002 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
1003 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
1004 "asl2"
1005 *am33
1006 {
1007 int dstreg;
1008 int n, z;
1009
1010 PC = cia;
1011
1012 if (RN0 > 7 && RN0 < 12)
1013 dstreg = REG_A0 + RN0 - 8;
1014 else if (RN0 > 11 && RN0 < 16)
1015 dstreg = REG_D0 + RN0 - 12;
1016 else
1017 dstreg = REG_E0 + RN0;
1018
1019 State.regs[dstreg] <<= 2;
1020 z = (State.regs[dstreg] == 0);
1021 n = (State.regs[dstreg] & 0x80000000) != 0;
1022 PSW &= ~(PSW_Z | PSW_N);
1023 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1024 }
1025
1026 // 1111 1001 1000 1001 Rn Rn; ror Rn
1027 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
1028 "ror"
1029 *am33
1030 {
1031 int dstreg;
1032 int c, n, z;
1033 unsigned long value;
1034
1035 PC = cia;
1036
1037 if (RN0 > 7 && RN0 < 12)
1038 dstreg = REG_A0 + RN0 - 8;
1039 else if (RN0 > 11 && RN0 < 16)
1040 dstreg = REG_D0 + RN0 - 12;
1041 else
1042 dstreg = REG_E0 + RN0;
1043
1044 value = State.regs[dstreg];
1045 c = (value & 0x1);
1046
1047 value >>= 1;
1048 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1049 State.regs[dstreg] = value;
1050 z = (value == 0);
1051 n = (value & 0x80000000) != 0;
1052 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1053 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1054 }
1055
1056 // 1111 1001 1001 1001 Rn Rn; rol Rn
1057 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
1058 "rol"
1059 *am33
1060 {
1061 int dstreg;
1062 int c, n, z;
1063 unsigned long value;
1064
1065 PC = cia;
1066
1067 if (RN0 > 7 && RN0 < 12)
1068 dstreg = REG_A0 + RN0 - 8;
1069 else if (RN0 > 11 && RN0 < 16)
1070 dstreg = REG_D0 + RN0 - 12;
1071 else
1072 dstreg = REG_E0 + RN0;
1073
1074 value = State.regs[dstreg];
1075 c = (value & 0x80000000) ? 1 : 0;
1076
1077 value <<= 1;
1078 value |= ((PSW & PSW_C) != 0);
1079 State.regs[dstreg] = value;
1080 z = (value == 0);
1081 n = (value & 0x80000000) != 0;
1082 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1083 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1084 }
1085
1086 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
1087 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
1088 "mul"
1089 *am33
1090 {
1091 int srcreg, dstreg;
1092 unsigned long long temp;
1093 int n, z;
1094
1095 PC = cia;
1096
1097 if (RM2 > 7 && RM2 < 12)
1098 srcreg = REG_A0 + RM2 - 8;
1099 else if (RM2 > 11 && RM2 < 16)
1100 srcreg = REG_D0 + RM2 - 12;
1101 else
1102 srcreg = REG_E0 + RM2;
1103
1104 if (RN0 > 7 && RN0 < 12)
1105 dstreg = REG_A0 + RN0 - 8;
1106 else if (RN0 > 11 && RN0 < 16)
1107 dstreg = REG_D0 + RN0 - 12;
1108 else
1109 dstreg = REG_E0 + RN0;
1110
1111 temp = ((signed64)(signed32)State.regs[dstreg]
1112 * (signed64)(signed32)State.regs[srcreg]);
1113 State.regs[dstreg] = temp & 0xffffffff;
1114 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1115 z = (State.regs[dstreg] == 0);
1116 n = (State.regs[dstreg] & 0x80000000) != 0;
1117 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1118 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1119 }
1120
1121 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
1122 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
1123 "mulu"
1124 *am33
1125 {
1126 int srcreg, dstreg;
1127 unsigned long long temp;
1128 int n, z;
1129
1130 PC = cia;
1131
1132 if (RM2 > 7 && RM2 < 12)
1133 srcreg = REG_A0 + RM2 - 8;
1134 else if (RM2 > 11 && RM2 < 16)
1135 srcreg = REG_D0 + RM2 - 12;
1136 else
1137 srcreg = REG_E0 + RM2;
1138
1139 if (RN0 > 7 && RN0 < 12)
1140 dstreg = REG_A0 + RN0 - 8;
1141 else if (RN0 > 11 && RN0 < 16)
1142 dstreg = REG_D0 + RN0 - 12;
1143 else
1144 dstreg = REG_E0 + RN0;
1145
1146 temp = ((unsigned64)State.regs[dstreg]
1147 * (unsigned64)State.regs[srcreg]);
1148 State.regs[dstreg] = temp & 0xffffffff;
1149 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1150 z = (State.regs[dstreg] == 0);
1151 n = (State.regs[dstreg] & 0x80000000) != 0;
1152 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1154 }
1155
1156 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
1157 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
1158 "div"
1159 *am33
1160 {
1161 int srcreg, dstreg;
1162 unsigned long long temp;
1163 int n, z;
1164
1165 PC = cia;
1166
1167 if (RM2 > 7 && RM2 < 12)
1168 srcreg = REG_A0 + RM2 - 8;
1169 else if (RM2 > 11 && RM2 < 16)
1170 srcreg = REG_D0 + RM2 - 12;
1171 else
1172 srcreg = REG_E0 + RM2;
1173
1174 if (RN0 > 7 && RN0 < 12)
1175 dstreg = REG_A0 + RN0 - 8;
1176 else if (RN0 > 11 && RN0 < 16)
1177 dstreg = REG_D0 + RN0 - 12;
1178 else
1179 dstreg = REG_E0 + RN0;
1180
1181 temp = State.regs[REG_MDR];
1182 temp <<= 32;
1183 temp |= State.regs[dstreg];
1184 State.regs[REG_MDR] = temp % (long)State.regs[srcreg];
1185 temp /= (long)State.regs[srcreg];
1186 State.regs[dstreg] = temp & 0xffffffff;
1187 z = (State.regs[dstreg] == 0);
1188 n = (State.regs[dstreg] & 0x80000000) != 0;
1189 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1190 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1191 }
1192
1193 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
1194 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
1195 "divu"
1196 *am33
1197 {
1198 int srcreg, dstreg;
1199 unsigned long long temp;
1200 int n, z;
1201
1202 PC = cia;
1203
1204 if (RM2 > 7 && RM2 < 12)
1205 srcreg = REG_A0 + RM2 - 8;
1206 else if (RM2 > 11 && RM2 < 16)
1207 srcreg = REG_D0 + RM2 - 12;
1208 else
1209 srcreg = REG_E0 + RM2;
1210
1211 if (RN0 > 7 && RN0 < 12)
1212 dstreg = REG_A0 + RN0 - 8;
1213 else if (RN0 > 11 && RN0 < 16)
1214 dstreg = REG_D0 + RN0 - 12;
1215 else
1216 dstreg = REG_E0 + RN0;
1217
1218 temp = State.regs[REG_MDR];
1219 temp <<= 32;
1220 temp |= State.regs[dstreg];
1221 State.regs[REG_MDR] = temp % State.regs[srcreg];
1222 temp /= State.regs[srcreg];
1223 State.regs[dstreg] = temp & 0xffffffff;
1224 z = (State.regs[dstreg] == 0);
1225 n = (State.regs[dstreg] & 0x80000000) != 0;
1226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1227 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1228 }
1229
1230
1231 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
1232 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
1233 "mov"
1234 *am33
1235 {
1236 int srcreg, dstreg;
1237
1238 PC = cia;
1239
1240 if (RM0 > 7 && RM0 < 12)
1241 srcreg = REG_A0 + RM0 - 8;
1242 else if (RM0 > 11 && RM0 < 16)
1243 srcreg = REG_D0 + RM0 - 12;
1244 else
1245 srcreg = REG_E0 + RM0;
1246
1247 if (RN2 > 7 && RN2 < 12)
1248 dstreg = REG_A0 + RN2 - 8;
1249 else if (RN2 > 11 && RN2 < 16)
1250 dstreg = REG_D0 + RN2 - 12;
1251 else
1252 dstreg = REG_E0 + RN2;
1253
1254 State.regs[dstreg] = load_word (State.regs[srcreg]);
1255 }
1256
1257 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
1258 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
1259 "mov"
1260 *am33
1261 {
1262 int srcreg, dstreg;
1263
1264 PC = cia;
1265
1266 if (RM2 > 7 && RM2 < 12)
1267 srcreg = REG_A0 + RM2 - 8;
1268 else if (RM2 > 11 && RM2 < 16)
1269 srcreg = REG_D0 + RM2 - 12;
1270 else
1271 srcreg = REG_E0 + RM2;
1272
1273 if (RN0 > 7 && RN0 < 12)
1274 dstreg = REG_A0 + RN0 - 8;
1275 else if (RN0 > 11 && RN0 < 16)
1276 dstreg = REG_D0 + RN0 - 12;
1277 else
1278 dstreg = REG_E0 + RN0;
1279
1280 store_word (State.regs[dstreg], State.regs[srcreg]);
1281 }
1282
1283 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
1284 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
1285 "movbu"
1286 *am33
1287 {
1288 int srcreg, dstreg;
1289
1290 PC = cia;
1291
1292 if (RM0 > 7 && RM0 < 12)
1293 srcreg = REG_A0 + RM0 - 8;
1294 else if (RM0 > 11 && RM0 < 16)
1295 srcreg = REG_D0 + RM0 - 12;
1296 else
1297 srcreg = REG_E0 + RM0;
1298
1299 if (RN2 > 7 && RN2 < 12)
1300 dstreg = REG_A0 + RN2 - 8;
1301 else if (RN2 > 11 && RN2 < 16)
1302 dstreg = REG_D0 + RN2 - 12;
1303 else
1304 dstreg = REG_E0 + RN2;
1305
1306 State.regs[dstreg] = load_byte (State.regs[srcreg]);
1307 }
1308
1309 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
1310 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
1311 "movbu"
1312 *am33
1313 {
1314 int srcreg, dstreg;
1315
1316 PC = cia;
1317
1318 if (RM2 > 7 && RM2 < 12)
1319 srcreg = REG_A0 + RM2 - 8;
1320 else if (RM2 > 11 && RM2 < 16)
1321 srcreg = REG_D0 + RM2 - 12;
1322 else
1323 srcreg = REG_E0 + RM2;
1324
1325 if (RN0 > 7 && RN0 < 12)
1326 dstreg = REG_A0 + RN0 - 8;
1327 else if (RN0 > 11 && RN0 < 16)
1328 dstreg = REG_D0 + RN0 - 12;
1329 else
1330 dstreg = REG_E0 + RN0;
1331
1332 store_byte (State.regs[dstreg], State.regs[srcreg]);
1333 }
1334
1335 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
1336 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
1337 "movhu"
1338 *am33
1339 {
1340 int srcreg, dstreg;
1341
1342 PC = cia;
1343
1344 if (RM0 > 7 && RM0 < 12)
1345 srcreg = REG_A0 + RM0 - 8;
1346 else if (RM0 > 11 && RM0 < 16)
1347 srcreg = REG_D0 + RM0 - 12;
1348 else
1349 srcreg = REG_E0 + RM0;
1350
1351 if (RN2 > 7 && RN2 < 12)
1352 dstreg = REG_A0 + RN2 - 8;
1353 else if (RN2 > 11 && RN2 < 16)
1354 dstreg = REG_D0 + RN2 - 12;
1355 else
1356 dstreg = REG_E0 + RN2;
1357
1358 State.regs[dstreg] = load_half (State.regs[srcreg]);
1359 }
1360
1361 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1362 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1363 "movhu"
1364 *am33
1365 {
1366 int srcreg, dstreg;
1367
1368 PC = cia;
1369
1370 if (RM2 > 7 && RM2 < 12)
1371 srcreg = REG_A0 + RM2 - 8;
1372 else if (RM2 > 11 && RM2 < 16)
1373 srcreg = REG_D0 + RM2 - 12;
1374 else
1375 srcreg = REG_E0 + RM2;
1376
1377 if (RN0 > 7 && RN0 < 12)
1378 dstreg = REG_A0 + RN0 - 8;
1379 else if (RN0 > 11 && RN0 < 16)
1380 dstreg = REG_D0 + RN0 - 12;
1381 else
1382 dstreg = REG_E0 + RN0;
1383
1384 store_half (State.regs[dstreg], State.regs[srcreg]);
1385 }
1386
1387 // ??? mov
1388 // ??? mov
1389
1390 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1391 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1392 "mov"
1393 *am33
1394 {
1395 int srcreg, dstreg;
1396
1397 PC = cia;
1398
1399 if (RN2 > 7 && RN2 < 12)
1400 dstreg = REG_A0 + RN2 - 8;
1401 else if (RN2 > 11 && RN2 < 16)
1402 dstreg = REG_D0 + RN2 - 12;
1403 else
1404 dstreg = REG_E0 + RN2;
1405
1406 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1407 }
1408
1409 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1410 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1411 "mov"
1412 *am33
1413 {
1414 int srcreg, dstreg;
1415
1416 PC = cia;
1417
1418 if (RM2 > 7 && RM2 < 12)
1419 dstreg = REG_A0 + RM2 - 8;
1420 else if (RM2 > 11 && RM2 < 16)
1421 dstreg = REG_D0 + RM2 - 12;
1422 else
1423 dstreg = REG_E0 + RM2;
1424
1425 store_word (State.regs[REG_SP], State.regs[dstreg]);
1426 }
1427
1428 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1429 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1430 "movbu"
1431 *am33
1432 {
1433 int srcreg, dstreg;
1434
1435 PC = cia;
1436
1437 if (RN2 > 7 && RN2 < 12)
1438 dstreg = REG_A0 + RN2 - 8;
1439 else if (RN2 > 11 && RN2 < 16)
1440 dstreg = REG_D0 + RN2 - 12;
1441 else
1442 dstreg = REG_E0 + RN2;
1443
1444 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1445 }
1446
1447 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1448 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1449 "movbu"
1450 *am33
1451 {
1452 int srcreg, dstreg;
1453
1454 PC = cia;
1455
1456 if (RM2 > 7 && RM2 < 12)
1457 dstreg = REG_A0 + RM2 - 8;
1458 else if (RM2 > 11 && RM2 < 16)
1459 dstreg = REG_D0 + RM2 - 12;
1460 else
1461 dstreg = REG_E0 + RM2;
1462
1463 store_byte (State.regs[REG_SP], State.regs[dstreg]);
1464 }
1465
1466 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1467 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1468 "movhu"
1469 *am33
1470 {
1471 int srcreg, dstreg;
1472
1473 PC = cia;
1474
1475 if (RN2 > 7 && RN2 < 12)
1476 dstreg = REG_A0 + RN2 - 8;
1477 else if (RN2 > 11 && RN2 < 16)
1478 dstreg = REG_D0 + RN2 - 12;
1479 else
1480 dstreg = REG_E0 + RN2;
1481
1482 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1483 }
1484
1485 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1486 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1487 "movhu"
1488 *am33
1489 {
1490 int srcreg, dstreg;
1491
1492 PC = cia;
1493
1494 if (RM2 > 7 && RM2 < 12)
1495 dstreg = REG_A0 + RM2 - 8;
1496 else if (RM2 > 11 && RM2 < 16)
1497 dstreg = REG_D0 + RM2 - 12;
1498 else
1499 dstreg = REG_E0 + RM2;
1500
1501 store_half (State.regs[REG_SP], State.regs[dstreg]);
1502 }
1503
1504 // ??? movhu
1505 // ??? movhu
1506 // ??? mac
1507 // ??? macu
1508 // ??? macb
1509 // ??? macbu
1510 // ??? mach
1511 // ??? machu
1512 // ??? dmach
1513 // ??? dmachu
1514 // ??? dmulh
1515 // ??? dmulhu
1516 // ??? sat16
1517 // ??? mcste
1518 // ??? swap
1519 // ??? bsch
1520
1521 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1522 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1523 "mov"
1524 *am33
1525 {
1526 int dstreg;
1527
1528 PC = cia;
1529
1530 if (RN0 > 7 && RN0 < 12)
1531 dstreg = REG_A0 + RN0 - 8;
1532 else if (RN0 > 11 && RN0 < 16)
1533 dstreg = REG_D0 + RN0 - 12;
1534 else
1535 dstreg = REG_E0 + RN0;
1536
1537 State.regs[dstreg] = EXTEND8 (IMM8);
1538 }
1539
1540 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1541 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1542 "movu"
1543 *am33
1544 {
1545 int dstreg;
1546
1547 PC = cia;
1548
1549 if (RN0 > 7 && RN0 < 12)
1550 dstreg = REG_A0 + RN0 - 8;
1551 else if (RN0 > 11 && RN0 < 16)
1552 dstreg = REG_D0 + RN0 - 12;
1553 else
1554 dstreg = REG_E0 + RN0;
1555
1556 State.regs[dstreg] = IMM8 & 0xff;
1557 }
1558
1559 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1560 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1561 "add"
1562 *am33
1563 {
1564 int dstreg;
1565
1566 PC = cia;
1567
1568 if (RN0 > 7 && RN0 < 12)
1569 dstreg = REG_A0 + RN0 - 8;
1570 else if (RN0 > 11 && RN0 < 16)
1571 dstreg = REG_D0 + RN0 - 12;
1572 else
1573 dstreg = REG_E0 + RN0;
1574
1575 genericAdd (EXTEND8 (IMM8), dstreg);
1576 }
1577
1578 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1579 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1580 "addc"
1581 *am33
1582 {
1583 int dstreg, imm;
1584 int z, c, n, v;
1585 unsigned long reg1, reg2, sum;
1586
1587 PC = cia;
1588
1589 if (RN0 > 7 && RN0 < 12)
1590 dstreg = REG_A0 + RN0 - 8;
1591 else if (RN0 > 11 && RN0 < 16)
1592 dstreg = REG_D0 + RN0 - 12;
1593 else
1594 dstreg = REG_E0 + RN0;
1595
1596 imm = EXTEND8 (IMM8);
1597 reg2 = State.regs[dstreg];
1598 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1599 State.regs[dstreg] = sum;
1600
1601 z = (sum == 0);
1602 n = (sum & 0x80000000);
1603 c = (sum < imm) || (sum < reg2);
1604 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1605 && (reg2 & 0x80000000) != (sum & 0x80000000));
1606
1607 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1608 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1609 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1610 }
1611
1612 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1613 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1614 "sub"
1615 *am33
1616 {
1617 int dstreg;
1618
1619 PC = cia;
1620
1621 if (RN0 > 7 && RN0 < 12)
1622 dstreg = REG_A0 + RN0 - 8;
1623 else if (RN0 > 11 && RN0 < 16)
1624 dstreg = REG_D0 + RN0 - 12;
1625 else
1626 dstreg = REG_E0 + RN0;
1627
1628 genericSub (EXTEND8 (IMM8), dstreg);
1629 }
1630
1631 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1632 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1633 "subc"
1634 *am33
1635 {
1636 int imm, dstreg;
1637 int z, c, n, v;
1638 unsigned long reg1, reg2, difference;
1639
1640 PC = cia;
1641
1642 if (RN0 > 7 && RN0 < 12)
1643 dstreg = REG_A0 + RN0 - 8;
1644 else if (RN0 > 11 && RN0 < 16)
1645 dstreg = REG_D0 + RN0 - 12;
1646 else
1647 dstreg = REG_E0 + RN0;
1648
1649 imm = EXTEND8 (IMM8);
1650 reg2 = State.regs[dstreg];
1651 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1652 State.regs[dstreg] = difference;
1653
1654 z = (difference == 0);
1655 n = (difference & 0x80000000);
1656 c = (imm > reg2);
1657 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1658 && (reg2 & 0x80000000) != (difference & 0x80000000));
1659
1660 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1661 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1662 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1663 }
1664
1665 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1666 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1667 "cmp"
1668 *am33
1669 {
1670 int srcreg;
1671
1672 PC = cia;
1673
1674 if (RN0 > 7 && RN0 < 12)
1675 srcreg = REG_A0 + RN0 - 8;
1676 else if (RN0 > 11 && RN0 < 16)
1677 srcreg = REG_D0 + RN0 - 12;
1678 else
1679 srcreg = REG_E0 + RN0;
1680
1681 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1682 }
1683
1684 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1685 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1686 "mov"
1687 *am33
1688 {
1689 int dstreg;
1690
1691 PC = cia;
1692
1693 if (XRN0 == 0)
1694 State.regs[REG_SP] = EXTEND8 (IMM8);
1695 else
1696 abort ();
1697 }
1698
1699 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1700 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1701 "and"
1702 *am33
1703 {
1704 int dstreg;
1705 int z, n;
1706
1707 PC = cia;
1708
1709 if (RN0 > 7 && RN0 < 12)
1710 dstreg = REG_A0 + RN0 - 8;
1711 else if (RN0 > 11 && RN0 < 16)
1712 dstreg = REG_D0 + RN0 - 12;
1713 else
1714 dstreg = REG_E0 + RN0;
1715
1716 State.regs[dstreg] &= (IMM8 & 0xff);
1717 z = (State.regs[dstreg] == 0);
1718 n = (State.regs[dstreg] & 0x80000000) != 0;
1719 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1720 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1721 }
1722
1723 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1724 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1725 "or"
1726 *am33
1727 {
1728 int dstreg;
1729 int z, n;
1730
1731 PC = cia;
1732
1733 if (RN0 > 7 && RN0 < 12)
1734 dstreg = REG_A0 + RN0 - 8;
1735 else if (RN0 > 11 && RN0 < 16)
1736 dstreg = REG_D0 + RN0 - 12;
1737 else
1738 dstreg = REG_E0 + RN0;
1739
1740 State.regs[dstreg] |= (IMM8 & 0xff);
1741 z = (State.regs[dstreg] == 0);
1742 n = (State.regs[dstreg] & 0x80000000) != 0;
1743 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1745 }
1746
1747 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1748 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1749 "xor"
1750 *am33
1751 {
1752 int dstreg;
1753 int z, n;
1754
1755 PC = cia;
1756
1757 if (RN0 > 7 && RN0 < 12)
1758 dstreg = REG_A0 + RN0 - 8;
1759 else if (RN0 > 11 && RN0 < 16)
1760 dstreg = REG_D0 + RN0 - 12;
1761 else
1762 dstreg = REG_E0 + RN0;
1763
1764 State.regs[dstreg] ^= (IMM8 & 0xff);
1765 z = (State.regs[dstreg] == 0);
1766 n = (State.regs[dstreg] & 0x80000000) != 0;
1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1769 }
1770
1771 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1772 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1773 "asr"
1774 *am33
1775 {
1776 int dstreg;
1777 long temp;
1778 int c, z, n;
1779
1780 PC = cia;
1781
1782 if (RN0 > 7 && RN0 < 12)
1783 dstreg = REG_A0 + RN0 - 8;
1784 else if (RN0 > 11 && RN0 < 16)
1785 dstreg = REG_D0 + RN0 - 12;
1786 else
1787 dstreg = REG_E0 + RN0;
1788
1789 temp = State.regs[dstreg];
1790 c = temp & 1;
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1797 }
1798
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1801 "lsr"
1802 *am33
1803 {
1804 int dstreg;
1805 int z, n, c;
1806
1807 PC = cia;
1808
1809 if (RN0 > 7 && RN0 < 12)
1810 dstreg = REG_A0 + RN0 - 8;
1811 else if (RN0 > 11 && RN0 < 16)
1812 dstreg = REG_D0 + RN0 - 12;
1813 else
1814 dstreg = REG_E0 + RN0;
1815
1816 c = State.regs[dstreg] & 1;
1817 State.regs[dstreg] >>= (IMM8 & 0xff);
1818 z = (State.regs[dstreg] == 0);
1819 n = (State.regs[dstreg] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1822 }
1823
1824 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1825 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1826 "asl"
1827 *am33
1828 {
1829 int srcreg, dstreg;
1830 int z, n;
1831
1832 PC = cia;
1833
1834 if (RN0 > 7 && RN0 < 12)
1835 dstreg = REG_A0 + RN0 - 8;
1836 else if (RN0 > 11 && RN0 < 16)
1837 dstreg = REG_D0 + RN0 - 12;
1838 else
1839 dstreg = REG_E0 + RN0;
1840
1841 State.regs[dstreg] <<= (IMM8 & 0xff);
1842 z = (State.regs[dstreg] == 0);
1843 n = (State.regs[dstreg] & 0x80000000) != 0;
1844 PSW &= ~(PSW_Z | PSW_N);
1845 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1846 }
1847
1848 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1849 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1850 "mul"
1851 *am33
1852 {
1853 int dstreg;
1854 unsigned long long temp;
1855 int z, n;
1856
1857 PC = cia;
1858
1859 if (RN0 > 7 && RN0 < 12)
1860 dstreg = REG_A0 + RN0 - 8;
1861 else if (RN0 > 11 && RN0 < 16)
1862 dstreg = REG_D0 + RN0 - 12;
1863 else
1864 dstreg = REG_E0 + RN0;
1865
1866 temp = ((signed64)(signed32)State.regs[dstreg]
1867 * (signed64)(signed32)EXTEND8 (IMM8));
1868 State.regs[dstreg] = temp & 0xffffffff;
1869 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1870 z = (State.regs[dstreg] == 0);
1871 n = (State.regs[dstreg] & 0x80000000) != 0;
1872 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1873 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1874 }
1875
1876 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1877 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1878 "mulu"
1879 *am33
1880 {
1881 int dstreg;
1882 unsigned long long temp;
1883 int z, n;
1884
1885 PC = cia;
1886
1887 if (RN0 > 7 && RN0 < 12)
1888 dstreg = REG_A0 + RN0 - 8;
1889 else if (RN0 > 11 && RN0 < 16)
1890 dstreg = REG_D0 + RN0 - 12;
1891 else
1892 dstreg = REG_E0 + RN0;
1893
1894 temp = ((unsigned64)State.regs[dstreg]
1895 * (unsigned64)(IMM8 & 0xff));
1896 State.regs[dstreg] = temp & 0xffffffff;
1897 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1898 z = (State.regs[dstreg] == 0);
1899 n = (State.regs[dstreg] & 0x80000000) != 0;
1900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1902 }
1903
1904 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1905 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1906 "btst"
1907 *am33
1908 {
1909 int srcreg;
1910
1911 PC = cia;
1912
1913 if (RM0 > 7 && RM0 < 12)
1914 srcreg = REG_A0 + RM0 - 8;
1915 else if (RM0 > 11 && RM0 < 16)
1916 srcreg = REG_D0 + RM0 - 12;
1917 else
1918 srcreg = REG_E0 + RM0;
1919
1920 genericBtst(IMM8, State.regs[srcreg]);
1921
1922 }
1923
1924
1925 // XYZ
1926 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1927 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1928 "mov"
1929 *am33
1930 {
1931 int srcreg, dstreg;
1932
1933 PC = cia;
1934
1935 if (RM0 > 7 && RM0 < 12)
1936 srcreg = REG_A0 + RM0 - 8;
1937 else if (RM0 > 11 && RM0 < 16)
1938 srcreg = REG_D0 + RM0 - 12;
1939 else
1940 srcreg = REG_E0 + RM0;
1941
1942 if (RN2 > 7 && RN2 < 12)
1943 dstreg = REG_A0 + RN2 - 8;
1944 else if (RN2 > 11 && RN2 < 16)
1945 dstreg = REG_D0 + RN2 - 12;
1946 else
1947 dstreg = REG_E0 + RN2;
1948
1949 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1950 }
1951
1952 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1953 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1954 "mov"
1955 {
1956 int srcreg, dstreg;
1957
1958 PC = cia;
1959
1960 if (RM2 > 7 && RM2 < 12)
1961 srcreg = REG_A0 + RM2 - 8;
1962 else if (RM2 > 11 && RM2 < 16)
1963 srcreg = REG_D0 + RM2 - 12;
1964 else
1965 srcreg = REG_E0 + RM2;
1966
1967 if (RN0 > 7 && RN0 < 12)
1968 dstreg = REG_A0 + RN0 - 8;
1969 else if (RN0 > 11 && RN0 < 16)
1970 dstreg = REG_D0 + RN0 - 12;
1971 else
1972 dstreg = REG_E0 + RN0;
1973
1974 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1975 }
1976
1977 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1978 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1979 "movbu"
1980 {
1981 int srcreg, dstreg;
1982
1983 PC = cia;
1984
1985 if (RM0 > 7 && RM0 < 12)
1986 srcreg = REG_A0 + RM0 - 8;
1987 else if (RM0 > 11 && RM0 < 16)
1988 srcreg = REG_D0 + RM0 - 12;
1989 else
1990 srcreg = REG_E0 + RM0;
1991
1992 if (RN2 > 7 && RN2 < 12)
1993 dstreg = REG_A0 + RN2 - 8;
1994 else if (RN2 > 11 && RN2 < 16)
1995 dstreg = REG_D0 + RN2 - 12;
1996 else
1997 dstreg = REG_E0 + RN2;
1998
1999 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
2000 }
2001
2002 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
2003 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
2004 "movbu"
2005 {
2006 int srcreg, dstreg;
2007
2008 PC = cia;
2009
2010 if (RM2 > 7 && RM2 < 12)
2011 srcreg = REG_A0 + RM2 - 8;
2012 else if (RM2 > 11 && RM2 < 16)
2013 srcreg = REG_D0 + RM2 - 12;
2014 else
2015 srcreg = REG_E0 + RM2;
2016
2017 if (RN0 > 7 && RN0 < 12)
2018 dstreg = REG_A0 + RN0 - 8;
2019 else if (RN0 > 11 && RN0 < 16)
2020 dstreg = REG_D0 + RN0 - 12;
2021 else
2022 dstreg = REG_E0 + RN0;
2023
2024 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2025 }
2026
2027 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
2028 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
2029 "movhu"
2030 {
2031 int srcreg, dstreg;
2032
2033 PC = cia;
2034
2035 if (RM0 > 7 && RM0 < 12)
2036 srcreg = REG_A0 + RM0 - 8;
2037 else if (RM0 > 11 && RM0 < 16)
2038 srcreg = REG_D0 + RM0 - 12;
2039 else
2040 srcreg = REG_E0 + RM0;
2041
2042 if (RN2 > 7 && RN2 < 12)
2043 dstreg = REG_A0 + RN2 - 8;
2044 else if (RN2 > 11 && RN2 < 16)
2045 dstreg = REG_D0 + RN2 - 12;
2046 else
2047 dstreg = REG_E0 + RN2;
2048
2049 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2050 }
2051
2052 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
2053 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
2054 "movhu"
2055 {
2056 int srcreg, dstreg;
2057
2058 PC = cia;
2059
2060 if (RM2 > 7 && RM2 < 12)
2061 srcreg = REG_A0 + RM2 - 8;
2062 else if (RM2 > 11 && RM2 < 16)
2063 srcreg = REG_D0 + RM2 - 12;
2064 else
2065 srcreg = REG_E0 + RM2;
2066
2067 if (RN0 > 7 && RN0 < 12)
2068 dstreg = REG_A0 + RN0 - 8;
2069 else if (RN0 > 11 && RN0 < 16)
2070 dstreg = REG_D0 + RN0 - 12;
2071 else
2072 dstreg = REG_E0 + RN0;
2073
2074 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2075 }
2076
2077 // ??? mov
2078 // ??? mov
2079
2080 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2081 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2082 "mov"
2083 {
2084 int dstreg;
2085
2086 PC = cia;
2087
2088 if (RN2 > 7 && RN2 < 12)
2089 dstreg = REG_A0 + RN2 - 8;
2090 else if (RN2 > 11 && RN2 < 16)
2091 dstreg = REG_D0 + RN2 - 12;
2092 else
2093 dstreg = REG_E0 + RN2;
2094
2095 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2096 }
2097
2098 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2099 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2100 "mov"
2101 {
2102 int srcreg;
2103
2104 PC = cia;
2105
2106 if (RM2 > 7 && RM2 < 12)
2107 srcreg = REG_A0 + RM2 - 8;
2108 else if (RM2 > 11 && RM2 < 16)
2109 srcreg = REG_D0 + RM2 - 12;
2110 else
2111 srcreg = REG_E0 + RM2;
2112
2113 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2114 }
2115
2116 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2117 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2118 "movbu"
2119 {
2120 int dstreg;
2121
2122 PC = cia;
2123
2124 if (RN2 > 7 && RN2 < 12)
2125 dstreg = REG_A0 + RN2 - 8;
2126 else if (RN2 > 11 && RN2 < 16)
2127 dstreg = REG_D0 + RN2 - 12;
2128 else
2129 dstreg = REG_E0 + RN2;
2130
2131 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2132 }
2133
2134 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2135 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2136 "movbu"
2137 {
2138 int srcreg;
2139
2140 PC = cia;
2141
2142 if (RM2 > 7 && RM2 < 12)
2143 srcreg = REG_A0 + RM2 - 8;
2144 else if (RM2 > 11 && RM2 < 16)
2145 srcreg = REG_D0 + RM2 - 12;
2146 else
2147 srcreg = REG_E0 + RM2;
2148
2149 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2150 }
2151
2152 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2153 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2154 "movhu"
2155 {
2156 int dstreg;
2157
2158 PC = cia;
2159
2160 if (RN2 > 7 && RN2 < 12)
2161 dstreg = REG_A0 + RN2 - 8;
2162 else if (RN2 > 11 && RN2 < 16)
2163 dstreg = REG_D0 + RN2 - 12;
2164 else
2165 dstreg = REG_E0 + RN2;
2166
2167 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2168 }
2169
2170 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2171 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2172 "movhu"
2173 {
2174 int srcreg;
2175
2176 PC = cia;
2177
2178 if (RM2 > 7 && RM2 < 12)
2179 srcreg = REG_A0 + RM2 - 8;
2180 else if (RM2 > 11 && RM2 < 16)
2181 srcreg = REG_D0 + RM2 - 12;
2182 else
2183 srcreg = REG_E0 + RM2;
2184
2185 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2186 }
2187
2188 // ??? movhu
2189 // ??? movhu
2190 // ??? mac
2191 // ??? macu
2192 // ??? macb
2193 // ??? macbu
2194 // ??? mach
2195 // ??? machu
2196 // ??? mcste
2197
2198 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2199 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2200 "add"
2201 *am33
2202 {
2203 int z, c, n, v;
2204 unsigned long sum, source1, source2;
2205 int srcreg1, srcreg2, dstreg;
2206
2207 PC = cia;
2208
2209 if (RM2 > 7 && RM2 < 12)
2210 srcreg1 = REG_A0 + RM2 - 8;
2211 else if (RM2 > 11 && RM2 < 16)
2212 srcreg1 = REG_D0 + RM2 - 12;
2213 else
2214 srcreg1 = REG_E0 + RM2;
2215
2216 if (RN0 > 7 && RN0 < 12)
2217 srcreg2 = REG_A0 + RN0 - 8;
2218 else if (RN0 > 11 && RN0 < 16)
2219 srcreg2 = REG_D0 + RN0 - 12;
2220 else
2221 srcreg2 = REG_E0 + RN0;
2222
2223 if (RD0 > 7 && RD0 < 12)
2224 dstreg = REG_A0 + RD0 - 8;
2225 else if (RD0 > 11 && RD0 < 16)
2226 dstreg = REG_D0 + RD0 - 12;
2227 else
2228 dstreg = REG_E0 + RD0;
2229
2230 source1 = State.regs[srcreg1];
2231 source2 = State.regs[srcreg2];
2232 sum = source1 + source2;
2233 State.regs[dstreg] = sum;
2234
2235 z = (sum == 0);
2236 n = (sum & 0x80000000);
2237 c = (sum < source1) || (sum < source2);
2238 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2239 && (source1 & 0x80000000) != (sum & 0x80000000));
2240
2241 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2242 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2243 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2244 }
2245
2246 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2247 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2248 "addc"
2249 *am33
2250 {
2251 int z, c, n, v;
2252 unsigned long sum, source1, source2;
2253 int srcreg1, srcreg2, dstreg;
2254
2255 PC = cia;
2256
2257 if (RM2 > 7 && RM2 < 12)
2258 srcreg1 = REG_A0 + RM2 - 8;
2259 else if (RM2 > 11 && RM2 < 16)
2260 srcreg1 = REG_D0 + RM2 - 12;
2261 else
2262 srcreg1 = REG_E0 + RM2;
2263
2264 if (RN0 > 7 && RN0 < 12)
2265 srcreg2 = REG_A0 + RN0 - 8;
2266 else if (RN0 > 11 && RN0 < 16)
2267 srcreg2 = REG_D0 + RN0 - 12;
2268 else
2269 srcreg2 = REG_E0 + RN0;
2270
2271 if (RD0 > 7 && RD0 < 12)
2272 dstreg = REG_A0 + RD0 - 8;
2273 else if (RD0 > 11 && RD0 < 16)
2274 dstreg = REG_D0 + RD0 - 12;
2275 else
2276 dstreg = REG_E0 + RD0;
2277
2278 source1 = State.regs[srcreg1];
2279 source2 = State.regs[srcreg2];
2280 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2281 State.regs[dstreg] = sum;
2282
2283 z = (sum == 0);
2284 n = (sum & 0x80000000);
2285 c = (sum < source1) || (sum < source2);
2286 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2287 && (source1 & 0x80000000) != (sum & 0x80000000));
2288
2289 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2290 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2291 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2292 }
2293
2294 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2295 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2296 "sub"
2297 *am33
2298 {
2299 int z, c, n, v;
2300 unsigned long difference, source1, source2;
2301 int srcreg1, srcreg2, dstreg;
2302
2303 PC = cia;
2304
2305 if (RM2 > 7 && RM2 < 12)
2306 srcreg1 = REG_A0 + RM2 - 8;
2307 else if (RM2 > 11 && RM2 < 16)
2308 srcreg1 = REG_D0 + RM2 - 12;
2309 else
2310 srcreg1 = REG_E0 + RM2;
2311
2312 if (RN0 > 7 && RN0 < 12)
2313 srcreg2 = REG_A0 + RN0 - 8;
2314 else if (RN0 > 11 && RN0 < 16)
2315 srcreg2 = REG_D0 + RN0 - 12;
2316 else
2317 srcreg2 = REG_E0 + RN0;
2318
2319 if (RD0 > 7 && RD0 < 12)
2320 dstreg = REG_A0 + RD0 - 8;
2321 else if (RD0 > 11 && RD0 < 16)
2322 dstreg = REG_D0 + RD0 - 12;
2323 else
2324 dstreg = REG_E0 + RD0;
2325
2326 source1 = State.regs[srcreg1];
2327 source2 = State.regs[srcreg2];
2328 difference = source2 - source1;
2329 State.regs[dstreg] = difference;
2330
2331 z = (difference == 0);
2332 n = (difference & 0x80000000);
2333 c = (source1 > source1);
2334 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2335 && (source1 & 0x80000000) != (difference & 0x80000000));
2336
2337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2338 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2339 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2340 }
2341
2342 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2343 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2344 "subc"
2345 *am33
2346 {
2347 int z, c, n, v;
2348 unsigned long difference, source1, source2;
2349 int srcreg1, srcreg2, dstreg;
2350
2351 PC = cia;
2352
2353 if (RM2 > 7 && RM2 < 12)
2354 srcreg1 = REG_A0 + RM2 - 8;
2355 else if (RM2 > 11 && RM2 < 16)
2356 srcreg1 = REG_D0 + RM2 - 12;
2357 else
2358 srcreg1 = REG_E0 + RM2;
2359
2360 if (RN0 > 7 && RN0 < 12)
2361 srcreg2 = REG_A0 + RN0 - 8;
2362 else if (RN0 > 11 && RN0 < 16)
2363 srcreg2 = REG_D0 + RN0 - 12;
2364 else
2365 srcreg2 = REG_E0 + RN0;
2366
2367 if (RD0 > 7 && RD0 < 12)
2368 dstreg = REG_A0 + RD0 - 8;
2369 else if (RD0 > 11 && RD0 < 16)
2370 dstreg = REG_D0 + RD0 - 12;
2371 else
2372 dstreg = REG_E0 + RD0;
2373
2374 source1 = State.regs[srcreg1];
2375 source2 = State.regs[srcreg2];
2376 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2377 State.regs[dstreg] = difference;
2378
2379 z = (difference == 0);
2380 n = (difference & 0x80000000);
2381 c = (source1 > source2);
2382 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2383 && (source1 & 0x80000000) != (difference & 0x80000000));
2384
2385 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2386 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2387 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2388 }
2389
2390 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2391 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2392 "and"
2393 *am33
2394 {
2395 int z, c, n, v;
2396 int srcreg1, srcreg2, dstreg;
2397
2398 PC = cia;
2399
2400 if (RM2 > 7 && RM2 < 12)
2401 srcreg1 = REG_A0 + RM2 - 8;
2402 else if (RM2 > 11 && RM2 < 16)
2403 srcreg1 = REG_D0 + RM2 - 12;
2404 else
2405 srcreg1 = REG_E0 + RM2;
2406
2407 if (RN0 > 7 && RN0 < 12)
2408 srcreg2 = REG_A0 + RN0 - 8;
2409 else if (RN0 > 11 && RN0 < 16)
2410 srcreg2 = REG_D0 + RN0 - 12;
2411 else
2412 srcreg2 = REG_E0 + RN0;
2413
2414 if (RD0 > 7 && RD0 < 12)
2415 dstreg = REG_A0 + RD0 - 8;
2416 else if (RD0 > 11 && RD0 < 16)
2417 dstreg = REG_D0 + RD0 - 12;
2418 else
2419 dstreg = REG_E0 + RD0;
2420
2421 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2422
2423 z = (State.regs[dstreg] == 0);
2424 n = (State.regs[dstreg] & 0x80000000);
2425
2426 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2427 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2428 }
2429
2430 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2431 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2432 "or"
2433 *am33
2434 {
2435 int z, c, n, v;
2436 int srcreg1, srcreg2, dstreg;
2437
2438 PC = cia;
2439
2440 if (RM2 > 7 && RM2 < 12)
2441 srcreg1 = REG_A0 + RM2 - 8;
2442 else if (RM2 > 11 && RM2 < 16)
2443 srcreg1 = REG_D0 + RM2 - 12;
2444 else
2445 srcreg1 = REG_E0 + RM2;
2446
2447 if (RN0 > 7 && RN0 < 12)
2448 srcreg2 = REG_A0 + RN0 - 8;
2449 else if (RN0 > 11 && RN0 < 16)
2450 srcreg2 = REG_D0 + RN0 - 12;
2451 else
2452 srcreg2 = REG_E0 + RN0;
2453
2454 if (RD0 > 7 && RD0 < 12)
2455 dstreg = REG_A0 + RD0 - 8;
2456 else if (RD0 > 11 && RD0 < 16)
2457 dstreg = REG_D0 + RD0 - 12;
2458 else
2459 dstreg = REG_E0 + RD0;
2460
2461 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2462
2463 z = (State.regs[dstreg] == 0);
2464 n = (State.regs[dstreg] & 0x80000000);
2465
2466 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2467 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2468 }
2469
2470 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2471 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2472 "xor"
2473 *am33
2474 {
2475 int z, c, n, v;
2476 int srcreg1, srcreg2, dstreg;
2477
2478 PC = cia;
2479
2480 if (RM2 > 7 && RM2 < 12)
2481 srcreg1 = REG_A0 + RM2 - 8;
2482 else if (RM2 > 11 && RM2 < 16)
2483 srcreg1 = REG_D0 + RM2 - 12;
2484 else
2485 srcreg1 = REG_E0 + RM2;
2486
2487 if (RN0 > 7 && RN0 < 12)
2488 srcreg2 = REG_A0 + RN0 - 8;
2489 else if (RN0 > 11 && RN0 < 16)
2490 srcreg2 = REG_D0 + RN0 - 12;
2491 else
2492 srcreg2 = REG_E0 + RN0;
2493
2494 if (RD0 > 7 && RD0 < 12)
2495 dstreg = REG_A0 + RD0 - 8;
2496 else if (RD0 > 11 && RD0 < 16)
2497 dstreg = REG_D0 + RD0 - 12;
2498 else
2499 dstreg = REG_E0 + RD0;
2500
2501 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2502
2503 z = (State.regs[dstreg] == 0);
2504 n = (State.regs[dstreg] & 0x80000000);
2505
2506 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2507 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2508 }
2509
2510 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2511 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2512 "asr"
2513 *am33
2514 {
2515 int z, c, n, v;
2516 long temp;
2517 int srcreg1, srcreg2, dstreg;
2518
2519 PC = cia;
2520
2521 if (RM2 > 7 && RM2 < 12)
2522 srcreg1 = REG_A0 + RM2 - 8;
2523 else if (RM2 > 11 && RM2 < 16)
2524 srcreg1 = REG_D0 + RM2 - 12;
2525 else
2526 srcreg1 = REG_E0 + RM2;
2527
2528 if (RN0 > 7 && RN0 < 12)
2529 srcreg2 = REG_A0 + RN0 - 8;
2530 else if (RN0 > 11 && RN0 < 16)
2531 srcreg2 = REG_D0 + RN0 - 12;
2532 else
2533 srcreg2 = REG_E0 + RN0;
2534
2535 if (RD0 > 7 && RD0 < 12)
2536 dstreg = REG_A0 + RD0 - 8;
2537 else if (RD0 > 11 && RD0 < 16)
2538 dstreg = REG_D0 + RD0 - 12;
2539 else
2540 dstreg = REG_E0 + RD0;
2541
2542 temp = State.regs[srcreg2];
2543 c = temp & 1;
2544 temp >>= State.regs[srcreg1];
2545 State.regs[dstreg] = temp;
2546
2547 z = (State.regs[dstreg] == 0);
2548 n = (State.regs[dstreg] & 0x80000000);
2549
2550 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2551 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2552 }
2553
2554 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2555 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2556 "lsr"
2557 *am33
2558 {
2559 int z, c, n, v;
2560 int srcreg1, srcreg2, dstreg;
2561
2562 PC = cia;
2563
2564 if (RM2 > 7 && RM2 < 12)
2565 srcreg1 = REG_A0 + RM2 - 8;
2566 else if (RM2 > 11 && RM2 < 16)
2567 srcreg1 = REG_D0 + RM2 - 12;
2568 else
2569 srcreg1 = REG_E0 + RM2;
2570
2571 if (RN0 > 7 && RN0 < 12)
2572 srcreg2 = REG_A0 + RN0 - 8;
2573 else if (RN0 > 11 && RN0 < 16)
2574 srcreg2 = REG_D0 + RN0 - 12;
2575 else
2576 srcreg2 = REG_E0 + RN0;
2577
2578 if (RD0 > 7 && RD0 < 12)
2579 dstreg = REG_A0 + RD0 - 8;
2580 else if (RD0 > 11 && RD0 < 16)
2581 dstreg = REG_D0 + RD0 - 12;
2582 else
2583 dstreg = REG_E0 + RD0;
2584
2585 c = State.regs[srcreg2] & 1;
2586 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2587
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2590
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2593 }
2594
2595 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2596 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2597 "asl"
2598 *am33
2599 {
2600 int z, c, n, v;
2601 int srcreg1, srcreg2, dstreg;
2602
2603 PC = cia;
2604
2605 if (RM2 > 7 && RM2 < 12)
2606 srcreg1 = REG_A0 + RM2 - 8;
2607 else if (RM2 > 11 && RM2 < 16)
2608 srcreg1 = REG_D0 + RM2 - 12;
2609 else
2610 srcreg1 = REG_E0 + RM2;
2611
2612 if (RN0 > 7 && RN0 < 12)
2613 srcreg2 = REG_A0 + RN0 - 8;
2614 else if (RN0 > 11 && RN0 < 16)
2615 srcreg2 = REG_D0 + RN0 - 12;
2616 else
2617 srcreg2 = REG_E0 + RN0;
2618
2619 if (RD0 > 7 && RD0 < 12)
2620 dstreg = REG_A0 + RD0 - 8;
2621 else if (RD0 > 11 && RD0 < 16)
2622 dstreg = REG_D0 + RD0 - 12;
2623 else
2624 dstreg = REG_E0 + RD0;
2625
2626 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2627
2628 z = (State.regs[dstreg] == 0);
2629 n = (State.regs[dstreg] & 0x80000000);
2630
2631 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2632 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2633 }
2634
2635 // mul
2636 // mulu
2637 // mov
2638 // mov
2639 // movbu
2640 // movbu
2641 // movhu
2642 // movhu
2643 // mov
2644 // mov
2645 // movbu
2646 // movbu
2647 // movhu
2648 // movhu
2649 // mac
2650 // macu
2651 // macb
2652 // macbu
2653 // mach
2654 // machu
2655 // dmach
2656 // dmachu
2657 // dmulh
2658 // dmulhu
2659 // sat24
2660 // bsch
2661
2662 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
2663 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
2664 "mov"
2665 *am33
2666 {
2667 int dstreg;
2668
2669 PC = cia;
2670
2671 if (RN0 > 7 && RN0 < 12)
2672 dstreg = REG_A0 + RN0 - 8;
2673 else if (RN0 > 11 && RN0 < 16)
2674 dstreg = REG_D0 + RN0 - 12;
2675 else
2676 dstreg = REG_E0 + RN0;
2677
2678 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2679 }
2680
2681 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
2682 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
2683 "movu"
2684 *am33
2685 {
2686 int dstreg;
2687
2688 PC = cia;
2689
2690 if (RN0 > 7 && RN0 < 12)
2691 dstreg = REG_A0 + RN0 - 8;
2692 else if (RN0 > 11 && RN0 < 16)
2693 dstreg = REG_D0 + RN0 - 12;
2694 else
2695 dstreg = REG_E0 + RN0;
2696
2697 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2698 }
2699
2700 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
2701 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
2702 "add"
2703 *am33
2704 {
2705 int dstreg;
2706
2707 PC = cia;
2708
2709 if (RN0 > 7 && RN0 < 12)
2710 dstreg = REG_A0 + RN0 - 8;
2711 else if (RN0 > 11 && RN0 < 16)
2712 dstreg = REG_D0 + RN0 - 12;
2713 else
2714 dstreg = REG_E0 + RN0;
2715
2716 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2717 }
2718
2719 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
2720 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
2721 "addc"
2722 *am33
2723 {
2724 int dstreg, z, n, c, v;
2725 unsigned long sum, imm, reg2;
2726
2727 PC = cia;
2728
2729 if (RN0 > 7 && RN0 < 12)
2730 dstreg = REG_A0 + RN0 - 8;
2731 else if (RN0 > 11 && RN0 < 16)
2732 dstreg = REG_D0 + RN0 - 12;
2733 else
2734 dstreg = REG_E0 + RN0;
2735
2736 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2737 reg2 = State.regs[dstreg];
2738 sum = imm + reg2 + ((PSW & PSW_C) != 0);
2739 State.regs[dstreg] = sum;
2740
2741 z = (sum == 0);
2742 n = (sum & 0x80000000);
2743 c = (sum < imm) || (sum < reg2);
2744 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2745 && (reg2 & 0x80000000) != (sum & 0x80000000));
2746
2747 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2748 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2749 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2750 }
2751
2752 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
2753 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
2754 "sub"
2755 *am33
2756 {
2757 int dstreg;
2758
2759 PC = cia;
2760
2761 if (RN0 > 7 && RN0 < 12)
2762 dstreg = REG_A0 + RN0 - 8;
2763 else if (RN0 > 11 && RN0 < 16)
2764 dstreg = REG_D0 + RN0 - 12;
2765 else
2766 dstreg = REG_E0 + RN0;
2767
2768 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2769 }
2770
2771 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
2772 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
2773 "subc"
2774 *am33
2775 {
2776 int dstreg, z, n, c, v;
2777 unsigned long difference, imm, reg2;
2778
2779 PC = cia;
2780
2781 if (RN0 > 7 && RN0 < 12)
2782 dstreg = REG_A0 + RN0 - 8;
2783 else if (RN0 > 11 && RN0 < 16)
2784 dstreg = REG_D0 + RN0 - 12;
2785 else
2786 dstreg = REG_E0 + RN0;
2787
2788 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2789 reg2 = State.regs[dstreg];
2790 difference = reg2 - imm - ((PSW & PSW_C) != 0);
2791 State.regs[dstreg] = difference;
2792
2793 z = (difference == 0);
2794 n = (difference & 0x80000000);
2795 c = (imm > reg2);
2796 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2797 && (reg2 & 0x80000000) != (difference & 0x80000000));
2798
2799 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2800 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2801 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2802 }
2803
2804 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
2805 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
2806 "cmp"
2807 *am33
2808 {
2809 int srcreg;
2810
2811 PC = cia;
2812
2813 if (RN0 > 7 && RN0 < 12)
2814 srcreg = REG_A0 + RN0 - 8;
2815 else if (RN0 > 11 && RN0 < 16)
2816 srcreg = REG_D0 + RN0 - 12;
2817 else
2818 srcreg = REG_E0 + RN0;
2819
2820 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
2821 }
2822
2823 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
2824 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
2825 "mov"
2826 *am33
2827 {
2828 int dstreg;
2829
2830 PC = cia;
2831
2832 if (XRN0 == 0)
2833 {
2834 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2835 }
2836 else
2837 abort ();
2838 }
2839
2840 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
2841 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
2842 "and"
2843 *am33
2844 {
2845 int dstreg;
2846 int z,n;
2847
2848 PC = cia;
2849
2850 if (RN0 > 7 && RN0 < 12)
2851 dstreg = REG_A0 + RN0 - 8;
2852 else if (RN0 > 11 && RN0 < 16)
2853 dstreg = REG_D0 + RN0 - 12;
2854 else
2855 dstreg = REG_E0 + RN0;
2856
2857 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2858 z = (State.regs[dstreg] == 0);
2859 n = (State.regs[dstreg] & 0x80000000) != 0;
2860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2862 }
2863
2864 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
2865 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
2866 "or"
2867 *am33
2868 {
2869 int dstreg;
2870 int z,n;
2871
2872 PC = cia;
2873
2874 if (RN0 > 7 && RN0 < 12)
2875 dstreg = REG_A0 + RN0 - 8;
2876 else if (RN0 > 11 && RN0 < 16)
2877 dstreg = REG_D0 + RN0 - 12;
2878 else
2879 dstreg = REG_E0 + RN0;
2880
2881 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2882 z = (State.regs[dstreg] == 0);
2883 n = (State.regs[dstreg] & 0x80000000) != 0;
2884 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2885 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2886 }
2887
2888 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
2889 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
2890 "xor"
2891 *am33
2892 {
2893 int dstreg;
2894 int z,n;
2895
2896 PC = cia;
2897
2898 if (RN0 > 7 && RN0 < 12)
2899 dstreg = REG_A0 + RN0 - 8;
2900 else if (RN0 > 11 && RN0 < 16)
2901 dstreg = REG_D0 + RN0 - 12;
2902 else
2903 dstreg = REG_E0 + RN0;
2904
2905 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2906 z = (State.regs[dstreg] == 0);
2907 n = (State.regs[dstreg] & 0x80000000) != 0;
2908 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2909 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2910 }
2911
2912 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
2913 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
2914 "asr"
2915 *am33
2916 {
2917 int dstreg;
2918 long temp;
2919 int c, z, n;
2920
2921 PC = cia;
2922
2923 if (RN0 > 7 && RN0 < 12)
2924 dstreg = REG_A0 + RN0 - 8;
2925 else if (RN0 > 11 && RN0 < 16)
2926 dstreg = REG_D0 + RN0 - 12;
2927 else
2928 dstreg = REG_E0 + RN0;
2929
2930 temp = State.regs[dstreg];
2931 c = temp & 1;
2932 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2933 State.regs[dstreg] = temp;
2934 z = (State.regs[dstreg] == 0);
2935 n = (State.regs[dstreg] & 0x80000000) != 0;
2936 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2937 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2938 }
2939
2940
2941 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
2942 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
2943 "lsr"
2944 *am33
2945 {
2946 int dstreg;
2947 int z, n, c;
2948
2949 PC = cia;
2950
2951 if (RN0 > 7 && RN0 < 12)
2952 dstreg = REG_A0 + RN0 - 8;
2953 else if (RN0 > 11 && RN0 < 16)
2954 dstreg = REG_D0 + RN0 - 12;
2955 else
2956 dstreg = REG_E0 + RN0;
2957
2958 c = State.regs[dstreg] & 1;
2959 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2960 z = (State.regs[dstreg] == 0);
2961 n = (State.regs[dstreg] & 0x80000000) != 0;
2962 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2963 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2964 }
2965
2966 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
2967 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
2968 "asl"
2969 *am33
2970 {
2971 int srcreg, dstreg;
2972 int z, n;
2973
2974 PC = cia;
2975
2976 if (RN0 > 7 && RN0 < 12)
2977 dstreg = REG_A0 + RN0 - 8;
2978 else if (RN0 > 11 && RN0 < 16)
2979 dstreg = REG_D0 + RN0 - 12;
2980 else
2981 dstreg = REG_E0 + RN0;
2982
2983 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
2984 z = (State.regs[dstreg] == 0);
2985 n = (State.regs[dstreg] & 0x80000000) != 0;
2986 PSW &= ~(PSW_Z | PSW_N);
2987 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2988 }
2989
2990 // mul
2991 // mulu
2992
2993 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
2994 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
2995 "btst"
2996 *am33
2997 {
2998 int srcreg;
2999
3000 PC = cia;
3001
3002 if (RN0 > 7 && RN0 < 12)
3003 srcreg = REG_A0 + RN0 - 8;
3004 else if (RN0 > 11 && RN0 < 16)
3005 srcreg = REG_D0 + RN0 - 12;
3006 else
3007 srcreg = REG_E0 + RN0;
3008
3009 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3010 }
3011
3012 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3013 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3014 "mov"
3015 *am33
3016 {
3017 int srcreg, dstreg;
3018
3019 PC = cia;
3020
3021 if (RM0 > 7 && RM0 < 12)
3022 srcreg = REG_A0 + RM0 - 8;
3023 else if (RM0 > 11 && RM0 < 16)
3024 srcreg = REG_D0 + RM0 - 12;
3025 else
3026 srcreg = REG_E0 + RM0;
3027
3028 if (RN2 > 7 && RN2 < 12)
3029 dstreg = REG_A0 + RN2 - 8;
3030 else if (RN2 > 11 && RN2 < 16)
3031 dstreg = REG_D0 + RN2 - 12;
3032 else
3033 dstreg = REG_E0 + RN2;
3034
3035 State.regs[dstreg] = load_word (State.regs[srcreg]
3036 + FETCH24 (IMM24A, IMM24B, IMM24C));
3037 }
3038
3039 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3040 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3041 "mov"
3042 *am33
3043 {
3044 int srcreg, dstreg;
3045
3046 PC = cia;
3047
3048 if (RM2 > 7 && RM2 < 12)
3049 srcreg = REG_A0 + RM2 - 8;
3050 else if (RM2 > 11 && RM2 < 16)
3051 srcreg = REG_D0 + RM2 - 12;
3052 else
3053 srcreg = REG_E0 + RM2;
3054
3055 if (RN0 > 7 && RN0 < 12)
3056 dstreg = REG_A0 + RN0 - 8;
3057 else if (RN0 > 11 && RN0 < 16)
3058 dstreg = REG_D0 + RN0 - 12;
3059 else
3060 dstreg = REG_E0 + RN0;
3061
3062 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3063 State.regs[srcreg]);
3064 }
3065
3066 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3067 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3068 "movbu"
3069 *am33
3070 {
3071 int srcreg, dstreg;
3072
3073 PC = cia;
3074
3075 if (RM0 > 7 && RM0 < 12)
3076 srcreg = REG_A0 + RM0 - 8;
3077 else if (RM0 > 11 && RM0 < 16)
3078 srcreg = REG_D0 + RM0 - 12;
3079 else
3080 srcreg = REG_E0 + RM0;
3081
3082 if (RN2 > 7 && RN2 < 12)
3083 dstreg = REG_A0 + RN2 - 8;
3084 else if (RN2 > 11 && RN2 < 16)
3085 dstreg = REG_D0 + RN2 - 12;
3086 else
3087 dstreg = REG_E0 + RN2;
3088
3089 State.regs[dstreg] = load_byte (State.regs[srcreg]
3090 + FETCH24 (IMM24A, IMM24B, IMM24C));
3091 }
3092
3093 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3094 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3095 "movbu"
3096 *am33
3097 {
3098 int srcreg, dstreg;
3099
3100 PC = cia;
3101
3102 if (RM2 > 7 && RM2 < 12)
3103 srcreg = REG_A0 + RM2 - 8;
3104 else if (RM2 > 11 && RM2 < 16)
3105 srcreg = REG_D0 + RM2 - 12;
3106 else
3107 srcreg = REG_E0 + RM2;
3108
3109 if (RN0 > 7 && RN0 < 12)
3110 dstreg = REG_A0 + RN0 - 8;
3111 else if (RN0 > 11 && RN0 < 16)
3112 dstreg = REG_D0 + RN0 - 12;
3113 else
3114 dstreg = REG_E0 + RN0;
3115
3116 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3117 State.regs[srcreg]);
3118 }
3119
3120 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3121 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3122 "movhu"
3123 *am33
3124 {
3125 int srcreg, dstreg;
3126
3127 PC = cia;
3128
3129 if (RM0 > 7 && RM0 < 12)
3130 srcreg = REG_A0 + RM0 - 8;
3131 else if (RM0 > 11 && RM0 < 16)
3132 srcreg = REG_D0 + RM0 - 12;
3133 else
3134 srcreg = REG_E0 + RM0;
3135
3136 if (RN2 > 7 && RN2 < 12)
3137 dstreg = REG_A0 + RN2 - 8;
3138 else if (RN2 > 11 && RN2 < 16)
3139 dstreg = REG_D0 + RN2 - 12;
3140 else
3141 dstreg = REG_E0 + RN2;
3142
3143 State.regs[dstreg] = load_half (State.regs[srcreg]
3144 + FETCH24 (IMM24A, IMM24B, IMM24C));
3145 }
3146
3147 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3148 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3149 "movhu"
3150 *am33
3151 {
3152 int srcreg, dstreg;
3153
3154 PC = cia;
3155
3156 if (RM2 > 7 && RM2 < 12)
3157 srcreg = REG_A0 + RM2 - 8;
3158 else if (RM2 > 11 && RM2 < 16)
3159 srcreg = REG_D0 + RM2 - 12;
3160 else
3161 srcreg = REG_E0 + RM2;
3162
3163 if (RN0 > 7 && RN0 < 12)
3164 dstreg = REG_A0 + RN0 - 8;
3165 else if (RN0 > 11 && RN0 < 16)
3166 dstreg = REG_D0 + RN0 - 12;
3167 else
3168 dstreg = REG_E0 + RN0;
3169
3170 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3171 State.regs[srcreg]);
3172 }
3173
3174 // mov
3175 // mov
3176
3177 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3178 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3179 "mov"
3180 *am33
3181 {
3182 int dstreg;
3183
3184 PC = cia;
3185
3186 if (RN2 > 7 && RN2 < 12)
3187 dstreg = REG_A0 + RN2 - 8;
3188 else if (RN2 > 11 && RN2 < 16)
3189 dstreg = REG_D0 + RN2 - 12;
3190 else
3191 dstreg = REG_E0 + RN2;
3192
3193 State.regs[dstreg] = load_word (State.regs[REG_SP]
3194 + FETCH24 (IMM24A, IMM24B, IMM24C));
3195 }
3196
3197 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3198 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3199 "mov"
3200 *am33
3201 {
3202 int srcreg;
3203
3204 PC = cia;
3205
3206 if (RM2 > 7 && RM2 < 12)
3207 srcreg = REG_A0 + RM2 - 8;
3208 else if (RM2 > 11 && RM2 < 16)
3209 srcreg = REG_D0 + RM2 - 12;
3210 else
3211 srcreg = REG_E0 + RM2;
3212
3213 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3214 State.regs[srcreg]);
3215 }
3216
3217 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3218 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3219 "movbu"
3220 *am33
3221 {
3222 int dstreg;
3223
3224 PC = cia;
3225
3226 if (RN2 > 7 && RN2 < 12)
3227 dstreg = REG_A0 + RN2 - 8;
3228 else if (RN2 > 11 && RN2 < 16)
3229 dstreg = REG_D0 + RN2 - 12;
3230 else
3231 dstreg = REG_E0 + RN2;
3232
3233 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3234 + FETCH24 (IMM24A, IMM24B, IMM24C));
3235 }
3236
3237 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3238 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3239 "movbu"
3240 *am33
3241 {
3242 int srcreg;
3243
3244 PC = cia;
3245
3246 if (RM2 > 7 && RM2 < 12)
3247 srcreg = REG_A0 + RM2 - 8;
3248 else if (RM2 > 11 && RM2 < 16)
3249 srcreg = REG_D0 + RM2 - 12;
3250 else
3251 srcreg = REG_E0 + RM2;
3252
3253 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3254 State.regs[srcreg]);
3255 }
3256
3257 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3258 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3259 "movhu"
3260 *am33
3261 {
3262 int dstreg;
3263
3264 PC = cia;
3265
3266 if (RN2 > 7 && RN2 < 12)
3267 dstreg = REG_A0 + RN2 - 8;
3268 else if (RN2 > 11 && RN2 < 16)
3269 dstreg = REG_D0 + RN2 - 12;
3270 else
3271 dstreg = REG_E0 + RN2;
3272
3273 State.regs[dstreg] = load_half (State.regs[REG_SP]
3274 + FETCH24 (IMM24A, IMM24B, IMM24C));
3275 }
3276
3277 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3278 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3279 "movhu"
3280 *am33
3281 {
3282 int srcreg;
3283
3284 PC = cia;
3285
3286 if (RM2 > 7 && RM2 < 12)
3287 srcreg = REG_A0 + RM2 - 8;
3288 else if (RM2 > 11 && RM2 < 16)
3289 srcreg = REG_D0 + RM2 - 12;
3290 else
3291 srcreg = REG_E0 + RM2;
3292
3293 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3294 State.regs[srcreg]);
3295 }
3296
3297 // movhu
3298 // movhu
3299 // mac
3300 // macb
3301 // macbu
3302 // mach
3303 // machu
3304
3305 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3306 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3307 "mov"
3308 *am33
3309 {
3310 int dstreg;
3311
3312 PC = cia;
3313
3314 if (RN2 > 7 && RN2 < 12)
3315 dstreg = REG_A0 + RN2 - 8;
3316 else if (RN2 > 11 && RN2 < 16)
3317 dstreg = REG_D0 + RN2 - 12;
3318 else
3319 dstreg = REG_E0 + RN2;
3320
3321 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3322 }
3323
3324 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3325 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3326 "mov"
3327 *am33
3328 {
3329 int srcreg;
3330
3331 PC = cia;
3332
3333 if (RM2 > 7 && RM2 < 12)
3334 srcreg = REG_A0 + RM2 - 8;
3335 else if (RM2 > 11 && RM2 < 16)
3336 srcreg = REG_D0 + RM2 - 12;
3337 else
3338 srcreg = REG_E0 + RM2;
3339
3340 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3341 }
3342
3343
3344 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3345 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3346 "movbu"
3347 *am33
3348 {
3349 int dstreg;
3350
3351 PC = cia;
3352
3353 if (RN2 > 7 && RN2 < 12)
3354 dstreg = REG_A0 + RN2 - 8;
3355 else if (RN2 > 11 && RN2 < 16)
3356 dstreg = REG_D0 + RN2 - 12;
3357 else
3358 dstreg = REG_E0 + RN2;
3359
3360 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3361 }
3362
3363 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3364 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3365 "movbu"
3366 *am33
3367 {
3368 int srcreg;
3369
3370 PC = cia;
3371
3372 if (RM2 > 7 && RM2 < 12)
3373 srcreg = REG_A0 + RM2 - 8;
3374 else if (RM2 > 11 && RM2 < 16)
3375 srcreg = REG_D0 + RM2 - 12;
3376 else
3377 srcreg = REG_E0 + RM2;
3378
3379 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3380 }
3381
3382
3383 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3384 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3385 "movhu"
3386 *am33
3387 {
3388 int dstreg;
3389
3390 PC = cia;
3391
3392 if (RN2 > 7 && RN2 < 12)
3393 dstreg = REG_A0 + RN2 - 8;
3394 else if (RN2 > 11 && RN2 < 16)
3395 dstreg = REG_D0 + RN2 - 12;
3396 else
3397 dstreg = REG_E0 + RN2;
3398
3399 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3400 }
3401
3402 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3403 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3404 "movhu"
3405 *am33
3406 {
3407 int srcreg;
3408
3409 PC = cia;
3410
3411 if (RM2 > 7 && RM2 < 12)
3412 srcreg = REG_A0 + RM2 - 8;
3413 else if (RM2 > 11 && RM2 < 16)
3414 srcreg = REG_D0 + RM2 - 12;
3415 else
3416 srcreg = REG_E0 + RM2;
3417
3418 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3419 }
3420
3421
3422 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3423 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3424 "mov"
3425 *am33
3426 {
3427 int dstreg;
3428
3429 PC = cia;
3430
3431 if (RN0 > 7 && RN0 < 12)
3432 dstreg = REG_A0 + RN0 - 8;
3433 else if (RN0 > 11 && RN0 < 16)
3434 dstreg = REG_D0 + RN0 - 12;
3435 else
3436 dstreg = REG_E0 + RN0;
3437
3438 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3439 }
3440
3441 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3442 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3443 "movu"
3444 *am33
3445 {
3446 int dstreg;
3447
3448 PC = cia;
3449
3450 if (RN0 > 7 && RN0 < 12)
3451 dstreg = REG_A0 + RN0 - 8;
3452 else if (RN0 > 11 && RN0 < 16)
3453 dstreg = REG_D0 + RN0 - 12;
3454 else
3455 dstreg = REG_E0 + RN0;
3456
3457 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3458 }
3459
3460 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3461 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3462 "add"
3463 *am33
3464 {
3465 int dstreg;
3466
3467 PC = cia;
3468
3469 if (RN0 > 7 && RN0 < 12)
3470 dstreg = REG_A0 + RN0 - 8;
3471 else if (RN0 > 11 && RN0 < 16)
3472 dstreg = REG_D0 + RN0 - 12;
3473 else
3474 dstreg = REG_E0 + RN0;
3475
3476 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3477 }
3478
3479 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3480 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3481 "addc"
3482 *am33
3483 {
3484 int dstreg;
3485 unsigned int imm, reg2, sum;
3486 int z, n, c, v;
3487
3488 PC = cia;
3489
3490 if (RN0 > 7 && RN0 < 12)
3491 dstreg = REG_A0 + RN0 - 8;
3492 else if (RN0 > 11 && RN0 < 16)
3493 dstreg = REG_D0 + RN0 - 12;
3494 else
3495 dstreg = REG_E0 + RN0;
3496
3497 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3498 reg2 = State.regs[dstreg];
3499 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3500 State.regs[dstreg] = sum;
3501
3502 z = (sum == 0);
3503 n = (sum & 0x80000000);
3504 c = (sum < imm) || (sum < reg2);
3505 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3506 && (reg2 & 0x80000000) != (sum & 0x80000000));
3507
3508 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3509 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3510 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3511 }
3512
3513 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3514 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3515 "sub"
3516 *am33
3517 {
3518 int dstreg;
3519
3520 PC = cia;
3521
3522 if (RN0 > 7 && RN0 < 12)
3523 dstreg = REG_A0 + RN0 - 8;
3524 else if (RN0 > 11 && RN0 < 16)
3525 dstreg = REG_D0 + RN0 - 12;
3526 else
3527 dstreg = REG_E0 + RN0;
3528
3529 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3530 }
3531
3532 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3533 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3534 "subc"
3535 *am33
3536 {
3537 int dstreg;
3538 unsigned int imm, reg2, difference;
3539 int z, n, c, v;
3540
3541 PC = cia;
3542
3543 if (RN0 > 7 && RN0 < 12)
3544 dstreg = REG_A0 + RN0 - 8;
3545 else if (RN0 > 11 && RN0 < 16)
3546 dstreg = REG_D0 + RN0 - 12;
3547 else
3548 dstreg = REG_E0 + RN0;
3549
3550 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3551 reg2 = State.regs[dstreg];
3552 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3553 State.regs[dstreg] = difference;
3554
3555 z = (difference == 0);
3556 n = (difference & 0x80000000);
3557 c = (imm > reg2);
3558 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3559 && (reg2 & 0x80000000) != (difference & 0x80000000));
3560
3561 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3562 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3563 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3564 }
3565
3566 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3567 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3568 "cmp"
3569 *am33
3570 {
3571 int srcreg;
3572
3573 PC = cia;
3574
3575 if (RN0 > 7 && RN0 < 12)
3576 srcreg = REG_A0 + RN0 - 8;
3577 else if (RN0 > 11 && RN0 < 16)
3578 srcreg = REG_D0 + RN0 - 12;
3579 else
3580 srcreg = REG_E0 + RN0;
3581
3582 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3583 }
3584
3585 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3586 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3587 "mov"
3588 *am33
3589 {
3590 int dstreg;
3591
3592 PC = cia;
3593
3594 if (XRN0 == 0)
3595 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3596 else
3597 abort ();
3598 }
3599
3600 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3601 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
3602 "and"
3603 *am33
3604 {
3605 int dstreg;
3606 int z,n;
3607
3608 PC = cia;
3609
3610 if (RN0 > 7 && RN0 < 12)
3611 dstreg = REG_A0 + RN0 - 8;
3612 else if (RN0 > 11 && RN0 < 16)
3613 dstreg = REG_D0 + RN0 - 12;
3614 else
3615 dstreg = REG_E0 + RN0;
3616
3617 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3618 z = (State.regs[dstreg] == 0);
3619 n = (State.regs[dstreg] & 0x80000000) != 0;
3620 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3621 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3622 }
3623
3624 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
3625 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
3626 "or"
3627 *am33
3628 {
3629 int dstreg;
3630 int z,n;
3631
3632 PC = cia;
3633
3634 if (RN0 > 7 && RN0 < 12)
3635 dstreg = REG_A0 + RN0 - 8;
3636 else if (RN0 > 11 && RN0 < 16)
3637 dstreg = REG_D0 + RN0 - 12;
3638 else
3639 dstreg = REG_E0 + RN0;
3640
3641 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3642 z = (State.regs[dstreg] == 0);
3643 n = (State.regs[dstreg] & 0x80000000) != 0;
3644 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3645 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3646 }
3647
3648 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
3649 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
3650 "xor"
3651 *am33
3652 {
3653 int dstreg;
3654 int z,n;
3655
3656 PC = cia;
3657
3658 if (RN0 > 7 && RN0 < 12)
3659 dstreg = REG_A0 + RN0 - 8;
3660 else if (RN0 > 11 && RN0 < 16)
3661 dstreg = REG_D0 + RN0 - 12;
3662 else
3663 dstreg = REG_E0 + RN0;
3664
3665 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3666 z = (State.regs[dstreg] == 0);
3667 n = (State.regs[dstreg] & 0x80000000) != 0;
3668 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3669 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3670 }
3671
3672 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
3673 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
3674 "asr"
3675 *am33
3676 {
3677 int dstreg;
3678 long temp;
3679 int c, z, n;
3680
3681 PC = cia;
3682
3683 if (RN0 > 7 && RN0 < 12)
3684 dstreg = REG_A0 + RN0 - 8;
3685 else if (RN0 > 11 && RN0 < 16)
3686 dstreg = REG_D0 + RN0 - 12;
3687 else
3688 dstreg = REG_E0 + RN0;
3689
3690 temp = State.regs[dstreg];
3691 c = temp & 1;
3692 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3693 State.regs[dstreg] = temp;
3694 z = (State.regs[dstreg] == 0);
3695 n = (State.regs[dstreg] & 0x80000000) != 0;
3696 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3697 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3698 }
3699
3700 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
3701 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
3702 "lsr"
3703 *am33
3704 {
3705 int dstreg;
3706 int z, n, c;
3707
3708 PC = cia;
3709
3710 if (RN0 > 7 && RN0 < 12)
3711 dstreg = REG_A0 + RN0 - 8;
3712 else if (RN0 > 11 && RN0 < 16)
3713 dstreg = REG_D0 + RN0 - 12;
3714 else
3715 dstreg = REG_E0 + RN0;
3716
3717 c = State.regs[dstreg] & 1;
3718 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3719 z = (State.regs[dstreg] == 0);
3720 n = (State.regs[dstreg] & 0x80000000) != 0;
3721 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3722 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3723 }
3724
3725 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
3726 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
3727 "asl"
3728 *am33
3729 {
3730 int srcreg, dstreg;
3731 int z, n;
3732
3733 PC = cia;
3734
3735 if (RN0 > 7 && RN0 < 12)
3736 dstreg = REG_A0 + RN0 - 8;
3737 else if (RN0 > 11 && RN0 < 16)
3738 dstreg = REG_D0 + RN0 - 12;
3739 else
3740 dstreg = REG_E0 + RN0;
3741
3742 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3743 z = (State.regs[dstreg] == 0);
3744 n = (State.regs[dstreg] & 0x80000000) != 0;
3745 PSW &= ~(PSW_Z | PSW_N);
3746 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3747 }
3748
3749 // mul
3750 // mulu
3751
3752 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
3753 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
3754 "btst"
3755 *am33
3756 {
3757 int srcreg;
3758
3759 PC = cia;
3760
3761 if (RN0 > 7 && RN0 < 12)
3762 srcreg = REG_A0 + RN0 - 8;
3763 else if (RN0 > 11 && RN0 < 16)
3764 srcreg = REG_D0 + RN0 - 12;
3765 else
3766 srcreg = REG_E0 + RN0;
3767
3768 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3769 }
3770
3771 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
3772 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
3773 "mov"
3774 *am33
3775 {
3776 int srcreg, dstreg;
3777
3778 PC = cia;
3779
3780 if (RM0 > 7 && RM0 < 12)
3781 srcreg = REG_A0 + RM0 - 8;
3782 else if (RM0 > 11 && RM0 < 16)
3783 srcreg = REG_D0 + RM0 - 12;
3784 else
3785 srcreg = REG_E0 + RM0;
3786
3787 if (RN2 > 7 && RN2 < 12)
3788 dstreg = REG_A0 + RN2 - 8;
3789 else if (RN2 > 11 && RN2 < 16)
3790 dstreg = REG_D0 + RN2 - 12;
3791 else
3792 dstreg = REG_E0 + RN2;
3793
3794 State.regs[dstreg] = load_word (State.regs[srcreg]
3795 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3796 }
3797
3798 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
3799 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
3800 "mov"
3801 *am33
3802 {
3803 int srcreg, dstreg;
3804
3805 PC = cia;
3806
3807 if (RM2 > 7 && RM2 < 12)
3808 srcreg = REG_A0 + RM2 - 8;
3809 else if (RM2 > 11 && RM2 < 16)
3810 srcreg = REG_D0 + RM2 - 12;
3811 else
3812 srcreg = REG_E0 + RM2;
3813
3814 if (RN0 > 7 && RN0 < 12)
3815 dstreg = REG_A0 + RN0 - 8;
3816 else if (RN0 > 11 && RN0 < 16)
3817 dstreg = REG_D0 + RN0 - 12;
3818 else
3819 dstreg = REG_E0 + RN0;
3820
3821 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3822 State.regs[srcreg]);
3823 }
3824
3825 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
3826 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
3827 "movbu"
3828 *am33
3829 {
3830 int srcreg, dstreg;
3831
3832 PC = cia;
3833
3834 if (RM0 > 7 && RM0 < 12)
3835 srcreg = REG_A0 + RM0 - 8;
3836 else if (RM0 > 11 && RM0 < 16)
3837 srcreg = REG_D0 + RM0 - 12;
3838 else
3839 srcreg = REG_E0 + RM0;
3840
3841 if (RN2 > 7 && RN2 < 12)
3842 dstreg = REG_A0 + RN2 - 8;
3843 else if (RN2 > 11 && RN2 < 16)
3844 dstreg = REG_D0 + RN2 - 12;
3845 else
3846 dstreg = REG_E0 + RN2;
3847
3848 State.regs[dstreg] = load_byte (State.regs[srcreg]
3849 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3850 }
3851
3852 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
3853 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
3854 "movbu"
3855 *am33
3856 {
3857 int srcreg, dstreg;
3858
3859 PC = cia;
3860
3861 if (RM2 > 7 && RM2 < 12)
3862 srcreg = REG_A0 + RM2 - 8;
3863 else if (RM2 > 11 && RM2 < 16)
3864 srcreg = REG_D0 + RM2 - 12;
3865 else
3866 srcreg = REG_E0 + RM2;
3867
3868 if (RN0 > 7 && RN0 < 12)
3869 dstreg = REG_A0 + RN0 - 8;
3870 else if (RN0 > 11 && RN0 < 16)
3871 dstreg = REG_D0 + RN0 - 12;
3872 else
3873 dstreg = REG_E0 + RN0;
3874
3875 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3876 State.regs[srcreg]);
3877 }
3878
3879 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
3880 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
3881 "movhu"
3882 *am33
3883 {
3884 int srcreg, dstreg;
3885
3886 PC = cia;
3887
3888 if (RM0 > 7 && RM0 < 12)
3889 srcreg = REG_A0 + RM0 - 8;
3890 else if (RM0 > 11 && RM0 < 16)
3891 srcreg = REG_D0 + RM0 - 12;
3892 else
3893 srcreg = REG_E0 + RM0;
3894
3895 if (RN2 > 7 && RN2 < 12)
3896 dstreg = REG_A0 + RN2 - 8;
3897 else if (RN2 > 11 && RN2 < 16)
3898 dstreg = REG_D0 + RN2 - 12;
3899 else
3900 dstreg = REG_E0 + RN2;
3901
3902 State.regs[dstreg] = load_half (State.regs[srcreg]
3903 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3904 }
3905
3906 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
3907 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
3908 "movhu"
3909 *am33
3910 {
3911 int srcreg, dstreg;
3912
3913 PC = cia;
3914
3915 if (RM2 > 7 && RM2 < 12)
3916 srcreg = REG_A0 + RM2 - 8;
3917 else if (RM2 > 11 && RM2 < 16)
3918 srcreg = REG_D0 + RM2 - 12;
3919 else
3920 srcreg = REG_E0 + RM2;
3921
3922 if (RN0 > 7 && RN0 < 12)
3923 dstreg = REG_A0 + RN0 - 8;
3924 else if (RN0 > 11 && RN0 < 16)
3925 dstreg = REG_D0 + RN0 - 12;
3926 else
3927 dstreg = REG_E0 + RN0;
3928
3929 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3930 State.regs[srcreg]);
3931 }
3932
3933 // mov
3934 // mov
3935
3936 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
3937 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
3938 "mov"
3939 *am33
3940 {
3941 int dstreg;
3942
3943 PC = cia;
3944
3945 if (RN2 > 7 && RN2 < 12)
3946 dstreg = REG_A0 + RN2 - 8;
3947 else if (RN2 > 11 && RN2 < 16)
3948 dstreg = REG_D0 + RN2 - 12;
3949 else
3950 dstreg = REG_E0 + RN2;
3951
3952 State.regs[dstreg] = load_word (State.regs[REG_SP]
3953 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3954 }
3955
3956 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
3957 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
3958 "mov"
3959 *am33
3960 {
3961 int srcreg;
3962
3963 PC = cia;
3964
3965 if (RM2 > 7 && RM2 < 12)
3966 srcreg = REG_A0 + RM2 - 8;
3967 else if (RM2 > 11 && RM2 < 16)
3968 srcreg = REG_D0 + RM2 - 12;
3969 else
3970 srcreg = REG_E0 + RM2;
3971
3972 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3973 State.regs[srcreg]);
3974 }
3975
3976 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
3977 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
3978 "movbu"
3979 *am33
3980 {
3981 int dstreg;
3982
3983 PC = cia;
3984
3985 if (RN2 > 7 && RN2 < 12)
3986 dstreg = REG_A0 + RN2 - 8;
3987 else if (RN2 > 11 && RN2 < 16)
3988 dstreg = REG_D0 + RN2 - 12;
3989 else
3990 dstreg = REG_E0 + RN2;
3991
3992 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3993 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3994 }
3995
3996 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
3997 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
3998 "movbu"
3999 *am33
4000 {
4001 int srcreg;
4002
4003 PC = cia;
4004
4005 if (RM2 > 7 && RM2 < 12)
4006 srcreg = REG_A0 + RM2 - 8;
4007 else if (RM2 > 11 && RM2 < 16)
4008 srcreg = REG_D0 + RM2 - 12;
4009 else
4010 srcreg = REG_E0 + RM2;
4011
4012 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4013 State.regs[srcreg]);
4014 }
4015
4016 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4017 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4018 "movhu"
4019 *am33
4020 {
4021 int dstreg;
4022
4023 PC = cia;
4024
4025 if (RN2 > 7 && RN2 < 12)
4026 dstreg = REG_A0 + RN2 - 8;
4027 else if (RN2 > 11 && RN2 < 16)
4028 dstreg = REG_D0 + RN2 - 12;
4029 else
4030 dstreg = REG_E0 + RN2;
4031
4032 State.regs[dstreg] = load_half (State.regs[REG_SP]
4033 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4034 }
4035
4036 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4037 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4038 "movhu"
4039 *am33
4040 {
4041 int srcreg;
4042
4043 PC = cia;
4044
4045 if (RM2 > 7 && RM2 < 12)
4046 srcreg = REG_A0 + RM2 - 8;
4047 else if (RM2 > 11 && RM2 < 16)
4048 srcreg = REG_D0 + RM2 - 12;
4049 else
4050 srcreg = REG_E0 + RM2;
4051
4052 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4053 State.regs[srcreg]);
4054 }
4055
4056
4057 // movhu
4058 // movhu
4059
4060 // mac
4061 // macu
4062 // macb
4063 // macbu
4064 // mach
4065 // machu
4066 // dmach
4067 // dmachu
4068 // dmulh
4069 // dmulhu
4070
4071 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4072 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4073 "mov"
4074 *am33
4075 {
4076 int dstreg;
4077
4078 PC = cia;
4079
4080 if (RN2 > 7 && RN2 < 12)
4081 dstreg = REG_A0 + RN2 - 8;
4082 else if (RN2 > 11 && RN2 < 16)
4083 dstreg = REG_D0 + RN2 - 12;
4084 else
4085 dstreg = REG_E0 + RN2;
4086
4087 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4088 }
4089
4090 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4091 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4092 "mov"
4093 *am33
4094 {
4095 int srcreg;
4096
4097 PC = cia;
4098
4099 if (RM2 > 7 && RM2 < 12)
4100 srcreg = REG_A0 + RM2 - 8;
4101 else if (RM2 > 11 && RM2 < 16)
4102 srcreg = REG_D0 + RM2 - 12;
4103 else
4104 srcreg = REG_E0 + RM2;
4105
4106 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4107 }
4108
4109 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4110 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4111 "movbu"
4112 *am33
4113 {
4114 int dstreg;
4115
4116 PC = cia;
4117
4118 if (RN2 > 7 && RN2 < 12)
4119 dstreg = REG_A0 + RN2 - 8;
4120 else if (RN2 > 11 && RN2 < 16)
4121 dstreg = REG_D0 + RN2 - 12;
4122 else
4123 dstreg = REG_E0 + RN2;
4124
4125 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4126 }
4127
4128 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4129 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4130 "movbu"
4131 *am33
4132 {
4133 int srcreg;
4134
4135 PC = cia;
4136
4137 if (RM2 > 7 && RM2 < 12)
4138 srcreg = REG_A0 + RM2 - 8;
4139 else if (RM2 > 11 && RM2 < 16)
4140 srcreg = REG_D0 + RM2 - 12;
4141 else
4142 srcreg = REG_E0 + RM2;
4143
4144 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4145 }
4146
4147 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4148 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4149 "movhu"
4150 *am33
4151 {
4152 int dstreg;
4153
4154 PC = cia;
4155
4156 if (RN2 > 7 && RN2 < 12)
4157 dstreg = REG_A0 + RN2 - 8;
4158 else if (RN2 > 11 && RN2 < 16)
4159 dstreg = REG_D0 + RN2 - 12;
4160 else
4161 dstreg = REG_E0 + RN2;
4162
4163 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4164 }
4165
4166 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4167 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4168 "movhu"
4169 *am33
4170 {
4171 int srcreg;
4172
4173 PC = cia;
4174
4175 if (RM2 > 7 && RM2 < 12)
4176 srcreg = REG_A0 + RM2 - 8;
4177 else if (RM2 > 11 && RM2 < 16)
4178 srcreg = REG_D0 + RM2 - 12;
4179 else
4180 srcreg = REG_E0 + RM2;
4181
4182 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4183 }
4184
4185 // movbu
4186 // movbu
4187 // movhu
4188 // movhu
4189
4190 // DSP
GDB Binutils - Deliverables
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