3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
58 State.regs[REG_A0 + AN0] = PC;
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
95 unsigned int sp, next_pc;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
113 State.regs[REG_D0 + DN0] = PSW;
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
123 PSW = State.regs[REG_D0 + DM1];
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
131 int destreg = translate_rreg (SD_, RN0);
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
142 int destreg = translate_rreg (SD_, RN0);
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
153 int destreg = translate_rreg (SD_, RM1);
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
164 int destreg = translate_rreg (SD_, RM1);
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
176 unsigned long usp = State.regs[REG_USP];
185 State.regs[REG_LAR] = load_word (usp);
187 State.regs[REG_LIR] = load_word (usp);
189 State.regs[REG_MDR] = load_word (usp);
191 State.regs[REG_A0 + 1] = load_word (usp);
193 State.regs[REG_A0] = load_word (usp);
195 State.regs[REG_D0 + 1] = load_word (usp);
197 State.regs[REG_D0] = load_word (usp);
203 State.regs[REG_A0 + 3] = load_word (usp);
209 State.regs[REG_A0 + 2] = load_word (usp);
215 State.regs[REG_D0 + 3] = load_word (usp);
221 State.regs[REG_D0 + 2] = load_word (usp);
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
232 State.regs[REG_E0 + 1] = load_word (usp);
234 State.regs[REG_E0 + 0] = load_word (usp);
240 State.regs[REG_E0 + 7] = load_word (usp);
242 State.regs[REG_E0 + 6] = load_word (usp);
244 State.regs[REG_E0 + 5] = load_word (usp);
246 State.regs[REG_E0 + 4] = load_word (usp);
252 State.regs[REG_E0 + 3] = load_word (usp);
254 State.regs[REG_E0 + 2] = load_word (usp);
258 /* end-sanitize-am33 */
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
269 unsigned long usp = State.regs[REG_USP];
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
277 store_word (usp, State.regs[REG_E0 + 2]);
279 store_word (usp, State.regs[REG_E0 + 3]);
285 store_word (usp, State.regs[REG_E0 + 4]);
287 store_word (usp, State.regs[REG_E0 + 5]);
289 store_word (usp, State.regs[REG_E0 + 6]);
291 store_word (usp, State.regs[REG_E0 + 7]);
297 store_word (usp, State.regs[REG_E0 + 0]);
299 store_word (usp, State.regs[REG_E0 + 1]);
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
304 /* end-sanitize-am33 */
309 store_word (usp, State.regs[REG_D0 + 2]);
315 store_word (usp, State.regs[REG_D0 + 3]);
321 store_word (usp, State.regs[REG_A0 + 2]);
327 store_word (usp, State.regs[REG_A0 + 3]);
333 store_word (usp, State.regs[REG_D0]);
335 store_word (usp, State.regs[REG_D0 + 1]);
337 store_word (usp, State.regs[REG_A0]);
339 store_word (usp, State.regs[REG_A0 + 1]);
341 store_word (usp, State.regs[REG_MDR]);
343 store_word (usp, State.regs[REG_LIR]);
345 store_word (usp, State.regs[REG_LAR]);
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
397 State.regs[REG_MDR] = 0;
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
486 unsigned long reg1, reg2, sum;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
528 unsigned long reg1, reg2, difference;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
540 n = (difference & 0x80000000);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
579 int srcreg1, srcreg2;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
595 dstreg = translate_rreg (SD_, RN0);
599 State.regs[dstreg] = State.regs[REG_SP];
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
613 srcreg = translate_rreg (SD_, RM2);
617 State.regs[REG_SP] = State.regs[srcreg];
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
690 dstreg = translate_rreg (SD_, RN0);
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
712 temp = State.regs[dstreg];
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
771 dstreg = translate_rreg (SD_, RN0);
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790 dstreg = translate_rreg (SD_, RN0);
792 value = State.regs[dstreg];
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814 dstreg = translate_rreg (SD_, RN0);
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
834 unsigned long long temp;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
857 unsigned long long temp;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
887 temp = State.regs[REG_MDR];
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (signed32)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
905 unsigned long long temp;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
912 temp = State.regs[REG_MDR];
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1157 State.regs[REG_MCVF] = 1;
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1185 State.regs[REG_MCVF] = 1;
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1193 int srcreg1, srcreg2;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1208 State.regs[REG_MCVF] = 1;
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1231 State.regs[REG_MCVF] = 1;
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1259 State.regs[REG_MCVF] = 1;
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1287 State.regs[REG_MCVF] = 1;
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCVF] = 1;
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1337 State.regs[REG_MCVF] = 1;
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1392 value = State.regs[srcreg];
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1399 State.regs[dstreg] = value;
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1407 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1408 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1426 tmp = State.regs[REG_MCRH];
1428 tmp += State.regs[REG_MCRL];
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1435 State.regs[dstreg] = tmp;
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1442 tmp = State.regs[REG_MCRH];
1444 tmp += State.regs[REG_MCRL];
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1451 State.regs[dstreg] = tmp;
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1458 tmp = State.regs[REG_MCRH];
1460 tmp += State.regs[REG_MCRL];
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1467 State.regs[dstreg] = tmp;
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1474 tmp = State.regs[REG_MCRH];
1476 tmp += State.regs[REG_MCRL];
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1483 State.regs[dstreg] = tmp;
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1490 tmp = State.regs[REG_MCRH];
1492 tmp += State.regs[REG_MCRL];
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1500 State.regs[dstreg] = tmp;
1504 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1505 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
1521 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1522 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1538 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1539 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
1553 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1554 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1571 for (i = start; i >= 0; i--)
1573 if (temp & (1 << i))
1576 State.regs[dstreg] = i;
1584 State.regs[dstreg] = 0;
1587 PSW |= (c ? PSW_C : 0);
1591 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1592 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1599 dstreg = translate_rreg (SD_, RN0);
1600 State.regs[dstreg] = EXTEND8 (IMM8);
1603 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1604 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1611 dstreg = translate_rreg (SD_, RN0);
1612 State.regs[dstreg] = IMM8 & 0xff;
1615 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1616 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1623 dstreg = translate_rreg (SD_, RN0);
1624 genericAdd (EXTEND8 (IMM8), dstreg);
1627 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1628 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1634 unsigned long reg1, reg2, sum;
1637 dstreg = translate_rreg (SD_, RN0);
1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1644 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1655 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1656 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1663 dstreg = translate_rreg (SD_, RN0);
1665 genericSub (EXTEND8 (IMM8), dstreg);
1668 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1669 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1675 unsigned long reg1, reg2, difference;
1678 dstreg = translate_rreg (SD_, RN0);
1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
1685 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1686 n = (difference & 0x80000000);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1696 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1697 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1704 srcreg = translate_rreg (SD_, RN0);
1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1708 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1709 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1718 State.regs[REG_SP] = IMM8;
1723 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1724 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1732 dstreg = translate_rreg (SD_, RN0);
1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1741 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1742 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1750 dstreg = translate_rreg (SD_, RN0);
1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1759 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1760 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1768 dstreg = translate_rreg (SD_, RN0);
1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1777 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1778 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1787 dstreg = translate_rreg (SD_, RN0);
1789 temp = State.regs[dstreg];
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1808 dstreg = translate_rreg (SD_, RN0);
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1818 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1819 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1827 dstreg = translate_rreg (SD_, RN0);
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1836 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1837 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1842 unsigned long long temp;
1846 dstreg = translate_rreg (SD_, RN0);
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1858 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1859 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1864 unsigned long long temp;
1868 dstreg = translate_rreg (SD_, RN0);
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1880 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1881 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1888 srcreg = translate_rreg (SD_, RM0);
1889 genericBtst(IMM8, State.regs[srcreg]);
1892 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1893 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1900 srcreg = translate_rreg (SD_, RM0);
1901 dstreg = translate_rreg (SD_, RN2);
1902 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1905 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1906 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1912 srcreg = translate_rreg (SD_, RM2);
1913 dstreg = translate_rreg (SD_, RN0);
1914 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1917 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1918 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1924 srcreg = translate_rreg (SD_, RM0);
1925 dstreg = translate_rreg (SD_, RN2);
1926 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1929 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1930 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1936 srcreg = translate_rreg (SD_, RM2);
1937 dstreg = translate_rreg (SD_, RN0);
1938 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1941 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1942 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1948 srcreg = translate_rreg (SD_, RM0);
1949 dstreg = translate_rreg (SD_, RN2);
1950 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1953 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1954 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1960 srcreg = translate_rreg (SD_, RM2);
1961 dstreg = translate_rreg (SD_, RN0);
1962 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1965 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1966 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1973 srcreg = translate_rreg (SD_, RM0);
1974 dstreg = translate_rreg (SD_, RN2);
1975 State.regs[dstreg] = load_word (State.regs[srcreg]);
1976 State.regs[srcreg] += EXTEND8 (IMM8);
1979 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1980 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1986 srcreg = translate_rreg (SD_, RM2);
1987 dstreg = translate_rreg (SD_, RN0);
1988 store_word (State.regs[dstreg], State.regs[srcreg]);
1989 State.regs[dstreg] += EXTEND8 (IMM8);
1993 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1994 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2000 dstreg = translate_rreg (SD_, RN2);
2001 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2004 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2005 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2011 srcreg = translate_rreg (SD_, RM2);
2012 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2015 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2016 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2022 dstreg = translate_rreg (SD_, RN2);
2023 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2026 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2027 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2033 srcreg = translate_rreg (SD_, RM2);
2034 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2037 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2038 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2044 dstreg = translate_rreg (SD_, RN2);
2045 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2048 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2049 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2055 srcreg = translate_rreg (SD_, RM2);
2056 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2059 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2060 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2067 srcreg = translate_rreg (SD_, RM0);
2068 dstreg = translate_rreg (SD_, RN2);
2069 State.regs[dstreg] = load_half (State.regs[srcreg]);
2070 State.regs[srcreg] += EXTEND8 (IMM8);
2073 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2074 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2080 srcreg = translate_rreg (SD_, RM2);
2081 dstreg = translate_rreg (SD_, RN0);
2082 store_half (State.regs[dstreg], State.regs[srcreg]);
2083 State.regs[dstreg] += EXTEND8 (IMM8);
2087 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2088 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2092 long long temp, sum;
2096 srcreg = translate_rreg (SD_, RN2);
2098 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2099 * (signed64)(signed32)State.regs[srcreg]);
2100 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2101 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2102 State.regs[REG_MCRL] = sum;
2105 sum = State.regs[REG_MCRH] + temp + c;
2106 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2107 && (temp & 0x80000000) != (sum & 0x80000000));
2108 State.regs[REG_MCRH] = sum;
2110 State.regs[REG_MCVF] = 1;
2113 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2114 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2118 long long temp, sum;
2122 srcreg = translate_rreg (SD_, RN2);
2124 temp = ((unsigned64) (IMM8)
2125 * (unsigned64)State.regs[srcreg]);
2126 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2127 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2128 State.regs[REG_MCRL] = sum;
2131 sum = State.regs[REG_MCRH] + temp + c;
2132 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2133 && (temp & 0x80000000) != (sum & 0x80000000));
2134 State.regs[REG_MCRH] = sum;
2136 State.regs[REG_MCVF] = 1;
2139 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2140 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2144 long long temp, sum;
2148 srcreg = translate_rreg (SD_, RN2);
2150 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2151 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2152 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2153 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2154 State.regs[REG_MCRL] = sum;
2157 sum = State.regs[REG_MCRH] + temp + c;
2158 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2159 && (temp & 0x80000000) != (sum & 0x80000000));
2160 State.regs[REG_MCRH] = sum;
2162 State.regs[REG_MCVF] = 1;
2165 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2166 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2170 long long temp, sum;
2174 srcreg = translate_rreg (SD_, RN2);
2176 temp = ((unsigned64) (IMM8)
2177 * (unsigned64)State.regs[srcreg] & 0xff);
2178 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2179 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2180 State.regs[REG_MCRL] = sum;
2183 sum = State.regs[REG_MCRH] + temp + c;
2184 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2185 && (temp & 0x80000000) != (sum & 0x80000000));
2186 State.regs[REG_MCRH] = sum;
2188 State.regs[REG_MCVF] = 1;
2191 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2192 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2196 long long temp, sum;
2200 srcreg = translate_rreg (SD_, RN2);
2202 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2203 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2204 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2205 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2206 State.regs[REG_MCRL] = sum;
2209 sum = State.regs[REG_MCRH] + temp + c;
2210 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2211 && (temp & 0x80000000) != (sum & 0x80000000));
2212 State.regs[REG_MCRH] = sum;
2214 State.regs[REG_MCVF] = 1;
2217 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2218 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2222 long long temp, sum;
2226 srcreg = translate_rreg (SD_, RN2);
2228 temp = ((unsigned64) (IMM8)
2229 * (unsigned64)State.regs[srcreg] & 0xffff);
2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2240 State.regs[REG_MCVF] = 1;
2243 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2244 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2250 dstreg = translate_rreg (SD_, RN0);
2252 PSW &= ~(PSW_V | PSW_C);
2253 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2255 /* 32bit saturation. */
2260 tmp = State.regs[REG_MCRH];
2262 tmp += State.regs[REG_MCRL];
2264 if (tmp > 0x7fffffff)
2265 State.regs[dstreg] = 0x7fffffff;
2266 else if (tmp < 0xffffffff80000000LL)
2267 State.regs[dstreg] = 0x80000000;
2269 State.regs[dstreg] = tmp;
2271 /* 16bit saturation */
2272 else if (IMM8 == 0x10)
2276 tmp = State.regs[REG_MCRH];
2278 tmp += State.regs[REG_MCRL];
2281 State.regs[dstreg] = 0x7fff;
2282 else if (tmp < 0xffffffffffff8000LL)
2283 State.regs[dstreg] = 0x8000;
2285 State.regs[dstreg] = tmp;
2287 /* 8 bit saturation */
2288 else if (IMM8 == 0x8)
2292 tmp = State.regs[REG_MCRH];
2294 tmp += State.regs[REG_MCRL];
2297 State.regs[dstreg] = 0x7f;
2298 else if (tmp < 0xffffffffffffff80LL)
2299 State.regs[dstreg] = 0x80;
2301 State.regs[dstreg] = tmp;
2303 /* 9 bit saturation */
2304 else if (IMM8 == 0x9)
2308 tmp = State.regs[REG_MCRH];
2310 tmp += State.regs[REG_MCRL];
2313 State.regs[dstreg] = 0x80;
2314 else if (tmp < 0xffffffffffffff81LL)
2315 State.regs[dstreg] = 0x81;
2317 State.regs[dstreg] = tmp;
2319 /* 9 bit saturation */
2320 else if (IMM8 == 0x30)
2324 tmp = State.regs[REG_MCRH];
2326 tmp += State.regs[REG_MCRL];
2328 if (tmp > 0x7fffffffffffLL)
2329 tmp = 0x7fffffffffffLL;
2330 else if (tmp < 0xffff800000000000LL)
2331 tmp = 0xffff800000000000LL;
2334 State.regs[dstreg] = tmp;
2338 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2339 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2344 unsigned long sum, source1, source2;
2345 int srcreg1, srcreg2, dstreg;
2348 srcreg1 = translate_rreg (SD_, RM2);
2349 srcreg2 = translate_rreg (SD_, RN0);
2350 dstreg = translate_rreg (SD_, RD0);
2352 source1 = State.regs[srcreg1];
2353 source2 = State.regs[srcreg2];
2354 sum = source1 + source2;
2355 State.regs[dstreg] = sum;
2358 n = (sum & 0x80000000);
2359 c = (sum < source1) || (sum < source2);
2360 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2361 && (source1 & 0x80000000) != (sum & 0x80000000));
2363 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2364 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2365 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2368 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2369 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2374 unsigned long sum, source1, source2;
2375 int srcreg1, srcreg2, dstreg;
2378 srcreg1 = translate_rreg (SD_, RM2);
2379 srcreg2 = translate_rreg (SD_, RN0);
2380 dstreg = translate_rreg (SD_, RD0);
2382 source1 = State.regs[srcreg1];
2383 source2 = State.regs[srcreg2];
2384 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2385 State.regs[dstreg] = sum;
2387 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2388 n = (sum & 0x80000000);
2389 c = (sum < source1) || (sum < source2);
2390 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2391 && (source1 & 0x80000000) != (sum & 0x80000000));
2393 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2394 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2395 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2398 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2399 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2404 unsigned long difference, source1, source2;
2405 int srcreg1, srcreg2, dstreg;
2408 srcreg1 = translate_rreg (SD_, RM2);
2409 srcreg2 = translate_rreg (SD_, RN0);
2410 dstreg = translate_rreg (SD_, RD0);
2412 source1 = State.regs[srcreg1];
2413 source2 = State.regs[srcreg2];
2414 difference = source2 - source1;
2415 State.regs[dstreg] = difference;
2417 z = (difference == 0);
2418 n = (difference & 0x80000000);
2419 c = (source1 > source1);
2420 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2421 && (source1 & 0x80000000) != (difference & 0x80000000));
2423 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2424 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2425 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2428 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2429 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2434 unsigned long difference, source1, source2;
2435 int srcreg1, srcreg2, dstreg;
2438 srcreg1 = translate_rreg (SD_, RM2);
2439 srcreg2 = translate_rreg (SD_, RN0);
2440 dstreg = translate_rreg (SD_, RD0);
2442 source1 = State.regs[srcreg1];
2443 source2 = State.regs[srcreg2];
2444 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2445 State.regs[dstreg] = difference;
2447 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2448 n = (difference & 0x80000000);
2449 c = (source1 > source2);
2450 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2451 && (source1 & 0x80000000) != (difference & 0x80000000));
2453 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2454 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2455 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2458 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2459 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2464 int srcreg1, srcreg2, dstreg;
2467 srcreg1 = translate_rreg (SD_, RM2);
2468 srcreg2 = translate_rreg (SD_, RN0);
2469 dstreg = translate_rreg (SD_, RD0);
2471 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2473 z = (State.regs[dstreg] == 0);
2474 n = (State.regs[dstreg] & 0x80000000);
2476 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2477 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2480 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2481 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2486 int srcreg1, srcreg2, dstreg;
2489 srcreg1 = translate_rreg (SD_, RM2);
2490 srcreg2 = translate_rreg (SD_, RN0);
2491 dstreg = translate_rreg (SD_, RD0);
2493 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2495 z = (State.regs[dstreg] == 0);
2496 n = (State.regs[dstreg] & 0x80000000);
2498 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2499 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2502 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2503 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2508 int srcreg1, srcreg2, dstreg;
2511 srcreg1 = translate_rreg (SD_, RM2);
2512 srcreg2 = translate_rreg (SD_, RN0);
2513 dstreg = translate_rreg (SD_, RD0);
2515 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2517 z = (State.regs[dstreg] == 0);
2518 n = (State.regs[dstreg] & 0x80000000);
2520 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2521 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2524 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2525 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2531 int srcreg1, srcreg2, dstreg;
2534 srcreg1 = translate_rreg (SD_, RM2);
2535 srcreg2 = translate_rreg (SD_, RN0);
2536 dstreg = translate_rreg (SD_, RD0);
2538 temp = State.regs[srcreg2];
2540 temp >>= State.regs[srcreg1];
2541 State.regs[dstreg] = temp;
2543 z = (State.regs[dstreg] == 0);
2544 n = (State.regs[dstreg] & 0x80000000);
2546 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2547 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2550 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2551 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2556 int srcreg1, srcreg2, dstreg;
2559 srcreg1 = translate_rreg (SD_, RM2);
2560 srcreg2 = translate_rreg (SD_, RN0);
2561 dstreg = translate_rreg (SD_, RD0);
2563 c = State.regs[srcreg2] & 1;
2564 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2566 z = (State.regs[dstreg] == 0);
2567 n = (State.regs[dstreg] & 0x80000000);
2569 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2570 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2573 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2574 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2579 int srcreg1, srcreg2, dstreg;
2582 srcreg1 = translate_rreg (SD_, RM2);
2583 srcreg2 = translate_rreg (SD_, RN0);
2584 dstreg = translate_rreg (SD_, RD0);
2586 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2595 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2596 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2600 int srcreg1, srcreg2, dstreg1, dstreg2;
2601 signed long long temp;
2605 srcreg1 = translate_rreg (SD_, RM2);
2606 srcreg2 = translate_rreg (SD_, RN0);
2607 dstreg1 = translate_rreg (SD_, RD0);
2608 dstreg2 = translate_rreg (SD_, RD2);
2610 temp = ((signed64)(signed32)State.regs[srcreg1]
2611 * (signed64)(signed32)State.regs[srcreg2]);
2612 State.regs[dstreg1] = temp & 0xffffffff;
2613 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2615 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2616 n = (State.regs[dstreg2] & 0x80000000);
2618 PSW &= ~(PSW_Z | PSW_N);
2619 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2622 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2623 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2627 int srcreg1, srcreg2, dstreg1, dstreg2;
2628 signed long long temp;
2632 srcreg1 = translate_rreg (SD_, RM2);
2633 srcreg2 = translate_rreg (SD_, RN0);
2634 dstreg1 = translate_rreg (SD_, RD0);
2635 dstreg2 = translate_rreg (SD_, RD2);
2637 temp = ((unsigned64)State.regs[srcreg1]
2638 * (unsigned64)State.regs[srcreg2]);
2639 State.regs[dstreg1] = temp & 0xffffffff;
2640 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2642 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2643 n = (State.regs[dstreg2] & 0x80000000);
2645 PSW &= ~(PSW_Z | PSW_N);
2646 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2649 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2650 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2657 dstreg = translate_rreg (SD_, RN2);
2658 State.regs[dstreg] = load_word (IMM8);
2661 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2662 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2669 srcreg = translate_rreg (SD_, RM2);
2670 store_word (IMM8, State.regs[srcreg]);
2673 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2674 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2681 dstreg = translate_rreg (SD_, RN2);
2682 State.regs[dstreg] = load_byte (IMM8);
2685 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2686 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2693 srcreg = translate_rreg (SD_, RM2);
2694 store_byte (IMM8, State.regs[srcreg]);
2697 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2698 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2705 dstreg = translate_rreg (SD_, RN2);
2706 State.regs[dstreg] = load_half (IMM8);
2709 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2710 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2717 srcreg = translate_rreg (SD_, RM2);
2718 store_half (IMM8, State.regs[srcreg]);
2721 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2722 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2726 int srcreg1, srcreg2, dstreg;
2729 srcreg1 = translate_rreg (SD_, RM0);
2730 srcreg1 = translate_rreg (SD_, RI0);
2731 dstreg = translate_rreg (SD_, RN0);
2732 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2735 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2736 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2740 int srcreg, dstreg1, dstreg2;
2743 srcreg = translate_rreg (SD_, RM0);
2744 dstreg1 = translate_rreg (SD_, RI0);
2745 dstreg2 = translate_rreg (SD_, RN0);
2746 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2749 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2750 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2754 int srcreg1, srcreg2, dstreg;
2757 srcreg1 = translate_rreg (SD_, RM0);
2758 srcreg1 = translate_rreg (SD_, RI0);
2759 dstreg = translate_rreg (SD_, RN0);
2760 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2763 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2764 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2768 int srcreg, dstreg1, dstreg2;
2771 srcreg = translate_rreg (SD_, RM0);
2772 dstreg1 = translate_rreg (SD_, RI0);
2773 dstreg2 = translate_rreg (SD_, RN0);
2774 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2777 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2778 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2782 int srcreg1, srcreg2, dstreg;
2785 srcreg1 = translate_rreg (SD_, RM0);
2786 srcreg1 = translate_rreg (SD_, RI0);
2787 dstreg = translate_rreg (SD_, RN0);
2788 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2791 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2792 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2796 int srcreg, dstreg1, dstreg2;
2799 srcreg = translate_rreg (SD_, RM0);
2800 dstreg1 = translate_rreg (SD_, RI0);
2801 dstreg2 = translate_rreg (SD_, RN0);
2802 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2805 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2806 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2810 int srcreg1, srcreg2, dstreg1, dstreg2;
2811 signed long long temp;
2816 srcreg1 = translate_rreg (SD_, RM2);
2817 srcreg2 = translate_rreg (SD_, RN0);
2818 dstreg1 = translate_rreg (SD_, RD0);
2819 dstreg2 = translate_rreg (SD_, RD2);
2821 temp = ((signed64)(signed32)State.regs[srcreg1]
2822 * (signed64)(signed32)State.regs[srcreg2]);
2824 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2825 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2826 State.regs[dstreg2] = sum;
2829 sum = State.regs[dstreg1] + temp + c;
2830 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2831 && (temp & 0x80000000) != (sum & 0x80000000));
2832 State.regs[dstreg1] = sum;
2835 State.regs[REG_MCVF] = 1;
2837 PSW |= (( v ? PSW_V : 0));
2841 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2842 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2846 int srcreg1, srcreg2, dstreg1, dstreg2;
2847 signed long long temp;
2852 srcreg1 = translate_rreg (SD_, RM2);
2853 srcreg2 = translate_rreg (SD_, RN0);
2854 dstreg1 = translate_rreg (SD_, RD0);
2855 dstreg2 = translate_rreg (SD_, RD2);
2857 temp = ((unsigned64)State.regs[srcreg1]
2858 * (unsigned64)State.regs[srcreg2]);
2860 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2861 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2862 State.regs[dstreg2] = sum;
2865 sum = State.regs[dstreg1] + temp + c;
2866 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2867 && (temp & 0x80000000) != (sum & 0x80000000));
2868 State.regs[dstreg1] = sum;
2871 State.regs[REG_MCVF] = 1;
2873 PSW |= (( v ? PSW_V : 0));
2877 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2878 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2882 int srcreg1, srcreg2, dstreg;
2887 srcreg1 = translate_rreg (SD_, RM2);
2888 srcreg2 = translate_rreg (SD_, RN0);
2889 dstreg = translate_rreg (SD_, RD0);
2891 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2892 * (signed32)(State.regs[srcreg1] & 0xff));
2893 sum = State.regs[dstreg] + temp;
2894 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2895 && (temp & 0x80000000) != (sum & 0x80000000));
2896 State.regs[dstreg] = sum;
2899 State.regs[REG_MCVF] = 1;
2901 PSW |= ((v ? PSW_V : 0));
2905 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2906 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2910 int srcreg1, srcreg2, dstreg;
2915 srcreg1 = translate_rreg (SD_, RM2);
2916 srcreg2 = translate_rreg (SD_, RN0);
2917 dstreg = translate_rreg (SD_, RD0);
2919 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2920 * (unsigned32)(State.regs[srcreg1] & 0xff));
2921 sum = State.regs[dstreg] + temp;
2922 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2923 && (temp & 0x80000000) != (sum & 0x80000000));
2924 State.regs[dstreg] = sum;
2927 State.regs[REG_MCVF] = 1;
2929 PSW |= ((v ? PSW_V : 0));
2933 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2934 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2938 int srcreg1, srcreg2, dstreg;
2943 srcreg1 = translate_rreg (SD_, RM2);
2944 srcreg2 = translate_rreg (SD_, RN0);
2945 dstreg = translate_rreg (SD_, RD0);
2947 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2948 * (signed32)(State.regs[srcreg1] & 0xffff));
2949 sum = State.regs[dstreg] + temp;
2950 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2951 && (temp & 0x80000000) != (sum & 0x80000000));
2952 State.regs[dstreg] = sum;
2955 State.regs[REG_MCVF] = 1;
2957 PSW |= ((v ? PSW_V : 0));
2961 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2962 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2966 int srcreg1, srcreg2, dstreg;
2971 srcreg1 = translate_rreg (SD_, RM2);
2972 srcreg2 = translate_rreg (SD_, RN0);
2973 dstreg = translate_rreg (SD_, RD0);
2975 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2976 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2977 sum = State.regs[dstreg] + temp;
2978 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2979 && (temp & 0x80000000) != (sum & 0x80000000));
2980 State.regs[dstreg] = sum;
2983 State.regs[REG_MCVF] = 1;
2985 PSW |= ((v ? PSW_V : 0));
2989 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2990 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2994 int srcreg1, srcreg2, dstreg;
2995 long temp, temp2, sum;
2999 srcreg1 = translate_rreg (SD_, RM2);
3000 srcreg2 = translate_rreg (SD_, RN0);
3001 dstreg = translate_rreg (SD_, RD0);
3003 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3004 * (signed32)(State.regs[srcreg1] & 0xffff));
3005 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3006 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3007 sum = temp + temp2 + State.regs[dstreg];
3008 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3009 && (temp & 0x80000000) != (sum & 0x80000000));
3010 State.regs[dstreg] = sum;
3013 State.regs[REG_MCVF] = 1;
3015 PSW |= ((v ? PSW_V : 0));
3019 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3020 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3024 int srcreg1, srcreg2, dstreg;
3025 long temp, temp2, sum;
3029 srcreg1 = translate_rreg (SD_, RM2);
3030 srcreg2 = translate_rreg (SD_, RN0);
3031 dstreg = translate_rreg (SD_, RD0);
3033 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3034 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3035 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3036 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3037 sum = temp + temp2 + State.regs[dstreg];
3038 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3039 && (temp & 0x80000000) != (sum & 0x80000000));
3040 State.regs[dstreg] = sum;
3043 State.regs[REG_MCVF] = 1;
3045 PSW |= ((v ? PSW_V : 0));
3049 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3050 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3054 int srcreg1, srcreg2, dstreg1, dstreg2;
3055 signed long long temp;
3058 srcreg1 = translate_rreg (SD_, RM2);
3059 srcreg2 = translate_rreg (SD_, RN0);
3060 dstreg1 = translate_rreg (SD_, RD0);
3061 dstreg2 = translate_rreg (SD_, RD2);
3063 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3064 * (signed32)(State.regs[srcreg1] & 0xffff));
3065 State.regs[dstreg2] = temp;
3066 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3067 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3068 State.regs[dstreg1] = temp;
3071 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3072 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3076 int srcreg1, srcreg2, dstreg1, dstreg2;
3077 signed long long temp;
3080 srcreg1 = translate_rreg (SD_, RM2);
3081 srcreg2 = translate_rreg (SD_, RN0);
3082 dstreg1 = translate_rreg (SD_, RD0);
3083 dstreg2 = translate_rreg (SD_, RD2);
3085 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3086 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3087 State.regs[dstreg2] = temp;
3088 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3089 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3090 State.regs[dstreg1] = temp;
3093 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3094 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3102 srcreg = translate_rreg (SD_, RM2);
3103 dstreg = translate_rreg (SD_, RN0);
3105 value = State.regs[srcreg];
3107 if (value >= 0x7fffff)
3108 State.regs[dstreg] = 0x7fffff;
3109 else if (value <= 0xff800000)
3110 State.regs[dstreg] = 0xff800000;
3112 State.regs[dstreg] = value;
3114 n = (State.regs[dstreg] & 0x800000) != 0;
3115 z = (State.regs[dstreg] == 0);
3116 PSW &= ~(PSW_Z | PSW_N);
3117 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3120 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3121 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3126 int srcreg1, srcreg2, dstreg;
3130 srcreg1 = translate_rreg (SD_, RM2);
3131 srcreg2 = translate_rreg (SD_, RN0);
3132 dstreg = translate_rreg (SD_, RD0);
3134 temp = State.regs[srcreg1];
3135 start = (State.regs[srcreg2] & 0x1f) - 1;
3139 for (i = start; i >= 0; i--)
3141 if (temp & (1 << i))
3144 State.regs[dstreg] = i;
3152 State.regs[dstreg] = 0;
3155 PSW |= (c ? PSW_C : 0);
3158 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3159 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3166 dstreg = translate_rreg (SD_, RN0);
3167 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3170 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3171 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3178 dstreg = translate_rreg (SD_, RN0);
3179 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3182 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3183 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3190 dstreg = translate_rreg (SD_, RN0);
3191 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3194 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3195 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3199 int dstreg, z, n, c, v;
3200 unsigned long sum, imm, reg2;
3203 dstreg = translate_rreg (SD_, RN0);
3205 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3206 reg2 = State.regs[dstreg];
3207 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3208 State.regs[dstreg] = sum;
3210 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3211 n = (sum & 0x80000000);
3212 c = (sum < imm) || (sum < reg2);
3213 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3214 && (reg2 & 0x80000000) != (sum & 0x80000000));
3216 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3217 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3218 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3221 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3222 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3229 dstreg = translate_rreg (SD_, RN0);
3230 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3233 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3234 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3238 int dstreg, z, n, c, v;
3239 unsigned long difference, imm, reg2;
3242 dstreg = translate_rreg (SD_, RN0);
3244 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3245 reg2 = State.regs[dstreg];
3246 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3247 State.regs[dstreg] = difference;
3249 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3250 n = (difference & 0x80000000);
3252 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3253 && (reg2 & 0x80000000) != (difference & 0x80000000));
3255 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3256 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3257 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3260 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3261 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3268 srcreg = translate_rreg (SD_, RN0);
3269 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3272 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3273 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3281 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3287 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3288 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3296 dstreg = translate_rreg (SD_, RN0);
3298 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3299 z = (State.regs[dstreg] == 0);
3300 n = (State.regs[dstreg] & 0x80000000) != 0;
3301 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3302 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3305 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3306 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3314 dstreg = translate_rreg (SD_, RN0);
3316 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3317 z = (State.regs[dstreg] == 0);
3318 n = (State.regs[dstreg] & 0x80000000) != 0;
3319 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3320 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3323 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3324 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3332 dstreg = translate_rreg (SD_, RN0);
3334 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3335 z = (State.regs[dstreg] == 0);
3336 n = (State.regs[dstreg] & 0x80000000) != 0;
3337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3338 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3341 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3342 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3351 dstreg = translate_rreg (SD_, RN0);
3353 temp = State.regs[dstreg];
3355 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3356 State.regs[dstreg] = temp;
3357 z = (State.regs[dstreg] == 0);
3358 n = (State.regs[dstreg] & 0x80000000) != 0;
3359 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3360 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3364 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3365 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3373 dstreg = translate_rreg (SD_, RN0);
3375 c = State.regs[dstreg] & 1;
3376 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3377 z = (State.regs[dstreg] == 0);
3378 n = (State.regs[dstreg] & 0x80000000) != 0;
3379 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3380 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3383 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3384 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3392 dstreg = translate_rreg (SD_, RN0);
3394 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3395 z = (State.regs[dstreg] == 0);
3396 n = (State.regs[dstreg] & 0x80000000) != 0;
3397 PSW &= ~(PSW_Z | PSW_N);
3398 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3401 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3402 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3407 unsigned long long temp;
3411 dstreg = translate_rreg (SD_, RN0);
3413 temp = ((signed64)(signed32)State.regs[dstreg]
3414 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3415 State.regs[dstreg] = temp & 0xffffffff;
3416 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3417 z = (State.regs[dstreg] == 0);
3418 n = (State.regs[dstreg] & 0x80000000) != 0;
3419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3423 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3424 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3429 unsigned long long temp;
3433 dstreg = translate_rreg (SD_, RN0);
3435 temp = ((unsigned64)State.regs[dstreg]
3436 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3437 State.regs[dstreg] = temp & 0xffffffff;
3438 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3439 z = (State.regs[dstreg] == 0);
3440 n = (State.regs[dstreg] & 0x80000000) != 0;
3441 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3442 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3445 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3446 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3453 srcreg = translate_rreg (SD_, RN0);
3454 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3457 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3458 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3465 srcreg = translate_rreg (SD_, RM0);
3466 dstreg = translate_rreg (SD_, RN2);
3467 State.regs[dstreg] = load_word (State.regs[srcreg]
3468 + EXTEND24 (FETCH24 (IMM24A,
3472 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3473 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3480 srcreg = translate_rreg (SD_, RM2);
3481 dstreg = translate_rreg (SD_, RN0);
3482 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3483 State.regs[srcreg]);
3486 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3487 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3494 srcreg = translate_rreg (SD_, RM0);
3495 dstreg = translate_rreg (SD_, RN2);
3496 State.regs[dstreg] = load_byte (State.regs[srcreg]
3497 + EXTEND24 (FETCH24 (IMM24A,
3501 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3502 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3509 srcreg = translate_rreg (SD_, RM2);
3510 dstreg = translate_rreg (SD_, RN0);
3511 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3512 State.regs[srcreg]);
3515 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3516 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3523 srcreg = translate_rreg (SD_, RM0);
3524 dstreg = translate_rreg (SD_, RN2);
3525 State.regs[dstreg] = load_half (State.regs[srcreg]
3526 + EXTEND24 (FETCH24 (IMM24A,
3530 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3531 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3538 srcreg = translate_rreg (SD_, RM2);
3539 dstreg = translate_rreg (SD_, RN0);
3540 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3541 State.regs[srcreg]);
3544 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3545 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3552 srcreg = translate_rreg (SD_, RM0);
3553 dstreg = translate_rreg (SD_, RN2);
3554 State.regs[dstreg] = load_word (State.regs[srcreg]);
3555 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3558 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3559 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3566 srcreg = translate_rreg (SD_, RM2);
3567 dstreg = translate_rreg (SD_, RN0);
3568 store_word (State.regs[dstreg], State.regs[srcreg]);
3569 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3573 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3574 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3581 dstreg = translate_rreg (SD_, RN2);
3582 State.regs[dstreg] = load_word (State.regs[REG_SP]
3583 + EXTEND24 (FETCH24 (IMM24A,
3587 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3588 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3595 srcreg = translate_rreg (SD_, RM2);
3596 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3597 State.regs[srcreg]);
3600 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3601 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3608 dstreg = translate_rreg (SD_, RN2);
3609 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3610 + EXTEND24 (FETCH24 (IMM24A,
3614 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3615 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3622 srcreg = translate_rreg (SD_, RM2);
3623 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3624 State.regs[srcreg]);
3627 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3628 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3635 dstreg = translate_rreg (SD_, RN2);
3636 State.regs[dstreg] = load_half (State.regs[REG_SP]
3637 + EXTEND24 (FETCH24 (IMM24A,
3641 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3642 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3649 srcreg = translate_rreg (SD_, RM2);
3650 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3651 State.regs[srcreg]);
3654 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3655 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3662 srcreg = translate_rreg (SD_, RM0);
3663 dstreg = translate_rreg (SD_, RN2);
3664 State.regs[dstreg] = load_half (State.regs[srcreg]);
3665 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3668 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3669 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3676 srcreg = translate_rreg (SD_, RM2);
3677 dstreg = translate_rreg (SD_, RN0);
3678 store_half (State.regs[dstreg], State.regs[srcreg]);
3679 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3682 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3683 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3688 long long temp, sum;
3692 srcreg = translate_rreg (SD_, RN2);
3694 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3695 * (signed64)State.regs[srcreg]);
3696 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3697 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3698 State.regs[REG_MCRL] = sum;
3701 sum = State.regs[REG_MCRH] + temp + c;
3702 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3703 && (temp & 0x80000000) != (sum & 0x80000000));
3704 State.regs[REG_MCRH] = sum;
3706 State.regs[REG_MCVF] = 1;
3709 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3710 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3715 long long temp, sum;
3719 srcreg = translate_rreg (SD_, RN2);
3721 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3722 * (unsigned64)State.regs[srcreg]);
3723 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3724 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3725 State.regs[REG_MCRL] = sum;
3728 sum = State.regs[REG_MCRH] + temp + c;
3729 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3730 && (temp & 0x80000000) != (sum & 0x80000000));
3731 State.regs[REG_MCRH] = sum;
3733 State.regs[REG_MCVF] = 1;
3736 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3737 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3742 long long temp, sum;
3746 srcreg = translate_rreg (SD_, RN2);
3748 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3749 * (signed64)State.regs[srcreg] & 0xff);
3750 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3751 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3752 State.regs[REG_MCRL] = sum;
3755 sum = State.regs[REG_MCRH] + temp + c;
3756 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3757 && (temp & 0x80000000) != (sum & 0x80000000));
3758 State.regs[REG_MCRH] = sum;
3760 State.regs[REG_MCVF] = 1;
3763 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3764 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3769 long long temp, sum;
3773 srcreg = translate_rreg (SD_, RN2);
3775 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3776 * (unsigned64)State.regs[srcreg] & 0xff);
3777 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3778 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3779 State.regs[REG_MCRL] = sum;
3782 sum = State.regs[REG_MCRH] + temp + c;
3783 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3784 && (temp & 0x80000000) != (sum & 0x80000000));
3785 State.regs[REG_MCRH] = sum;
3787 State.regs[REG_MCVF] = 1;
3790 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3791 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3796 long long temp, sum;
3800 srcreg = translate_rreg (SD_, RN2);
3802 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3803 * (signed64)State.regs[srcreg] & 0xffff);
3804 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3805 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3806 State.regs[REG_MCRL] = sum;
3809 sum = State.regs[REG_MCRH] + temp + c;
3810 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3811 && (temp & 0x80000000) != (sum & 0x80000000));
3812 State.regs[REG_MCRH] = sum;
3814 State.regs[REG_MCVF] = 1;
3817 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3818 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3823 long long temp, sum;
3827 srcreg = translate_rreg (SD_, RN2);
3829 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3830 * (unsigned64)State.regs[srcreg] & 0xffff);
3831 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3832 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3833 State.regs[REG_MCRL] = sum;
3836 sum = State.regs[REG_MCRH] + temp + c;
3837 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3838 && (temp & 0x80000000) != (sum & 0x80000000));
3839 State.regs[REG_MCRH] = sum;
3841 State.regs[REG_MCVF] = 1;
3844 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3845 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3852 dstreg = translate_rreg (SD_, RN2);
3853 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3856 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3857 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3864 srcreg = translate_rreg (SD_, RM2);
3865 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3869 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3870 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3877 dstreg = translate_rreg (SD_, RN2);
3878 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3881 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3882 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3889 srcreg = translate_rreg (SD_, RM2);
3890 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3894 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3895 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3902 dstreg = translate_rreg (SD_, RN2);
3903 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3906 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3907 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3914 srcreg = translate_rreg (SD_, RM2);
3915 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3919 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3920 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3927 dstreg = translate_rreg (SD_, RN0);
3928 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3931 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3932 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3939 dstreg = translate_rreg (SD_, RN0);
3940 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3943 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3944 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3951 dstreg = translate_rreg (SD_, RN0);
3952 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3955 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3956 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3961 unsigned int imm, reg2, sum;
3965 dstreg = translate_rreg (SD_, RN0);
3967 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3968 reg2 = State.regs[dstreg];
3969 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3970 State.regs[dstreg] = sum;
3972 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3973 n = (sum & 0x80000000);
3974 c = (sum < imm) || (sum < reg2);
3975 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3976 && (reg2 & 0x80000000) != (sum & 0x80000000));
3978 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3979 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3980 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3983 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3984 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3991 dstreg = translate_rreg (SD_, RN0);
3992 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3995 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3996 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4001 unsigned int imm, reg2, difference;
4005 dstreg = translate_rreg (SD_, RN0);
4007 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4008 reg2 = State.regs[dstreg];
4009 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4010 State.regs[dstreg] = difference;
4012 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4013 n = (difference & 0x80000000);
4015 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4016 && (reg2 & 0x80000000) != (difference & 0x80000000));
4018 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4019 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4020 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4023 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4024 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4031 srcreg = translate_rreg (SD_, RN0);
4032 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4035 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4036 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4043 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4048 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4049 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4057 dstreg = translate_rreg (SD_, RN0);
4059 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4060 z = (State.regs[dstreg] == 0);
4061 n = (State.regs[dstreg] & 0x80000000) != 0;
4062 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4063 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4066 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4067 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4075 dstreg = translate_rreg (SD_, RN0);
4077 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4078 z = (State.regs[dstreg] == 0);
4079 n = (State.regs[dstreg] & 0x80000000) != 0;
4080 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4081 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4084 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4085 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4093 dstreg = translate_rreg (SD_, RN0);
4095 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4096 z = (State.regs[dstreg] == 0);
4097 n = (State.regs[dstreg] & 0x80000000) != 0;
4098 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4099 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4102 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4103 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4112 dstreg = translate_rreg (SD_, RN0);
4114 temp = State.regs[dstreg];
4116 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4117 State.regs[dstreg] = temp;
4118 z = (State.regs[dstreg] == 0);
4119 n = (State.regs[dstreg] & 0x80000000) != 0;
4120 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4121 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4124 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4125 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4133 dstreg = translate_rreg (SD_, RN0);
4135 c = State.regs[dstreg] & 1;
4136 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4137 z = (State.regs[dstreg] == 0);
4138 n = (State.regs[dstreg] & 0x80000000) != 0;
4139 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4140 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4143 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4144 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4152 dstreg = translate_rreg (SD_, RN0);
4154 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4155 z = (State.regs[dstreg] == 0);
4156 n = (State.regs[dstreg] & 0x80000000) != 0;
4157 PSW &= ~(PSW_Z | PSW_N);
4158 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4161 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4162 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4167 unsigned long long temp;
4171 dstreg = translate_rreg (SD_, RN0);
4173 temp = ((signed64)(signed32)State.regs[dstreg]
4174 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4175 State.regs[dstreg] = temp & 0xffffffff;
4176 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4177 z = (State.regs[dstreg] == 0);
4178 n = (State.regs[dstreg] & 0x80000000) != 0;
4179 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4180 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4183 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4184 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4189 unsigned long long temp;
4193 dstreg = translate_rreg (SD_, RN0);
4195 temp = ((unsigned64)State.regs[dstreg]
4196 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4197 State.regs[dstreg] = temp & 0xffffffff;
4198 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4199 z = (State.regs[dstreg] == 0);
4200 n = (State.regs[dstreg] & 0x80000000) != 0;
4201 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4202 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4205 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4206 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4213 srcreg = translate_rreg (SD_, RN0);
4214 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4217 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4218 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4225 srcreg = translate_rreg (SD_, RM0);
4226 dstreg = translate_rreg (SD_, RN2);
4227 State.regs[dstreg] = load_word (State.regs[srcreg]
4228 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4231 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4232 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4239 srcreg = translate_rreg (SD_, RM2);
4240 dstreg = translate_rreg (SD_, RN0);
4241 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4242 State.regs[srcreg]);
4245 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4246 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4253 srcreg = translate_rreg (SD_, RM0);
4254 dstreg = translate_rreg (SD_, RN2);
4255 State.regs[dstreg] = load_byte (State.regs[srcreg]
4256 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4259 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4260 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4267 srcreg = translate_rreg (SD_, RM2);
4268 dstreg = translate_rreg (SD_, RN0);
4269 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4270 State.regs[srcreg]);
4273 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4274 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4281 srcreg = translate_rreg (SD_, RM0);
4282 dstreg = translate_rreg (SD_, RN2);
4283 State.regs[dstreg] = load_half (State.regs[srcreg]
4284 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4287 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4288 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4295 srcreg = translate_rreg (SD_, RM2);
4296 dstreg = translate_rreg (SD_, RN0);
4297 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4298 State.regs[srcreg]);
4301 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4302 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4309 srcreg = translate_rreg (SD_, RM0);
4310 dstreg = translate_rreg (SD_, RN2);
4311 State.regs[dstreg] = load_word (State.regs[srcreg]);
4312 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4315 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4316 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4323 srcreg = translate_rreg (SD_, RM2);
4324 dstreg = translate_rreg (SD_, RN0);
4325 store_word (State.regs[dstreg], State.regs[srcreg]);
4326 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4330 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4331 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4338 dstreg = translate_rreg (SD_, RN2);
4339 State.regs[dstreg] = load_word (State.regs[REG_SP]
4340 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4343 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4344 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4351 srcreg = translate_rreg (SD_, RM2);
4352 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4353 State.regs[srcreg]);
4356 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4357 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4364 dstreg = translate_rreg (SD_, RN2);
4365 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4366 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4369 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4370 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4377 srcreg = translate_rreg (SD_, RM2);
4378 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4379 State.regs[srcreg]);
4382 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4383 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4390 dstreg = translate_rreg (SD_, RN2);
4391 State.regs[dstreg] = load_half (State.regs[REG_SP]
4392 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4395 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4396 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4403 srcreg = translate_rreg (SD_, RM2);
4404 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4405 State.regs[srcreg]);
4409 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4410 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4417 srcreg = translate_rreg (SD_, RM0);
4418 dstreg = translate_rreg (SD_, RN2);
4419 State.regs[dstreg] = load_half (State.regs[srcreg]);
4420 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4423 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4424 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4431 srcreg = translate_rreg (SD_, RM2);
4432 dstreg = translate_rreg (SD_, RN0);
4433 store_half (State.regs[dstreg], State.regs[srcreg]);
4434 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4449 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4450 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4457 dstreg = translate_rreg (SD_, RN2);
4458 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4461 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4462 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4469 srcreg = translate_rreg (SD_, RM2);
4470 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4473 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4474 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4481 dstreg = translate_rreg (SD_, RN2);
4482 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4485 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4486 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4493 srcreg = translate_rreg (SD_, RM2);
4494 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4497 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4498 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4505 dstreg = translate_rreg (SD_, RN2);
4506 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4509 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4510 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4517 srcreg = translate_rreg (SD_, RM2);
4518 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4521 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4522 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4526 int srcreg1, srcreg2, dstreg1, dstreg2;
4529 srcreg1 = translate_rreg (SD_, RM1);
4530 srcreg2 = translate_rreg (SD_, RM2);
4531 dstreg1 = translate_rreg (SD_, RN1);
4532 dstreg2 = translate_rreg (SD_, RN2);
4534 State.regs[dstreg1] += State.regs[srcreg1];
4535 State.regs[dstreg2] += State.regs[srcreg2];
4538 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4539 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4543 int srcreg1, dstreg1, dstreg2;
4546 srcreg1 = translate_rreg (SD_, RM1);
4547 dstreg1 = translate_rreg (SD_, RN1);
4548 dstreg2 = translate_rreg (SD_, RN2);
4550 State.regs[dstreg1] += State.regs[srcreg1];
4551 State.regs[dstreg2] += EXTEND4 (IMM4);
4554 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4555 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4559 int srcreg1, srcreg2, dstreg1, dstreg2;
4562 srcreg1 = translate_rreg (SD_, RM1);
4563 srcreg2 = translate_rreg (SD_, RM2);
4564 dstreg1 = translate_rreg (SD_, RN1);
4565 dstreg2 = translate_rreg (SD_, RN2);
4567 State.regs[dstreg1] += State.regs[srcreg1];
4568 State.regs[dstreg2] -= State.regs[srcreg2];
4571 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4572 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4576 int srcreg1, dstreg1, dstreg2;
4579 srcreg1 = translate_rreg (SD_, RM1);
4580 dstreg1 = translate_rreg (SD_, RN1);
4581 dstreg2 = translate_rreg (SD_, RN2);
4583 State.regs[dstreg1] += State.regs[srcreg1];
4584 State.regs[dstreg2] -= EXTEND4 (IMM4);
4587 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4588 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4592 int srcreg1, srcreg2, dstreg1, dstreg2;
4595 srcreg1 = translate_rreg (SD_, RM1);
4596 srcreg2 = translate_rreg (SD_, RM2);
4597 dstreg1 = translate_rreg (SD_, RN1);
4598 dstreg2 = translate_rreg (SD_, RN2);
4600 State.regs[dstreg1] += State.regs[srcreg1];
4601 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4604 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4605 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4609 int srcreg1, dstreg1, dstreg2;
4612 srcreg1 = translate_rreg (SD_, RM1);
4613 dstreg1 = translate_rreg (SD_, RN1);
4614 dstreg2 = translate_rreg (SD_, RN2);
4616 State.regs[dstreg1] += State.regs[srcreg1];
4617 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4620 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4621 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4625 int srcreg1, srcreg2, dstreg1, dstreg2;
4628 srcreg1 = translate_rreg (SD_, RM1);
4629 srcreg2 = translate_rreg (SD_, RM2);
4630 dstreg1 = translate_rreg (SD_, RN1);
4631 dstreg2 = translate_rreg (SD_, RN2);
4633 State.regs[dstreg1] += State.regs[srcreg1];
4634 State.regs[dstreg2] = State.regs[srcreg2];
4637 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4638 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4642 int srcreg1, dstreg1, dstreg2;
4645 srcreg1 = translate_rreg (SD_, RM1);
4646 dstreg1 = translate_rreg (SD_, RN1);
4647 dstreg2 = translate_rreg (SD_, RN2);
4649 State.regs[dstreg1] += State.regs[srcreg1];
4650 State.regs[dstreg2] = EXTEND4 (IMM4);
4653 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4654 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4658 int srcreg1, srcreg2, dstreg1, dstreg2;
4662 srcreg1 = translate_rreg (SD_, RM1);
4663 srcreg2 = translate_rreg (SD_, RM2);
4664 dstreg1 = translate_rreg (SD_, RN1);
4665 dstreg2 = translate_rreg (SD_, RN2);
4667 State.regs[dstreg1] += State.regs[srcreg1];
4668 temp = State.regs[dstreg2];
4669 temp >>= State.regs[srcreg2];
4670 State.regs[dstreg2] = temp;
4673 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4674 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4678 int srcreg1, dstreg1, dstreg2;
4682 srcreg1 = translate_rreg (SD_, RM1);
4683 dstreg1 = translate_rreg (SD_, RN1);
4684 dstreg2 = translate_rreg (SD_, RN2);
4686 State.regs[dstreg1] += State.regs[srcreg1];
4687 temp = State.regs[dstreg2];
4689 State.regs[dstreg2] = temp;
4692 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4693 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4697 int srcreg1, srcreg2, dstreg1, dstreg2;
4700 srcreg1 = translate_rreg (SD_, RM1);
4701 srcreg2 = translate_rreg (SD_, RM2);
4702 dstreg1 = translate_rreg (SD_, RN1);
4703 dstreg2 = translate_rreg (SD_, RN2);
4705 State.regs[dstreg1] += State.regs[srcreg1];
4706 State.regs[dstreg2] >>= State.regs[srcreg2];
4709 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4710 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4714 int srcreg1, dstreg1, dstreg2;
4718 srcreg1 = translate_rreg (SD_, RM1);
4719 dstreg1 = translate_rreg (SD_, RN1);
4720 dstreg2 = translate_rreg (SD_, RN2);
4722 State.regs[dstreg1] += State.regs[srcreg1];
4723 State.regs[dstreg2] >>= IMM4;
4727 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
4728 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4732 int srcreg1, srcreg2, dstreg1, dstreg2;
4735 srcreg1 = translate_rreg (SD_, RM1);
4736 srcreg2 = translate_rreg (SD_, RM2);
4737 dstreg1 = translate_rreg (SD_, RN1);
4738 dstreg2 = translate_rreg (SD_, RN2);
4740 State.regs[dstreg1] += State.regs[srcreg1];
4741 State.regs[dstreg2] <<= State.regs[srcreg2];
4744 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
4745 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4749 int srcreg1, dstreg1, dstreg2;
4753 srcreg1 = translate_rreg (SD_, RM1);
4754 dstreg1 = translate_rreg (SD_, RN1);
4755 dstreg2 = translate_rreg (SD_, RN2);
4757 State.regs[dstreg1] += State.regs[srcreg1];
4758 State.regs[dstreg2] <<= IMM4;
4761 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
4762 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
4766 int srcreg1, srcreg2, dstreg1, dstreg2;
4769 srcreg1 = translate_rreg (SD_, RM1);
4770 srcreg2 = translate_rreg (SD_, RM2);
4771 dstreg1 = translate_rreg (SD_, RN1);
4772 dstreg2 = translate_rreg (SD_, RN2);
4774 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4775 State.regs[dstreg2] += State.regs[srcreg2];
4778 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
4779 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
4783 int srcreg1, dstreg1, dstreg2;
4786 srcreg1 = translate_rreg (SD_, RM1);
4787 dstreg1 = translate_rreg (SD_, RN1);
4788 dstreg2 = translate_rreg (SD_, RN2);
4790 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4791 State.regs[dstreg2] += EXTEND4 (IMM4);
4794 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
4795 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
4799 int srcreg1, srcreg2, dstreg1, dstreg2;
4802 srcreg1 = translate_rreg (SD_, RM1);
4803 srcreg2 = translate_rreg (SD_, RM2);
4804 dstreg1 = translate_rreg (SD_, RN1);
4805 dstreg2 = translate_rreg (SD_, RN2);
4807 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4808 State.regs[dstreg2] -= State.regs[srcreg2];
4811 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
4812 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
4816 int srcreg1, dstreg1, dstreg2;
4819 srcreg1 = translate_rreg (SD_, RM1);
4820 dstreg1 = translate_rreg (SD_, RN1);
4821 dstreg2 = translate_rreg (SD_, RN2);
4823 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4824 State.regs[dstreg2] -= EXTEND4 (IMM4);
4827 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
4828 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
4832 int srcreg1, srcreg2, dstreg1, dstreg2;
4835 srcreg1 = translate_rreg (SD_, RM1);
4836 srcreg2 = translate_rreg (SD_, RM2);
4837 dstreg1 = translate_rreg (SD_, RN1);
4838 dstreg2 = translate_rreg (SD_, RN2);
4840 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4841 State.regs[dstreg2] = State.regs[srcreg2];
4844 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
4845 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
4849 int srcreg1, dstreg1, dstreg2;
4852 srcreg1 = translate_rreg (SD_, RM1);
4853 dstreg1 = translate_rreg (SD_, RN1);
4854 dstreg2 = translate_rreg (SD_, RN2);
4856 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4857 State.regs[dstreg2] = EXTEND4 (IMM4);
4860 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
4861 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
4865 int srcreg1, srcreg2, dstreg1, dstreg2;
4869 srcreg1 = translate_rreg (SD_, RM1);
4870 srcreg2 = translate_rreg (SD_, RM2);
4871 dstreg1 = translate_rreg (SD_, RN1);
4872 dstreg2 = translate_rreg (SD_, RN2);
4874 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4875 temp = State.regs[dstreg2];
4876 temp >>= State.regs[srcreg2];
4877 State.regs[dstreg2] = temp;
4880 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
4881 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
4885 int srcreg1, dstreg1, dstreg2;
4889 srcreg1 = translate_rreg (SD_, RM1);
4890 dstreg1 = translate_rreg (SD_, RN1);
4891 dstreg2 = translate_rreg (SD_, RN2);
4893 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4894 temp = State.regs[dstreg2];
4896 State.regs[dstreg2] = temp;
4899 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
4900 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
4904 int srcreg1, srcreg2, dstreg1, dstreg2;
4907 srcreg1 = translate_rreg (SD_, RM1);
4908 srcreg2 = translate_rreg (SD_, RM2);
4909 dstreg1 = translate_rreg (SD_, RN1);
4910 dstreg2 = translate_rreg (SD_, RN2);
4912 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4913 State.regs[dstreg2] >>= State.regs[srcreg2];
4916 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
4917 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
4921 int srcreg1, dstreg1, dstreg2;
4925 srcreg1 = translate_rreg (SD_, RM1);
4926 dstreg1 = translate_rreg (SD_, RN1);
4927 dstreg2 = translate_rreg (SD_, RN2);
4929 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4930 State.regs[dstreg2] >>= IMM4;
4934 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
4935 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
4939 int srcreg1, srcreg2, dstreg1, dstreg2;
4942 srcreg1 = translate_rreg (SD_, RM1);
4943 srcreg2 = translate_rreg (SD_, RM2);
4944 dstreg1 = translate_rreg (SD_, RN1);
4945 dstreg2 = translate_rreg (SD_, RN2);
4947 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4948 State.regs[dstreg2] <<= State.regs[srcreg2];
4951 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
4952 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
4956 int srcreg1, dstreg1, dstreg2;
4960 srcreg1 = translate_rreg (SD_, RM1);
4961 dstreg1 = translate_rreg (SD_, RN1);
4962 dstreg2 = translate_rreg (SD_, RN2);
4964 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
4965 State.regs[dstreg2] <<= IMM4;
4968 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
4969 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
4973 int srcreg1, srcreg2, dstreg1, dstreg2;
4976 srcreg1 = translate_rreg (SD_, RM1);
4977 srcreg2 = translate_rreg (SD_, RM2);
4978 dstreg1 = translate_rreg (SD_, RN1);
4979 dstreg2 = translate_rreg (SD_, RN2);
4981 State.regs[dstreg1] -= State.regs[srcreg1];
4982 State.regs[dstreg2] += State.regs[srcreg2];
4985 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
4986 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
4990 int srcreg1, dstreg1, dstreg2;
4993 srcreg1 = translate_rreg (SD_, RM1);
4994 dstreg1 = translate_rreg (SD_, RN1);
4995 dstreg2 = translate_rreg (SD_, RN2);
4997 State.regs[dstreg1] -= State.regs[srcreg1];
4998 State.regs[dstreg2] += EXTEND4 (IMM4);
5001 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5002 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5006 int srcreg1, srcreg2, dstreg1, dstreg2;
5009 srcreg1 = translate_rreg (SD_, RM1);
5010 srcreg2 = translate_rreg (SD_, RM2);
5011 dstreg1 = translate_rreg (SD_, RN1);
5012 dstreg2 = translate_rreg (SD_, RN2);
5014 State.regs[dstreg1] -= State.regs[srcreg1];
5015 State.regs[dstreg2] -= State.regs[srcreg2];
5018 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5019 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5023 int srcreg1, dstreg1, dstreg2;
5026 srcreg1 = translate_rreg (SD_, RM1);
5027 dstreg1 = translate_rreg (SD_, RN1);
5028 dstreg2 = translate_rreg (SD_, RN2);
5030 State.regs[dstreg1] -= State.regs[srcreg1];
5031 State.regs[dstreg2] -= EXTEND4 (IMM4);
5034 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5035 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5039 int srcreg1, srcreg2, dstreg1, dstreg2;
5042 srcreg1 = translate_rreg (SD_, RM1);
5043 srcreg2 = translate_rreg (SD_, RM2);
5044 dstreg1 = translate_rreg (SD_, RN1);
5045 dstreg2 = translate_rreg (SD_, RN2);
5047 State.regs[dstreg1] -= State.regs[srcreg1];
5048 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5051 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5052 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5056 int srcreg1, dstreg1, dstreg2;
5059 srcreg1 = translate_rreg (SD_, RM1);
5060 dstreg1 = translate_rreg (SD_, RN1);
5061 dstreg2 = translate_rreg (SD_, RN2);
5063 State.regs[dstreg1] -= State.regs[srcreg1];
5064 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5067 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5068 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5072 int srcreg1, srcreg2, dstreg1, dstreg2;
5075 srcreg1 = translate_rreg (SD_, RM1);
5076 srcreg2 = translate_rreg (SD_, RM2);
5077 dstreg1 = translate_rreg (SD_, RN1);
5078 dstreg2 = translate_rreg (SD_, RN2);
5080 State.regs[dstreg1] -= State.regs[srcreg1];
5081 State.regs[dstreg2] = State.regs[srcreg2];
5084 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5085 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5089 int srcreg1, dstreg1, dstreg2;
5092 srcreg1 = translate_rreg (SD_, RM1);
5093 dstreg1 = translate_rreg (SD_, RN1);
5094 dstreg2 = translate_rreg (SD_, RN2);
5096 State.regs[dstreg1] -= State.regs[srcreg1];
5097 State.regs[dstreg2] = EXTEND4 (IMM4);
5100 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5101 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5105 int srcreg1, srcreg2, dstreg1, dstreg2;
5109 srcreg1 = translate_rreg (SD_, RM1);
5110 srcreg2 = translate_rreg (SD_, RM2);
5111 dstreg1 = translate_rreg (SD_, RN1);
5112 dstreg2 = translate_rreg (SD_, RN2);
5114 State.regs[dstreg1] -= State.regs[srcreg1];
5115 temp = State.regs[dstreg2];
5116 temp >>= State.regs[srcreg2];
5117 State.regs[dstreg2] = temp;
5120 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5121 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5125 int srcreg1, dstreg1, dstreg2;
5129 srcreg1 = translate_rreg (SD_, RM1);
5130 dstreg1 = translate_rreg (SD_, RN1);
5131 dstreg2 = translate_rreg (SD_, RN2);
5133 State.regs[dstreg1] -= State.regs[srcreg1];
5134 temp = State.regs[dstreg2];
5136 State.regs[dstreg2] = temp;
5139 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5140 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5144 int srcreg1, srcreg2, dstreg1, dstreg2;
5147 srcreg1 = translate_rreg (SD_, RM1);
5148 srcreg2 = translate_rreg (SD_, RM2);
5149 dstreg1 = translate_rreg (SD_, RN1);
5150 dstreg2 = translate_rreg (SD_, RN2);
5152 State.regs[dstreg1] -= State.regs[srcreg1];
5153 State.regs[dstreg2] >>= State.regs[srcreg2];
5156 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5157 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5161 int srcreg1, dstreg1, dstreg2;
5165 srcreg1 = translate_rreg (SD_, RM1);
5166 dstreg1 = translate_rreg (SD_, RN1);
5167 dstreg2 = translate_rreg (SD_, RN2);
5169 State.regs[dstreg1] -= State.regs[srcreg1];
5170 State.regs[dstreg2] >>= IMM4;
5174 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5175 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5179 int srcreg1, srcreg2, dstreg1, dstreg2;
5182 srcreg1 = translate_rreg (SD_, RM1);
5183 srcreg2 = translate_rreg (SD_, RM2);
5184 dstreg1 = translate_rreg (SD_, RN1);
5185 dstreg2 = translate_rreg (SD_, RN2);
5187 State.regs[dstreg1] -= State.regs[srcreg1];
5188 State.regs[dstreg2] <<= State.regs[srcreg2];
5191 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5192 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5196 int srcreg1, dstreg1, dstreg2;
5200 srcreg1 = translate_rreg (SD_, RM1);
5201 dstreg1 = translate_rreg (SD_, RN1);
5202 dstreg2 = translate_rreg (SD_, RN2);
5204 State.regs[dstreg1] -= State.regs[srcreg1];
5205 State.regs[dstreg2] <<= IMM4;
5208 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5209 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5213 int srcreg1, srcreg2, dstreg1, dstreg2;
5216 srcreg1 = translate_rreg (SD_, RM1);
5217 srcreg2 = translate_rreg (SD_, RM2);
5218 dstreg1 = translate_rreg (SD_, RN1);
5219 dstreg2 = translate_rreg (SD_, RN2);
5221 State.regs[dstreg1] = State.regs[srcreg1];
5222 State.regs[dstreg2] += State.regs[srcreg2];
5225 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5226 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5230 int srcreg1, dstreg1, dstreg2;
5233 srcreg1 = translate_rreg (SD_, RM1);
5234 dstreg1 = translate_rreg (SD_, RN1);
5235 dstreg2 = translate_rreg (SD_, RN2);
5237 State.regs[dstreg1] = State.regs[srcreg1];
5238 State.regs[dstreg2] += EXTEND4 (IMM4);
5241 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5242 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5246 int srcreg1, srcreg2, dstreg1, dstreg2;
5249 srcreg1 = translate_rreg (SD_, RM1);
5250 srcreg2 = translate_rreg (SD_, RM2);
5251 dstreg1 = translate_rreg (SD_, RN1);
5252 dstreg2 = translate_rreg (SD_, RN2);
5254 State.regs[dstreg1] = State.regs[srcreg1];
5255 State.regs[dstreg2] -= State.regs[srcreg2];
5258 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5259 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5263 int srcreg1, dstreg1, dstreg2;
5266 srcreg1 = translate_rreg (SD_, RM1);
5267 dstreg1 = translate_rreg (SD_, RN1);
5268 dstreg2 = translate_rreg (SD_, RN2);
5270 State.regs[dstreg1] = State.regs[srcreg1];
5271 State.regs[dstreg2] -= EXTEND4 (IMM4);
5274 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5275 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5279 int srcreg1, srcreg2, dstreg1, dstreg2;
5282 srcreg1 = translate_rreg (SD_, RM1);
5283 srcreg2 = translate_rreg (SD_, RM2);
5284 dstreg1 = translate_rreg (SD_, RN1);
5285 dstreg2 = translate_rreg (SD_, RN2);
5287 State.regs[dstreg1] = State.regs[srcreg1];
5288 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5291 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5292 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5296 int srcreg1, dstreg1, dstreg2;
5299 srcreg1 = translate_rreg (SD_, RM1);
5300 dstreg1 = translate_rreg (SD_, RN1);
5301 dstreg2 = translate_rreg (SD_, RN2);
5303 State.regs[dstreg1] = State.regs[srcreg1];
5304 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5307 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5308 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5312 int srcreg1, srcreg2, dstreg1, dstreg2;
5315 srcreg1 = translate_rreg (SD_, RM1);
5316 srcreg2 = translate_rreg (SD_, RM2);
5317 dstreg1 = translate_rreg (SD_, RN1);
5318 dstreg2 = translate_rreg (SD_, RN2);
5320 State.regs[dstreg1] = State.regs[srcreg1];
5321 State.regs[dstreg2] = State.regs[srcreg2];
5324 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5325 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5329 int srcreg1, dstreg1, dstreg2;
5332 srcreg1 = translate_rreg (SD_, RM1);
5333 dstreg1 = translate_rreg (SD_, RN1);
5334 dstreg2 = translate_rreg (SD_, RN2);
5336 State.regs[dstreg1] = State.regs[srcreg1];
5337 State.regs[dstreg2] = EXTEND4 (IMM4);
5340 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5341 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5345 int srcreg1, srcreg2, dstreg1, dstreg2;
5349 srcreg1 = translate_rreg (SD_, RM1);
5350 srcreg2 = translate_rreg (SD_, RM2);
5351 dstreg1 = translate_rreg (SD_, RN1);
5352 dstreg2 = translate_rreg (SD_, RN2);
5354 State.regs[dstreg1] = State.regs[srcreg1];
5355 temp = State.regs[dstreg2];
5356 temp >>= State.regs[srcreg2];
5357 State.regs[dstreg2] = temp;
5360 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5361 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5365 int srcreg1, dstreg1, dstreg2;
5369 srcreg1 = translate_rreg (SD_, RM1);
5370 dstreg1 = translate_rreg (SD_, RN1);
5371 dstreg2 = translate_rreg (SD_, RN2);
5373 State.regs[dstreg1] = State.regs[srcreg1];
5374 temp = State.regs[dstreg2];
5376 State.regs[dstreg2] = temp;
5379 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5380 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5384 int srcreg1, srcreg2, dstreg1, dstreg2;
5387 srcreg1 = translate_rreg (SD_, RM1);
5388 srcreg2 = translate_rreg (SD_, RM2);
5389 dstreg1 = translate_rreg (SD_, RN1);
5390 dstreg2 = translate_rreg (SD_, RN2);
5392 State.regs[dstreg1] = State.regs[srcreg1];
5393 State.regs[dstreg2] >>= State.regs[srcreg2];
5396 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5397 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5401 int srcreg1, dstreg1, dstreg2;
5405 srcreg1 = translate_rreg (SD_, RM1);
5406 dstreg1 = translate_rreg (SD_, RN1);
5407 dstreg2 = translate_rreg (SD_, RN2);
5409 State.regs[dstreg1] = State.regs[srcreg1];
5410 State.regs[dstreg2] >>= IMM4;
5414 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5415 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5419 int srcreg1, srcreg2, dstreg1, dstreg2;
5422 srcreg1 = translate_rreg (SD_, RM1);
5423 srcreg2 = translate_rreg (SD_, RM2);
5424 dstreg1 = translate_rreg (SD_, RN1);
5425 dstreg2 = translate_rreg (SD_, RN2);
5427 State.regs[dstreg1] = State.regs[srcreg1];
5428 State.regs[dstreg2] <<= State.regs[srcreg2];
5431 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5432 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5436 int srcreg1, dstreg1, dstreg2;
5440 srcreg1 = translate_rreg (SD_, RM1);
5441 dstreg1 = translate_rreg (SD_, RN1);
5442 dstreg2 = translate_rreg (SD_, RN2);
5444 State.regs[dstreg1] = State.regs[srcreg1];
5445 State.regs[dstreg2] <<= IMM4;
5448 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5449 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5453 int srcreg2, dstreg1, dstreg2;
5456 srcreg2 = translate_rreg (SD_, RM2);
5457 dstreg1 = translate_rreg (SD_, RN1);
5458 dstreg2 = translate_rreg (SD_, RN2);
5460 State.regs[dstreg1] += EXTEND4 (IMM4A);
5461 State.regs[dstreg2] += State.regs[srcreg2];
5464 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5465 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5469 int dstreg1, dstreg2;
5472 dstreg1 = translate_rreg (SD_, RN1);
5473 dstreg2 = translate_rreg (SD_, RN2);
5475 State.regs[dstreg1] += EXTEND4 (IMM4A);
5476 State.regs[dstreg2] += EXTEND4 (IMM4);
5479 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5480 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5484 int srcreg2, dstreg1, dstreg2;
5487 srcreg2 = translate_rreg (SD_, RM2);
5488 dstreg1 = translate_rreg (SD_, RN1);
5489 dstreg2 = translate_rreg (SD_, RN2);
5491 State.regs[dstreg1] += EXTEND4 (IMM4A);
5492 State.regs[dstreg2] -= State.regs[srcreg2];
5495 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5496 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5500 int dstreg1, dstreg2;
5503 dstreg1 = translate_rreg (SD_, RN1);
5504 dstreg2 = translate_rreg (SD_, RN2);
5506 State.regs[dstreg1] += EXTEND4 (IMM4A);
5507 State.regs[dstreg2] -= EXTEND4 (IMM4);
5510 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5511 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5515 int srcreg2, dstreg1, dstreg2;
5518 srcreg2 = translate_rreg (SD_, RM2);
5519 dstreg1 = translate_rreg (SD_, RN1);
5520 dstreg2 = translate_rreg (SD_, RN2);
5522 State.regs[dstreg1] += EXTEND4 (IMM4A);
5523 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5526 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5527 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5531 int dstreg1, dstreg2;
5534 dstreg1 = translate_rreg (SD_, RN1);
5535 dstreg2 = translate_rreg (SD_, RN2);
5537 State.regs[dstreg1] += EXTEND4 (IMM4A);
5538 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5541 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5542 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5546 int srcreg2, dstreg1, dstreg2;
5549 srcreg2 = translate_rreg (SD_, RM2);
5550 dstreg1 = translate_rreg (SD_, RN1);
5551 dstreg2 = translate_rreg (SD_, RN2);
5553 State.regs[dstreg1] += EXTEND4 (IMM4A);
5554 State.regs[dstreg2] = State.regs[srcreg2];
5557 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5558 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5562 int dstreg1, dstreg2;
5565 dstreg1 = translate_rreg (SD_, RN1);
5566 dstreg2 = translate_rreg (SD_, RN2);
5568 State.regs[dstreg1] += EXTEND4 (IMM4A);
5569 State.regs[dstreg2] = EXTEND4 (IMM4);
5572 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5573 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5577 int srcreg2, dstreg1, dstreg2;
5581 srcreg2 = translate_rreg (SD_, RM2);
5582 dstreg1 = translate_rreg (SD_, RN1);
5583 dstreg2 = translate_rreg (SD_, RN2);
5585 State.regs[dstreg1] += EXTEND4 (IMM4A);
5586 temp = State.regs[dstreg2];
5587 temp >>= State.regs[srcreg2];
5588 State.regs[dstreg2] = temp;
5591 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5592 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5596 int dstreg1, dstreg2;
5600 dstreg1 = translate_rreg (SD_, RN1);
5601 dstreg2 = translate_rreg (SD_, RN2);
5603 State.regs[dstreg1] += EXTEND4 (IMM4A);
5604 temp = State.regs[dstreg2];
5606 State.regs[dstreg2] = temp;
5609 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5610 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5614 int srcreg2, dstreg1, dstreg2;
5617 srcreg2 = translate_rreg (SD_, RM2);
5618 dstreg1 = translate_rreg (SD_, RN1);
5619 dstreg2 = translate_rreg (SD_, RN2);
5621 State.regs[dstreg1] += EXTEND4 (IMM4A);
5622 State.regs[dstreg2] >>= State.regs[srcreg2];
5625 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5626 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5630 int dstreg1, dstreg2;
5634 dstreg1 = translate_rreg (SD_, RN1);
5635 dstreg2 = translate_rreg (SD_, RN2);
5637 State.regs[dstreg1] += EXTEND4 (IMM4A);
5638 State.regs[dstreg2] >>= IMM4;
5642 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5643 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5647 int srcreg2, dstreg1, dstreg2;
5650 srcreg2 = translate_rreg (SD_, RM2);
5651 dstreg1 = translate_rreg (SD_, RN1);
5652 dstreg2 = translate_rreg (SD_, RN2);
5654 State.regs[dstreg1] += EXTEND4 (IMM4A);
5655 State.regs[dstreg2] <<= State.regs[srcreg2];
5658 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
5659 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5663 int dstreg1, dstreg2;
5667 dstreg1 = translate_rreg (SD_, RN1);
5668 dstreg2 = translate_rreg (SD_, RN2);
5670 State.regs[dstreg1] += EXTEND4 (IMM4A);
5671 State.regs[dstreg2] <<= IMM4;
5674 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
5675 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5679 int srcreg2, dstreg1, dstreg2;
5682 srcreg2 = translate_rreg (SD_, RM2);
5683 dstreg1 = translate_rreg (SD_, RN1);
5684 dstreg2 = translate_rreg (SD_, RN2);
5686 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5687 State.regs[dstreg2] += State.regs[srcreg2];
5690 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
5691 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5695 int dstreg1, dstreg2;
5698 dstreg1 = translate_rreg (SD_, RN1);
5699 dstreg2 = translate_rreg (SD_, RN2);
5701 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5702 State.regs[dstreg2] += EXTEND4 (IMM4);
5705 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
5706 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5710 int srcreg2, dstreg1, dstreg2;
5713 srcreg2 = translate_rreg (SD_, RM2);
5714 dstreg1 = translate_rreg (SD_, RN1);
5715 dstreg2 = translate_rreg (SD_, RN2);
5717 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5718 State.regs[dstreg2] -= State.regs[srcreg2];
5721 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
5722 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5726 int dstreg1, dstreg2;
5729 dstreg1 = translate_rreg (SD_, RN1);
5730 dstreg2 = translate_rreg (SD_, RN2);
5732 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5733 State.regs[dstreg2] -= EXTEND4 (IMM4);
5736 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
5737 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5741 int srcreg2, dstreg1, dstreg2;
5744 srcreg2 = translate_rreg (SD_, RM2);
5745 dstreg1 = translate_rreg (SD_, RN1);
5746 dstreg2 = translate_rreg (SD_, RN2);
5748 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5749 State.regs[dstreg2] = State.regs[srcreg2];
5752 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
5753 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5757 int dstreg1, dstreg2;
5760 dstreg1 = translate_rreg (SD_, RN1);
5761 dstreg2 = translate_rreg (SD_, RN2);
5763 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5764 State.regs[dstreg2] = EXTEND4 (IMM4);
5767 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
5768 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
5772 int srcreg2, dstreg1, dstreg2;
5776 srcreg2 = translate_rreg (SD_, RM2);
5777 dstreg1 = translate_rreg (SD_, RN1);
5778 dstreg2 = translate_rreg (SD_, RN2);
5780 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5781 temp = State.regs[dstreg2];
5782 temp >>= State.regs[srcreg2];
5783 State.regs[dstreg2] = temp;
5786 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
5787 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
5791 int dstreg1, dstreg2;
5795 dstreg1 = translate_rreg (SD_, RN1);
5796 dstreg2 = translate_rreg (SD_, RN2);
5798 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5799 temp = State.regs[dstreg2];
5801 State.regs[dstreg2] = temp;
5804 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
5805 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
5809 int srcreg2, dstreg1, dstreg2;
5812 srcreg2 = translate_rreg (SD_, RM2);
5813 dstreg1 = translate_rreg (SD_, RN1);
5814 dstreg2 = translate_rreg (SD_, RN2);
5816 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5817 State.regs[dstreg2] >>= State.regs[srcreg2];
5820 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
5821 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
5825 int dstreg1, dstreg2;
5829 dstreg1 = translate_rreg (SD_, RN1);
5830 dstreg2 = translate_rreg (SD_, RN2);
5832 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5833 State.regs[dstreg2] >>= IMM4;
5837 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
5838 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
5842 int srcreg2, dstreg1, dstreg2;
5845 srcreg2 = translate_rreg (SD_, RM2);
5846 dstreg1 = translate_rreg (SD_, RN1);
5847 dstreg2 = translate_rreg (SD_, RN2);
5849 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5850 State.regs[dstreg2] <<= State.regs[srcreg2];
5853 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
5854 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
5858 int dstreg1, dstreg2;
5862 dstreg1 = translate_rreg (SD_, RN1);
5863 dstreg2 = translate_rreg (SD_, RN2);
5865 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5866 State.regs[dstreg2] <<= IMM4;
5869 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
5870 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
5874 int srcreg2, dstreg1, dstreg2;
5877 srcreg2 = translate_rreg (SD_, RM2);
5878 dstreg1 = translate_rreg (SD_, RN1);
5879 dstreg2 = translate_rreg (SD_, RN2);
5881 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5882 State.regs[dstreg2] += State.regs[srcreg2];
5885 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
5886 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
5890 int dstreg1, dstreg2;
5893 dstreg1 = translate_rreg (SD_, RN1);
5894 dstreg2 = translate_rreg (SD_, RN2);
5896 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5897 State.regs[dstreg2] += EXTEND4 (IMM4);
5900 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
5901 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
5905 int srcreg2, dstreg1, dstreg2;
5908 srcreg2 = translate_rreg (SD_, RM2);
5909 dstreg1 = translate_rreg (SD_, RN1);
5910 dstreg2 = translate_rreg (SD_, RN2);
5912 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5913 State.regs[dstreg2] -= State.regs[srcreg2];
5916 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
5917 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
5921 int dstreg1, dstreg2;
5924 dstreg1 = translate_rreg (SD_, RN1);
5925 dstreg2 = translate_rreg (SD_, RN2);
5927 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5928 State.regs[dstreg2] -= EXTEND4 (IMM4);
5931 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
5932 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
5936 int srcreg2, dstreg1, dstreg2;
5939 srcreg2 = translate_rreg (SD_, RM2);
5940 dstreg1 = translate_rreg (SD_, RN1);
5941 dstreg2 = translate_rreg (SD_, RN2);
5943 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5944 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5947 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
5948 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
5952 int dstreg1, dstreg2;
5955 dstreg1 = translate_rreg (SD_, RN1);
5956 dstreg2 = translate_rreg (SD_, RN2);
5958 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5959 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5962 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
5963 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
5967 int srcreg2, dstreg1, dstreg2;
5970 srcreg2 = translate_rreg (SD_, RM2);
5971 dstreg1 = translate_rreg (SD_, RN1);
5972 dstreg2 = translate_rreg (SD_, RN2);
5974 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5975 State.regs[dstreg2] = State.regs[srcreg2];
5978 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
5979 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
5983 int dstreg1, dstreg2;
5986 dstreg1 = translate_rreg (SD_, RN1);
5987 dstreg2 = translate_rreg (SD_, RN2);
5989 State.regs[dstreg1] -= EXTEND4 (IMM4A);
5990 State.regs[dstreg2] = EXTEND4 (IMM4);
5993 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
5994 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
5998 int srcreg2, dstreg1, dstreg2;
6002 srcreg2 = translate_rreg (SD_, RM2);
6003 dstreg1 = translate_rreg (SD_, RN1);
6004 dstreg2 = translate_rreg (SD_, RN2);
6006 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6007 temp = State.regs[dstreg2];
6008 temp >>= State.regs[srcreg2];
6009 State.regs[dstreg2] = temp;
6012 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6013 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6017 int dstreg1, dstreg2;
6021 dstreg1 = translate_rreg (SD_, RN1);
6022 dstreg2 = translate_rreg (SD_, RN2);
6024 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6025 temp = State.regs[dstreg2];
6027 State.regs[dstreg2] = temp;
6030 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6031 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6035 int srcreg2, dstreg1, dstreg2;
6038 srcreg2 = translate_rreg (SD_, RM2);
6039 dstreg1 = translate_rreg (SD_, RN1);
6040 dstreg2 = translate_rreg (SD_, RN2);
6042 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6043 State.regs[dstreg2] >>= State.regs[srcreg2];
6046 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6047 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6051 int dstreg1, dstreg2;
6055 dstreg1 = translate_rreg (SD_, RN1);
6056 dstreg2 = translate_rreg (SD_, RN2);
6058 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6059 State.regs[dstreg2] >>= IMM4;
6063 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6064 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6068 int srcreg2, dstreg1, dstreg2;
6071 srcreg2 = translate_rreg (SD_, RM2);
6072 dstreg1 = translate_rreg (SD_, RN1);
6073 dstreg2 = translate_rreg (SD_, RN2);
6075 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6076 State.regs[dstreg2] <<= State.regs[srcreg2];
6079 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6080 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6084 int dstreg1, dstreg2;
6088 dstreg1 = translate_rreg (SD_, RN1);
6089 dstreg2 = translate_rreg (SD_, RN2);
6091 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6092 State.regs[dstreg2] <<= IMM4;
6095 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6096 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6100 int srcreg2, dstreg1, dstreg2;
6103 srcreg2 = translate_rreg (SD_, RM2);
6104 dstreg1 = translate_rreg (SD_, RN1);
6105 dstreg2 = translate_rreg (SD_, RN2);
6107 State.regs[dstreg1] = EXTEND4 (IMM4A);
6108 State.regs[dstreg2] += State.regs[srcreg2];
6111 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6112 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6116 int dstreg1, dstreg2;
6119 dstreg1 = translate_rreg (SD_, RN1);
6120 dstreg2 = translate_rreg (SD_, RN2);
6122 State.regs[dstreg1] = EXTEND4 (IMM4A);
6123 State.regs[dstreg2] += EXTEND4 (IMM4);
6126 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6127 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6131 int srcreg2, dstreg1, dstreg2;
6134 srcreg2 = translate_rreg (SD_, RM2);
6135 dstreg1 = translate_rreg (SD_, RN1);
6136 dstreg2 = translate_rreg (SD_, RN2);
6138 State.regs[dstreg1] = EXTEND4 (IMM4A);
6139 State.regs[dstreg2] -= State.regs[srcreg2];
6142 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6143 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6147 int dstreg1, dstreg2;
6150 dstreg1 = translate_rreg (SD_, RN1);
6151 dstreg2 = translate_rreg (SD_, RN2);
6153 State.regs[dstreg1] = EXTEND4 (IMM4A);
6154 State.regs[dstreg2] -= EXTEND4 (IMM4);
6157 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6158 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6162 int srcreg2, dstreg1, dstreg2;
6165 srcreg2 = translate_rreg (SD_, RM2);
6166 dstreg1 = translate_rreg (SD_, RN1);
6167 dstreg2 = translate_rreg (SD_, RN2);
6169 State.regs[dstreg1] = EXTEND4 (IMM4A);
6170 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6173 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6174 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6178 int dstreg1, dstreg2;
6181 dstreg1 = translate_rreg (SD_, RN1);
6182 dstreg2 = translate_rreg (SD_, RN2);
6184 State.regs[dstreg1] = EXTEND4 (IMM4A);
6185 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6188 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6189 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6193 int srcreg2, dstreg1, dstreg2;
6196 srcreg2 = translate_rreg (SD_, RM2);
6197 dstreg1 = translate_rreg (SD_, RN1);
6198 dstreg2 = translate_rreg (SD_, RN2);
6200 State.regs[dstreg1] = EXTEND4 (IMM4A);
6201 State.regs[dstreg2] = State.regs[srcreg2];
6204 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6205 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6209 int dstreg1, dstreg2;
6212 dstreg1 = translate_rreg (SD_, RN1);
6213 dstreg2 = translate_rreg (SD_, RN2);
6215 State.regs[dstreg1] = EXTEND4 (IMM4A);
6216 State.regs[dstreg2] = EXTEND4 (IMM4);
6219 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6220 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6224 int srcreg2, dstreg1, dstreg2;
6228 srcreg2 = translate_rreg (SD_, RM2);
6229 dstreg1 = translate_rreg (SD_, RN1);
6230 dstreg2 = translate_rreg (SD_, RN2);
6232 State.regs[dstreg1] = EXTEND4 (IMM4A);
6233 temp = State.regs[dstreg2];
6234 temp >>= State.regs[srcreg2];
6235 State.regs[dstreg2] = temp;
6238 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6239 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6243 int dstreg1, dstreg2;
6247 dstreg1 = translate_rreg (SD_, RN1);
6248 dstreg2 = translate_rreg (SD_, RN2);
6250 State.regs[dstreg1] = EXTEND4 (IMM4A);
6251 temp = State.regs[dstreg2];
6253 State.regs[dstreg2] = temp;
6256 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6257 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6261 int srcreg2, dstreg1, dstreg2;
6264 srcreg2 = translate_rreg (SD_, RM2);
6265 dstreg1 = translate_rreg (SD_, RN1);
6266 dstreg2 = translate_rreg (SD_, RN2);
6268 State.regs[dstreg1] = EXTEND4 (IMM4A);
6269 State.regs[dstreg2] >>= State.regs[srcreg2];
6272 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6273 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6277 int dstreg1, dstreg2;
6281 dstreg1 = translate_rreg (SD_, RN1);
6282 dstreg2 = translate_rreg (SD_, RN2);
6284 State.regs[dstreg1] = EXTEND4 (IMM4A);
6285 State.regs[dstreg2] >>= IMM4;
6289 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6290 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6294 int srcreg2, dstreg1, dstreg2;
6297 srcreg2 = translate_rreg (SD_, RM2);
6298 dstreg1 = translate_rreg (SD_, RN1);
6299 dstreg2 = translate_rreg (SD_, RN2);
6301 State.regs[dstreg1] = EXTEND4 (IMM4A);
6302 State.regs[dstreg2] <<= State.regs[srcreg2];
6305 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6306 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6310 int dstreg1, dstreg2;
6314 dstreg1 = translate_rreg (SD_, RN1);
6315 dstreg2 = translate_rreg (SD_, RN2);
6317 State.regs[dstreg1] = EXTEND4 (IMM4A);
6318 State.regs[dstreg2] <<= IMM4;
6321 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6322 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6326 int srcreg1, srcreg2, dstreg1, dstreg2;
6329 srcreg1 = translate_rreg (SD_, RM1);
6330 srcreg2 = translate_rreg (SD_, RM2);
6331 dstreg1 = translate_rreg (SD_, RN1);
6332 dstreg2 = translate_rreg (SD_, RN2);
6334 State.regs[dstreg1] &= State.regs[srcreg1];
6335 State.regs[dstreg2] += State.regs[srcreg2];
6338 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6339 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6343 int srcreg1, dstreg1, dstreg2;
6346 srcreg1 = translate_rreg (SD_, RM1);
6347 dstreg1 = translate_rreg (SD_, RN1);
6348 dstreg2 = translate_rreg (SD_, RN2);
6350 State.regs[dstreg1] &= State.regs[srcreg1];
6351 State.regs[dstreg2] += EXTEND4 (IMM4);
6354 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6355 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6359 int srcreg1, srcreg2, dstreg1, dstreg2;
6362 srcreg1 = translate_rreg (SD_, RM1);
6363 srcreg2 = translate_rreg (SD_, RM2);
6364 dstreg1 = translate_rreg (SD_, RN1);
6365 dstreg2 = translate_rreg (SD_, RN2);
6367 State.regs[dstreg1] &= State.regs[srcreg1];
6368 State.regs[dstreg2] -= State.regs[srcreg2];
6371 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6372 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6376 int srcreg1, dstreg1, dstreg2;
6379 srcreg1 = translate_rreg (SD_, RM1);
6380 dstreg1 = translate_rreg (SD_, RN1);
6381 dstreg2 = translate_rreg (SD_, RN2);
6383 State.regs[dstreg1] &= State.regs[srcreg1];
6384 State.regs[dstreg2] -= EXTEND4 (IMM4);
6387 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6388 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6392 int srcreg1, srcreg2, dstreg1, dstreg2;
6395 srcreg1 = translate_rreg (SD_, RM1);
6396 srcreg2 = translate_rreg (SD_, RM2);
6397 dstreg1 = translate_rreg (SD_, RN1);
6398 dstreg2 = translate_rreg (SD_, RN2);
6400 State.regs[dstreg1] &= State.regs[srcreg1];
6401 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6404 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6405 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6409 int srcreg1, dstreg1, dstreg2;
6412 srcreg1 = translate_rreg (SD_, RM1);
6413 dstreg1 = translate_rreg (SD_, RN1);
6414 dstreg2 = translate_rreg (SD_, RN2);
6416 State.regs[dstreg1] &= State.regs[srcreg1];
6417 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6420 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6421 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6425 int srcreg1, srcreg2, dstreg1, dstreg2;
6428 srcreg1 = translate_rreg (SD_, RM1);
6429 srcreg2 = translate_rreg (SD_, RM2);
6430 dstreg1 = translate_rreg (SD_, RN1);
6431 dstreg2 = translate_rreg (SD_, RN2);
6433 State.regs[dstreg1] &= State.regs[srcreg1];
6434 State.regs[dstreg2] = State.regs[srcreg2];
6437 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6438 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6442 int srcreg1, dstreg1, dstreg2;
6445 srcreg1 = translate_rreg (SD_, RM1);
6446 dstreg1 = translate_rreg (SD_, RN1);
6447 dstreg2 = translate_rreg (SD_, RN2);
6449 State.regs[dstreg1] &= State.regs[srcreg1];
6450 State.regs[dstreg2] = EXTEND4 (IMM4);
6453 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6454 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6458 int srcreg1, srcreg2, dstreg1, dstreg2;
6462 srcreg1 = translate_rreg (SD_, RM1);
6463 srcreg2 = translate_rreg (SD_, RM2);
6464 dstreg1 = translate_rreg (SD_, RN1);
6465 dstreg2 = translate_rreg (SD_, RN2);
6467 State.regs[dstreg1] &= State.regs[srcreg1];
6468 temp = State.regs[dstreg2];
6469 temp >>= State.regs[srcreg2];
6470 State.regs[dstreg2] = temp;
6473 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6474 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6478 int srcreg1, dstreg1, dstreg2;
6482 srcreg1 = translate_rreg (SD_, RM1);
6483 dstreg1 = translate_rreg (SD_, RN1);
6484 dstreg2 = translate_rreg (SD_, RN2);
6486 State.regs[dstreg1] &= State.regs[srcreg1];
6487 temp = State.regs[dstreg2];
6489 State.regs[dstreg2] = temp;
6492 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6493 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6497 int srcreg1, srcreg2, dstreg1, dstreg2;
6500 srcreg1 = translate_rreg (SD_, RM1);
6501 srcreg2 = translate_rreg (SD_, RM2);
6502 dstreg1 = translate_rreg (SD_, RN1);
6503 dstreg2 = translate_rreg (SD_, RN2);
6505 State.regs[dstreg1] &= State.regs[srcreg1];
6506 State.regs[dstreg2] >>= State.regs[srcreg2];
6509 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6510 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6514 int srcreg1, dstreg1, dstreg2;
6518 srcreg1 = translate_rreg (SD_, RM1);
6519 dstreg1 = translate_rreg (SD_, RN1);
6520 dstreg2 = translate_rreg (SD_, RN2);
6522 State.regs[dstreg1] &= State.regs[srcreg1];
6523 State.regs[dstreg2] >>= IMM4;
6527 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6528 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6532 int srcreg1, srcreg2, dstreg1, dstreg2;
6535 srcreg1 = translate_rreg (SD_, RM1);
6536 srcreg2 = translate_rreg (SD_, RM2);
6537 dstreg1 = translate_rreg (SD_, RN1);
6538 dstreg2 = translate_rreg (SD_, RN2);
6540 State.regs[dstreg1] &= State.regs[srcreg1];
6541 State.regs[dstreg2] <<= State.regs[srcreg2];
6544 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6545 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6549 int srcreg1, dstreg1, dstreg2;
6553 srcreg1 = translate_rreg (SD_, RM1);
6554 dstreg1 = translate_rreg (SD_, RN1);
6555 dstreg2 = translate_rreg (SD_, RN2);
6557 State.regs[dstreg1] &= State.regs[srcreg1];
6558 State.regs[dstreg2] <<= IMM4;
6561 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6562 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6566 int srcreg1, srcreg2, dstreg1, dstreg2;
6567 long temp, temp2, sum;
6570 srcreg1 = translate_rreg (SD_, RM1);
6571 srcreg2 = translate_rreg (SD_, RM2);
6572 dstreg1 = translate_rreg (SD_, RN1);
6573 dstreg2 = translate_rreg (SD_, RN2);
6575 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6576 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6577 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6578 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6579 sum = temp + temp2 + State.regs[REG_MCRL];
6581 State.regs[dstreg1] = sum;
6582 State.regs[dstreg2] += State.regs[srcreg2];
6585 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6586 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6590 int srcreg1, dstreg1, dstreg2;
6591 long temp, temp2, sum;
6594 srcreg1 = translate_rreg (SD_, RM1);
6595 dstreg1 = translate_rreg (SD_, RN1);
6596 dstreg2 = translate_rreg (SD_, RN2);
6598 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6599 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6600 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6601 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6602 sum = temp + temp2 + State.regs[REG_MCRL];
6604 State.regs[dstreg1] = sum;
6605 State.regs[dstreg2] += EXTEND4 (IMM4);
6608 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
6609 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6613 int srcreg1, srcreg2, dstreg1, dstreg2;
6614 long temp, temp2, sum;
6617 srcreg1 = translate_rreg (SD_, RM1);
6618 srcreg2 = translate_rreg (SD_, RM2);
6619 dstreg1 = translate_rreg (SD_, RN1);
6620 dstreg2 = translate_rreg (SD_, RN2);
6622 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6623 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6624 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6625 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6626 sum = temp + temp2 + State.regs[REG_MCRL];
6628 State.regs[dstreg1] = sum;
6629 State.regs[dstreg2] -= State.regs[srcreg2];
6632 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
6633 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6637 int srcreg1, dstreg1, dstreg2;
6638 long temp, temp2, sum;
6641 srcreg1 = translate_rreg (SD_, RM1);
6642 dstreg1 = translate_rreg (SD_, RN1);
6643 dstreg2 = translate_rreg (SD_, RN2);
6645 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6646 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6647 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6648 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6649 sum = temp + temp2 + State.regs[REG_MCRL];
6651 State.regs[dstreg1] = sum;
6652 State.regs[dstreg2] -= EXTEND4 (IMM4);
6655 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
6656 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6660 int srcreg1, srcreg2, dstreg1, dstreg2;
6661 long temp, temp2, sum;
6664 srcreg1 = translate_rreg (SD_, RM1);
6665 srcreg2 = translate_rreg (SD_, RM2);
6666 dstreg1 = translate_rreg (SD_, RN1);
6667 dstreg2 = translate_rreg (SD_, RN2);
6669 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6670 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6671 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6672 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6673 sum = temp + temp2 + State.regs[REG_MCRL];
6675 State.regs[dstreg1] = sum;
6676 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6679 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
6680 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6684 int srcreg1, dstreg1, dstreg2;
6685 long temp, temp2, sum;
6688 srcreg1 = translate_rreg (SD_, RM1);
6689 dstreg1 = translate_rreg (SD_, RN1);
6690 dstreg2 = translate_rreg (SD_, RN2);
6692 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6693 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6694 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6695 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6696 sum = temp + temp2 + State.regs[REG_MCRL];
6698 State.regs[dstreg1] = sum;
6699 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6702 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
6703 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6707 int srcreg1, srcreg2, dstreg1, dstreg2;
6708 long temp, temp2, sum;
6711 srcreg1 = translate_rreg (SD_, RM1);
6712 srcreg2 = translate_rreg (SD_, RM2);
6713 dstreg1 = translate_rreg (SD_, RN1);
6714 dstreg2 = translate_rreg (SD_, RN2);
6716 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6717 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6718 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6719 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6720 sum = temp + temp2 + State.regs[REG_MCRL];
6722 State.regs[dstreg1] = sum;
6723 State.regs[dstreg2] = State.regs[srcreg2];
6726 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
6727 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6731 int srcreg1, dstreg1, dstreg2;
6732 long temp, temp2, sum;
6735 srcreg1 = translate_rreg (SD_, RM1);
6736 dstreg1 = translate_rreg (SD_, RN1);
6737 dstreg2 = translate_rreg (SD_, RN2);
6739 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6740 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6741 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6742 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6743 sum = temp + temp2 + State.regs[REG_MCRL];
6745 State.regs[dstreg1] = sum;
6746 State.regs[dstreg2] = EXTEND4 (IMM4);
6749 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
6750 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6754 int srcreg1, srcreg2, dstreg1, dstreg2;
6755 long temp, temp2, sum;
6758 srcreg1 = translate_rreg (SD_, RM1);
6759 srcreg2 = translate_rreg (SD_, RM2);
6760 dstreg1 = translate_rreg (SD_, RN1);
6761 dstreg2 = translate_rreg (SD_, RN2);
6763 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6764 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6765 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6766 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6767 sum = temp + temp2 + State.regs[REG_MCRL];
6769 State.regs[dstreg1] = sum;
6770 temp = State.regs[dstreg2];
6771 temp >>= State.regs[srcreg2];
6772 State.regs[dstreg2] = temp;
6775 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
6776 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
6780 int srcreg1, dstreg1, dstreg2;
6781 long temp, temp2, sum;
6784 srcreg1 = translate_rreg (SD_, RM1);
6785 dstreg1 = translate_rreg (SD_, RN1);
6786 dstreg2 = translate_rreg (SD_, RN2);
6788 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6789 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6790 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6791 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6792 sum = temp + temp2 + State.regs[REG_MCRL];
6794 State.regs[dstreg1] = sum;
6795 temp = State.regs[dstreg2];
6797 State.regs[dstreg2] = temp;
6800 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
6801 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
6805 int srcreg1, srcreg2, dstreg1, dstreg2;
6806 long temp, temp2, sum;
6809 srcreg1 = translate_rreg (SD_, RM1);
6810 srcreg2 = translate_rreg (SD_, RM2);
6811 dstreg1 = translate_rreg (SD_, RN1);
6812 dstreg2 = translate_rreg (SD_, RN2);
6814 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6815 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6816 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6817 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6818 sum = temp + temp2 + State.regs[REG_MCRL];
6820 State.regs[dstreg1] = sum;
6821 State.regs[dstreg2] >>= State.regs[srcreg2];
6824 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
6825 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
6829 int srcreg1, dstreg1, dstreg2;
6830 long temp, temp2, sum;
6833 srcreg1 = translate_rreg (SD_, RM1);
6834 dstreg1 = translate_rreg (SD_, RN1);
6835 dstreg2 = translate_rreg (SD_, RN2);
6837 State.regs[dstreg2] >>= IMM4;
6841 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
6842 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
6846 int srcreg1, srcreg2, dstreg1, dstreg2;
6847 long temp, temp2, sum;
6850 srcreg1 = translate_rreg (SD_, RM1);
6851 srcreg2 = translate_rreg (SD_, RM2);
6852 dstreg1 = translate_rreg (SD_, RN1);
6853 dstreg2 = translate_rreg (SD_, RN2);
6855 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6856 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6857 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6858 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6859 sum = temp + temp2 + State.regs[REG_MCRL];
6861 State.regs[dstreg1] = sum;
6862 State.regs[dstreg2] <<= State.regs[srcreg2];
6865 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
6866 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
6870 int srcreg1, dstreg1, dstreg2;
6871 long temp, temp2, sum;
6874 srcreg1 = translate_rreg (SD_, RM1);
6875 dstreg1 = translate_rreg (SD_, RN1);
6876 dstreg2 = translate_rreg (SD_, RN2);
6878 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6879 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6880 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6881 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6882 sum = temp + temp2 + State.regs[REG_MCRL];
6884 State.regs[dstreg1] = sum;
6885 State.regs[dstreg2] <<= IMM4;
6888 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
6889 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
6893 int srcreg1, srcreg2, dstreg1, dstreg2;
6896 srcreg1 = translate_rreg (SD_, RM1);
6897 srcreg2 = translate_rreg (SD_, RM2);
6898 dstreg1 = translate_rreg (SD_, RN1);
6899 dstreg2 = translate_rreg (SD_, RN2);
6901 State.regs[dstreg1] ^= State.regs[srcreg1];
6902 State.regs[dstreg2] += State.regs[srcreg2];
6905 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
6906 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
6910 int srcreg1, dstreg1, dstreg2;
6913 srcreg1 = translate_rreg (SD_, RM1);
6914 dstreg1 = translate_rreg (SD_, RN1);
6915 dstreg2 = translate_rreg (SD_, RN2);
6917 State.regs[dstreg1] ^= State.regs[srcreg1];
6918 State.regs[dstreg2] += EXTEND4 (IMM4);
6921 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
6922 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
6926 int srcreg1, srcreg2, dstreg1, dstreg2;
6929 srcreg1 = translate_rreg (SD_, RM1);
6930 srcreg2 = translate_rreg (SD_, RM2);
6931 dstreg1 = translate_rreg (SD_, RN1);
6932 dstreg2 = translate_rreg (SD_, RN2);
6934 State.regs[dstreg1] ^= State.regs[srcreg1];
6935 State.regs[dstreg2] -= State.regs[srcreg2];
6938 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
6939 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
6943 int srcreg1, dstreg1, dstreg2;
6946 srcreg1 = translate_rreg (SD_, RM1);
6947 dstreg1 = translate_rreg (SD_, RN1);
6948 dstreg2 = translate_rreg (SD_, RN2);
6950 State.regs[dstreg1] ^= State.regs[srcreg1];
6951 State.regs[dstreg2] -= EXTEND4 (IMM4);
6954 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
6955 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
6959 int srcreg1, srcreg2, dstreg1, dstreg2;
6962 srcreg1 = translate_rreg (SD_, RM1);
6963 srcreg2 = translate_rreg (SD_, RM2);
6964 dstreg1 = translate_rreg (SD_, RN1);
6965 dstreg2 = translate_rreg (SD_, RN2);
6967 State.regs[dstreg1] ^= State.regs[srcreg1];
6968 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6971 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
6972 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
6976 int srcreg1, dstreg1, dstreg2;
6979 srcreg1 = translate_rreg (SD_, RM1);
6980 dstreg1 = translate_rreg (SD_, RN1);
6981 dstreg2 = translate_rreg (SD_, RN2);
6983 State.regs[dstreg1] ^= State.regs[srcreg1];
6984 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6987 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
6988 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
6992 int srcreg1, srcreg2, dstreg1, dstreg2;
6995 srcreg1 = translate_rreg (SD_, RM1);
6996 srcreg2 = translate_rreg (SD_, RM2);
6997 dstreg1 = translate_rreg (SD_, RN1);
6998 dstreg2 = translate_rreg (SD_, RN2);
7000 State.regs[dstreg1] ^= State.regs[srcreg1];
7001 State.regs[dstreg2] = State.regs[srcreg2];
7004 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7005 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7009 int srcreg1, dstreg1, dstreg2;
7012 srcreg1 = translate_rreg (SD_, RM1);
7013 dstreg1 = translate_rreg (SD_, RN1);
7014 dstreg2 = translate_rreg (SD_, RN2);
7016 State.regs[dstreg1] ^= State.regs[srcreg1];
7017 State.regs[dstreg2] = EXTEND4 (IMM4);
7020 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7021 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7025 int srcreg1, srcreg2, dstreg1, dstreg2;
7029 srcreg1 = translate_rreg (SD_, RM1);
7030 srcreg2 = translate_rreg (SD_, RM2);
7031 dstreg1 = translate_rreg (SD_, RN1);
7032 dstreg2 = translate_rreg (SD_, RN2);
7034 State.regs[dstreg1] ^= State.regs[srcreg1];
7035 temp = State.regs[dstreg2];
7036 temp >>= State.regs[srcreg2];
7037 State.regs[dstreg2] = temp;
7040 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7041 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7045 int srcreg1, dstreg1, dstreg2;
7049 srcreg1 = translate_rreg (SD_, RM1);
7050 dstreg1 = translate_rreg (SD_, RN1);
7051 dstreg2 = translate_rreg (SD_, RN2);
7053 State.regs[dstreg1] ^= State.regs[srcreg1];
7054 temp = State.regs[dstreg2];
7056 State.regs[dstreg2] = temp;
7059 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7060 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7064 int srcreg1, srcreg2, dstreg1, dstreg2;
7067 srcreg1 = translate_rreg (SD_, RM1);
7068 srcreg2 = translate_rreg (SD_, RM2);
7069 dstreg1 = translate_rreg (SD_, RN1);
7070 dstreg2 = translate_rreg (SD_, RN2);
7072 State.regs[dstreg1] ^= State.regs[srcreg1];
7073 State.regs[dstreg2] >>= State.regs[srcreg2];
7076 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7077 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7081 int srcreg1, dstreg1, dstreg2;
7085 srcreg1 = translate_rreg (SD_, RM1);
7086 dstreg1 = translate_rreg (SD_, RN1);
7087 dstreg2 = translate_rreg (SD_, RN2);
7089 State.regs[dstreg1] ^= State.regs[srcreg1];
7090 State.regs[dstreg2] >>= IMM4;
7094 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7095 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7099 int srcreg1, srcreg2, dstreg1, dstreg2;
7102 srcreg1 = translate_rreg (SD_, RM1);
7103 srcreg2 = translate_rreg (SD_, RM2);
7104 dstreg1 = translate_rreg (SD_, RN1);
7105 dstreg2 = translate_rreg (SD_, RN2);
7107 State.regs[dstreg1] ^= State.regs[srcreg1];
7108 State.regs[dstreg2] <<= State.regs[srcreg2];
7111 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7112 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7116 int srcreg1, dstreg1, dstreg2;
7120 srcreg1 = translate_rreg (SD_, RM1);
7121 dstreg1 = translate_rreg (SD_, RN1);
7122 dstreg2 = translate_rreg (SD_, RN2);
7124 State.regs[dstreg1] ^= State.regs[srcreg1];
7125 State.regs[dstreg2] <<= IMM4;
7128 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7129 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7133 int srcreg1, srcreg2, dstreg1, dstreg2;
7136 srcreg1 = translate_rreg (SD_, RM1);
7137 srcreg2 = translate_rreg (SD_, RM2);
7138 dstreg1 = translate_rreg (SD_, RN1);
7139 dstreg2 = translate_rreg (SD_, RN2);
7141 State.regs[dstreg1] ^= State.regs[srcreg1];
7142 State.regs[dstreg2] += State.regs[srcreg2];
7145 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7146 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7150 int srcreg1, dstreg1, dstreg2;
7153 srcreg1 = translate_rreg (SD_, RM1);
7154 dstreg1 = translate_rreg (SD_, RN1);
7155 dstreg2 = translate_rreg (SD_, RN2);
7157 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7158 | ((State.regs[srcreg1] >> 16) & 0xffff));
7159 State.regs[dstreg2] += EXTEND4 (IMM4);
7162 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7163 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7167 int srcreg1, srcreg2, dstreg1, dstreg2;
7170 srcreg1 = translate_rreg (SD_, RM1);
7171 srcreg2 = translate_rreg (SD_, RM2);
7172 dstreg1 = translate_rreg (SD_, RN1);
7173 dstreg2 = translate_rreg (SD_, RN2);
7175 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7176 | ((State.regs[srcreg1] >> 16) & 0xffff));
7177 State.regs[dstreg2] -= State.regs[srcreg2];
7180 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7181 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7185 int srcreg1, dstreg1, dstreg2;
7188 srcreg1 = translate_rreg (SD_, RM1);
7189 dstreg1 = translate_rreg (SD_, RN1);
7190 dstreg2 = translate_rreg (SD_, RN2);
7192 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7193 | ((State.regs[srcreg1] >> 16) & 0xffff));
7194 State.regs[dstreg2] -= EXTEND4 (IMM4);
7197 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7198 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7202 int srcreg1, srcreg2, dstreg1, dstreg2;
7205 srcreg1 = translate_rreg (SD_, RM1);
7206 srcreg2 = translate_rreg (SD_, RM2);
7207 dstreg1 = translate_rreg (SD_, RN1);
7208 dstreg2 = translate_rreg (SD_, RN2);
7210 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7211 | ((State.regs[srcreg1] >> 16) & 0xffff));
7212 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7215 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7216 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7220 int srcreg1, dstreg1, dstreg2;
7223 srcreg1 = translate_rreg (SD_, RM1);
7224 dstreg1 = translate_rreg (SD_, RN1);
7225 dstreg2 = translate_rreg (SD_, RN2);
7227 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7228 | ((State.regs[srcreg1] >> 16) & 0xffff));
7229 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7232 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7233 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7237 int srcreg1, srcreg2, dstreg1, dstreg2;
7240 srcreg1 = translate_rreg (SD_, RM1);
7241 srcreg2 = translate_rreg (SD_, RM2);
7242 dstreg1 = translate_rreg (SD_, RN1);
7243 dstreg2 = translate_rreg (SD_, RN2);
7245 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7246 | ((State.regs[srcreg1] >> 16) & 0xffff));
7247 State.regs[dstreg2] = State.regs[srcreg2];
7250 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7251 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7255 int srcreg1, dstreg1, dstreg2;
7258 srcreg1 = translate_rreg (SD_, RM1);
7259 dstreg1 = translate_rreg (SD_, RN1);
7260 dstreg2 = translate_rreg (SD_, RN2);
7262 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7263 | ((State.regs[srcreg1] >> 16) & 0xffff));
7264 State.regs[dstreg2] = EXTEND4 (IMM4);
7267 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7268 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7272 int srcreg1, srcreg2, dstreg1, dstreg2;
7276 srcreg1 = translate_rreg (SD_, RM1);
7277 srcreg2 = translate_rreg (SD_, RM2);
7278 dstreg1 = translate_rreg (SD_, RN1);
7279 dstreg2 = translate_rreg (SD_, RN2);
7281 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7282 | ((State.regs[srcreg1] >> 16) & 0xffff));
7283 temp = State.regs[dstreg2];
7284 temp >>= State.regs[srcreg2];
7285 State.regs[dstreg2] = temp;
7288 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7289 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7293 int srcreg1, dstreg1, dstreg2;
7297 srcreg1 = translate_rreg (SD_, RM1);
7298 dstreg1 = translate_rreg (SD_, RN1);
7299 dstreg2 = translate_rreg (SD_, RN2);
7301 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7302 | ((State.regs[srcreg1] >> 16) & 0xffff));
7303 temp = State.regs[dstreg2];
7305 State.regs[dstreg2] = temp;
7308 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7309 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7313 int srcreg1, srcreg2, dstreg1, dstreg2;
7316 srcreg1 = translate_rreg (SD_, RM1);
7317 srcreg2 = translate_rreg (SD_, RM2);
7318 dstreg1 = translate_rreg (SD_, RN1);
7319 dstreg2 = translate_rreg (SD_, RN2);
7321 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7322 | ((State.regs[srcreg1] >> 16) & 0xffff));
7323 State.regs[dstreg2] >>= State.regs[srcreg2];
7326 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7327 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7331 int srcreg1, dstreg1, dstreg2;
7335 srcreg1 = translate_rreg (SD_, RM1);
7336 dstreg1 = translate_rreg (SD_, RN1);
7337 dstreg2 = translate_rreg (SD_, RN2);
7339 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7340 | ((State.regs[srcreg1] >> 16) & 0xffff));
7341 State.regs[dstreg2] >>= IMM4;
7345 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7346 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7350 int srcreg1, srcreg2, dstreg1, dstreg2;
7353 srcreg1 = translate_rreg (SD_, RM1);
7354 srcreg2 = translate_rreg (SD_, RM2);
7355 dstreg1 = translate_rreg (SD_, RN1);
7356 dstreg2 = translate_rreg (SD_, RN2);
7358 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7359 | ((State.regs[srcreg1] >> 16) & 0xffff));
7360 State.regs[dstreg2] <<= State.regs[srcreg2];
7363 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7364 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7368 int srcreg1, dstreg1, dstreg2;
7372 srcreg1 = translate_rreg (SD_, RM1);
7373 dstreg1 = translate_rreg (SD_, RN1);
7374 dstreg2 = translate_rreg (SD_, RN2);
7376 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7377 | ((State.regs[srcreg1] >> 16) & 0xffff));
7378 State.regs[dstreg2] <<= IMM4;
7381 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7382 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7386 int srcreg1, srcreg2, dstreg1, dstreg2;
7389 srcreg1 = translate_rreg (SD_, RM1);
7390 srcreg2 = translate_rreg (SD_, RM2);
7391 dstreg1 = translate_rreg (SD_, RN1);
7392 dstreg2 = translate_rreg (SD_, RN2);
7394 State.regs[dstreg1] |= State.regs[srcreg1];
7395 State.regs[dstreg2] += State.regs[srcreg2];
7398 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7399 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7403 int srcreg1, dstreg1, dstreg2;
7406 srcreg1 = translate_rreg (SD_, RM1);
7407 dstreg1 = translate_rreg (SD_, RN1);
7408 dstreg2 = translate_rreg (SD_, RN2);
7410 State.regs[dstreg1] |= State.regs[srcreg1];
7411 State.regs[dstreg2] += EXTEND4 (IMM4);
7414 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7415 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7419 int srcreg1, srcreg2, dstreg1, dstreg2;
7422 srcreg1 = translate_rreg (SD_, RM1);
7423 srcreg2 = translate_rreg (SD_, RM2);
7424 dstreg1 = translate_rreg (SD_, RN1);
7425 dstreg2 = translate_rreg (SD_, RN2);
7427 State.regs[dstreg1] |= State.regs[srcreg1];
7428 State.regs[dstreg2] -= State.regs[srcreg2];
7431 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7432 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7436 int srcreg1, dstreg1, dstreg2;
7439 srcreg1 = translate_rreg (SD_, RM1);
7440 dstreg1 = translate_rreg (SD_, RN1);
7441 dstreg2 = translate_rreg (SD_, RN2);
7443 State.regs[dstreg1] |= State.regs[srcreg1];
7444 State.regs[dstreg2] -= EXTEND4 (IMM4);
7447 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7448 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7452 int srcreg1, srcreg2, dstreg1, dstreg2;
7455 srcreg1 = translate_rreg (SD_, RM1);
7456 srcreg2 = translate_rreg (SD_, RM2);
7457 dstreg1 = translate_rreg (SD_, RN1);
7458 dstreg2 = translate_rreg (SD_, RN2);
7460 State.regs[dstreg1] |= State.regs[srcreg1];
7461 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7464 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7465 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7469 int srcreg1, dstreg1, dstreg2;
7472 srcreg1 = translate_rreg (SD_, RM1);
7473 dstreg1 = translate_rreg (SD_, RN1);
7474 dstreg2 = translate_rreg (SD_, RN2);
7476 State.regs[dstreg1] |= State.regs[srcreg1];
7477 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7480 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7481 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7485 int srcreg1, srcreg2, dstreg1, dstreg2;
7488 srcreg1 = translate_rreg (SD_, RM1);
7489 srcreg2 = translate_rreg (SD_, RM2);
7490 dstreg1 = translate_rreg (SD_, RN1);
7491 dstreg2 = translate_rreg (SD_, RN2);
7493 State.regs[dstreg1] |= State.regs[srcreg1];
7494 State.regs[dstreg2] = State.regs[srcreg2];
7497 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7498 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7502 int srcreg1, dstreg1, dstreg2;
7505 srcreg1 = translate_rreg (SD_, RM1);
7506 dstreg1 = translate_rreg (SD_, RN1);
7507 dstreg2 = translate_rreg (SD_, RN2);
7509 State.regs[dstreg1] |= State.regs[srcreg1];
7510 State.regs[dstreg2] = EXTEND4 (IMM4);
7513 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7514 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7518 int srcreg1, srcreg2, dstreg1, dstreg2;
7522 srcreg1 = translate_rreg (SD_, RM1);
7523 srcreg2 = translate_rreg (SD_, RM2);
7524 dstreg1 = translate_rreg (SD_, RN1);
7525 dstreg2 = translate_rreg (SD_, RN2);
7527 State.regs[dstreg1] |= State.regs[srcreg1];
7528 temp = State.regs[dstreg2];
7529 temp >>= State.regs[srcreg2];
7530 State.regs[dstreg2] = temp;
7533 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
7534 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7538 int srcreg1, dstreg1, dstreg2;
7542 srcreg1 = translate_rreg (SD_, RM1);
7543 dstreg1 = translate_rreg (SD_, RN1);
7544 dstreg2 = translate_rreg (SD_, RN2);
7546 State.regs[dstreg1] |= State.regs[srcreg1];
7547 temp = State.regs[dstreg2];
7549 State.regs[dstreg2] = temp;
7552 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
7553 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7557 int srcreg1, srcreg2, dstreg1, dstreg2;
7560 srcreg1 = translate_rreg (SD_, RM1);
7561 srcreg2 = translate_rreg (SD_, RM2);
7562 dstreg1 = translate_rreg (SD_, RN1);
7563 dstreg2 = translate_rreg (SD_, RN2);
7565 State.regs[dstreg1] |= State.regs[srcreg1];
7566 State.regs[dstreg2] >>= State.regs[srcreg2];
7569 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
7570 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7574 int srcreg1, dstreg1, dstreg2;
7578 srcreg1 = translate_rreg (SD_, RM1);
7579 dstreg1 = translate_rreg (SD_, RN1);
7580 dstreg2 = translate_rreg (SD_, RN2);
7582 State.regs[dstreg1] |= State.regs[srcreg1];
7583 State.regs[dstreg2] >>= IMM4;
7587 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
7588 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7592 int srcreg1, srcreg2, dstreg1, dstreg2;
7595 srcreg1 = translate_rreg (SD_, RM1);
7596 srcreg2 = translate_rreg (SD_, RM2);
7597 dstreg1 = translate_rreg (SD_, RN1);
7598 dstreg2 = translate_rreg (SD_, RN2);
7600 State.regs[dstreg1] |= State.regs[srcreg1];
7601 State.regs[dstreg2] <<= State.regs[srcreg2];
7604 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
7605 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7609 int srcreg1, dstreg1, dstreg2;
7613 srcreg1 = translate_rreg (SD_, RM1);
7614 dstreg1 = translate_rreg (SD_, RN1);
7615 dstreg2 = translate_rreg (SD_, RN2);
7617 State.regs[dstreg1] |= State.regs[srcreg1];
7618 State.regs[dstreg2] <<= IMM4;
7621 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
7622 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7626 int srcreg1, srcreg2, dstreg1, dstreg2;
7629 srcreg1 = translate_rreg (SD_, RM1);
7630 srcreg2 = translate_rreg (SD_, RM2);
7631 dstreg1 = translate_rreg (SD_, RN1);
7632 dstreg2 = translate_rreg (SD_, RN2);
7634 if (State.regs[srcreg1] >= 0x7fff)
7635 State.regs[dstreg1] = 0x7fff;
7636 else if (State.regs[srcreg1] <= 0xffff8000)
7637 State.regs[dstreg1] = 0xffff8000;
7639 State.regs[dstreg1] = State.regs[srcreg1];
7641 State.regs[dstreg2] += State.regs[srcreg2];
7644 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
7645 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7649 int srcreg1, dstreg1, dstreg2;
7652 srcreg1 = translate_rreg (SD_, RM1);
7653 dstreg1 = translate_rreg (SD_, RN1);
7654 dstreg2 = translate_rreg (SD_, RN2);
7656 if (State.regs[srcreg1] >= 0x7fff)
7657 State.regs[dstreg1] = 0x7fff;
7658 else if (State.regs[srcreg1] <= 0xffff8000)
7659 State.regs[dstreg1] = 0xffff8000;
7661 State.regs[dstreg1] = State.regs[srcreg1];
7663 State.regs[dstreg2] += EXTEND4 (IMM4);
7666 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
7667 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7671 int srcreg1, srcreg2, dstreg1, dstreg2;
7674 srcreg1 = translate_rreg (SD_, RM1);
7675 srcreg2 = translate_rreg (SD_, RM2);
7676 dstreg1 = translate_rreg (SD_, RN1);
7677 dstreg2 = translate_rreg (SD_, RN2);
7679 if (State.regs[srcreg1] >= 0x7fff)
7680 State.regs[dstreg1] = 0x7fff;
7681 else if (State.regs[srcreg1] <= 0xffff8000)
7682 State.regs[dstreg1] = 0xffff8000;
7684 State.regs[dstreg1] = State.regs[srcreg1];
7686 State.regs[dstreg2] -= State.regs[srcreg2];
7689 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
7690 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7694 int srcreg1, dstreg1, dstreg2;
7697 srcreg1 = translate_rreg (SD_, RM1);
7698 dstreg1 = translate_rreg (SD_, RN1);
7699 dstreg2 = translate_rreg (SD_, RN2);
7701 if (State.regs[srcreg1] >= 0x7fff)
7702 State.regs[dstreg1] = 0x7fff;
7703 else if (State.regs[srcreg1] <= 0xffff8000)
7704 State.regs[dstreg1] = 0xffff8000;
7706 State.regs[dstreg1] = State.regs[srcreg1];
7708 State.regs[dstreg2] -= EXTEND4 (IMM4);
7711 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
7712 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7716 int srcreg1, srcreg2, dstreg1, dstreg2;
7719 srcreg1 = translate_rreg (SD_, RM1);
7720 srcreg2 = translate_rreg (SD_, RM2);
7721 dstreg1 = translate_rreg (SD_, RN1);
7722 dstreg2 = translate_rreg (SD_, RN2);
7724 if (State.regs[srcreg1] >= 0x7fff)
7725 State.regs[dstreg1] = 0x7fff;
7726 else if (State.regs[srcreg1] <= 0xffff8000)
7727 State.regs[dstreg1] = 0xffff8000;
7729 State.regs[dstreg1] = State.regs[srcreg1];
7731 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7734 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
7735 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7739 int srcreg1, dstreg1, dstreg2;
7742 srcreg1 = translate_rreg (SD_, RM1);
7743 dstreg1 = translate_rreg (SD_, RN1);
7744 dstreg2 = translate_rreg (SD_, RN2);
7746 if (State.regs[srcreg1] >= 0x7fff)
7747 State.regs[dstreg1] = 0x7fff;
7748 else if (State.regs[srcreg1] <= 0xffff8000)
7749 State.regs[dstreg1] = 0xffff8000;
7751 State.regs[dstreg1] = State.regs[srcreg1];
7753 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7756 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
7757 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7761 int srcreg1, srcreg2, dstreg1, dstreg2;
7764 srcreg1 = translate_rreg (SD_, RM1);
7765 srcreg2 = translate_rreg (SD_, RM2);
7766 dstreg1 = translate_rreg (SD_, RN1);
7767 dstreg2 = translate_rreg (SD_, RN2);
7769 if (State.regs[srcreg1] >= 0x7fff)
7770 State.regs[dstreg1] = 0x7fff;
7771 else if (State.regs[srcreg1] <= 0xffff8000)
7772 State.regs[dstreg1] = 0xffff8000;
7774 State.regs[dstreg1] = State.regs[srcreg1];
7776 State.regs[dstreg2] = State.regs[srcreg2];
7779 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
7780 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
7784 int srcreg1, dstreg1, dstreg2;
7787 srcreg1 = translate_rreg (SD_, RM1);
7788 dstreg1 = translate_rreg (SD_, RN1);
7789 dstreg2 = translate_rreg (SD_, RN2);
7791 if (State.regs[srcreg1] >= 0x7fff)
7792 State.regs[dstreg1] = 0x7fff;
7793 else if (State.regs[srcreg1] <= 0xffff8000)
7794 State.regs[dstreg1] = 0xffff8000;
7796 State.regs[dstreg1] = State.regs[srcreg1];
7798 State.regs[dstreg2] = EXTEND4 (IMM4);
7801 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
7802 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
7806 int srcreg1, srcreg2, dstreg1, dstreg2;
7810 srcreg1 = translate_rreg (SD_, RM1);
7811 srcreg2 = translate_rreg (SD_, RM2);
7812 dstreg1 = translate_rreg (SD_, RN1);
7813 dstreg2 = translate_rreg (SD_, RN2);
7815 if (State.regs[srcreg1] >= 0x7fff)
7816 State.regs[dstreg1] = 0x7fff;
7817 else if (State.regs[srcreg1] <= 0xffff8000)
7818 State.regs[dstreg1] = 0xffff8000;
7820 State.regs[dstreg1] = State.regs[srcreg1];
7822 temp = State.regs[dstreg2];
7823 temp >>= State.regs[srcreg2];
7824 State.regs[dstreg2] = temp;
7827 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
7828 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
7832 int srcreg1, dstreg1, dstreg2;
7836 srcreg1 = translate_rreg (SD_, RM1);
7837 dstreg1 = translate_rreg (SD_, RN1);
7838 dstreg2 = translate_rreg (SD_, RN2);
7840 if (State.regs[srcreg1] >= 0x7fff)
7841 State.regs[dstreg1] = 0x7fff;
7842 else if (State.regs[srcreg1] <= 0xffff8000)
7843 State.regs[dstreg1] = 0xffff8000;
7845 State.regs[dstreg1] = State.regs[srcreg1];
7847 temp = State.regs[dstreg2];
7849 State.regs[dstreg2] = temp;
7852 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
7853 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
7857 int srcreg1, srcreg2, dstreg1, dstreg2;
7860 srcreg1 = translate_rreg (SD_, RM1);
7861 srcreg2 = translate_rreg (SD_, RM2);
7862 dstreg1 = translate_rreg (SD_, RN1);
7863 dstreg2 = translate_rreg (SD_, RN2);
7865 if (State.regs[srcreg1] >= 0x7fff)
7866 State.regs[dstreg1] = 0x7fff;
7867 else if (State.regs[srcreg1] <= 0xffff8000)
7868 State.regs[dstreg1] = 0xffff8000;
7870 State.regs[dstreg1] = State.regs[srcreg1];
7872 State.regs[dstreg2] >>= State.regs[srcreg2];
7875 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
7876 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
7880 int srcreg1, dstreg1, dstreg2;
7884 srcreg1 = translate_rreg (SD_, RM1);
7885 dstreg1 = translate_rreg (SD_, RN1);
7886 dstreg2 = translate_rreg (SD_, RN2);
7888 if (State.regs[srcreg1] >= 0x7fff)
7889 State.regs[dstreg1] = 0x7fff;
7890 else if (State.regs[srcreg1] <= 0xffff8000)
7891 State.regs[dstreg1] = 0xffff8000;
7893 State.regs[dstreg1] = State.regs[srcreg1];
7895 State.regs[dstreg2] >>= IMM4;
7899 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
7900 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
7904 int srcreg1, srcreg2, dstreg1, dstreg2;
7907 srcreg1 = translate_rreg (SD_, RM1);
7908 srcreg2 = translate_rreg (SD_, RM2);
7909 dstreg1 = translate_rreg (SD_, RN1);
7910 dstreg2 = translate_rreg (SD_, RN2);
7912 if (State.regs[srcreg1] >= 0x7fff)
7913 State.regs[dstreg1] = 0x7fff;
7914 else if (State.regs[srcreg1] <= 0xffff8000)
7915 State.regs[dstreg1] = 0xffff8000;
7917 State.regs[dstreg1] = State.regs[srcreg1];
7919 State.regs[dstreg2] <<= State.regs[srcreg2];
7922 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
7923 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
7927 int srcreg1, dstreg1, dstreg2;
7931 srcreg1 = translate_rreg (SD_, RM1);
7932 dstreg1 = translate_rreg (SD_, RN1);
7933 dstreg2 = translate_rreg (SD_, RN2);
7935 if (State.regs[srcreg1] >= 0x7fff)
7936 State.regs[dstreg1] = 0x7fff;
7937 else if (State.regs[srcreg1] <= 0xffff8000)
7938 State.regs[dstreg1] = 0xffff8000;
7940 State.regs[dstreg1] = State.regs[srcreg1];
7942 State.regs[dstreg2] <<= IMM4;
7945 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
7946 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
7953 srcreg = translate_rreg (SD_, RM);
7954 dstreg = translate_rreg (SD_, RN);
7956 State.regs[dstreg] = load_word (State.regs[srcreg]);
7957 State.regs[srcreg] += EXTEND4 (IMM4);
7959 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
7961 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
7966 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
7967 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
7974 srcreg = translate_rreg (SD_, RM);
7975 dstreg = translate_rreg (SD_, RN);
7977 State.regs[dstreg] = load_word (State.regs[srcreg]);
7978 State.regs[srcreg] += EXTEND4 (IMM4);
7981 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
7983 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
7988 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
7989 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
7996 srcreg = translate_rreg (SD_, RM);
7997 dstreg = translate_rreg (SD_, RN);
7999 State.regs[dstreg] = load_word (State.regs[srcreg]);
8000 State.regs[srcreg] += EXTEND4 (IMM4);
8002 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8004 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8009 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8010 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
8017 srcreg = translate_rreg (SD_, RM);
8018 dstreg = translate_rreg (SD_, RN);
8020 State.regs[dstreg] = load_word (State.regs[srcreg]);
8021 State.regs[srcreg] += EXTEND4 (IMM4);
8024 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8026 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8031 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8032 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
8039 srcreg = translate_rreg (SD_, RM);
8040 dstreg = translate_rreg (SD_, RN);
8042 State.regs[dstreg] = load_word (State.regs[srcreg]);
8043 State.regs[srcreg] += EXTEND4 (IMM4);
8047 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8052 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8053 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
8060 srcreg = translate_rreg (SD_, RM);
8061 dstreg = translate_rreg (SD_, RN);
8063 State.regs[dstreg] = load_word (State.regs[srcreg]);
8064 State.regs[srcreg] += EXTEND4 (IMM4);
8066 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8068 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8073 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8074 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
8081 srcreg = translate_rreg (SD_, RM);
8082 dstreg = translate_rreg (SD_, RN);
8084 State.regs[dstreg] = load_word (State.regs[srcreg]);
8085 State.regs[srcreg] += EXTEND4 (IMM4);
8089 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8094 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8095 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
8102 srcreg = translate_rreg (SD_, RM);
8103 dstreg = translate_rreg (SD_, RN);
8105 State.regs[dstreg] = load_word (State.regs[srcreg]);
8106 State.regs[srcreg] += EXTEND4 (IMM4);
8108 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8110 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8115 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8116 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
8123 srcreg = translate_rreg (SD_, RM);
8124 dstreg = translate_rreg (SD_, RN);
8126 State.regs[dstreg] = load_word (State.regs[srcreg]);
8127 State.regs[srcreg] += EXTEND4 (IMM4);
8131 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8136 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8137 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
8144 srcreg = translate_rreg (SD_, RM);
8145 dstreg = translate_rreg (SD_, RN);
8147 State.regs[dstreg] = load_word (State.regs[srcreg]);
8148 State.regs[srcreg] += EXTEND4 (IMM4);
8152 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8157 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8158 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
8165 srcreg = translate_rreg (SD_, RM);
8166 dstreg = translate_rreg (SD_, RN);
8168 State.regs[dstreg] = load_word (State.regs[srcreg]);
8169 State.regs[srcreg] += EXTEND4 (IMM4);
8171 State.regs[REG_PC] = State.regs[REG_LAR] - 4;