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* am33.igen (translate_rreg): New function. Use it as appropriate.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // Helper:
2 //
3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
6 //
7 //
8
9 :function:::int:translate_rreg:int rreg
10 {
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20 }
21
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
24 "mov"
25 *am33
26 {
27 PC = cia;
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
29 }
30
31
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
34 "mov"
35 *am33
36 {
37 PC = cia;
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
39 }
40
41
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
44 "mov"
45 *am33
46 {
47 PC = cia;
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
49 }
50
51
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
54 "mov"
55 *am33
56 {
57 PC = cia;
58 State.regs[REG_A0 + AN0] = PC;
59 }
60
61
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
64 "mov"
65 *am33
66 {
67 PC = cia;
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
69 }
70
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
73 "mov"
74 *am33
75 {
76 PC = cia;
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
78 }
79
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
82 "mov"
83 *am33
84 {
85 PC = cia;
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
87 }
88
89
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
92 "syscall"
93 *am33
94 {
95 unsigned int sp, next_pc;
96
97 PC = cia;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
103 nia = PC;
104 }
105
106
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
109 "mov"
110 *am33
111 {
112 PC = cia;
113 State.regs[REG_D0 + DN0] = PSW;
114 }
115
116
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
119 "mov"
120 *am33
121 {
122 PC = cia;
123 PSW = State.regs[REG_D0 + DM1];
124 }
125
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
128 "mov"
129 *am33
130 {
131 int destreg = translate_rreg (SD_, RN0);
132
133 PC = cia;
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
135 }
136
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
139 "mov"
140 *am33
141 {
142 int destreg = translate_rreg (SD_, RN0);
143
144 PC = cia;
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
146 }
147
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
150 "mov"
151 *am33
152 {
153 int destreg = translate_rreg (SD_, RM1);
154
155 PC = cia;
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
157 }
158
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
161 "mov"
162 *am33
163 {
164 int destreg = translate_rreg (SD_, RM1);
165
166 PC = cia;
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
168 }
169
170
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
173 "movm"
174 *am33
175 {
176 unsigned long usp = State.regs[REG_USP];
177 unsigned long mask;
178
179 PC = cia;
180 mask = REGS;
181
182 if (mask & 0x8)
183 {
184 usp += 4;
185 State.regs[REG_LAR] = load_word (usp);
186 usp += 4;
187 State.regs[REG_LIR] = load_word (usp);
188 usp += 4;
189 State.regs[REG_MDR] = load_word (usp);
190 usp += 4;
191 State.regs[REG_A0 + 1] = load_word (usp);
192 usp += 4;
193 State.regs[REG_A0] = load_word (usp);
194 usp += 4;
195 State.regs[REG_D0 + 1] = load_word (usp);
196 usp += 4;
197 State.regs[REG_D0] = load_word (usp);
198 usp += 4;
199 }
200
201 if (mask & 0x10)
202 {
203 State.regs[REG_A0 + 3] = load_word (usp);
204 usp += 4;
205 }
206
207 if (mask & 0x20)
208 {
209 State.regs[REG_A0 + 2] = load_word (usp);
210 usp += 4;
211 }
212
213 if (mask & 0x40)
214 {
215 State.regs[REG_D0 + 3] = load_word (usp);
216 usp += 4;
217 }
218
219 if (mask & 0x80)
220 {
221 State.regs[REG_D0 + 2] = load_word (usp);
222 usp += 4;
223 }
224
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
227 {
228 if (mask & 0x1)
229 {
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 usp += 16;
232 State.regs[REG_E0 + 1] = load_word (usp);
233 usp += 4;
234 State.regs[REG_E0 + 0] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x2)
239 {
240 State.regs[REG_E0 + 7] = load_word (usp);
241 usp += 4;
242 State.regs[REG_E0 + 6] = load_word (usp);
243 usp += 4;
244 State.regs[REG_E0 + 5] = load_word (usp);
245 usp += 4;
246 State.regs[REG_E0 + 4] = load_word (usp);
247 usp += 4;
248 }
249
250 if (mask & 0x4)
251 {
252 State.regs[REG_E0 + 3] = load_word (usp);
253 usp += 4;
254 State.regs[REG_E0 + 2] = load_word (usp);
255 usp += 4;
256 }
257 }
258 /* end-sanitize-am33 */
259
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
262 }
263
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
266 "movm"
267 *am33
268 {
269 unsigned long usp = State.regs[REG_USP];
270 unsigned long mask;
271
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
273 {
274 if (mask & 0x4)
275 {
276 usp -= 4;
277 store_word (usp, State.regs[REG_E0 + 2]);
278 usp -= 4;
279 store_word (usp, State.regs[REG_E0 + 3]);
280 }
281
282 if (mask & 0x2)
283 {
284 usp -= 4;
285 store_word (usp, State.regs[REG_E0 + 4]);
286 usp -= 4;
287 store_word (usp, State.regs[REG_E0 + 5]);
288 usp -= 4;
289 store_word (usp, State.regs[REG_E0 + 6]);
290 usp -= 4;
291 store_word (usp, State.regs[REG_E0 + 7]);
292 }
293
294 if (mask & 0x1)
295 {
296 usp -= 4;
297 store_word (usp, State.regs[REG_E0 + 0]);
298 usp -= 4;
299 store_word (usp, State.regs[REG_E0 + 1]);
300 usp -= 16;
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
302 }
303 }
304 /* end-sanitize-am33 */
305
306 if (mask & 0x80)
307 {
308 usp -= 4;
309 store_word (usp, State.regs[REG_D0 + 2]);
310 }
311
312 if (mask & 0x40)
313 {
314 usp -= 4;
315 store_word (usp, State.regs[REG_D0 + 3]);
316 }
317
318 if (mask & 0x20)
319 {
320 usp -= 4;
321 store_word (usp, State.regs[REG_A0 + 2]);
322 }
323
324 if (mask & 0x10)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_A0 + 3]);
328 }
329
330 if (mask & 0x8)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0]);
334 usp -= 4;
335 store_word (usp, State.regs[REG_D0 + 1]);
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0]);
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 1]);
340 usp -= 4;
341 store_word (usp, State.regs[REG_MDR]);
342 usp -= 4;
343 store_word (usp, State.regs[REG_LIR]);
344 usp -= 4;
345 store_word (usp, State.regs[REG_LAR]);
346 usp -= 4;
347 }
348
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
351 }
352
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
355 "and"
356 *am33
357 {
358 PC = cia;
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
360 }
361
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
364 "or"
365 *am33
366 {
367 PC = cia;
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
369 }
370
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
373 "mov"
374 *am33
375 {
376 int srcreg, dstreg;
377
378 PC = cia;
379
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
383 }
384
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
387 "mov"
388 *am33
389 {
390 int srcreg;
391
392 PC = cia;
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
396 else
397 State.regs[REG_MDR] = 0;
398 }
399
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
402 "extb"
403 *am33
404 {
405 int srcreg, dstreg;
406
407 PC = cia;
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
411 }
412
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
415 "extbu"
416 *am33
417 {
418 int srcreg, dstreg;
419
420 PC = cia;
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
424 }
425
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
428 "exth"
429 *am33
430 {
431 int srcreg, dstreg;
432
433 PC = cia;
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
437 }
438
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
441 "exthu"
442 *am33
443 {
444 int srcreg, dstreg;
445
446 PC = cia;
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
450 }
451
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
454 "clr"
455 *am33
456 {
457 int dstreg;
458
459 PC = cia;
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
462 PSW |= PSW_Z;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
464 }
465
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
468 "add"
469 *am33
470 {
471 int srcreg, dstreg;
472
473 PC = cia;
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
477 }
478
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
481 "addc"
482 *am33
483 {
484 int srcreg, dstreg;
485 int z, c, n, v;
486 unsigned long reg1, reg2, sum;
487
488 PC = cia;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
491
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
496
497 z = (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
502
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
506 }
507
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
510 "sub"
511 *am33
512 {
513 int srcreg, dstreg;
514
515 PC = cia;
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
519 }
520
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
523 "subc"
524 *am33
525 {
526 int srcreg, dstreg;
527 int z, c, n, v;
528 unsigned long reg1, reg2, difference;
529
530 PC = cia;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
533
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
538
539 z = (difference == 0);
540 n = (difference & 0x80000000);
541 c = (reg1 > reg2);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
544
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
548 }
549
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
552 "inc"
553 *am33
554 {
555 int dstreg;
556
557 PC = cia;
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
560 }
561
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
564 "inc4"
565 *am33
566 {
567 int dstreg;
568
569 PC = cia;
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
572 }
573
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
576 "cmp"
577 *am33
578 {
579 int srcreg1, srcreg2;
580
581 PC = cia;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
585 }
586
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
589 "mov"
590 *am33
591 {
592 int dstreg;
593
594 PC = cia;
595 dstreg = translate_rreg (SD_, RN0);
596
597 if (XRM2 == 0)
598 {
599 State.regs[dstreg] = State.regs[REG_SP];
600 }
601 else
602 abort ();
603 }
604
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
607 "mov"
608 *am33
609 {
610 int srcreg;
611
612 PC = cia;
613 srcreg = translate_rreg (SD_, RM2);
614
615 if (XRN0 == 0)
616 {
617 State.regs[REG_SP] = State.regs[srcreg];
618 }
619 else
620 abort ();
621 }
622
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
625 "and"
626 *am33
627 {
628 int srcreg, dstreg;
629 int z, n;
630
631 PC = cia;
632
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
635
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
641 }
642
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
645 "or"
646 *am33
647 {
648 int srcreg, dstreg;
649 int z, n;
650
651 PC = cia;
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
654
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
660 }
661
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
664 "xor"
665 *am33
666 {
667 int srcreg, dstreg;
668 int z, n;
669
670 PC = cia;
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
673
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
679 }
680
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
683 "not"
684 *am33
685 {
686 int dstreg;
687 int z, n;
688
689 PC = cia;
690 dstreg = translate_rreg (SD_, RN0);
691
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
697 }
698
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
701 "asr"
702 *am33
703 {
704 int srcreg, dstreg;
705 long temp;
706 int c, z, n;
707
708 PC = cia;
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
711
712 temp = State.regs[dstreg];
713 c = temp & 1;
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
720 }
721
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
724 "lsr"
725 *am33
726 {
727 int srcreg, dstreg;
728 int z, n, c;
729
730 PC = cia;
731
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
734
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
741 }
742
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
745 "asl"
746 *am33
747 {
748 int srcreg, dstreg;
749 int z, n;
750
751 PC = cia;
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
754
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
760 }
761
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
764 "asl2"
765 *am33
766 {
767 int dstreg;
768 int n, z;
769
770 PC = cia;
771 dstreg = translate_rreg (SD_, RN0);
772
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
778 }
779
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
782 "ror"
783 *am33
784 {
785 int dstreg;
786 int c, n, z;
787 unsigned long value;
788
789 PC = cia;
790 dstreg = translate_rreg (SD_, RN0);
791
792 value = State.regs[dstreg];
793 c = (value & 0x1);
794
795 value >>= 1;
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
798 z = (value == 0);
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
802 }
803
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
806 "rol"
807 *am33
808 {
809 int dstreg;
810 int c, n, z;
811 unsigned long value;
812
813 PC = cia;
814 dstreg = translate_rreg (SD_, RN0);
815
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
818
819 value <<= 1;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
822 z = (value == 0);
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
826 }
827
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
830 "mul"
831 *am33
832 {
833 int srcreg, dstreg;
834 unsigned long long temp;
835 int n, z;
836
837 PC = cia;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
840
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849 }
850
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
853 "mulu"
854 *am33
855 {
856 int srcreg, dstreg;
857 unsigned long long temp;
858 int n, z;
859
860 PC = cia;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
863
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
872 }
873
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
876 "div"
877 *am33
878 {
879 int srcreg, dstreg;
880 long long temp;
881 int n, z;
882
883 PC = cia;
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
886
887 temp = State.regs[REG_MDR];
888 temp <<= 32;
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (long)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
897 }
898
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
901 "divu"
902 *am33
903 {
904 int srcreg, dstreg;
905 unsigned long long temp;
906 int n, z;
907
908 PC = cia;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
911
912 temp = State.regs[REG_MDR];
913 temp <<= 32;
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
922 }
923
924
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
927 "mov"
928 *am33
929 {
930 int srcreg, dstreg;
931
932 PC = cia;
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
936 }
937
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
940 "mov"
941 *am33
942 {
943 int srcreg, dstreg;
944
945 PC = cia;
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
949 }
950
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
953 "movbu"
954 *am33
955 {
956 int srcreg, dstreg;
957
958 PC = cia;
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
962 }
963
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
966 "movbu"
967 *am33
968 {
969 int srcreg, dstreg;
970
971 PC = cia;
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
975 }
976
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
979 "movhu"
980 *am33
981 {
982 int srcreg, dstreg;
983
984 PC = cia;
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
988 }
989
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
992 "movhu"
993 *am33
994 {
995 int srcreg, dstreg;
996
997 PC = cia;
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1001 }
1002
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1005 "mov"
1006 *am33
1007 {
1008 int srcreg, dstreg;
1009
1010 PC = cia;
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1015 }
1016
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1019 "mov"
1020 *am33
1021 {
1022 int srcreg, dstreg;
1023
1024 PC = cia;
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1029 }
1030
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1033 "mov"
1034 *am33
1035 {
1036 int dstreg;
1037
1038 PC = cia;
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1041 }
1042
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1045 "mov"
1046 *am33
1047 {
1048 int srcreg;
1049
1050 PC = cia;
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1053 }
1054
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1057 "movbu"
1058 *am33
1059 {
1060 int dstreg;
1061
1062 PC = cia;
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1065 }
1066
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1069 "movbu"
1070 *am33
1071 {
1072 int srcreg;
1073
1074 PC = cia;
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1077 }
1078
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1081 "movhu"
1082 *am33
1083 {
1084 int dstreg;
1085
1086 PC = cia;
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1089 }
1090
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1093 "movhu"
1094 *am33
1095 {
1096 int srcreg;
1097
1098 PC = cia;
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1101 }
1102
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1105 "movhu"
1106 *am33
1107 {
1108 int srcreg, dstreg;
1109
1110 PC = cia;
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1115 }
1116
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1119 "movhu"
1120 *am33
1121 {
1122 int srcreg, dstreg;
1123
1124 PC = cia;
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1129 }
1130
1131
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1134 "mac"
1135 *am33
1136 {
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1139 int c, v;
1140
1141 PC = cia;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1144
1145 temp = ((signed64)State.regs[srcreg2]
1146 * (signed64)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1150 temp >>= 32;
1151 temp &= 0xffffffff;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1156 if (v)
1157 State.regs[REG_MCVF] = 1;
1158 }
1159
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1162 "macu"
1163 *am33
1164 {
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1167 int c, v;
1168
1169 PC = cia;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1172
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1178 temp >>= 32;
1179 temp &= 0xffffffff;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1184 if (v)
1185 State.regs[REG_MCVF] = 1;
1186 }
1187
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1190 "macb"
1191 *am33
1192 {
1193 int srcreg1, srcreg2;
1194 long temp, sum;
1195 int v;
1196
1197 PC = cia;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1200
1201 temp = ((signed32)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1207 if (v)
1208 State.regs[REG_MCVF] = 1;
1209 }
1210
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1213 "macbu"
1214 *am33
1215 {
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1218 int v;
1219
1220 PC = cia;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1223
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1230 if (v)
1231 State.regs[REG_MCVF] = 1;
1232 }
1233
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1236 "mach"
1237 *am33
1238 {
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1241 int c, v;
1242
1243 PC = cia;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1246
1247 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1252 temp >>= 32;
1253 temp &= 0xffffffff;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1258 if (v)
1259 State.regs[REG_MCVF] = 1;
1260 }
1261
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1264 "machu"
1265 *am33
1266 {
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1269 int c, v;
1270
1271 PC = cia;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1274
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1280 temp >>= 32;
1281 temp &= 0xffffffff;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1286 if (v)
1287 State.regs[REG_MCVF] = 1;
1288 }
1289
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1292 "dmach"
1293 *am33
1294 {
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1297 int v;
1298
1299 PC = cia;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1302
1303 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1311 if (v)
1312 State.regs[REG_MCVF] = 1;
1313 }
1314
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1317 "dmachu"
1318 *am33
1319 {
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1322 int v;
1323
1324 PC = cia;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1327
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1336 if (v)
1337 State.regs[REG_MCVF] = 1;
1338 }
1339
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1342 "dmulh"
1343 *am33
1344 {
1345 int srcreg, dstreg;
1346 long temp;
1347
1348 PC = cia;
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1351
1352 temp = ((signed32)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1358 }
1359
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1362 "dmachu"
1363 *am33
1364 {
1365 int srcreg, dstreg;
1366 unsigned long temp;
1367
1368 PC = cia;
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1371
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1378 }
1379
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1382 "sat16"
1383 *am33
1384 {
1385 int srcreg, dstreg;
1386 int value;
1387
1388 PC = cia;
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1391
1392 value = State.regs[srcreg];
1393
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1398 else
1399 State.regs[dstreg] = value;
1400 }
1401
1402 // ??? mcste
1403
1404 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1405 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1406 "swap"
1407 *am33
1408 {
1409 int srcreg, dstreg;
1410
1411 PC = cia;
1412 srcreg = translate_rreg (SD_, RM2);
1413 dstreg = translate_rreg (SD_, RN0);
1414
1415 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1416 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1417 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1418 | ((State.regs[srcreg] >> 24) & 0xff));
1419 }
1420
1421 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1422 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1423 "swaph"
1424 *am33
1425 {
1426 int srcreg, dstreg;
1427
1428 PC = cia;
1429 srcreg = translate_rreg (SD_, RM2);
1430 dstreg = translate_rreg (SD_, RN0);
1431
1432 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1433 | ((State.regs[srcreg] >> 8) & 0xff)
1434 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1435 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1436 }
1437
1438 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1439 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1440 "swhw"
1441 *am33
1442 {
1443 int srcreg, dstreg;
1444
1445 PC = cia;
1446 srcreg = translate_rreg (SD_, RM2);
1447 dstreg = translate_rreg (SD_, RN0);
1448
1449 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1450 | ((State.regs[srcreg] >> 16) & 0xffff));
1451 }
1452
1453 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1454 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1455 "bsch"
1456 *am33
1457 {
1458 int temp, c, i;
1459 int srcreg, dstreg;
1460 int start;
1461
1462 PC = cia;
1463 srcreg = translate_rreg (SD_, RM2);
1464 dstreg = translate_rreg (SD_, RN0);
1465
1466 temp = State.regs[srcreg];
1467 start = (State.regs[dstreg] & 0x1f) - 1;
1468 if (start == -1)
1469 start = 31;
1470
1471 for (i = start; i >= 0; i--)
1472 {
1473 if (temp & (1 << i))
1474 {
1475 c = 1;
1476 State.regs[dstreg] = i;
1477 break;
1478 }
1479 }
1480
1481 if (i < 0)
1482 {
1483 c = 0;
1484 State.regs[dstreg] = 0;
1485 }
1486 PSW &= ~(PSW_C);
1487 PSW |= (c ? PSW_C : 0);
1488 }
1489
1490
1491 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1492 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1493 "mov"
1494 *am33
1495 {
1496 int dstreg;
1497
1498 PC = cia;
1499 dstreg = translate_rreg (SD_, RN0);
1500 State.regs[dstreg] = EXTEND8 (IMM8);
1501 }
1502
1503 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1504 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1505 "movu"
1506 *am33
1507 {
1508 int dstreg;
1509
1510 PC = cia;
1511 dstreg = translate_rreg (SD_, RN0);
1512 State.regs[dstreg] = IMM8 & 0xff;
1513 }
1514
1515 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1516 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1517 "add"
1518 *am33
1519 {
1520 int dstreg;
1521
1522 PC = cia;
1523 dstreg = translate_rreg (SD_, RN0);
1524 genericAdd (EXTEND8 (IMM8), dstreg);
1525 }
1526
1527 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1528 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1529 "addc"
1530 *am33
1531 {
1532 int dstreg, imm;
1533 int z, c, n, v;
1534 unsigned long reg1, reg2, sum;
1535
1536 PC = cia;
1537 dstreg = translate_rreg (SD_, RN0);
1538
1539 imm = EXTEND8 (IMM8);
1540 reg2 = State.regs[dstreg];
1541 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1542 State.regs[dstreg] = sum;
1543
1544 z = (sum == 0);
1545 n = (sum & 0x80000000);
1546 c = (sum < imm) || (sum < reg2);
1547 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1548 && (reg2 & 0x80000000) != (sum & 0x80000000));
1549
1550 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1551 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1552 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1553 }
1554
1555 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1556 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1557 "sub"
1558 *am33
1559 {
1560 int dstreg;
1561
1562 PC = cia;
1563 dstreg = translate_rreg (SD_, RN0);
1564
1565 genericSub (EXTEND8 (IMM8), dstreg);
1566 }
1567
1568 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1569 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1570 "subc"
1571 *am33
1572 {
1573 int imm, dstreg;
1574 int z, c, n, v;
1575 unsigned long reg1, reg2, difference;
1576
1577 PC = cia;
1578 dstreg = translate_rreg (SD_, RN0);
1579
1580 imm = EXTEND8 (IMM8);
1581 reg2 = State.regs[dstreg];
1582 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1583 State.regs[dstreg] = difference;
1584
1585 z = (difference == 0);
1586 n = (difference & 0x80000000);
1587 c = (imm > reg2);
1588 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1589 && (reg2 & 0x80000000) != (difference & 0x80000000));
1590
1591 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1593 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1594 }
1595
1596 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1597 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1598 "cmp"
1599 *am33
1600 {
1601 int srcreg;
1602
1603 PC = cia;
1604 srcreg = translate_rreg (SD_, RN0);
1605 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1606 }
1607
1608 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1609 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1610 "mov"
1611 *am33
1612 {
1613 int dstreg;
1614
1615 PC = cia;
1616
1617 if (XRN0 == 0)
1618 State.regs[REG_SP] = EXTEND8 (IMM8);
1619 else
1620 abort ();
1621 }
1622
1623 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1624 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1625 "and"
1626 *am33
1627 {
1628 int dstreg;
1629 int z, n;
1630
1631 PC = cia;
1632 dstreg = translate_rreg (SD_, RN0);
1633
1634 State.regs[dstreg] &= (IMM8 & 0xff);
1635 z = (State.regs[dstreg] == 0);
1636 n = (State.regs[dstreg] & 0x80000000) != 0;
1637 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1638 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1639 }
1640
1641 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1642 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1643 "or"
1644 *am33
1645 {
1646 int dstreg;
1647 int z, n;
1648
1649 PC = cia;
1650 dstreg = translate_rreg (SD_, RN0);
1651
1652 State.regs[dstreg] |= (IMM8 & 0xff);
1653 z = (State.regs[dstreg] == 0);
1654 n = (State.regs[dstreg] & 0x80000000) != 0;
1655 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1656 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1657 }
1658
1659 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1660 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1661 "xor"
1662 *am33
1663 {
1664 int dstreg;
1665 int z, n;
1666
1667 PC = cia;
1668 dstreg = translate_rreg (SD_, RN0);
1669
1670 State.regs[dstreg] ^= (IMM8 & 0xff);
1671 z = (State.regs[dstreg] == 0);
1672 n = (State.regs[dstreg] & 0x80000000) != 0;
1673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1674 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1675 }
1676
1677 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1678 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1679 "asr"
1680 *am33
1681 {
1682 int dstreg;
1683 long temp;
1684 int c, z, n;
1685
1686 PC = cia;
1687 dstreg = translate_rreg (SD_, RN0);
1688
1689 temp = State.regs[dstreg];
1690 c = temp & 1;
1691 temp >>= (IMM8 & 0xff);
1692 State.regs[dstreg] = temp;
1693 z = (State.regs[dstreg] == 0);
1694 n = (State.regs[dstreg] & 0x80000000) != 0;
1695 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1697 }
1698
1699 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1700 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1701 "lsr"
1702 *am33
1703 {
1704 int dstreg;
1705 int z, n, c;
1706
1707 PC = cia;
1708 dstreg = translate_rreg (SD_, RN0);
1709
1710 c = State.regs[dstreg] & 1;
1711 State.regs[dstreg] >>= (IMM8 & 0xff);
1712 z = (State.regs[dstreg] == 0);
1713 n = (State.regs[dstreg] & 0x80000000) != 0;
1714 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1715 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1716 }
1717
1718 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1719 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1720 "asl"
1721 *am33
1722 {
1723 int srcreg, dstreg;
1724 int z, n;
1725
1726 PC = cia;
1727 dstreg = translate_rreg (SD_, RN0);
1728
1729 State.regs[dstreg] <<= (IMM8 & 0xff);
1730 z = (State.regs[dstreg] == 0);
1731 n = (State.regs[dstreg] & 0x80000000) != 0;
1732 PSW &= ~(PSW_Z | PSW_N);
1733 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1734 }
1735
1736 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1737 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1738 "mul"
1739 *am33
1740 {
1741 int dstreg;
1742 unsigned long long temp;
1743 int z, n;
1744
1745 PC = cia;
1746 dstreg = translate_rreg (SD_, RN0);
1747
1748 temp = ((signed64)(signed32)State.regs[dstreg]
1749 * (signed64)(signed32)EXTEND8 (IMM8));
1750 State.regs[dstreg] = temp & 0xffffffff;
1751 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1752 z = (State.regs[dstreg] == 0);
1753 n = (State.regs[dstreg] & 0x80000000) != 0;
1754 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1755 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1756 }
1757
1758 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1759 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1760 "mulu"
1761 *am33
1762 {
1763 int dstreg;
1764 unsigned long long temp;
1765 int z, n;
1766
1767 PC = cia;
1768 dstreg = translate_rreg (SD_, RN0);
1769
1770 temp = ((unsigned64)State.regs[dstreg]
1771 * (unsigned64)(IMM8 & 0xff));
1772 State.regs[dstreg] = temp & 0xffffffff;
1773 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1774 z = (State.regs[dstreg] == 0);
1775 n = (State.regs[dstreg] & 0x80000000) != 0;
1776 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1778 }
1779
1780 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1781 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1782 "btst"
1783 *am33
1784 {
1785 int srcreg;
1786
1787 PC = cia;
1788 srcreg = translate_rreg (SD_, RM0);
1789 genericBtst(IMM8, State.regs[srcreg]);
1790 }
1791
1792
1793 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1794 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1795 "mov"
1796 *am33
1797 {
1798 int srcreg, dstreg;
1799
1800 PC = cia;
1801 srcreg = translate_rreg (SD_, RM0);
1802 dstreg = translate_rreg (SD_, RN2);
1803 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1804 }
1805
1806 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1807 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1808 "mov"
1809 {
1810 int srcreg, dstreg;
1811
1812 PC = cia;
1813 srcreg = translate_rreg (SD_, RM2);
1814 dstreg = translate_rreg (SD_, RN0);
1815 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1816 }
1817
1818 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1819 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1820 "movbu"
1821 {
1822 int srcreg, dstreg;
1823
1824 PC = cia;
1825 srcreg = translate_rreg (SD_, RM0);
1826 dstreg = translate_rreg (SD_, RN2);
1827 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1828 }
1829
1830 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1831 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1832 "movbu"
1833 {
1834 int srcreg, dstreg;
1835
1836 PC = cia;
1837 srcreg = translate_rreg (SD_, RM2);
1838 dstreg = translate_rreg (SD_, RN0);
1839 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1840 }
1841
1842 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1843 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1844 "movhu"
1845 {
1846 int srcreg, dstreg;
1847
1848 PC = cia;
1849 srcreg = translate_rreg (SD_, RM0);
1850 dstreg = translate_rreg (SD_, RN2);
1851 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1852 }
1853
1854 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1855 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1856 "movhu"
1857 {
1858 int srcreg, dstreg;
1859
1860 PC = cia;
1861 srcreg = translate_rreg (SD_, RM2);
1862 dstreg = translate_rreg (SD_, RN0);
1863 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1864 }
1865
1866 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1867 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1868 "mov"
1869 *am33
1870 {
1871 int srcreg, dstreg;
1872
1873 PC = cia;
1874 srcreg = translate_rreg (SD_, RM0);
1875 dstreg = translate_rreg (SD_, RN2);
1876 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1877 State.regs[srcreg] += 4;
1878 }
1879
1880 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1881 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1882 "mov"
1883 {
1884 int srcreg, dstreg;
1885
1886 PC = cia;
1887 srcreg = translate_rreg (SD_, RM2);
1888 dstreg = translate_rreg (SD_, RN0);
1889 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1890 State.regs[dstreg] += 4;
1891 }
1892
1893
1894 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1895 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1896 "mov"
1897 {
1898 int dstreg;
1899
1900 PC = cia;
1901 dstreg = translate_rreg (SD_, RN2);
1902 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
1903 }
1904
1905 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
1906 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
1907 "mov"
1908 {
1909 int srcreg;
1910
1911 PC = cia;
1912 srcreg = translate_rreg (SD_, RM2);
1913 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
1914 }
1915
1916 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
1917 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
1918 "movbu"
1919 {
1920 int dstreg;
1921
1922 PC = cia;
1923 dstreg = translate_rreg (SD_, RN2);
1924 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
1925 }
1926
1927 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
1928 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
1929 "movbu"
1930 {
1931 int srcreg;
1932
1933 PC = cia;
1934 srcreg = translate_rreg (SD_, RM2);
1935 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
1936 }
1937
1938 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
1939 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
1940 "movhu"
1941 {
1942 int dstreg;
1943
1944 PC = cia;
1945 dstreg = translate_rreg (SD_, RN2);
1946 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
1947 }
1948
1949 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
1950 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
1951 "movhu"
1952 {
1953 int srcreg;
1954
1955 PC = cia;
1956 srcreg = translate_rreg (SD_, RM2);
1957 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
1958 }
1959
1960 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
1961 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
1962 "movhu"
1963 *am33
1964 {
1965 int srcreg, dstreg;
1966
1967 PC = cia;
1968 srcreg = translate_rreg (SD_, RM0);
1969 dstreg = translate_rreg (SD_, RN2);
1970 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1971 State.regs[srcreg] += 2;
1972 }
1973
1974 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
1975 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
1976 "movhu"
1977 {
1978 int srcreg, dstreg;
1979
1980 PC = cia;
1981 srcreg = translate_rreg (SD_, RM2);
1982 dstreg = translate_rreg (SD_, RN0);
1983 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1984 State.regs[dstreg] += 2;
1985 }
1986
1987
1988 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
1989 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
1990 "mac"
1991 {
1992 int srcreg;
1993 long long temp, sum;
1994 int c, v;
1995
1996 PC = cia;
1997 srcreg = translate_rreg (SD_, RN2);
1998
1999 temp = ((signed64)EXTEND8 (IMM8)
2000 * (signed64)State.regs[srcreg]);
2001 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2002 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2003 State.regs[REG_MCRL] = sum;
2004 temp >>= 32;
2005 temp &= 0xffffffff;
2006 sum = State.regs[REG_MCRH] + temp + c;
2007 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2008 && (temp & 0x80000000) != (sum & 0x80000000));
2009 State.regs[REG_MCRH] = sum;
2010 if (v)
2011 State.regs[REG_MCVF] = 1;
2012 }
2013
2014 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2015 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2016 "macu"
2017 {
2018 int srcreg;
2019 long long temp, sum;
2020 int c, v;
2021
2022 PC = cia;
2023 srcreg = translate_rreg (SD_, RN2);
2024
2025 temp = ((unsigned64) (IMM8)
2026 * (unsigned64)State.regs[srcreg]);
2027 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2028 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2029 State.regs[REG_MCRL] = sum;
2030 temp >>= 32;
2031 temp &= 0xffffffff;
2032 sum = State.regs[REG_MCRH] + temp + c;
2033 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2034 && (temp & 0x80000000) != (sum & 0x80000000));
2035 State.regs[REG_MCRH] = sum;
2036 if (v)
2037 State.regs[REG_MCVF] = 1;
2038 }
2039
2040 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2041 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2042 "macb"
2043 {
2044 int srcreg;
2045 long long temp, sum;
2046 int c, v;
2047
2048 PC = cia;
2049 srcreg = translate_rreg (SD_, RN2);
2050
2051 temp = ((signed64)EXTEND8 (IMM8)
2052 * (signed64)State.regs[srcreg] & 0xff);
2053 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2054 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2055 State.regs[REG_MCRL] = sum;
2056 temp >>= 32;
2057 temp &= 0xffffffff;
2058 sum = State.regs[REG_MCRH] + temp + c;
2059 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2060 && (temp & 0x80000000) != (sum & 0x80000000));
2061 State.regs[REG_MCRH] = sum;
2062 if (v)
2063 State.regs[REG_MCVF] = 1;
2064 }
2065
2066 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2067 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2068 "macbu"
2069 {
2070 int srcreg;
2071 long long temp, sum;
2072 int c, v;
2073
2074 PC = cia;
2075 srcreg = translate_rreg (SD_, RN2);
2076
2077 temp = ((unsigned64) (IMM8)
2078 * (unsigned64)State.regs[srcreg] & 0xff);
2079 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2080 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2081 State.regs[REG_MCRL] = sum;
2082 temp >>= 32;
2083 temp &= 0xffffffff;
2084 sum = State.regs[REG_MCRH] + temp + c;
2085 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2086 && (temp & 0x80000000) != (sum & 0x80000000));
2087 State.regs[REG_MCRH] = sum;
2088 if (v)
2089 State.regs[REG_MCVF] = 1;
2090 }
2091
2092 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2093 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2094 "mach"
2095 {
2096 int srcreg;
2097 long long temp, sum;
2098 int c, v;
2099
2100 PC = cia;
2101 srcreg = translate_rreg (SD_, RN2);
2102
2103 temp = ((signed64)EXTEND8 (IMM8)
2104 * (signed64)State.regs[srcreg] & 0xffff);
2105 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2106 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2107 State.regs[REG_MCRL] = sum;
2108 temp >>= 32;
2109 temp &= 0xffffffff;
2110 sum = State.regs[REG_MCRH] + temp + c;
2111 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2112 && (temp & 0x80000000) != (sum & 0x80000000));
2113 State.regs[REG_MCRH] = sum;
2114 if (v)
2115 State.regs[REG_MCVF] = 1;
2116 }
2117
2118 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2119 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2120 "machu"
2121 {
2122 int srcreg;
2123 long long temp, sum;
2124 int c, v;
2125
2126 PC = cia;
2127 srcreg = translate_rreg (SD_, RN2);
2128
2129 temp = ((unsigned64) (IMM8)
2130 * (unsigned64)State.regs[srcreg] & 0xffff);
2131 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2132 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2133 State.regs[REG_MCRL] = sum;
2134 temp >>= 32;
2135 temp &= 0xffffffff;
2136 sum = State.regs[REG_MCRH] + temp + c;
2137 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2138 && (temp & 0x80000000) != (sum & 0x80000000));
2139 State.regs[REG_MCRH] = sum;
2140 if (v)
2141 State.regs[REG_MCVF] = 1;
2142 }
2143
2144 // ??? mcste
2145
2146 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2147 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2148 "add"
2149 *am33
2150 {
2151 int z, c, n, v;
2152 unsigned long sum, source1, source2;
2153 int srcreg1, srcreg2, dstreg;
2154
2155 PC = cia;
2156 srcreg1 = translate_rreg (SD_, RM2);
2157 srcreg2 = translate_rreg (SD_, RN0);
2158 dstreg = translate_rreg (SD_, RD0);
2159
2160 source1 = State.regs[srcreg1];
2161 source2 = State.regs[srcreg2];
2162 sum = source1 + source2;
2163 State.regs[dstreg] = sum;
2164
2165 z = (sum == 0);
2166 n = (sum & 0x80000000);
2167 c = (sum < source1) || (sum < source2);
2168 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2169 && (source1 & 0x80000000) != (sum & 0x80000000));
2170
2171 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2172 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2173 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2174 }
2175
2176 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2177 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2178 "addc"
2179 *am33
2180 {
2181 int z, c, n, v;
2182 unsigned long sum, source1, source2;
2183 int srcreg1, srcreg2, dstreg;
2184
2185 PC = cia;
2186 srcreg1 = translate_rreg (SD_, RM2);
2187 srcreg2 = translate_rreg (SD_, RN0);
2188 dstreg = translate_rreg (SD_, RD0);
2189
2190 source1 = State.regs[srcreg1];
2191 source2 = State.regs[srcreg2];
2192 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2193 State.regs[dstreg] = sum;
2194
2195 z = (sum == 0);
2196 n = (sum & 0x80000000);
2197 c = (sum < source1) || (sum < source2);
2198 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2199 && (source1 & 0x80000000) != (sum & 0x80000000));
2200
2201 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2202 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2203 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2204 }
2205
2206 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2207 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2208 "sub"
2209 *am33
2210 {
2211 int z, c, n, v;
2212 unsigned long difference, source1, source2;
2213 int srcreg1, srcreg2, dstreg;
2214
2215 PC = cia;
2216 srcreg1 = translate_rreg (SD_, RM2);
2217 srcreg2 = translate_rreg (SD_, RN0);
2218 dstreg = translate_rreg (SD_, RD0);
2219
2220 source1 = State.regs[srcreg1];
2221 source2 = State.regs[srcreg2];
2222 difference = source2 - source1;
2223 State.regs[dstreg] = difference;
2224
2225 z = (difference == 0);
2226 n = (difference & 0x80000000);
2227 c = (source1 > source1);
2228 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2229 && (source1 & 0x80000000) != (difference & 0x80000000));
2230
2231 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2232 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2233 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2234 }
2235
2236 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2237 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2238 "subc"
2239 *am33
2240 {
2241 int z, c, n, v;
2242 unsigned long difference, source1, source2;
2243 int srcreg1, srcreg2, dstreg;
2244
2245 PC = cia;
2246 srcreg1 = translate_rreg (SD_, RM2);
2247 srcreg2 = translate_rreg (SD_, RN0);
2248 dstreg = translate_rreg (SD_, RD0);
2249
2250 source1 = State.regs[srcreg1];
2251 source2 = State.regs[srcreg2];
2252 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2253 State.regs[dstreg] = difference;
2254
2255 z = (difference == 0);
2256 n = (difference & 0x80000000);
2257 c = (source1 > source2);
2258 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2259 && (source1 & 0x80000000) != (difference & 0x80000000));
2260
2261 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2262 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2263 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2264 }
2265
2266 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2267 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2268 "and"
2269 *am33
2270 {
2271 int z, c, n, v;
2272 int srcreg1, srcreg2, dstreg;
2273
2274 PC = cia;
2275 srcreg1 = translate_rreg (SD_, RM2);
2276 srcreg2 = translate_rreg (SD_, RN0);
2277 dstreg = translate_rreg (SD_, RD0);
2278
2279 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2280
2281 z = (State.regs[dstreg] == 0);
2282 n = (State.regs[dstreg] & 0x80000000);
2283
2284 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2285 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2286 }
2287
2288 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2289 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2290 "or"
2291 *am33
2292 {
2293 int z, c, n, v;
2294 int srcreg1, srcreg2, dstreg;
2295
2296 PC = cia;
2297 srcreg1 = translate_rreg (SD_, RM2);
2298 srcreg2 = translate_rreg (SD_, RN0);
2299 dstreg = translate_rreg (SD_, RD0);
2300
2301 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2302
2303 z = (State.regs[dstreg] == 0);
2304 n = (State.regs[dstreg] & 0x80000000);
2305
2306 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2307 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2308 }
2309
2310 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2311 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2312 "xor"
2313 *am33
2314 {
2315 int z, c, n, v;
2316 int srcreg1, srcreg2, dstreg;
2317
2318 PC = cia;
2319 srcreg1 = translate_rreg (SD_, RM2);
2320 srcreg2 = translate_rreg (SD_, RN0);
2321 dstreg = translate_rreg (SD_, RD0);
2322
2323 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2324
2325 z = (State.regs[dstreg] == 0);
2326 n = (State.regs[dstreg] & 0x80000000);
2327
2328 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2329 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2330 }
2331
2332 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2333 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2334 "asr"
2335 *am33
2336 {
2337 int z, c, n, v;
2338 long temp;
2339 int srcreg1, srcreg2, dstreg;
2340
2341 PC = cia;
2342 srcreg1 = translate_rreg (SD_, RM2);
2343 srcreg2 = translate_rreg (SD_, RN0);
2344 dstreg = translate_rreg (SD_, RD0);
2345
2346 temp = State.regs[srcreg2];
2347 c = temp & 1;
2348 temp >>= State.regs[srcreg1];
2349 State.regs[dstreg] = temp;
2350
2351 z = (State.regs[dstreg] == 0);
2352 n = (State.regs[dstreg] & 0x80000000);
2353
2354 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2355 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2356 }
2357
2358 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2359 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2360 "lsr"
2361 *am33
2362 {
2363 int z, c, n, v;
2364 int srcreg1, srcreg2, dstreg;
2365
2366 PC = cia;
2367 srcreg1 = translate_rreg (SD_, RM2);
2368 srcreg2 = translate_rreg (SD_, RN0);
2369 dstreg = translate_rreg (SD_, RD0);
2370
2371 c = State.regs[srcreg2] & 1;
2372 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2373
2374 z = (State.regs[dstreg] == 0);
2375 n = (State.regs[dstreg] & 0x80000000);
2376
2377 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2378 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2379 }
2380
2381 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2382 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2383 "asl"
2384 *am33
2385 {
2386 int z, c, n, v;
2387 int srcreg1, srcreg2, dstreg;
2388
2389 PC = cia;
2390 srcreg1 = translate_rreg (SD_, RM2);
2391 srcreg2 = translate_rreg (SD_, RN0);
2392 dstreg = translate_rreg (SD_, RD0);
2393
2394 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2395
2396 z = (State.regs[dstreg] == 0);
2397 n = (State.regs[dstreg] & 0x80000000);
2398
2399 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2400 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2401 }
2402
2403 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2404 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2405 "mul"
2406 *am33
2407 {
2408 int srcreg1, srcreg2, dstreg1, dstreg2;
2409 signed long long temp;
2410
2411 PC = cia;
2412 srcreg1 = translate_rreg (SD_, RM2);
2413 srcreg2 = translate_rreg (SD_, RN0);
2414 dstreg1 = translate_rreg (SD_, RD0);
2415 dstreg2 = translate_rreg (SD_, RD2);
2416
2417 temp = ((signed64)(signed32)State.regs[srcreg1]
2418 * (signed64)(signed32)State.regs[srcreg2]);
2419 State.regs[dstreg1] = temp & 0xffffffff;
2420 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2421 }
2422
2423 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2424 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2425 "mulu"
2426 *am33
2427 {
2428 int srcreg1, srcreg2, dstreg1, dstreg2;
2429 signed long long temp;
2430
2431 PC = cia;
2432 srcreg1 = translate_rreg (SD_, RM2);
2433 srcreg2 = translate_rreg (SD_, RN0);
2434 dstreg1 = translate_rreg (SD_, RD0);
2435 dstreg2 = translate_rreg (SD_, RD2);
2436
2437 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
2438 * (unsigned64)(unsigned32)State.regs[srcreg2]);
2439 State.regs[dstreg1] = temp & 0xffffffff;
2440 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2441 }
2442
2443 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2444 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2445 "mov"
2446 *am33
2447 {
2448 int dstreg;
2449
2450 PC = cia;
2451 dstreg = translate_rreg (SD_, RN2);
2452 State.regs[dstreg] = load_word (IMM8);
2453 }
2454
2455 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2456 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2457 "mov"
2458 *am33
2459 {
2460 int srcreg;
2461
2462 PC = cia;
2463 srcreg = translate_rreg (SD_, RM2);
2464 store_word (IMM8, State.regs[srcreg]);
2465 }
2466
2467 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2468 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2469 "movbu"
2470 *am33
2471 {
2472 int dstreg;
2473
2474 PC = cia;
2475 dstreg = translate_rreg (SD_, RN2);
2476 State.regs[dstreg] = load_byte (IMM8);
2477 }
2478
2479 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2480 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2481 "movbu"
2482 *am33
2483 {
2484 int srcreg;
2485
2486 PC = cia;
2487 srcreg = translate_rreg (SD_, RM2);
2488 store_byte (IMM8, State.regs[srcreg]);
2489 }
2490
2491 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2492 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2493 "movhu"
2494 *am33
2495 {
2496 int dstreg;
2497
2498 PC = cia;
2499 dstreg = translate_rreg (SD_, RN2);
2500 State.regs[dstreg] = load_half (IMM8);
2501 }
2502
2503 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2504 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2505 "movhu"
2506 *am33
2507 {
2508 int srcreg;
2509
2510 PC = cia;
2511 srcreg = translate_rreg (SD_, RM2);
2512 store_half (IMM8, State.regs[srcreg]);
2513 }
2514
2515 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2516 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2517 "mov"
2518 *am33
2519 {
2520 int srcreg1, srcreg2, dstreg;
2521
2522 PC = cia;
2523 srcreg1 = translate_rreg (SD_, RM0);
2524 srcreg1 = translate_rreg (SD_, RI0);
2525 dstreg = translate_rreg (SD_, RN0);
2526 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2527 }
2528
2529 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2530 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2531 "mov"
2532 *am33
2533 {
2534 int srcreg, dstreg1, dstreg2;
2535
2536 PC = cia;
2537 srcreg = translate_rreg (SD_, RM0);
2538 dstreg1 = translate_rreg (SD_, RI0);
2539 dstreg2 = translate_rreg (SD_, RN0);
2540 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2541 }
2542
2543 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2544 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2545 "movbu"
2546 *am33
2547 {
2548 int srcreg1, srcreg2, dstreg;
2549
2550 PC = cia;
2551 srcreg1 = translate_rreg (SD_, RM0);
2552 srcreg1 = translate_rreg (SD_, RI0);
2553 dstreg = translate_rreg (SD_, RN0);
2554 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2555 }
2556
2557 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2558 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2559 "movbu"
2560 *am33
2561 {
2562 int srcreg, dstreg1, dstreg2;
2563
2564 PC = cia;
2565 srcreg = translate_rreg (SD_, RM0);
2566 dstreg1 = translate_rreg (SD_, RI0);
2567 dstreg2 = translate_rreg (SD_, RN0);
2568 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2569 }
2570
2571 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2572 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2573 "movhu"
2574 *am33
2575 {
2576 int srcreg1, srcreg2, dstreg;
2577
2578 PC = cia;
2579 srcreg1 = translate_rreg (SD_, RM0);
2580 srcreg1 = translate_rreg (SD_, RI0);
2581 dstreg = translate_rreg (SD_, RN0);
2582 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2583 }
2584
2585 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2586 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2587 "movhu"
2588 *am33
2589 {
2590 int srcreg, dstreg1, dstreg2;
2591
2592 PC = cia;
2593 srcreg = translate_rreg (SD_, RM0);
2594 dstreg1 = translate_rreg (SD_, RI0);
2595 dstreg2 = translate_rreg (SD_, RN0);
2596 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2597 }
2598
2599 // ??? mac
2600 // ??? macu
2601 // ??? macb
2602 // ??? macbu
2603 // ??? mach
2604 // ??? machu
2605 // ??? dmach
2606 // ??? dmachu
2607 // ??? dmulh
2608 // ??? dmulhu
2609
2610 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
2611 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
2612 "sat24"
2613 *am33
2614 {
2615 int srcreg, dstreg;
2616 int value;
2617
2618 PC = cia;
2619 srcreg = translate_rreg (SD_, RM2);
2620 dstreg = translate_rreg (SD_, RN0);
2621
2622 value = State.regs[srcreg];
2623
2624 if (value >= 0x7fffff)
2625 State.regs[dstreg] = 0x7fffff;
2626 else if (value <= 0xff800000)
2627 State.regs[dstreg] = 0xff800000;
2628 else
2629 State.regs[dstreg] = value;
2630 }
2631
2632 // ??? bsch
2633
2634 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
2635 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
2636 "mov"
2637 *am33
2638 {
2639 int dstreg;
2640
2641 PC = cia;
2642 dstreg = translate_rreg (SD_, RN0);
2643 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2644 }
2645
2646 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
2647 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
2648 "movu"
2649 *am33
2650 {
2651 int dstreg;
2652
2653 PC = cia;
2654 dstreg = translate_rreg (SD_, RN0);
2655 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2656 }
2657
2658 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
2659 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
2660 "add"
2661 *am33
2662 {
2663 int dstreg;
2664
2665 PC = cia;
2666 dstreg = translate_rreg (SD_, RN0);
2667 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2668 }
2669
2670 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
2671 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
2672 "addc"
2673 *am33
2674 {
2675 int dstreg, z, n, c, v;
2676 unsigned long sum, imm, reg2;
2677
2678 PC = cia;
2679 dstreg = translate_rreg (SD_, RN0);
2680
2681 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2682 reg2 = State.regs[dstreg];
2683 sum = imm + reg2 + ((PSW & PSW_C) != 0);
2684 State.regs[dstreg] = sum;
2685
2686 z = (sum == 0);
2687 n = (sum & 0x80000000);
2688 c = (sum < imm) || (sum < reg2);
2689 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2690 && (reg2 & 0x80000000) != (sum & 0x80000000));
2691
2692 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2693 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2694 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2695 }
2696
2697 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
2698 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
2699 "sub"
2700 *am33
2701 {
2702 int dstreg;
2703
2704 PC = cia;
2705 dstreg = translate_rreg (SD_, RN0);
2706 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2707 }
2708
2709 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
2710 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
2711 "subc"
2712 *am33
2713 {
2714 int dstreg, z, n, c, v;
2715 unsigned long difference, imm, reg2;
2716
2717 PC = cia;
2718 dstreg = translate_rreg (SD_, RN0);
2719
2720 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2721 reg2 = State.regs[dstreg];
2722 difference = reg2 - imm - ((PSW & PSW_C) != 0);
2723 State.regs[dstreg] = difference;
2724
2725 z = (difference == 0);
2726 n = (difference & 0x80000000);
2727 c = (imm > reg2);
2728 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2729 && (reg2 & 0x80000000) != (difference & 0x80000000));
2730
2731 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2732 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2733 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2734 }
2735
2736 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
2737 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
2738 "cmp"
2739 *am33
2740 {
2741 int srcreg;
2742
2743 PC = cia;
2744 srcreg = translate_rreg (SD_, RN0);
2745 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
2746 }
2747
2748 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
2749 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
2750 "mov"
2751 *am33
2752 {
2753 PC = cia;
2754
2755 if (XRN0 == 0)
2756 {
2757 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2758 }
2759 else
2760 abort ();
2761 }
2762
2763 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
2764 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
2765 "and"
2766 *am33
2767 {
2768 int dstreg;
2769 int z,n;
2770
2771 PC = cia;
2772 dstreg = translate_rreg (SD_, RN0);
2773
2774 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2775 z = (State.regs[dstreg] == 0);
2776 n = (State.regs[dstreg] & 0x80000000) != 0;
2777 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2778 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2779 }
2780
2781 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
2782 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
2783 "or"
2784 *am33
2785 {
2786 int dstreg;
2787 int z,n;
2788
2789 PC = cia;
2790 dstreg = translate_rreg (SD_, RN0);
2791
2792 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2793 z = (State.regs[dstreg] == 0);
2794 n = (State.regs[dstreg] & 0x80000000) != 0;
2795 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2797 }
2798
2799 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
2800 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
2801 "xor"
2802 *am33
2803 {
2804 int dstreg;
2805 int z,n;
2806
2807 PC = cia;
2808 dstreg = translate_rreg (SD_, RN0);
2809
2810 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2811 z = (State.regs[dstreg] == 0);
2812 n = (State.regs[dstreg] & 0x80000000) != 0;
2813 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2814 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2815 }
2816
2817 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
2818 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
2819 "asr"
2820 *am33
2821 {
2822 int dstreg;
2823 long temp;
2824 int c, z, n;
2825
2826 PC = cia;
2827 dstreg = translate_rreg (SD_, RN0);
2828
2829 temp = State.regs[dstreg];
2830 c = temp & 1;
2831 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2832 State.regs[dstreg] = temp;
2833 z = (State.regs[dstreg] == 0);
2834 n = (State.regs[dstreg] & 0x80000000) != 0;
2835 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2836 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2837 }
2838
2839
2840 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
2841 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
2842 "lsr"
2843 *am33
2844 {
2845 int dstreg;
2846 int z, n, c;
2847
2848 PC = cia;
2849 dstreg = translate_rreg (SD_, RN0);
2850
2851 c = State.regs[dstreg] & 1;
2852 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2853 z = (State.regs[dstreg] == 0);
2854 n = (State.regs[dstreg] & 0x80000000) != 0;
2855 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2856 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2857 }
2858
2859 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
2860 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
2861 "asl"
2862 *am33
2863 {
2864 int srcreg, dstreg;
2865 int z, n;
2866
2867 PC = cia;
2868 dstreg = translate_rreg (SD_, RN0);
2869
2870 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
2871 z = (State.regs[dstreg] == 0);
2872 n = (State.regs[dstreg] & 0x80000000) != 0;
2873 PSW &= ~(PSW_Z | PSW_N);
2874 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2875 }
2876
2877 // ??? mul
2878 // ??? mulu
2879
2880 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
2881 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
2882 "btst"
2883 *am33
2884 {
2885 int srcreg;
2886
2887 PC = cia;
2888 srcreg = translate_rreg (SD_, RN0);
2889 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
2890 }
2891
2892 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
2893 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
2894 "mov"
2895 *am33
2896 {
2897 int srcreg, dstreg;
2898
2899 PC = cia;
2900 srcreg = translate_rreg (SD_, RM0);
2901 dstreg = translate_rreg (SD_, RN2);
2902 State.regs[dstreg] = load_word (State.regs[srcreg]
2903 + FETCH24 (IMM24A, IMM24B, IMM24C));
2904 }
2905
2906 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
2907 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
2908 "mov"
2909 *am33
2910 {
2911 int srcreg, dstreg;
2912
2913 PC = cia;
2914 srcreg = translate_rreg (SD_, RM2);
2915 dstreg = translate_rreg (SD_, RN0);
2916 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
2917 State.regs[srcreg]);
2918 }
2919
2920 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
2921 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
2922 "movbu"
2923 *am33
2924 {
2925 int srcreg, dstreg;
2926
2927 PC = cia;
2928 srcreg = translate_rreg (SD_, RM0);
2929 dstreg = translate_rreg (SD_, RN2);
2930 State.regs[dstreg] = load_byte (State.regs[srcreg]
2931 + FETCH24 (IMM24A, IMM24B, IMM24C));
2932 }
2933
2934 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
2935 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
2936 "movbu"
2937 *am33
2938 {
2939 int srcreg, dstreg;
2940
2941 PC = cia;
2942 srcreg = translate_rreg (SD_, RM2);
2943 dstreg = translate_rreg (SD_, RN0);
2944 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
2945 State.regs[srcreg]);
2946 }
2947
2948 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
2949 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
2950 "movhu"
2951 *am33
2952 {
2953 int srcreg, dstreg;
2954
2955 PC = cia;
2956 srcreg = translate_rreg (SD_, RM0);
2957 dstreg = translate_rreg (SD_, RN2);
2958 State.regs[dstreg] = load_half (State.regs[srcreg]
2959 + FETCH24 (IMM24A, IMM24B, IMM24C));
2960 }
2961
2962 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
2963 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
2964 "movhu"
2965 *am33
2966 {
2967 int srcreg, dstreg;
2968
2969 PC = cia;
2970 srcreg = translate_rreg (SD_, RM2);
2971 dstreg = translate_rreg (SD_, RN0);
2972 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
2973 State.regs[srcreg]);
2974 }
2975
2976 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
2977 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
2978 "mov"
2979 *am33
2980 {
2981 int srcreg, dstreg;
2982
2983 PC = cia;
2984 srcreg = translate_rreg (SD_, RM0);
2985 dstreg = translate_rreg (SD_, RN2);
2986 State.regs[dstreg] = load_word (State.regs[srcreg]
2987 + FETCH24 (IMM24A, IMM24B, IMM24C));
2988 State.regs[srcreg] += 4;
2989 }
2990
2991 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
2992 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
2993 "mov"
2994 *am33
2995 {
2996 int srcreg, dstreg;
2997
2998 PC = cia;
2999 srcreg = translate_rreg (SD_, RM2);
3000 dstreg = translate_rreg (SD_, RN0);
3001 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3002 State.regs[srcreg]);
3003 State.regs[dstreg] += 4;
3004 }
3005
3006
3007 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3008 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3009 "mov"
3010 *am33
3011 {
3012 int dstreg;
3013
3014 PC = cia;
3015 dstreg = translate_rreg (SD_, RN2);
3016 State.regs[dstreg] = load_word (State.regs[REG_SP]
3017 + FETCH24 (IMM24A, IMM24B, IMM24C));
3018 }
3019
3020 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3021 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3022 "mov"
3023 *am33
3024 {
3025 int srcreg;
3026
3027 PC = cia;
3028 srcreg = translate_rreg (SD_, RM2);
3029 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3030 State.regs[srcreg]);
3031 }
3032
3033 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3034 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3035 "movbu"
3036 *am33
3037 {
3038 int dstreg;
3039
3040 PC = cia;
3041 dstreg = translate_rreg (SD_, RN2);
3042 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3043 + FETCH24 (IMM24A, IMM24B, IMM24C));
3044 }
3045
3046 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3047 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3048 "movbu"
3049 *am33
3050 {
3051 int srcreg;
3052
3053 PC = cia;
3054 srcreg = translate_rreg (SD_, RM2);
3055 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3056 State.regs[srcreg]);
3057 }
3058
3059 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3060 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3061 "movhu"
3062 *am33
3063 {
3064 int dstreg;
3065
3066 PC = cia;
3067 dstreg = translate_rreg (SD_, RN2);
3068 State.regs[dstreg] = load_half (State.regs[REG_SP]
3069 + FETCH24 (IMM24A, IMM24B, IMM24C));
3070 }
3071
3072 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3073 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3074 "movhu"
3075 *am33
3076 {
3077 int srcreg;
3078
3079 PC = cia;
3080 srcreg = translate_rreg (SD_, RM2);
3081 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3082 State.regs[srcreg]);
3083 }
3084
3085 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3086 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3087 "movhu"
3088 *am33
3089 {
3090 int srcreg, dstreg;
3091
3092 PC = cia;
3093 srcreg = translate_rreg (SD_, RM0);
3094 dstreg = translate_rreg (SD_, RN2);
3095 State.regs[dstreg] = load_half (State.regs[srcreg]
3096 + FETCH24 (IMM24A, IMM24B, IMM24C));
3097 State.regs[dstreg] += 2;
3098 }
3099
3100 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3101 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3102 "movhu"
3103 *am33
3104 {
3105 int srcreg, dstreg;
3106
3107 PC = cia;
3108 srcreg = translate_rreg (SD_, RM2);
3109 dstreg = translate_rreg (SD_, RN0);
3110 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3111 State.regs[srcreg]);
3112 State.regs[srcreg] += 2;
3113 }
3114
3115 // ??? mac
3116 // ??? macb
3117 // ??? macbu
3118 // ??? mach
3119 // ??? machu
3120
3121 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3122 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3123 "mov"
3124 *am33
3125 {
3126 int dstreg;
3127
3128 PC = cia;
3129 dstreg = translate_rreg (SD_, RN2);
3130 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3131 }
3132
3133 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3134 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3135 "mov"
3136 *am33
3137 {
3138 int srcreg;
3139
3140 PC = cia;
3141 srcreg = translate_rreg (SD_, RM2);
3142 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3143 }
3144
3145
3146 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3147 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3148 "movbu"
3149 *am33
3150 {
3151 int dstreg;
3152
3153 PC = cia;
3154 dstreg = translate_rreg (SD_, RN2);
3155 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3156 }
3157
3158 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3159 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3160 "movbu"
3161 *am33
3162 {
3163 int srcreg;
3164
3165 PC = cia;
3166 srcreg = translate_rreg (SD_, RM2);
3167 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3168 }
3169
3170
3171 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3172 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3173 "movhu"
3174 *am33
3175 {
3176 int dstreg;
3177
3178 PC = cia;
3179 dstreg = translate_rreg (SD_, RN2);
3180 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3181 }
3182
3183 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3184 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3185 "movhu"
3186 *am33
3187 {
3188 int srcreg;
3189
3190 PC = cia;
3191 srcreg = translate_rreg (SD_, RM2);
3192 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3193 }
3194
3195
3196 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3197 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3198 "mov"
3199 *am33
3200 {
3201 int dstreg;
3202
3203 PC = cia;
3204 dstreg = translate_rreg (SD_, RN0);
3205 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3206 }
3207
3208 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3209 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3210 "movu"
3211 *am33
3212 {
3213 int dstreg;
3214
3215 PC = cia;
3216 dstreg = translate_rreg (SD_, RN0);
3217 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3218 }
3219
3220 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3221 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3222 "add"
3223 *am33
3224 {
3225 int dstreg;
3226
3227 PC = cia;
3228 dstreg = translate_rreg (SD_, RN0);
3229 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3230 }
3231
3232 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3233 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3234 "addc"
3235 *am33
3236 {
3237 int dstreg;
3238 unsigned int imm, reg2, sum;
3239 int z, n, c, v;
3240
3241 PC = cia;
3242 dstreg = translate_rreg (SD_, RN0);
3243
3244 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3245 reg2 = State.regs[dstreg];
3246 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3247 State.regs[dstreg] = sum;
3248
3249 z = (sum == 0);
3250 n = (sum & 0x80000000);
3251 c = (sum < imm) || (sum < reg2);
3252 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3253 && (reg2 & 0x80000000) != (sum & 0x80000000));
3254
3255 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3256 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3257 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3258 }
3259
3260 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3261 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3262 "sub"
3263 *am33
3264 {
3265 int dstreg;
3266
3267 PC = cia;
3268 dstreg = translate_rreg (SD_, RN0);
3269 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3270 }
3271
3272 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3273 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3274 "subc"
3275 *am33
3276 {
3277 int dstreg;
3278 unsigned int imm, reg2, difference;
3279 int z, n, c, v;
3280
3281 PC = cia;
3282 dstreg = translate_rreg (SD_, RN0);
3283
3284 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3285 reg2 = State.regs[dstreg];
3286 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3287 State.regs[dstreg] = difference;
3288
3289 z = (difference == 0);
3290 n = (difference & 0x80000000);
3291 c = (imm > reg2);
3292 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3293 && (reg2 & 0x80000000) != (difference & 0x80000000));
3294
3295 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3296 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3297 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3298 }
3299
3300 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3301 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3302 "cmp"
3303 *am33
3304 {
3305 int srcreg;
3306
3307 PC = cia;
3308 srcreg = translate_rreg (SD_, RN0);
3309 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3310 }
3311
3312 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3313 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3314 "mov"
3315 *am33
3316 {
3317 PC = cia;
3318
3319 if (XRN0 == 0)
3320 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3321 else
3322 abort ();
3323 }
3324
3325 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3326 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
3327 "and"
3328 *am33
3329 {
3330 int dstreg;
3331 int z,n;
3332
3333 PC = cia;
3334 dstreg = translate_rreg (SD_, RN0);
3335
3336 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3337 z = (State.regs[dstreg] == 0);
3338 n = (State.regs[dstreg] & 0x80000000) != 0;
3339 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3340 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3341 }
3342
3343 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
3344 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
3345 "or"
3346 *am33
3347 {
3348 int dstreg;
3349 int z,n;
3350
3351 PC = cia;
3352 dstreg = translate_rreg (SD_, RN0);
3353
3354 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3355 z = (State.regs[dstreg] == 0);
3356 n = (State.regs[dstreg] & 0x80000000) != 0;
3357 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3358 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3359 }
3360
3361 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
3362 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
3363 "xor"
3364 *am33
3365 {
3366 int dstreg;
3367 int z,n;
3368
3369 PC = cia;
3370 dstreg = translate_rreg (SD_, RN0);
3371
3372 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3373 z = (State.regs[dstreg] == 0);
3374 n = (State.regs[dstreg] & 0x80000000) != 0;
3375 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3376 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3377 }
3378
3379 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
3380 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
3381 "asr"
3382 *am33
3383 {
3384 int dstreg;
3385 long temp;
3386 int c, z, n;
3387
3388 PC = cia;
3389 dstreg = translate_rreg (SD_, RN0);
3390
3391 temp = State.regs[dstreg];
3392 c = temp & 1;
3393 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3394 State.regs[dstreg] = temp;
3395 z = (State.regs[dstreg] == 0);
3396 n = (State.regs[dstreg] & 0x80000000) != 0;
3397 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3398 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3399 }
3400
3401 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
3402 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
3403 "lsr"
3404 *am33
3405 {
3406 int dstreg;
3407 int z, n, c;
3408
3409 PC = cia;
3410 dstreg = translate_rreg (SD_, RN0);
3411
3412 c = State.regs[dstreg] & 1;
3413 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3414 z = (State.regs[dstreg] == 0);
3415 n = (State.regs[dstreg] & 0x80000000) != 0;
3416 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3417 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3418 }
3419
3420 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
3421 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
3422 "asl"
3423 *am33
3424 {
3425 int srcreg, dstreg;
3426 int z, n;
3427
3428 PC = cia;
3429 dstreg = translate_rreg (SD_, RN0);
3430
3431 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3432 z = (State.regs[dstreg] == 0);
3433 n = (State.regs[dstreg] & 0x80000000) != 0;
3434 PSW &= ~(PSW_Z | PSW_N);
3435 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3436 }
3437
3438 // ??? mul
3439 // ??? mulu
3440
3441 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
3442 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
3443 "btst"
3444 *am33
3445 {
3446 int srcreg;
3447
3448 PC = cia;
3449 srcreg = translate_rreg (SD_, RN0);
3450 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3451 }
3452
3453 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
3454 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
3455 "mov"
3456 *am33
3457 {
3458 int srcreg, dstreg;
3459
3460 PC = cia;
3461 srcreg = translate_rreg (SD_, RM0);
3462 dstreg = translate_rreg (SD_, RN2);
3463 State.regs[dstreg] = load_word (State.regs[srcreg]
3464 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3465 }
3466
3467 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
3468 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
3469 "mov"
3470 *am33
3471 {
3472 int srcreg, dstreg;
3473
3474 PC = cia;
3475 srcreg = translate_rreg (SD_, RM2);
3476 dstreg = translate_rreg (SD_, RN0);
3477 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3478 State.regs[srcreg]);
3479 }
3480
3481 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
3482 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
3483 "movbu"
3484 *am33
3485 {
3486 int srcreg, dstreg;
3487
3488 PC = cia;
3489 srcreg = translate_rreg (SD_, RM0);
3490 dstreg = translate_rreg (SD_, RN2);
3491 State.regs[dstreg] = load_byte (State.regs[srcreg]
3492 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3493 }
3494
3495 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
3496 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
3497 "movbu"
3498 *am33
3499 {
3500 int srcreg, dstreg;
3501
3502 PC = cia;
3503 srcreg = translate_rreg (SD_, RM2);
3504 dstreg = translate_rreg (SD_, RN0);
3505 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3506 State.regs[srcreg]);
3507 }
3508
3509 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
3510 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
3511 "movhu"
3512 *am33
3513 {
3514 int srcreg, dstreg;
3515
3516 PC = cia;
3517 srcreg = translate_rreg (SD_, RM0);
3518 dstreg = translate_rreg (SD_, RN2);
3519 State.regs[dstreg] = load_half (State.regs[srcreg]
3520 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3521 }
3522
3523 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
3524 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
3525 "movhu"
3526 *am33
3527 {
3528 int srcreg, dstreg;
3529
3530 PC = cia;
3531 srcreg = translate_rreg (SD_, RM2);
3532 dstreg = translate_rreg (SD_, RN0);
3533 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3534 State.regs[srcreg]);
3535 }
3536
3537 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
3538 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
3539 "mov"
3540 *am33
3541 {
3542 int srcreg, dstreg;
3543
3544 PC = cia;
3545 srcreg = translate_rreg (SD_, RM0);
3546 dstreg = translate_rreg (SD_, RN2);
3547 State.regs[dstreg] = load_word (State.regs[srcreg]
3548 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3549 State.regs[srcreg] += 4;
3550 }
3551
3552 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
3553 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
3554 "mov"
3555 *am33
3556 {
3557 int srcreg, dstreg;
3558
3559 PC = cia;
3560 srcreg = translate_rreg (SD_, RM2);
3561 dstreg = translate_rreg (SD_, RN0);
3562 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3563 State.regs[srcreg]);
3564 State.regs[dstreg] += 4;
3565 }
3566
3567
3568 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
3569 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
3570 "mov"
3571 *am33
3572 {
3573 int dstreg;
3574
3575 PC = cia;
3576 dstreg = translate_rreg (SD_, RN2);
3577 State.regs[dstreg] = load_word (State.regs[REG_SP]
3578 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3579 }
3580
3581 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
3582 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
3583 "mov"
3584 *am33
3585 {
3586 int srcreg;
3587
3588 PC = cia;
3589 srcreg = translate_rreg (SD_, RM2);
3590 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3591 State.regs[srcreg]);
3592 }
3593
3594 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
3595 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
3596 "movbu"
3597 *am33
3598 {
3599 int dstreg;
3600
3601 PC = cia;
3602 dstreg = translate_rreg (SD_, RN2);
3603 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3604 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3605 }
3606
3607 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
3608 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
3609 "movbu"
3610 *am33
3611 {
3612 int srcreg;
3613
3614 PC = cia;
3615 srcreg = translate_rreg (SD_, RM2);
3616 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3617 State.regs[srcreg]);
3618 }
3619
3620 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
3621 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
3622 "movhu"
3623 *am33
3624 {
3625 int dstreg;
3626
3627 PC = cia;
3628 dstreg = translate_rreg (SD_, RN2);
3629 State.regs[dstreg] = load_half (State.regs[REG_SP]
3630 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3631 }
3632
3633 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
3634 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
3635 "movhu"
3636 *am33
3637 {
3638 int srcreg;
3639
3640 PC = cia;
3641 srcreg = translate_rreg (SD_, RM2);
3642 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3643 State.regs[srcreg]);
3644 }
3645
3646
3647 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
3648 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
3649 "movhu"
3650 *am33
3651 {
3652 int srcreg, dstreg;
3653
3654 PC = cia;
3655 srcreg = translate_rreg (SD_, RM0);
3656 dstreg = translate_rreg (SD_, RN2);
3657 State.regs[dstreg] = load_half (State.regs[srcreg]
3658 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3659 State.regs[srcreg] += 2;
3660 }
3661
3662 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
3663 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
3664 "movhu"
3665 *am33
3666 {
3667 int srcreg, dstreg;
3668
3669 PC = cia;
3670 srcreg = translate_rreg (SD_, RM2);
3671 dstreg = translate_rreg (SD_, RN0);
3672 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3673 State.regs[srcreg]);
3674 State.regs[dstreg] += 2;
3675 }
3676
3677
3678 // ??? mac
3679 // ??? macu
3680 // ??? macb
3681 // ??? macbu
3682 // ??? mach
3683 // ??? machu
3684 // ??? dmach
3685 // ??? dmachu
3686 // ??? dmulh
3687 // ??? dmulhu
3688
3689 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
3690 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
3691 "mov"
3692 *am33
3693 {
3694 int dstreg;
3695
3696 PC = cia;
3697 dstreg = translate_rreg (SD_, RN2);
3698 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3699 }
3700
3701 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
3702 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
3703 "mov"
3704 *am33
3705 {
3706 int srcreg;
3707
3708 PC = cia;
3709 srcreg = translate_rreg (SD_, RM2);
3710 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3711 }
3712
3713 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
3714 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
3715 "movbu"
3716 *am33
3717 {
3718 int dstreg;
3719
3720 PC = cia;
3721 dstreg = translate_rreg (SD_, RN2);
3722 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3723 }
3724
3725 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
3726 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
3727 "movbu"
3728 *am33
3729 {
3730 int srcreg;
3731
3732 PC = cia;
3733 srcreg = translate_rreg (SD_, RM2);
3734 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3735 }
3736
3737 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
3738 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
3739 "movhu"
3740 *am33
3741 {
3742 int dstreg;
3743
3744 PC = cia;
3745 dstreg = translate_rreg (SD_, RN2);
3746 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3747 }
3748
3749 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
3750 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
3751 "movhu"
3752 *am33
3753 {
3754 int srcreg;
3755
3756 PC = cia;
3757 srcreg = translate_rreg (SD_, RM2);
3758 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3759 }
3760
3761 // ??? DSP
GDB Binutils - Deliverables
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