sim/mn10300/am33.igen

   1 // 1111 0000 0010 00An; mov USP,An
   2 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
   3 "mov"
   4 *am33
   5 {
   6   PC = cia;
   7   State.regs[REG_A0 + AN0] = State.regs[REG_USP];
   8 }
   9
  10
  11 // 1111 0000 0010 01An; mov SSP,An
  12 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
  13 "mov"
  14 *am33
  15 {
  16   PC = cia;
  17   State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
  18 }
  19
  20
  21 // 1111 0000 0010 10An; mov MSP,An
  22 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
  23 "mov"
  24 *am33
  25 {
  26   PC = cia;
  27   State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
  28 }
  29
  30
  31 // 1111 0000 0010 11An; mov PC,An
  32 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
  33 "mov"
  34 *am33
  35 {
  36   PC = cia;
  37   State.regs[REG_A0 + AN0] = PC;
  38 }
  39
  40
  41 // 1111 0000 0011 Am00; mov Am,USP
  42 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
  43 "mov"
  44 // end-sanitize-am33
  45 {
  46   PC = cia;
  47   State.regs[REG_USP] = State.regs[REG_A0 + AM1];
  48 }
  49
  50 // 1111 0000 0011 Am01; mov Am,SSP
  51 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
  52 "mov"
  53 // end-sanitize-am33
  54 {
  55   PC = cia;
  56   State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
  57 }
  58
  59 // 1111 0000 0011 Am10; mov Am,MSP
  60 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
  61 "mov"
  62 // end-sanitize-am33
  63 {
  64   PC = cia;
  65   State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
  66 }
  67
  68
  69 // 1111 0000 1110 imm4; syscall
  70 8.0xf0+4.0xe,IMM4:D0t:::syscall
  71 "syscall"
  72 *am33
  73 {
  74   unsigned int sp, next_pc;
  75
  76   PC = cia;
  77   sp = State.regs[REG_SP];
  78   next_pc = State.regs[REG_PC] + 2;
  79   store_word (sp - 4, next_pc);
  80   store_word (sp - 8, PSW);
  81   State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
  82   nia = PC;
  83 }
  84
  85
  86 // 1111 0010 1110 11Dn; mov EPSW,Dn
  87 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
  88 "mov"
  89 *am33
  90 {
  91   PC = cia;
  92   State.regs[REG_D0 + DN0] = PSW;
  93 }
  94
  95
  96 // 1111 0010 1111 Dm01; mov Dm,EPSW
  97 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
  98 "mov"
  99 *am33
 100 {
 101   PC = cia;
 102   PSW = State.regs[REG_D0 + DM1];
 103 }
 104
 105 // 1111 0101 00Am Rn; mov Am,Rn
 106 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
 107 "mov"
 108 *am33
 109 {
 110   PC = cia;
 111   /* The higher register numbers actually correspond to the
 112      basic machine's address and data registers.  */
 113   if (RN0 > 7 && RN0 < 12)
 114     State.regs[REG_A0 + RN0 - 8] = State.regs[REG_A0 + AM1];
 115   else if (RN0 > 11 && RN0 < 16)
 116     State.regs[REG_D0 + RN0 - 12] = State.regs[REG_A0 + AM1];
 117   else
 118     State.regs[REG_E0 + RN0] = State.regs[REG_A0 + AM1] ;
 119 }
 120
 121 // 1111 0101 01Dm Rn; mov Dm,Rn
 122 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
 123 "mov"
 124 *am33
 125 {
 126   PC = cia;
 127   /* The higher register numbers actually correspond to the
 128      basic machine's address and data registers.  */
 129   if (RN0 > 7 && RN0 < 12)
 130     State.regs[REG_A0 + RN0 - 8] = State.regs[REG_D0 + DM1];
 131   else if (RN0 > 11 && RN0 < 16)
 132     State.regs[REG_D0 + RN0 - 12] = State.regs[REG_D0 + DM1];
 133   else
 134     State.regs[REG_E0 + RN0] = State.regs[REG_D0 + DM1] ;
 135 }
 136
 137 // 1111 0101 10Rm An; mov Rm,An
 138 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
 139 "mov"
 140 *am33
 141 {
 142   PC = cia;
 143   /* The higher register numbers actually correspond to the
 144      basic machine's address and data registers.  */
 145   if (RM1 > 7 && RM1 < 12)
 146     State.regs[REG_A0 + AN0] = State.regs[REG_A0 + RM1 - 8];
 147   else if (RM1 > 11 && RM1 < 16)
 148     State.regs[REG_A0 + AN0] = State.regs[REG_D0 + RM1 - 12];
 149   else
 150     State.regs[REG_A0 + AN0] = State.regs[REG_E0 + RM1];
 151 }
 152
 153 // 1111 0101 11Rm Dn; mov Rm,Dn
 154 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
 155 "mov"
 156 *am33
 157 {
 158   PC = cia;
 159   /* The higher register numbers actually correspond to the
 160      basic machine's address and data registers.  */
 161   if (RM1 > 7 && RM1 < 12)
 162     State.regs[REG_D0 + DN0] = State.regs[REG_A0 + RM1 - 8];
 163   else if (RM1 > 11 && RM1 < 16)
 164     State.regs[REG_D0 + DN0] = State.regs[REG_D0 + RM1 - 12];
 165   else
 166     State.regs[REG_D0 + DN0] = State.regs[REG_E0 + RM1];
 167 }
 168
 169
 170 // 1111 1000 1100 1110 regs....; movm (USP),regs
 171 8.0xf8+8.0xce+8.REGS:D1a:::movm
 172 "movm"
 173 {
 174   unsigned long usp = State.regs[REG_USP];
 175   unsigned long mask;
 176
 177   PC = cia;
 178   mask = REGS;
 179
 180   if (mask & 0x8)
 181     {
 182       usp += 4;
 183       State.regs[REG_LAR] = load_word (usp);
 184       usp += 4;
 185       State.regs[REG_LIR] = load_word (usp);
 186       usp += 4;
 187       State.regs[REG_MDR] = load_word (usp);
 188       usp += 4;
 189       State.regs[REG_A0 + 1] = load_word (usp);
 190       usp += 4;
 191       State.regs[REG_A0] = load_word (usp);
 192       usp += 4;
 193       State.regs[REG_D0 + 1] = load_word (usp);
 194       usp += 4;
 195       State.regs[REG_D0] = load_word (usp);
 196       usp += 4;
 197     }
 198
 199   if (mask & 0x10)
 200     {
 201       State.regs[REG_A0 + 3] = load_word (usp);
 202       usp += 4;
 203     }
 204
 205   if (mask & 0x20)
 206     {
 207       State.regs[REG_A0 + 2] = load_word (usp);
 208       usp += 4;
 209     }
 210
 211   if (mask & 0x40)
 212     {
 213       State.regs[REG_D0 + 3] = load_word (usp);
 214       usp += 4;
 215     }
 216
 217   if (mask & 0x80)
 218     {
 219       State.regs[REG_D0 + 2] = load_word (usp);
 220       usp += 4;
 221     }
 222
 223   /* start-sanitize-am33 */
 224   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
 225     {
 226       if (mask & 0x1)
 227         {
 228           /* Need to restore MDQR, MCRH, MCRL, and MCVF */
 229           usp += 16;
 230           State.regs[REG_E0 + 1] = load_word (usp);
 231           usp += 4;
 232           State.regs[REG_E0 + 0] = load_word (usp);
 233           usp += 4;
 234         }
 235
 236       if (mask & 0x2)
 237         {
 238           State.regs[REG_E0 + 7] = load_word (usp);
 239           usp += 4;
 240           State.regs[REG_E0 + 6] = load_word (usp);
 241           usp += 4;
 242           State.regs[REG_E0 + 5] = load_word (usp);
 243           usp += 4;
 244           State.regs[REG_E0 + 4] = load_word (usp);
 245           usp += 4;
 246         }
 247
 248       if (mask & 0x4)
 249         {
 250           State.regs[REG_E0 + 3] = load_word (usp);
 251           usp += 4;
 252           State.regs[REG_E0 + 2] = load_word (usp);
 253           usp += 4;
 254         }
 255     }
 256   /* end-sanitize-am33 */
 257
 258   /* And make sure to update the stack pointer.  */
 259   State.regs[REG_USP] = usp;
 260 }
 261
 262 // 1111 1000 1100 1111 regs....; movm (USP),regs
 263 8.0xf8+8.0xcf+8.REGS:D1b:::movm
 264 "movm"
 265 {
 266   unsigned long usp = State.regs[REG_USP];
 267   unsigned long mask;
 268
 269   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
 270     {
 271       if (mask & 0x4)
 272         {
 273           usp -= 4;
 274           store_word (usp, State.regs[REG_E0 + 2]);
 275           usp -= 4;
 276           store_word (usp, State.regs[REG_E0 + 3]);
 277         }
 278
 279       if (mask & 0x2)
 280         {
 281           usp -= 4;
 282           store_word (usp, State.regs[REG_E0 + 4]);
 283           usp -= 4;
 284           store_word (usp, State.regs[REG_E0 + 5]);
 285           usp -= 4;
 286           store_word (usp, State.regs[REG_E0 + 6]);
 287           usp -= 4;
 288           store_word (usp, State.regs[REG_E0 + 7]);
 289         }
 290
 291       if (mask & 0x1)
 292         {
 293           usp -= 4;
 294           store_word (usp, State.regs[REG_E0 + 0]);
 295           usp -= 4;
 296           store_word (usp, State.regs[REG_E0 + 1]);
 297           usp -= 16;
 298           /* Need to save MDQR, MCRH, MCRL, and MCVF */
 299         }
 300     }
 301   /* end-sanitize-am33 */
 302
 303   if (mask & 0x80)
 304     {
 305       usp -= 4;
 306       store_word (usp, State.regs[REG_D0 + 2]);
 307     }
 308
 309   if (mask & 0x40)
 310     {
 311       usp -= 4;
 312       store_word (usp, State.regs[REG_D0 + 3]);
 313     }
 314
 315   if (mask & 0x20)
 316     {
 317       usp -= 4;
 318       store_word (usp, State.regs[REG_A0 + 2]);
 319     }
 320
 321   if (mask & 0x10)
 322     {
 323       usp -= 4;
 324       store_word (usp, State.regs[REG_A0 + 3]);
 325     }
 326
 327   if (mask & 0x8)
 328     {
 329       usp -= 4;
 330       store_word (usp, State.regs[REG_D0]);
 331       usp -= 4;
 332       store_word (usp, State.regs[REG_D0 + 1]);
 333       usp -= 4;
 334       store_word (usp, State.regs[REG_A0]);
 335       usp -= 4;
 336       store_word (usp, State.regs[REG_A0 + 1]);
 337       usp -= 4;
 338       store_word (usp, State.regs[REG_MDR]);
 339       usp -= 4;
 340       store_word (usp, State.regs[REG_LIR]);
 341       usp -= 4;
 342       store_word (usp, State.regs[REG_LAR]);
 343       usp -= 4;
 344     }
 345
 346   /* And make sure to update the stack pointer.  */
 347   State.regs[REG_USP] = usp;
 348 }
 349
 350 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
 351 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
 352 "and"
 353 *am33
 354 {
 355   PC = cia;
 356   PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
 357 }
 358
 359 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
 360 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
 361 "or"
 362 *am33
 363 {
 364   PC = cia;
 365   PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
 366 }
 367
 368 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
 369 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
 370 "mov"
 371 *am33
 372 {
 373   int srcreg, dstreg;
 374
 375   PC = cia;
 376
 377   if (RM2 > 7 && RM2 < 12)
 378     srcreg = REG_A0 + RM2 - 8;
 379   else if (RM2 > 11 && RM2 < 16)
 380     srcreg = REG_D0 + RM2 - 12;
 381   else
 382     srcreg = REG_E0 + RM2;
 383
 384   if (RN0 > 7 && RN0 < 12)
 385     dstreg = REG_A0 + RN0 - 8;
 386   else if (RN0 > 11 && RN0 < 16)
 387     dstreg = REG_D0 + RN0 - 12;
 388   else
 389     dstreg = REG_E0 + RN0;
 390
 391   State.regs[dstreg] = State.regs[srcreg];
 392 }
 393
 394 // 1111 1001 0001 1000 Rn Rn; ext Rn
 395 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
 396 "mov"
 397 *am33
 398 {
 399   int srcreg, dstreg;
 400
 401   PC = cia;
 402
 403   if (RN0 > 7 && RN0 < 12)
 404     srcreg = REG_A0 + RN0 - 8;
 405   else if (RN0 > 11 && RN0 < 16)
 406     srcreg = REG_D0 + RN0 - 12;
 407   else
 408     srcreg = REG_E0 + RN0;
 409
 410   if (State.regs[srcreg] & 0x80000000)
 411     State.regs[REG_MDR] = -1;
 412   else
 413     State.regs[REG_MDR] = 0;
 414 }
 415
 416 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
 417 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
 418 "extb"
 419 *am33
 420 {
 421   int srcreg, dstreg;
 422
 423   PC = cia;
 424
 425   if (RM2 > 7 && RM2 < 12)
 426     srcreg = REG_A0 + RM2 - 8;
 427   else if (RM2 > 11 && RM2 < 16)
 428     srcreg = REG_D0 + RM2 - 12;
 429   else
 430     srcreg = REG_E0 + RM2;
 431
 432   if (RN0 > 7 && RN0 < 12)
 433     dstreg = REG_A0 + RN0 - 8;
 434   else if (RN0 > 11 && RN0 < 16)
 435     dstreg = REG_D0 + RN0 - 12;
 436   else
 437     dstreg = REG_E0 + RN0;
 438
 439   State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
 440 }
 441
 442 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
 443 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
 444 "extbu"
 445 *am33
 446 {
 447   int srcreg, dstreg;
 448
 449   PC = cia;
 450
 451   if (RM2 > 7 && RM2 < 12)
 452     srcreg = REG_A0 + RM2 - 8;
 453   else if (RM2 > 11 && RM2 < 16)
 454     srcreg = REG_D0 + RM2 - 12;
 455   else
 456     srcreg = REG_E0 + RM2;
 457
 458   if (RN0 > 7 && RN0 < 12)
 459     dstreg = REG_A0 + RN0 - 8;
 460   else if (RN0 > 11 && RN0 < 16)
 461     dstreg = REG_D0 + RN0 - 12;
 462   else
 463     dstreg = REG_E0 + RN0;
 464
 465   State.regs[dstreg] = State.regs[srcreg] & 0xff;
 466 }
 467
 468 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
 469 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
 470 "exth"
 471 *am33
 472 {
 473   int srcreg, dstreg;
 474
 475   PC = cia;
 476
 477   if (RM2 > 7 && RM2 < 12)
 478     srcreg = REG_A0 + RM2 - 8;
 479   else if (RM2 > 11 && RM2 < 16)
 480     srcreg = REG_D0 + RM2 - 12;
 481   else
 482     srcreg = REG_E0 + RM2;
 483
 484   if (RN0 > 7 && RN0 < 12)
 485     dstreg = REG_A0 + RN0 - 8;
 486   else if (RN0 > 11 && RN0 < 16)
 487     dstreg = REG_D0 + RN0 - 12;
 488   else
 489     dstreg = REG_E0 + RN0;
 490
 491   State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
 492 }
 493
 494 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
 495 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
 496 "exthu"
 497 *am33
 498 {
 499   int srcreg, dstreg;
 500
 501   PC = cia;
 502
 503   if (RM2 > 7 && RM2 < 12)
 504     srcreg = REG_A0 + RM2 - 8;
 505   else if (RM2 > 11 && RM2 < 16)
 506     srcreg = REG_D0 + RM2 - 12;
 507   else
 508     srcreg = REG_E0 + RM2;
 509
 510   if (RN0 > 7 && RN0 < 12)
 511     dstreg = REG_A0 + RN0 - 8;
 512   else if (RN0 > 11 && RN0 < 16)
 513     dstreg = REG_D0 + RN0 - 12;
 514   else
 515     dstreg = REG_E0 + RN0;
 516
 517   State.regs[dstreg] = State.regs[srcreg] & 0xffff;
 518 }
 519
 520 // 1111 1001 0110 1000 Rn Rn; clr Rn
 521 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
 522 "clr"
 523 *am33
 524 {
 525   int srcreg, dstreg;
 526
 527   PC = cia;
 528
 529   if (RN0 > 7 && RN0 < 12)
 530     dstreg = REG_A0 + RN0 - 8;
 531   else if (RN0 > 11 && RN0 < 16)
 532     dstreg = REG_D0 + RN0 - 12;
 533   else
 534     dstreg = REG_E0 + RN0;
 535
 536   State.regs[dstreg] = 0;
 537
 538   PSW |= PSW_Z;
 539   PSW &= ~(PSW_V | PSW_C | PSW_N);
 540 }
 541
 542 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
 543 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
 544 "add"
 545 *am33
 546 {
 547   int srcreg, dstreg;
 548
 549   PC = cia;
 550
 551   if (RM2 > 7 && RM2 < 12)
 552     srcreg = REG_A0 + RM2 - 8;
 553   else if (RM2 > 11 && RM2 < 16)
 554     srcreg = REG_D0 + RM2 - 12;
 555   else
 556     srcreg = REG_E0 + RM2;
 557
 558   if (RN0 > 7 && RN0 < 12)
 559     dstreg = REG_A0 + RN0 - 8;
 560   else if (RN0 > 11 && RN0 < 16)
 561     dstreg = REG_D0 + RN0 - 12;
 562   else
 563     dstreg = REG_E0 + RN0;
 564
 565   genericAdd (State.regs[srcreg], dstreg);
 566 }
 567
 568 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
 569 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
 570 "addc"
 571 *am33
 572 {
 573   int srcreg, dstreg;
 574   int z, c, n, v;
 575   unsigned long reg1, reg2, sum;
 576
 577   PC = cia;
 578
 579   if (RM2 > 7 && RM2 < 12)
 580     srcreg = REG_A0 + RM2 - 8;
 581   else if (RM2 > 11 && RM2 < 16)
 582     srcreg = REG_D0 + RM2 - 12;
 583   else
 584     srcreg = REG_E0 + RM2;
 585
 586   if (RN0 > 7 && RN0 < 12)
 587     dstreg = REG_A0 + RN0 - 8;
 588   else if (RN0 > 11 && RN0 < 16)
 589     dstreg = REG_D0 + RN0 - 12;
 590   else
 591     dstreg = REG_E0 + RN0;
 592
 593   reg1 = State.regs[srcreg];
 594   reg2 = State.regs[dstreg];
 595   sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
 596   State.regs[dstreg] = sum;
 597
 598   z = (sum == 0);
 599   n = (sum & 0x80000000);
 600   c = (sum < reg1) || (sum < reg2);
 601   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
 602        && (reg2 & 0x80000000) != (sum & 0x80000000));
 603
 604   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 605   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 606           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 607 }
 608
 609 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
 610 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
 611 "sub"
 612 *am33
 613 {
 614   int srcreg, dstreg;
 615
 616   PC = cia;
 617
 618   if (RM2 > 7 && RM2 < 12)
 619     srcreg = REG_A0 + RM2 - 8;
 620   else if (RM2 > 11 && RM2 < 16)
 621     srcreg = REG_D0 + RM2 - 12;
 622   else
 623     srcreg = REG_E0 + RM2;
 624
 625   if (RN0 > 7 && RN0 < 12)
 626     dstreg = REG_A0 + RN0 - 8;
 627   else if (RN0 > 11 && RN0 < 16)
 628     dstreg = REG_D0 + RN0 - 12;
 629   else
 630     dstreg = REG_E0 + RN0;
 631
 632   genericSub (State.regs[srcreg], dstreg);
 633 }
 634
 635 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
 636 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
 637 "subc"
 638 *am33
 639 {
 640   int srcreg, dstreg;
 641   int z, c, n, v;
 642   unsigned long reg1, reg2, difference;
 643
 644   PC = cia;
 645
 646   if (RM2 > 7 && RM2 < 12)
 647     srcreg = REG_A0 + RM2 - 8;
 648   else if (RM2 > 11 && RM2 < 16)
 649     srcreg = REG_D0 + RM2 - 12;
 650   else
 651     srcreg = REG_E0 + RM2;
 652
 653   if (RN0 > 7 && RN0 < 12)
 654     dstreg = REG_A0 + RN0 - 8;
 655   else if (RN0 > 11 && RN0 < 16)
 656     dstreg = REG_D0 + RN0 - 12;
 657   else
 658     dstreg = REG_E0 + RN0;
 659
 660   reg1 = State.regs[srcreg];
 661   reg2 = State.regs[dstreg];
 662   difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
 663   State.regs[dstreg] = difference;
 664
 665   z = (difference == 0);
 666   n = (difference & 0x80000000);
 667   c = (reg1 > reg2);
 668   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
 669        && (reg2 & 0x80000000) != (difference & 0x80000000));
 670
 671   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 672   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 673           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 674 }
 675
 676 // 1111 1001 1011 1000 Rn Rn; inc Rn
 677 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
 678 "inc"
 679 *am33
 680 {
 681   int dstreg;
 682
 683   PC = cia;
 684
 685   if (RN0 > 7 && RN0 < 12)
 686     dstreg = REG_A0 + RN0 - 8;
 687   else if (RN0 > 11 && RN0 < 16)
 688     dstreg = REG_D0 + RN0 - 12;
 689   else
 690     dstreg = REG_E0 + RN0;
 691
 692   genericAdd (1, dstreg);
 693 }
 694
 695 // 1111 1001 1101 1000 Rn Rn; inc Rn
 696 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
 697 "inc4"
 698 *am33
 699 {
 700   int dstreg;
 701
 702   PC = cia;
 703
 704   if (RN0 > 7 && RN0 < 12)
 705     dstreg = REG_A0 + RN0 - 8;
 706   else if (RN0 > 11 && RN0 < 16)
 707     dstreg = REG_D0 + RN0 - 12;
 708   else
 709     dstreg = REG_E0 + RN0;
 710   State.regs[dstreg] += 4;
 711 }
 712
 713 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
 714 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
 715 "cmp"
 716 *am33
 717 {
 718   int srcreg1, srcreg2;
 719
 720   PC = cia;
 721
 722   if (RN0 > 7 && RN0 < 12)
 723     srcreg1 = REG_A0 + RN0 - 8;
 724   else if (RN0 > 11 && RN0 < 16)
 725     srcreg1 = REG_D0 + RN0 - 12;
 726   else
 727     srcreg1 = REG_E0 + RN0;
 728
 729   if (RM2 > 7 && RM2 < 12)
 730     srcreg2 = REG_A0 + RM2 - 8;
 731   else if (RM2 > 11 && RM2 < 16)
 732     srcreg2 = REG_D0 + RM2 - 12;
 733   else
 734     srcreg2 = REG_E0 + RM2;
 735   genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
 736 }
 737
 738 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
 739 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
 740 "mov"
 741 *am33
 742 {
 743   int srcreg, dstreg;
 744
 745   PC = cia;
 746   if (RN0 > 7 && RN0 < 12)
 747     dstreg = REG_A0 + RN0 - 8;
 748   else if (RN0 > 11 && RN0 < 16)
 749     dstreg = REG_D0 + RN0 - 12;
 750   else
 751     dstreg = REG_E0 + RN0;
 752
 753   if (XRM2 == 0)
 754     {
 755       State.regs[dstreg] = State.regs[REG_SP];
 756     }
 757   else
 758     abort ();
 759 }
 760
 761 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
 762 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
 763 "mov"
 764 *am33
 765 {
 766   int srcreg;
 767
 768   PC = cia;
 769
 770   if (RM2 > 7 && RM2 < 12)
 771     srcreg = REG_A0 + RM2 - 8;
 772   else if (RM2 > 11 && RM2 < 16)
 773     srcreg = REG_D0 + RM2 - 12;
 774   else
 775     srcreg = REG_E0 + RM2;
 776
 777   if (XRN0 == 0)
 778     {
 779       State.regs[REG_SP] = State.regs[srcreg];
 780     }
 781   else
 782     abort ();
 783 }
 784
 785 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
 786 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
 787 "and"
 788 *am33
 789 {
 790   int srcreg, dstreg;
 791   int z, n;
 792
 793   PC = cia;
 794
 795   if (RM2 > 7 && RM2 < 12)
 796     srcreg = REG_A0 + RM2 - 8;
 797   else if (RM2 > 11 && RM2 < 16)
 798     srcreg = REG_D0 + RM2 - 12;
 799   else
 800     srcreg = REG_E0 + RM2;
 801
 802   if (RN0 > 7 && RN0 < 12)
 803     dstreg = REG_A0 + RN0 - 8;
 804   else if (RN0 > 11 && RN0 < 16)
 805     dstreg = REG_D0 + RN0 - 12;
 806   else
 807     dstreg = REG_E0 + RN0;
 808
 809   State.regs[dstreg] &= State.regs[srcreg];
 810   z = (State.regs[dstreg] == 0);
 811   n = (State.regs[dstreg] & 0x80000000) != 0;
 812   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 813   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 814 }
 815
 816 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
 817 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
 818 "or"
 819 *am33
 820 {
 821   int srcreg, dstreg;
 822   int z, n;
 823
 824   PC = cia;
 825
 826   if (RM2 > 7 && RM2 < 12)
 827     srcreg = REG_A0 + RM2 - 8;
 828   else if (RM2 > 11 && RM2 < 16)
 829     srcreg = REG_D0 + RM2 - 12;
 830   else
 831     srcreg = REG_E0 + RM2;
 832
 833   if (RN0 > 7 && RN0 < 12)
 834     dstreg = REG_A0 + RN0 - 8;
 835   else if (RN0 > 11 && RN0 < 16)
 836     dstreg = REG_D0 + RN0 - 12;
 837   else
 838     dstreg = REG_E0 + RN0;
 839
 840   State.regs[dstreg] |= State.regs[srcreg];
 841   z = (State.regs[dstreg] == 0);
 842   n = (State.regs[dstreg] & 0x80000000) != 0;
 843   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 844   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 845 }
 846
 847 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
 848 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
 849 "xor"
 850 *am33
 851 {
 852   int srcreg, dstreg;
 853   int z, n;
 854
 855   PC = cia;
 856
 857   if (RM2 > 7 && RM2 < 12)
 858     srcreg = REG_A0 + RM2 - 8;
 859   else if (RM2 > 11 && RM2 < 16)
 860     srcreg = REG_D0 + RM2 - 12;
 861   else
 862     srcreg = REG_E0 + RM2;
 863
 864   if (RN0 > 7 && RN0 < 12)
 865     dstreg = REG_A0 + RN0 - 8;
 866   else if (RN0 > 11 && RN0 < 16)
 867     dstreg = REG_D0 + RN0 - 12;
 868   else
 869     dstreg = REG_E0 + RN0;
 870
 871   State.regs[dstreg] ^= State.regs[srcreg];
 872   z = (State.regs[dstreg] == 0);
 873   n = (State.regs[dstreg] & 0x80000000) != 0;
 874   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 875   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 876 }
 877
 878 // 1111 1001 0011 1001 Rn Rn; not Rn
 879 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
 880 "not"
 881 *am33
 882 {
 883   int dstreg;
 884   int z, n;
 885
 886   PC = cia;
 887
 888   if (RN0 > 7 && RN0 < 12)
 889     dstreg = REG_A0 + RN0 - 8;
 890   else if (RN0 > 11 && RN0 < 16)
 891     dstreg = REG_D0 + RN0 - 12;
 892   else
 893     dstreg = REG_E0 + RN0;
 894
 895   State.regs[dstreg] = ~State.regs[dstreg];
 896   z = (State.regs[dstreg] == 0);
 897   n = (State.regs[dstreg] & 0x80000000) != 0;
 898   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 899   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 900 }
 901
 902 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
 903 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
 904 "asr"
 905 *am33
 906 {
 907   int srcreg, dstreg;
 908   long temp;
 909   int c, z, n;
 910
 911   PC = cia;
 912
 913   if (RM2 > 7 && RM2 < 12)
 914     srcreg = REG_A0 + RM2 - 8;
 915   else if (RM2 > 11 && RM2 < 16)
 916     srcreg = REG_D0 + RM2 - 12;
 917   else
 918     srcreg = REG_E0 + RM2;
 919
 920   if (RN0 > 7 && RN0 < 12)
 921     dstreg = REG_A0 + RN0 - 8;
 922   else if (RN0 > 11 && RN0 < 16)
 923     dstreg = REG_D0 + RN0 - 12;
 924   else
 925     dstreg = REG_E0 + RN0;
 926
 927   temp = State.regs[dstreg];
 928   c = temp & 1;
 929   temp >>= State.regs[srcreg];
 930   State.regs[dstreg] = temp;
 931   z = (State.regs[dstreg] == 0);
 932   n = (State.regs[dstreg] & 0x80000000) != 0;
 933   PSW &= ~(PSW_Z | PSW_N | PSW_C);
 934   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 935 }
 936
 937 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
 938 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
 939 "lsr"
 940 *am33
 941 {
 942   int srcreg, dstreg;
 943   int z, n, c;
 944
 945   PC = cia;
 946
 947   if (RM2 > 7 && RM2 < 12)
 948     srcreg = REG_A0 + RM2 - 8;
 949   else if (RM2 > 11 && RM2 < 16)
 950     srcreg = REG_D0 + RM2 - 12;
 951   else
 952     srcreg = REG_E0 + RM2;
 953
 954   if (RN0 > 7 && RN0 < 12)
 955     dstreg = REG_A0 + RN0 - 8;
 956   else if (RN0 > 11 && RN0 < 16)
 957     dstreg = REG_D0 + RN0 - 12;
 958   else
 959     dstreg = REG_E0 + RN0;
 960
 961   c = State.regs[dstreg] & 1;
 962   State.regs[dstreg] >>= State.regs[srcreg];
 963   z = (State.regs[dstreg] == 0);
 964   n = (State.regs[dstreg] & 0x80000000) != 0;
 965   PSW &= ~(PSW_Z | PSW_N | PSW_C);
 966   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 967 }
 968
 969 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
 970 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
 971 "asl"
 972 *am33
 973 {
 974   int srcreg, dstreg;
 975   int z, n;
 976
 977   PC = cia;
 978
 979   if (RM2 > 7 && RM2 < 12)
 980     srcreg = REG_A0 + RM2 - 8;
 981   else if (RM2 > 11 && RM2 < 16)
 982     srcreg = REG_D0 + RM2 - 12;
 983   else
 984     srcreg = REG_E0 + RM2;
 985
 986   if (RN0 > 7 && RN0 < 12)
 987     dstreg = REG_A0 + RN0 - 8;
 988   else if (RN0 > 11 && RN0 < 16)
 989     dstreg = REG_D0 + RN0 - 12;
 990   else
 991     dstreg = REG_E0 + RN0;
 992
 993   State.regs[dstreg] <<= State.regs[srcreg];
 994   z = (State.regs[dstreg] == 0);
 995   n = (State.regs[dstreg] & 0x80000000) != 0;
 996   PSW &= ~(PSW_Z | PSW_N);
 997   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 998 }
 999
1000 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
1001 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
1002 "asl2"
1003 *am33
1004 {
1005   int dstreg;
1006   int n, z;
1007
1008   PC = cia;
1009
1010   if (RN0 > 7 && RN0 < 12)
1011     dstreg = REG_A0 + RN0 - 8;
1012   else if (RN0 > 11 && RN0 < 16)
1013     dstreg = REG_D0 + RN0 - 12;
1014   else
1015     dstreg = REG_E0 + RN0;
1016
1017   State.regs[dstreg] <<= 2;
1018   z = (State.regs[dstreg] == 0);
1019   n = (State.regs[dstreg] & 0x80000000) != 0;
1020   PSW &= ~(PSW_Z | PSW_N);
1021   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1022 }
1023
1024 // 1111 1001 1000 1001 Rn Rn; ror Rn
1025 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
1026 "ror"
1027 *am33
1028 {
1029   int dstreg;
1030   int c, n, z;
1031   unsigned long value;
1032
1033   PC = cia;
1034
1035   if (RN0 > 7 && RN0 < 12)
1036     dstreg = REG_A0 + RN0 - 8;
1037   else if (RN0 > 11 && RN0 < 16)
1038     dstreg = REG_D0 + RN0 - 12;
1039   else
1040     dstreg = REG_E0 + RN0;
1041
1042   value = State.regs[dstreg];
1043   c = (value & 0x1);
1044
1045   value >>= 1;
1046   value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1047   State.regs[dstreg] = value;
1048   z = (value == 0);
1049   n = (value & 0x80000000) != 0;
1050   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1051   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1052 }
1053
1054 // 1111 1001 1001 1001 Rn Rn; rol Rn
1055 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
1056 "rol"
1057 *am33
1058 {
1059   int dstreg;
1060   int c, n, z;
1061   unsigned long value;
1062
1063   PC = cia;
1064
1065   if (RN0 > 7 && RN0 < 12)
1066     dstreg = REG_A0 + RN0 - 8;
1067   else if (RN0 > 11 && RN0 < 16)
1068     dstreg = REG_D0 + RN0 - 12;
1069   else
1070     dstreg = REG_E0 + RN0;
1071
1072   value = State.regs[dstreg];
1073   c = (value & 0x80000000) ? 1 : 0;
1074
1075   value <<= 1;
1076   value |= ((PSW & PSW_C) != 0);
1077   State.regs[dstreg] = value;
1078   z = (value == 0);
1079   n = (value & 0x80000000) != 0;
1080   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1081   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1082 }
1083
1084 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
1085 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
1086 "mul"
1087 *am33
1088 {
1089   int srcreg, dstreg;
1090   unsigned long long temp;
1091   int n, z;
1092
1093   PC = cia;
1094
1095   if (RM2 > 7 && RM2 < 12)
1096     srcreg = REG_A0 + RM2 - 8;
1097   else if (RM2 > 11 && RM2 < 16)
1098     srcreg = REG_D0 + RM2 - 12;
1099   else
1100     srcreg = REG_E0 + RM2;
1101
1102   if (RN0 > 7 && RN0 < 12)
1103     dstreg = REG_A0 + RN0 - 8;
1104   else if (RN0 > 11 && RN0 < 16)
1105     dstreg = REG_D0 + RN0 - 12;
1106   else
1107     dstreg = REG_E0 + RN0;
1108
1109   temp = ((signed64)(signed32)State.regs[dstreg]
1110           *  (signed64)(signed32)State.regs[srcreg]);
1111   State.regs[dstreg] = temp & 0xffffffff;
1112   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1113   z = (State.regs[dstreg] == 0);
1114   n = (State.regs[dstreg] & 0x80000000) != 0;
1115   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1116   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1117 }
1118
1119 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
1120 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
1121 "mulu"
1122 *am33
1123 {
1124   int srcreg, dstreg;
1125   unsigned long long temp;
1126   int n, z;
1127
1128   PC = cia;
1129
1130   if (RM2 > 7 && RM2 < 12)
1131     srcreg = REG_A0 + RM2 - 8;
1132   else if (RM2 > 11 && RM2 < 16)
1133     srcreg = REG_D0 + RM2 - 12;
1134   else
1135     srcreg = REG_E0 + RM2;
1136
1137   if (RN0 > 7 && RN0 < 12)
1138     dstreg = REG_A0 + RN0 - 8;
1139   else if (RN0 > 11 && RN0 < 16)
1140     dstreg = REG_D0 + RN0 - 12;
1141   else
1142     dstreg = REG_E0 + RN0;
1143
1144   temp = ((unsigned64)State.regs[dstreg]
1145           * (unsigned64)State.regs[srcreg]);
1146   State.regs[dstreg] = temp & 0xffffffff;
1147   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1148   z = (State.regs[dstreg] == 0);
1149   n = (State.regs[dstreg] & 0x80000000) != 0;
1150   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1151   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1152 }
1153
1154 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
1155 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
1156 "div"
1157 *am33
1158 {
1159   int srcreg, dstreg;
1160   unsigned long long temp;
1161   int n, z;
1162
1163   PC = cia;
1164
1165   if (RM2 > 7 && RM2 < 12)
1166     srcreg = REG_A0 + RM2 - 8;
1167   else if (RM2 > 11 && RM2 < 16)
1168     srcreg = REG_D0 + RM2 - 12;
1169   else
1170     srcreg = REG_E0 + RM2;
1171
1172   if (RN0 > 7 && RN0 < 12)
1173     dstreg = REG_A0 + RN0 - 8;
1174   else if (RN0 > 11 && RN0 < 16)
1175     dstreg = REG_D0 + RN0 - 12;
1176   else
1177     dstreg = REG_E0 + RN0;
1178
1179   temp = State.regs[REG_MDR];
1180   temp <<= 32;
1181   temp |= State.regs[dstreg];
1182   State.regs[REG_MDR] = temp % (long)State.regs[srcreg];
1183   temp /= (long)State.regs[srcreg];
1184   State.regs[dstreg] = temp & 0xffffffff;
1185   z = (State.regs[dstreg] == 0);
1186   n = (State.regs[dstreg] & 0x80000000) != 0;
1187   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1188   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1189 }
1190
1191 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
1192 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
1193 "divu"
1194 *am33
1195 {
1196   int srcreg, dstreg;
1197   unsigned long long temp;
1198   int n, z;
1199
1200   PC = cia;
1201
1202   if (RM2 > 7 && RM2 < 12)
1203     srcreg = REG_A0 + RM2 - 8;
1204   else if (RM2 > 11 && RM2 < 16)
1205     srcreg = REG_D0 + RM2 - 12;
1206   else
1207     srcreg = REG_E0 + RM2;
1208
1209   if (RN0 > 7 && RN0 < 12)
1210     dstreg = REG_A0 + RN0 - 8;
1211   else if (RN0 > 11 && RN0 < 16)
1212     dstreg = REG_D0 + RN0 - 12;
1213   else
1214     dstreg = REG_E0 + RN0;
1215
1216   temp = State.regs[REG_MDR];
1217   temp <<= 32;
1218   temp |= State.regs[dstreg];
1219   State.regs[REG_MDR] = temp % State.regs[srcreg];
1220   temp /= State.regs[srcreg];
1221   State.regs[dstreg] = temp & 0xffffffff;
1222   z = (State.regs[dstreg] == 0);
1223   n = (State.regs[dstreg] & 0x80000000) != 0;
1224   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1225   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1226 }
1227
1228
1229 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
1230 8.0xf9+8.0x0a+4.RM2,4.RN0:D1h:::mov
1231 "mov"
1232 *am33
1233 {
1234   int srcreg, dstreg;
1235
1236   PC = cia;
1237
1238   if (RM2 > 7 && RM2 < 12)
1239     srcreg = REG_A0 + RM2 - 8;
1240   else if (RM2 > 11 && RM2 < 16)
1241     srcreg = REG_D0 + RM2 - 12;
1242   else
1243     srcreg = REG_E0 + RM2;
1244
1245   if (RN0 > 7 && RN0 < 12)
1246     dstreg = REG_A0 + RN0 - 8;
1247   else if (RN0 > 11 && RN0 < 16)
1248     dstreg = REG_D0 + RN0 - 12;
1249   else
1250     dstreg = REG_E0 + RN0;
1251
1252   if (RN0 > 7 && RN0 < 12)
1253     dstreg = REG_A0 + RN0 - 8;
1254   else if (RN0 > 11 && RN0 < 16)
1255     dstreg = REG_D0 + RN0 - 12;
1256   else
1257     dstreg = REG_E0 + RN0;
1258
1259   State.regs[dstreg] = load_word (State.regs[srcreg]);
1260 }
1261
1262 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
1263 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
1264 "mov"
1265 *am33
1266 {
1267   int srcreg, dstreg;
1268
1269   PC = cia;
1270
1271   if (RM2 > 7 && RM2 < 12)
1272     srcreg = REG_A0 + RM2 - 8;
1273   else if (RM2 > 11 && RM2 < 16)
1274     srcreg = REG_D0 + RM2 - 12;
1275   else
1276     srcreg = REG_E0 + RM2;
1277
1278   if (RN0 > 7 && RN0 < 12)
1279     dstreg = REG_A0 + RN0 - 8;
1280   else if (RN0 > 11 && RN0 < 16)
1281     dstreg = REG_D0 + RN0 - 12;
1282   else
1283     dstreg = REG_E0 + RN0;
1284
1285   if (RN0 > 7 && RN0 < 12)
1286     dstreg = REG_A0 + RN0 - 8;
1287   else if (RN0 > 11 && RN0 < 16)
1288     dstreg = REG_D0 + RN0 - 12;
1289   else
1290     dstreg = REG_E0 + RN0;
1291
1292   store_word (State.regs[dstreg], State.regs[srcreg]);
1293 }
1294
1295 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
1296 8.0xf9+8.0x2a+4.RM2,4.RN0:D1g:::movbu
1297 "movbu"
1298 *am33
1299 {
1300   int srcreg, dstreg;
1301
1302   PC = cia;
1303
1304   if (RM2 > 7 && RM2 < 12)
1305     srcreg = REG_A0 + RM2 - 8;
1306   else if (RM2 > 11 && RM2 < 16)
1307     srcreg = REG_D0 + RM2 - 12;
1308   else
1309     srcreg = REG_E0 + RM2;
1310
1311   if (RN0 > 7 && RN0 < 12)
1312     dstreg = REG_A0 + RN0 - 8;
1313   else if (RN0 > 11 && RN0 < 16)
1314     dstreg = REG_D0 + RN0 - 12;
1315   else
1316     dstreg = REG_E0 + RN0;
1317
1318   if (RN0 > 7 && RN0 < 12)
1319     dstreg = REG_A0 + RN0 - 8;
1320   else if (RN0 > 11 && RN0 < 16)
1321     dstreg = REG_D0 + RN0 - 12;
1322   else
1323     dstreg = REG_E0 + RN0;
1324
1325   State.regs[dstreg] = load_byte (State.regs[srcreg]);
1326 }
1327
1328 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
1329 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
1330 "movbu"
1331 *am33
1332 {
1333   int srcreg, dstreg;
1334
1335   PC = cia;
1336
1337   if (RM2 > 7 && RM2 < 12)
1338     srcreg = REG_A0 + RM2 - 8;
1339   else if (RM2 > 11 && RM2 < 16)
1340     srcreg = REG_D0 + RM2 - 12;
1341   else
1342     srcreg = REG_E0 + RM2;
1343
1344   if (RN0 > 7 && RN0 < 12)
1345     dstreg = REG_A0 + RN0 - 8;
1346   else if (RN0 > 11 && RN0 < 16)
1347     dstreg = REG_D0 + RN0 - 12;
1348   else
1349     dstreg = REG_E0 + RN0;
1350
1351   if (RN0 > 7 && RN0 < 12)
1352     dstreg = REG_A0 + RN0 - 8;
1353   else if (RN0 > 11 && RN0 < 16)
1354     dstreg = REG_D0 + RN0 - 12;
1355   else
1356     dstreg = REG_E0 + RN0;
1357
1358   store_byte (State.regs[dstreg], State.regs[srcreg]);
1359 }
1360
1361 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
1362 8.0xf9+8.0x4a+4.RM2,4.RN0:D1g:::movhu
1363 "movhu"
1364 *am33
1365 {
1366   int srcreg, dstreg;
1367
1368   PC = cia;
1369
1370   if (RM2 > 7 && RM2 < 12)
1371     srcreg = REG_A0 + RM2 - 8;
1372   else if (RM2 > 11 && RM2 < 16)
1373     srcreg = REG_D0 + RM2 - 12;
1374   else
1375     srcreg = REG_E0 + RM2;
1376
1377   if (RN0 > 7 && RN0 < 12)
1378     dstreg = REG_A0 + RN0 - 8;
1379   else if (RN0 > 11 && RN0 < 16)
1380     dstreg = REG_D0 + RN0 - 12;
1381   else
1382     dstreg = REG_E0 + RN0;
1383
1384   if (RN0 > 7 && RN0 < 12)
1385     dstreg = REG_A0 + RN0 - 8;
1386   else if (RN0 > 11 && RN0 < 16)
1387     dstreg = REG_D0 + RN0 - 12;
1388   else
1389     dstreg = REG_E0 + RN0;
1390
1391   State.regs[dstreg] = load_half (State.regs[srcreg]);
1392 }
1393
1394 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1395 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1396 "movhu"
1397 *am33
1398 {
1399   int srcreg, dstreg;
1400
1401   PC = cia;
1402
1403   if (RM2 > 7 && RM2 < 12)
1404     srcreg = REG_A0 + RM2 - 8;
1405   else if (RM2 > 11 && RM2 < 16)
1406     srcreg = REG_D0 + RM2 - 12;
1407   else
1408     srcreg = REG_E0 + RM2;
1409
1410   if (RN0 > 7 && RN0 < 12)
1411     dstreg = REG_A0 + RN0 - 8;
1412   else if (RN0 > 11 && RN0 < 16)
1413     dstreg = REG_D0 + RN0 - 12;
1414   else
1415     dstreg = REG_E0 + RN0;
1416
1417   if (RN0 > 7 && RN0 < 12)
1418     dstreg = REG_A0 + RN0 - 8;
1419   else if (RN0 > 11 && RN0 < 16)
1420     dstreg = REG_D0 + RN0 - 12;
1421   else
1422     dstreg = REG_E0 + RN0;
1423
1424   store_half (State.regs[dstreg], State.regs[srcreg]);
1425 }
1426
1427 // ??? mov
1428 // ??? mov
1429
1430 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1431 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1432 "mov"
1433 *am33
1434 {
1435   int srcreg, dstreg;
1436
1437   PC = cia;
1438
1439   if (RN2 > 7 && RN2 < 12)
1440     dstreg = REG_A0 + RN2 - 8;
1441   else if (RN2 > 11 && RN2 < 16)
1442     dstreg = REG_D0 + RN2 - 12;
1443   else
1444     dstreg = REG_E0 + RN2;
1445
1446   State.regs[dstreg] = load_word (State.regs[REG_SP]);
1447 }
1448
1449 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1450 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1451 "mov"
1452 *am33
1453 {
1454   int srcreg, dstreg;
1455
1456   PC = cia;
1457
1458   if (RM2 > 7 && RM2 < 12)
1459     dstreg = REG_A0 + RM2 - 8;
1460   else if (RM2 > 11 && RM2 < 16)
1461     dstreg = REG_D0 + RM2 - 12;
1462   else
1463     dstreg = REG_E0 + RM2;
1464
1465   store_word (State.regs[REG_SP], State.regs[dstreg]);
1466 }
1467
1468 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1469 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1470 "movbu"
1471 *am33
1472 {
1473   int srcreg, dstreg;
1474
1475   PC = cia;
1476
1477   if (RN2 > 7 && RN2 < 12)
1478     dstreg = REG_A0 + RN2 - 8;
1479   else if (RN2 > 11 && RN2 < 16)
1480     dstreg = REG_D0 + RN2 - 12;
1481   else
1482     dstreg = REG_E0 + RN2;
1483
1484   State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1485 }
1486
1487 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1488 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1489 "movbu"
1490 *am33
1491 {
1492   int srcreg, dstreg;
1493
1494   PC = cia;
1495
1496   if (RM2 > 7 && RM2 < 12)
1497     dstreg = REG_A0 + RM2 - 8;
1498   else if (RM2 > 11 && RM2 < 16)
1499     dstreg = REG_D0 + RM2 - 12;
1500   else
1501     dstreg = REG_E0 + RM2;
1502
1503   store_byte (State.regs[REG_SP], State.regs[dstreg]);
1504 }
1505
1506 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1507 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1508 "movhu"
1509 *am33
1510 {
1511   int srcreg, dstreg;
1512
1513   PC = cia;
1514
1515   if (RN2 > 7 && RN2 < 12)
1516     dstreg = REG_A0 + RN2 - 8;
1517   else if (RN2 > 11 && RN2 < 16)
1518     dstreg = REG_D0 + RN2 - 12;
1519   else
1520     dstreg = REG_E0 + RN2;
1521
1522   State.regs[dstreg] = load_half (State.regs[REG_SP]);
1523 }
1524
1525 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1526 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1527 "movhu"
1528 *am33
1529 {
1530   int srcreg, dstreg;
1531
1532   PC = cia;
1533
1534   if (RM2 > 7 && RM2 < 12)
1535     dstreg = REG_A0 + RM2 - 8;
1536   else if (RM2 > 11 && RM2 < 16)
1537     dstreg = REG_D0 + RM2 - 12;
1538   else
1539     dstreg = REG_E0 + RM2;
1540
1541   store_half (State.regs[REG_SP], State.regs[dstreg]);
1542 }
1543
1544 // ??? movhu
1545 // ??? movhu
1546 // ??? mac
1547 // ??? macu
1548 // ??? macb
1549 // ??? macbu
1550 // ??? mach
1551 // ??? machu
1552 // ??? dmach
1553 // ??? dmachu
1554 // ??? dmulh
1555 // ??? dmulhu
1556 // ??? sat16
1557 // ??? mcste
1558 // ??? swap
1559 // ??? bsch
1560
1561 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1562 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1563 "mov"
1564 *am33
1565 {
1566   int dstreg;
1567
1568   PC = cia;
1569
1570   if (RN0 > 7 && RN0 < 12)
1571     dstreg = REG_A0 + RN0 - 8;
1572   else if (RN0 > 11 && RN0 < 16)
1573     dstreg = REG_D0 + RN0 - 12;
1574   else
1575     dstreg = REG_E0 + RN0;
1576
1577   State.regs[dstreg] = EXTEND8 (IMM8);
1578 }
1579
1580 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1581 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1582 "movu"
1583 *am33
1584 {
1585   int dstreg;
1586
1587   PC = cia;
1588
1589   if (RN0 > 7 && RN0 < 12)
1590     dstreg = REG_A0 + RN0 - 8;
1591   else if (RN0 > 11 && RN0 < 16)
1592     dstreg = REG_D0 + RN0 - 12;
1593   else
1594     dstreg = REG_E0 + RN0;
1595
1596   State.regs[dstreg] = IMM8 & 0xff;
1597 }
1598
1599 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1600 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1601 "add"
1602 *am33
1603 {
1604   int dstreg;
1605
1606   PC = cia;
1607
1608   if (RN0 > 7 && RN0 < 12)
1609     dstreg = REG_A0 + RN0 - 8;
1610   else if (RN0 > 11 && RN0 < 16)
1611     dstreg = REG_D0 + RN0 - 12;
1612   else
1613     dstreg = REG_E0 + RN0;
1614
1615   genericAdd (EXTEND8 (IMM8), dstreg);
1616 }
1617
1618 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1619 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1620 "addc"
1621 *am33
1622 {
1623   int dstreg, imm;
1624   int z, c, n, v;
1625   unsigned long reg1, reg2, sum;
1626
1627   PC = cia;
1628
1629   if (RN0 > 7 && RN0 < 12)
1630     dstreg = REG_A0 + RN0 - 8;
1631   else if (RN0 > 11 && RN0 < 16)
1632     dstreg = REG_D0 + RN0 - 12;
1633   else
1634     dstreg = REG_E0 + RN0;
1635
1636   imm = EXTEND8 (IMM8);
1637   reg2 = State.regs[dstreg];
1638   sum = imm + reg2 + ((PSW & PSW_C) != 0);
1639   State.regs[dstreg] = sum;
1640
1641   z = (sum == 0);
1642   n = (sum & 0x80000000);
1643   c = (sum < imm) || (sum < reg2);
1644   v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1645        && (reg2 & 0x80000000) != (sum & 0x80000000));
1646
1647   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1648   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1649           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1650 }
1651
1652 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1653 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1654 "sub"
1655 *am33
1656 {
1657   int dstreg;
1658
1659   PC = cia;
1660
1661   if (RN0 > 7 && RN0 < 12)
1662     dstreg = REG_A0 + RN0 - 8;
1663   else if (RN0 > 11 && RN0 < 16)
1664     dstreg = REG_D0 + RN0 - 12;
1665   else
1666     dstreg = REG_E0 + RN0;
1667
1668   genericSub (EXTEND8 (IMM8), dstreg);
1669 }
1670
1671 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1672 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1673 "subc"
1674 *am33
1675 {
1676   int imm, dstreg;
1677   int z, c, n, v;
1678   unsigned long reg1, reg2, difference;
1679
1680   PC = cia;
1681
1682   if (RN0 > 7 && RN0 < 12)
1683     dstreg = REG_A0 + RN0 - 8;
1684   else if (RN0 > 11 && RN0 < 16)
1685     dstreg = REG_D0 + RN0 - 12;
1686   else
1687     dstreg = REG_E0 + RN0;
1688
1689   imm = EXTEND8 (IMM8);
1690   reg2 = State.regs[dstreg];
1691   difference = reg2 - imm - ((PSW & PSW_C) != 0);
1692   State.regs[dstreg] = difference;
1693
1694   z = (difference == 0);
1695   n = (difference & 0x80000000);
1696   c = (imm > reg2);
1697   v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1698        && (reg2 & 0x80000000) != (difference & 0x80000000));
1699
1700   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1701   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1702           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1703 }
1704
1705 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1706 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1707 "cmp"
1708 *am33
1709 {
1710   int srcreg;
1711
1712   PC = cia;
1713
1714   if (RN0 > 7 && RN0 < 12)
1715     srcreg = REG_A0 + RN0 - 8;
1716   else if (RN0 > 11 && RN0 < 16)
1717     srcreg = REG_D0 + RN0 - 12;
1718   else
1719     srcreg = REG_E0 + RN0;
1720
1721   genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1722 }
1723
1724 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1725 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1726 "mov"
1727 *am33
1728 {
1729   int dstreg;
1730
1731   PC = cia;
1732
1733   if (XRN0 == 0)
1734     State.regs[REG_SP] = EXTEND8 (IMM8);
1735   else
1736     abort ();
1737 }
1738
1739 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1740 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1741 "and"
1742 *am33
1743 {
1744   int dstreg;
1745   int z, n;
1746
1747   PC = cia;
1748
1749   if (RN0 > 7 && RN0 < 12)
1750     dstreg = REG_A0 + RN0 - 8;
1751   else if (RN0 > 11 && RN0 < 16)
1752     dstreg = REG_D0 + RN0 - 12;
1753   else
1754     dstreg = REG_E0 + RN0;
1755
1756   State.regs[dstreg] &= (IMM8 & 0xff);
1757   z = (State.regs[dstreg] == 0);
1758   n = (State.regs[dstreg] & 0x80000000) != 0;
1759   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1760   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1761 }
1762
1763 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1764 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1765 "or"
1766 *am33
1767 {
1768   int dstreg;
1769   int z, n;
1770
1771   PC = cia;
1772
1773   if (RN0 > 7 && RN0 < 12)
1774     dstreg = REG_A0 + RN0 - 8;
1775   else if (RN0 > 11 && RN0 < 16)
1776     dstreg = REG_D0 + RN0 - 12;
1777   else
1778     dstreg = REG_E0 + RN0;
1779
1780   State.regs[dstreg] |= (IMM8 & 0xff);
1781   z = (State.regs[dstreg] == 0);
1782   n = (State.regs[dstreg] & 0x80000000) != 0;
1783   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1784   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1785 }
1786
1787 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1788 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1789 "xor"
1790 *am33
1791 {
1792   int dstreg;
1793   int z, n;
1794
1795   PC = cia;
1796
1797   if (RN0 > 7 && RN0 < 12)
1798     dstreg = REG_A0 + RN0 - 8;
1799   else if (RN0 > 11 && RN0 < 16)
1800     dstreg = REG_D0 + RN0 - 12;
1801   else
1802     dstreg = REG_E0 + RN0;
1803
1804   State.regs[dstreg] ^= (IMM8 & 0xff);
1805   z = (State.regs[dstreg] == 0);
1806   n = (State.regs[dstreg] & 0x80000000) != 0;
1807   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1808   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1809 }
1810
1811 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1812 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1813 "asr"
1814 *am33
1815 {
1816   int dstreg;
1817   long temp;
1818   int c, z, n;
1819
1820   PC = cia;
1821
1822   if (RN0 > 7 && RN0 < 12)
1823     dstreg = REG_A0 + RN0 - 8;
1824   else if (RN0 > 11 && RN0 < 16)
1825     dstreg = REG_D0 + RN0 - 12;
1826   else
1827     dstreg = REG_E0 + RN0;
1828
1829   temp = State.regs[dstreg];
1830   c = temp & 1;
1831   temp >>= (IMM8 & 0xff);
1832   State.regs[dstreg] = temp;
1833   z = (State.regs[dstreg] == 0);
1834   n = (State.regs[dstreg] & 0x80000000) != 0;
1835   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1836   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1837 }
1838
1839 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1840 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1841 "lsr"
1842 *am33
1843 {
1844   int dstreg;
1845   int z, n, c;
1846
1847   PC = cia;
1848
1849   if (RN0 > 7 && RN0 < 12)
1850     dstreg = REG_A0 + RN0 - 8;
1851   else if (RN0 > 11 && RN0 < 16)
1852     dstreg = REG_D0 + RN0 - 12;
1853   else
1854     dstreg = REG_E0 + RN0;
1855
1856   c = State.regs[dstreg] & 1;
1857   State.regs[dstreg] >>= (IMM8 & 0xff);
1858   z = (State.regs[dstreg] == 0);
1859   n = (State.regs[dstreg] & 0x80000000) != 0;
1860   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1861   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1862 }
1863
1864 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1865 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1866 "asl"
1867 *am33
1868 {
1869   int srcreg, dstreg;
1870   int z, n;
1871
1872   PC = cia;
1873
1874   if (RN0 > 7 && RN0 < 12)
1875     dstreg = REG_A0 + RN0 - 8;
1876   else if (RN0 > 11 && RN0 < 16)
1877     dstreg = REG_D0 + RN0 - 12;
1878   else
1879     dstreg = REG_E0 + RN0;
1880
1881   State.regs[dstreg] <<= (IMM8 & 0xff);
1882   z = (State.regs[dstreg] == 0);
1883   n = (State.regs[dstreg] & 0x80000000) != 0;
1884   PSW &= ~(PSW_Z | PSW_N);
1885   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1886 }
1887
1888 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1889 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1890 "mul"
1891 *am33
1892 {
1893   int dstreg;
1894   unsigned long long temp;
1895   int z, n;
1896
1897   PC = cia;
1898
1899   if (RN0 > 7 && RN0 < 12)
1900     dstreg = REG_A0 + RN0 - 8;
1901   else if (RN0 > 11 && RN0 < 16)
1902     dstreg = REG_D0 + RN0 - 12;
1903   else
1904     dstreg = REG_E0 + RN0;
1905
1906   temp = ((signed64)(signed32)State.regs[dstreg]
1907           *  (signed64)(signed32)EXTEND8 (IMM8));
1908   State.regs[dstreg] = temp & 0xffffffff;
1909   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1910   z = (State.regs[dstreg] == 0);
1911   n = (State.regs[dstreg] & 0x80000000) != 0;
1912   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1913   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1914 }
1915
1916 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1917 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1918 "mulu"
1919 *am33
1920 {
1921   int dstreg;
1922   unsigned long long temp;
1923   int z, n;
1924
1925   PC = cia;
1926
1927   if (RN0 > 7 && RN0 < 12)
1928     dstreg = REG_A0 + RN0 - 8;
1929   else if (RN0 > 11 && RN0 < 16)
1930     dstreg = REG_D0 + RN0 - 12;
1931   else
1932     dstreg = REG_E0 + RN0;
1933
1934   temp = ((unsigned64)State.regs[dstreg]
1935           * (unsigned64)(IMM8 & 0xff));
1936   State.regs[dstreg] = temp & 0xffffffff;
1937   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1938   z = (State.regs[dstreg] == 0);
1939   n = (State.regs[dstreg] & 0x80000000) != 0;
1940   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1941   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1942 }
1943
1944 // ??? btst
1945
1946 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1947 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1948 "mov"
1949 {
1950   int srcreg, dstreg;
1951
1952   PC = cia;
1953
1954   if (RM0 > 7 && RM0 < 12)
1955     srcreg = REG_A0 + RM0 - 8;
1956   else if (RM0 > 11 && RM0 < 16)
1957     srcreg = REG_D0 + RM0 - 12;
1958   else
1959     srcreg = REG_E0 + RM0;
1960
1961   if (RN2 > 7 && RN2 < 12)
1962     dstreg = REG_A0 + RN2 - 8;
1963   else if (RN2 > 11 && RN2 < 16)
1964     dstreg = REG_D0 + RN2 - 12;
1965   else
1966     dstreg = REG_E0 + RN2;
1967
1968   State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1969 }
1970
1971 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1972 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1973 "mov"
1974 {
1975   int srcreg, dstreg;
1976
1977   PC = cia;
1978
1979   if (RM2 > 7 && RM2 < 12)
1980     srcreg = REG_A0 + RM2 - 8;
1981   else if (RM2 > 11 && RM2 < 16)
1982     srcreg = REG_D0 + RM2 - 12;
1983   else
1984     srcreg = REG_E0 + RM2;
1985
1986   if (RN0 > 7 && RN0 < 12)
1987     dstreg = REG_A0 + RN0 - 8;
1988   else if (RN0 > 11 && RN0 < 16)
1989     dstreg = REG_D0 + RN0 - 12;
1990   else
1991     dstreg = REG_E0 + RN0;
1992
1993   store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1994 }
1995
1996 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1997 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1998 "movbu"
1999 {
2000   int srcreg, dstreg;
2001
2002   PC = cia;
2003
2004   if (RM0 > 7 && RM0 < 12)
2005     srcreg = REG_A0 + RM0 - 8;
2006   else if (RM0 > 11 && RM0 < 16)
2007     srcreg = REG_D0 + RM0 - 12;
2008   else
2009     srcreg = REG_E0 + RM0;
2010
2011   if (RN2 > 7 && RN2 < 12)
2012     dstreg = REG_A0 + RN2 - 8;
2013   else if (RN2 > 11 && RN2 < 16)
2014     dstreg = REG_D0 + RN2 - 12;
2015   else
2016     dstreg = REG_E0 + RN2;
2017
2018   State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
2019 }
2020
2021 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
2022 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
2023 "movbu"
2024 {
2025   int srcreg, dstreg;
2026
2027   PC = cia;
2028
2029   if (RM2 > 7 && RM2 < 12)
2030     srcreg = REG_A0 + RM2 - 8;
2031   else if (RM2 > 11 && RM2 < 16)
2032     srcreg = REG_D0 + RM2 - 12;
2033   else
2034     srcreg = REG_E0 + RM2;
2035
2036   if (RN0 > 7 && RN0 < 12)
2037     dstreg = REG_A0 + RN0 - 8;
2038   else if (RN0 > 11 && RN0 < 16)
2039     dstreg = REG_D0 + RN0 - 12;
2040   else
2041     dstreg = REG_E0 + RN0;
2042
2043   store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2044 }
2045
2046 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
2047 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
2048 "movhu"
2049 {
2050   int srcreg, dstreg;
2051
2052   PC = cia;
2053
2054   if (RM0 > 7 && RM0 < 12)
2055     srcreg = REG_A0 + RM0 - 8;
2056   else if (RM0 > 11 && RM0 < 16)
2057     srcreg = REG_D0 + RM0 - 12;
2058   else
2059     srcreg = REG_E0 + RM0;
2060
2061   if (RN2 > 7 && RN2 < 12)
2062     dstreg = REG_A0 + RN2 - 8;
2063   else if (RN2 > 11 && RN2 < 16)
2064     dstreg = REG_D0 + RN2 - 12;
2065   else
2066     dstreg = REG_E0 + RN2;
2067
2068   State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2069 }
2070
2071 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
2072 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
2073 "movhu"
2074 {
2075   int srcreg, dstreg;
2076
2077   PC = cia;
2078
2079   if (RM2 > 7 && RM2 < 12)
2080     srcreg = REG_A0 + RM2 - 8;
2081   else if (RM2 > 11 && RM2 < 16)
2082     srcreg = REG_D0 + RM2 - 12;
2083   else
2084     srcreg = REG_E0 + RM2;
2085
2086   if (RN0 > 7 && RN0 < 12)
2087     dstreg = REG_A0 + RN0 - 8;
2088   else if (RN0 > 11 && RN0 < 16)
2089     dstreg = REG_D0 + RN0 - 12;
2090   else
2091     dstreg = REG_E0 + RN0;
2092
2093   store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2094 }
2095
2096 // ??? mov
2097 // ??? mov
2098
2099 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2100 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2101 "mov"
2102 {
2103   int dstreg;
2104
2105   PC = cia;
2106
2107   if (RN2 > 7 && RN2 < 12)
2108     dstreg = REG_A0 + RN2 - 8;
2109   else if (RN2 > 11 && RN2 < 16)
2110     dstreg = REG_D0 + RN2 - 12;
2111   else
2112     dstreg = REG_E0 + RN2;
2113
2114   State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2115 }
2116
2117 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2118 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2119 "mov"
2120 {
2121   int srcreg;
2122
2123   PC = cia;
2124
2125   if (RM2 > 7 && RM2 < 12)
2126     srcreg = REG_A0 + RM2 - 8;
2127   else if (RM2 > 11 && RM2 < 16)
2128     srcreg = REG_D0 + RM2 - 12;
2129   else
2130     srcreg = REG_E0 + RM2;
2131
2132   store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2133 }
2134
2135 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2136 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2137 "movbu"
2138 {
2139   int dstreg;
2140
2141   PC = cia;
2142
2143   if (RN2 > 7 && RN2 < 12)
2144     dstreg = REG_A0 + RN2 - 8;
2145   else if (RN2 > 11 && RN2 < 16)
2146     dstreg = REG_D0 + RN2 - 12;
2147   else
2148     dstreg = REG_E0 + RN2;
2149
2150   State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2151 }
2152
2153 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2154 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2155 "movbu"
2156 {
2157   int srcreg;
2158
2159   PC = cia;
2160
2161   if (RM2 > 7 && RM2 < 12)
2162     srcreg = REG_A0 + RM2 - 8;
2163   else if (RM2 > 11 && RM2 < 16)
2164     srcreg = REG_D0 + RM2 - 12;
2165   else
2166     srcreg = REG_E0 + RM2;
2167
2168   store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2169 }
2170
2171 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2172 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2173 "movhu"
2174 {
2175   int dstreg;
2176
2177   PC = cia;
2178
2179   if (RN2 > 7 && RN2 < 12)
2180     dstreg = REG_A0 + RN2 - 8;
2181   else if (RN2 > 11 && RN2 < 16)
2182     dstreg = REG_D0 + RN2 - 12;
2183   else
2184     dstreg = REG_E0 + RN2;
2185
2186   State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2187 }
2188
2189 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2190 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2191 "movhu"
2192 {
2193   int srcreg;
2194
2195   PC = cia;
2196
2197   if (RM2 > 7 && RM2 < 12)
2198     srcreg = REG_A0 + RM2 - 8;
2199   else if (RM2 > 11 && RM2 < 16)
2200     srcreg = REG_D0 + RM2 - 12;
2201   else
2202     srcreg = REG_E0 + RM2;
2203
2204   store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2205 }
2206
2207 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2208 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2209 "add"
2210 *am33
2211 {
2212   int z, c, n, v;
2213   unsigned long sum;
2214   int srcreg1, srcreg2, dstreg;
2215
2216   PC = cia;
2217
2218   if (RM2 > 7 && RM2 < 12)
2219     srcreg1 = REG_A0 + RM2 - 8;
2220   else if (RM2 > 11 && RM2 < 16)
2221     srcreg1 = REG_D0 + RM2 - 12;
2222   else
2223     srcreg1 = REG_E0 + RM2;
2224
2225   if (RN0 > 7 && RN0 < 12)
2226     srcreg2 = REG_A0 + RN0 - 8;
2227   else if (RN0 > 11 && RN0 < 16)
2228     srcreg2 = REG_D0 + RN0 - 12;
2229   else
2230     srcreg2 = REG_E0 + RN0;
2231
2232   if (RD0 > 7 && RD0 < 12)
2233     dstreg = REG_A0 + RD0 - 8;
2234   else if (RD0 > 11 && RD0 < 16)
2235     dstreg = REG_D0 + RD0 - 12;
2236   else
2237     dstreg = REG_E0 + RD0;
2238
2239   sum = source1 + source2;
2240   State.regs[dstreg] = sum;
2241
2242   z = (sum == 0);
2243   n = (sum & 0x80000000);
2244   c = (sum < source1) || (sum < source2);
2245   v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2246        && (source1 & 0x80000000) != (sum & 0x80000000));
2247
2248   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2249   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2250           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2251 }
2252
2253 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
2254 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
2255 "cmp"
2256 *am33
2257 {
2258   int srcreg;
2259
2260   PC = cia;
2261
2262   if (RN0 > 7 && RN0 < 12)
2263     srcreg = REG_A0 + RN0 - 8;
2264   else if (RN0 > 11 && RN0 < 16)
2265     srcreg = REG_D0 + RN0 - 12;
2266   else
2267     srcreg = REG_E0 + RN0;
2268
2269   genericCmp (FETCH24(IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
2270 }
2271
2272 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
2273 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
2274 "mov"
2275 *am33
2276 {
2277   int dstreg;
2278
2279   PC = cia;
2280
2281   if (RN0 > 7 && RN0 < 12)
2282     dstreg = REG_A0 + RN0 - 8;
2283   else if (RN0 > 11 && RN0 < 16)
2284     dstreg = REG_D0 + RN0 - 12;
2285   else
2286     dstreg = REG_E0 + RN0;
2287
2288   State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2289 }
2290
2291 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
2292 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
2293 "movu"
2294 *am33
2295 {
2296   int dstreg;
2297
2298   PC = cia;
2299
2300   if (RN0 > 7 && RN0 < 12)
2301     dstreg = REG_A0 + RN0 - 8;
2302   else if (RN0 > 11 && RN0 < 16)
2303     dstreg = REG_D0 + RN0 - 12;
2304   else
2305     dstreg = REG_E0 + RN0;
2306
2307   State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2308 }
2309
2310 // 1111 1110 0000 1000 Rn Rn IMM32; add imm32,Rn
2311 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
2312 "mov"
2313 *am33
2314 {
2315   int dstreg;
2316
2317   PC = cia;
2318
2319   if (RN0 > 7 && RN0 < 12)
2320     dstreg = REG_A0 + RN0 - 8;
2321   else if (RN0 > 11 && RN0 < 16)
2322     dstreg = REG_D0 + RN0 - 12;
2323   else
2324     dstreg = REG_E0 + RN0;
2325
2326   genericAdd (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
2327 }
2328
2329 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
2330 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
2331 "cmp"
2332 *am33
2333 {
2334   int srcreg;
2335
2336   PC = cia;
2337
2338   if (RN0 > 7 && RN0 < 12)
2339     srcreg = REG_A0 + RN0 - 8;
2340   else if (RN0 > 11 && RN0 < 16)
2341     srcreg = REG_D0 + RN0 - 12;
2342   else
2343     srcreg = REG_E0 + RN0;
2344
2345   genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
2346 }
2347