sim/moxie/interp.c

   1 /* Simulator for the moxie processor
   2    Copyright (C) 2008-2014 Free Software Foundation, Inc.
   3    Contributed by Anthony Green
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include <fcntl.h>
  22 #include <signal.h>
  23 #include <stdlib.h>
  24 #include "sysdep.h"
  25 #include <sys/times.h>
  26 #include <sys/param.h>
  27 #include <netinet/in.h> /* for byte ordering macros */
  28 #include "bfd.h"
  29 #include "gdb/callback.h"
  30 #include "libiberty.h"
  31 #include "gdb/remote-sim.h"
  32
  33 #include "sim-main.h"
  34 #include "sim-base.h"
  35
  36 typedef int word;
  37 typedef unsigned int uword;
  38
  39 host_callback *       callback;
  40
  41 FILE *tracefile;
  42
  43 /* Extract the signed 10-bit offset from a 16-bit branch
  44    instruction.  */
  45 #define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
  46
  47 #define EXTRACT_WORD(addr) \
  48   ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
  49    + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
  50    + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
  51    + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
  52
  53 unsigned long
  54 moxie_extract_unsigned_integer (addr, len)
  55      unsigned char * addr;
  56      int len;
  57 {
  58   unsigned long retval;
  59   unsigned char * p;
  60   unsigned char * startaddr = (unsigned char *)addr;
  61   unsigned char * endaddr = startaddr + len;
  62
  63   if (len > (int) sizeof (unsigned long))
  64     printf ("That operation is not available on integers of more than %d bytes.",
  65             sizeof (unsigned long));
  66
  67   /* Start at the most significant end of the integer, and work towards
  68      the least significant.  */
  69   retval = 0;
  70
  71   for (p = endaddr; p > startaddr;)
  72     retval = (retval << 8) | * -- p;
  73
  74   return retval;
  75 }
  76
  77 void
  78 moxie_store_unsigned_integer (addr, len, val)
  79      unsigned char * addr;
  80      int len;
  81      unsigned long val;
  82 {
  83   unsigned char * p;
  84   unsigned char * startaddr = (unsigned char *)addr;
  85   unsigned char * endaddr = startaddr + len;
  86
  87   for (p = endaddr; p > startaddr;)
  88     {
  89       * -- p = val & 0xff;
  90       val >>= 8;
  91     }
  92 }
  93
  94 /* moxie register names.  */
  95 static const char *reg_names[16] =
  96   { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
  97     "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
  98
  99 /* The machine state.
 100
 101    This state is maintained in host byte order.  The fetch/store
 102    register functions must translate between host byte order and the
 103    target processor byte order.  Keeping this data in target byte
 104    order simplifies the register read/write functions.  Keeping this
 105    data in native order improves the performance of the simulator.
 106    Simulation speed is deemed more important.  */
 107
 108 #define NUM_MOXIE_REGS 17 /* Including PC */
 109 #define NUM_MOXIE_SREGS 256 /* The special registers */
 110 #define PC_REGNO     16
 111
 112 /* The ordering of the moxie_regset structure is matched in the
 113    gdb/config/moxie/tm-moxie.h file in the REGISTER_NAMES macro.  */
 114 struct moxie_regset
 115 {
 116   word            regs[NUM_MOXIE_REGS + 1]; /* primary registers */
 117   word            sregs[256];             /* special registers */
 118   word            cc;                   /* the condition code reg */
 119   int             exception;
 120   unsigned long long insts;                /* instruction counter */
 121 };
 122
 123 #define CC_GT  1<<0
 124 #define CC_LT  1<<1
 125 #define CC_EQ  1<<2
 126 #define CC_GTU 1<<3
 127 #define CC_LTU 1<<4
 128
 129 union
 130 {
 131   struct moxie_regset asregs;
 132   word asints [1];              /* but accessed larger... */
 133 } cpu;
 134
 135 static char *myname;
 136 static SIM_OPEN_KIND sim_kind;
 137 static int issue_messages = 0;
 138
 139 void
 140 sim_size (int s)
 141 {
 142 }
 143
 144 static void
 145 set_initial_gprs ()
 146 {
 147   int i;
 148   long space;
 149
 150   /* Set up machine just out of reset.  */
 151   cpu.asregs.regs[PC_REGNO] = 0;
 152
 153   /* Clean out the register contents.  */
 154   for (i = 0; i < NUM_MOXIE_REGS; i++)
 155     cpu.asregs.regs[i] = 0;
 156   for (i = 0; i < NUM_MOXIE_SREGS; i++)
 157     cpu.asregs.sregs[i] = 0;
 158 }
 159
 160 /* Write a 1 byte value to memory.  */
 161
 162 static void INLINE
 163 wbat (sim_cpu *scpu, word pc, word x, word v)
 164 {
 165   address_word cia = CIA_GET (scpu);
 166
 167   sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
 168 }
 169
 170 /* Write a 2 byte value to memory.  */
 171
 172 static void INLINE
 173 wsat (sim_cpu *scpu, word pc, word x, word v)
 174 {
 175   address_word cia = CIA_GET (scpu);
 176
 177   sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
 178 }
 179
 180 /* Write a 4 byte value to memory.  */
 181
 182 static void INLINE
 183 wlat (sim_cpu *scpu, word pc, word x, word v)
 184 {
 185   address_word cia = CIA_GET (scpu);
 186
 187   sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
 188 }
 189
 190 /* Read 2 bytes from memory.  */
 191
 192 static int INLINE
 193 rsat (sim_cpu *scpu, word pc, word x)
 194 {
 195   address_word cia = CIA_GET (scpu);
 196
 197   return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
 198 }
 199
 200 /* Read 1 byte from memory.  */
 201
 202 static int INLINE
 203 rbat (sim_cpu *scpu, word pc, word x)
 204 {
 205   address_word cia = CIA_GET (scpu);
 206
 207   return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
 208 }
 209
 210 /* Read 4 bytes from memory.  */
 211
 212 static int INLINE
 213 rlat (sim_cpu *scpu, word pc, word x)
 214 {
 215   address_word cia = CIA_GET (scpu);
 216
 217   return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
 218 }
 219
 220 #define CHECK_FLAG(T,H) if (tflags & T) { hflags |= H; tflags ^= T; }
 221
 222 unsigned int
 223 convert_target_flags (unsigned int tflags)
 224 {
 225   unsigned int hflags = 0x0;
 226
 227   CHECK_FLAG(0x0001, O_WRONLY);
 228   CHECK_FLAG(0x0002, O_RDWR);
 229   CHECK_FLAG(0x0008, O_APPEND);
 230   CHECK_FLAG(0x0200, O_CREAT);
 231   CHECK_FLAG(0x0400, O_TRUNC);
 232   CHECK_FLAG(0x0800, O_EXCL);
 233   CHECK_FLAG(0x2000, O_SYNC);
 234
 235   if (tflags != 0x0)
 236     fprintf (stderr,
 237              "Simulator Error: problem converting target open flags for host.  0x%x\n",
 238              tflags);
 239
 240   return hflags;
 241 }
 242
 243 #define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
 244
 245 static int tracing = 0;
 246
 247 void
 248 sim_resume (sd, step, siggnal)
 249      SIM_DESC sd;
 250      int step, siggnal;
 251 {
 252   word pc, opc;
 253   unsigned long long insts;
 254   unsigned short inst;
 255   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
 256   address_word cia = CIA_GET (scpu);
 257
 258   cpu.asregs.exception = step ? SIGTRAP: 0;
 259   pc = cpu.asregs.regs[PC_REGNO];
 260   insts = cpu.asregs.insts;
 261
 262   /* Run instructions here. */
 263   do
 264     {
 265       opc = pc;
 266
 267       /* Fetch the instruction at pc.  */
 268       inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8)
 269         + sim_core_read_aligned_1 (scpu, cia, read_map, pc+1);
 270
 271       /* Decode instruction.  */
 272       if (inst & (1 << 15))
 273         {
 274           if (inst & (1 << 14))
 275             {
 276               /* This is a Form 3 instruction.  */
 277               int opcode = (inst >> 10 & 0xf);
 278
 279               switch (opcode)
 280                 {
 281                 case 0x00: /* beq */
 282                   {
 283                     TRACE("beq");
 284                     if (cpu.asregs.cc & CC_EQ)
 285                       pc += INST2OFFSET(inst);
 286                   }
 287                   break;
 288                 case 0x01: /* bne */
 289                   {
 290                     TRACE("bne");
 291                     if (! (cpu.asregs.cc & CC_EQ))
 292                       pc += INST2OFFSET(inst);
 293                   }
 294                   break;
 295                 case 0x02: /* blt */
 296                   {
 297                     TRACE("blt");
 298                     if (cpu.asregs.cc & CC_LT)
 299                       pc += INST2OFFSET(inst);
 300                   }               break;
 301                 case 0x03: /* bgt */
 302                   {
 303                     TRACE("bgt");
 304                     if (cpu.asregs.cc & CC_GT)
 305                       pc += INST2OFFSET(inst);
 306                   }
 307                   break;
 308                 case 0x04: /* bltu */
 309                   {
 310                     TRACE("bltu");
 311                     if (cpu.asregs.cc & CC_LTU)
 312                       pc += INST2OFFSET(inst);
 313                   }
 314                   break;
 315                 case 0x05: /* bgtu */
 316                   {
 317                     TRACE("bgtu");
 318                     if (cpu.asregs.cc & CC_GTU)
 319                       pc += INST2OFFSET(inst);
 320                   }
 321                   break;
 322                 case 0x06: /* bge */
 323                   {
 324                     TRACE("bge");
 325                     if (cpu.asregs.cc & (CC_GT | CC_EQ))
 326                       pc += INST2OFFSET(inst);
 327                   }
 328                   break;
 329                 case 0x07: /* ble */
 330                   {
 331                     TRACE("ble");
 332                     if (cpu.asregs.cc & (CC_LT | CC_EQ))
 333                       pc += INST2OFFSET(inst);
 334                   }
 335                   break;
 336                 case 0x08: /* bgeu */
 337                   {
 338                     TRACE("bgeu");
 339                     if (cpu.asregs.cc & (CC_GTU | CC_EQ))
 340                       pc += INST2OFFSET(inst);
 341                   }
 342                   break;
 343                 case 0x09: /* bleu */
 344                   {
 345                     TRACE("bleu");
 346                     if (cpu.asregs.cc & (CC_LTU | CC_EQ))
 347                       pc += INST2OFFSET(inst);
 348                   }
 349                   break;
 350                 default:
 351                   {
 352                     TRACE("SIGILL3");
 353                     cpu.asregs.exception = SIGILL;
 354                     break;
 355                   }
 356                 }
 357             }
 358           else
 359             {
 360               /* This is a Form 2 instruction.  */
 361               int opcode = (inst >> 12 & 0x3);
 362               switch (opcode)
 363                 {
 364                 case 0x00: /* inc */
 365                   {
 366                     int a = (inst >> 8) & 0xf;
 367                     unsigned av = cpu.asregs.regs[a];
 368                     unsigned v = (inst & 0xff);
 369                     TRACE("inc");
 370                     cpu.asregs.regs[a] = av + v;
 371                   }
 372                   break;
 373                 case 0x01: /* dec */
 374                   {
 375                     int a = (inst >> 8) & 0xf;
 376                     unsigned av = cpu.asregs.regs[a];
 377                     unsigned v = (inst & 0xff);
 378                     TRACE("dec");
 379                     cpu.asregs.regs[a] = av - v;
 380                   }
 381                   break;
 382                 case 0x02: /* gsr */
 383                   {
 384                     int a = (inst >> 8) & 0xf;
 385                     unsigned v = (inst & 0xff);
 386                     TRACE("gsr");
 387                     cpu.asregs.regs[a] = cpu.asregs.sregs[v];
 388                   }
 389                   break;
 390                 case 0x03: /* ssr */
 391                   {
 392                     int a = (inst >> 8) & 0xf;
 393                     unsigned v = (inst & 0xff);
 394                     TRACE("ssr");
 395                     cpu.asregs.sregs[v] = cpu.asregs.regs[a];
 396                   }
 397                   break;
 398                 default:
 399                   TRACE("SIGILL2");
 400                   cpu.asregs.exception = SIGILL;
 401                   break;
 402                 }
 403             }
 404         }
 405       else
 406         {
 407           /* This is a Form 1 instruction.  */
 408           int opcode = inst >> 8;
 409           switch (opcode)
 410             {
 411             case 0x00: /* bad */
 412               opc = opcode;
 413               TRACE("SIGILL0");
 414               cpu.asregs.exception = SIGILL;
 415               break;
 416             case 0x01: /* ldi.l (immediate) */
 417               {
 418                 int reg = (inst >> 4) & 0xf;
 419                 TRACE("ldi.l");
 420                 unsigned int val = EXTRACT_WORD(pc+2);
 421                 cpu.asregs.regs[reg] = val;
 422                 pc += 4;
 423               }
 424               break;
 425             case 0x02: /* mov (register-to-register) */
 426               {
 427                 int dest  = (inst >> 4) & 0xf;
 428                 int src = (inst ) & 0xf;
 429                 TRACE("mov");
 430                 cpu.asregs.regs[dest] = cpu.asregs.regs[src];
 431               }
 432               break;
 433             case 0x03: /* jsra */
 434               {
 435                 unsigned int fn = EXTRACT_WORD(pc+2);
 436                 unsigned int sp = cpu.asregs.regs[1];
 437                 TRACE("jsra");
 438                 /* Save a slot for the static chain.  */
 439                 sp -= 4;
 440
 441                 /* Push the return address.  */
 442                 sp -= 4;
 443                 wlat (scpu, opc, sp, pc + 6);
 444
 445                 /* Push the current frame pointer.  */
 446                 sp -= 4;
 447                 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
 448
 449                 /* Uncache the stack pointer and set the pc and $fp.  */
 450                 cpu.asregs.regs[1] = sp;
 451                 cpu.asregs.regs[0] = sp;
 452                 pc = fn - 2;
 453               }
 454               break;
 455             case 0x04: /* ret */
 456               {
 457                 unsigned int sp = cpu.asregs.regs[0];
 458
 459                 TRACE("ret");
 460
 461                 /* Pop the frame pointer.  */
 462                 cpu.asregs.regs[0] = rlat (scpu, opc, sp);
 463                 sp += 4;
 464
 465                 /* Pop the return address.  */
 466                 pc = rlat (scpu, opc, sp) - 2;
 467                 sp += 4;
 468
 469                 /* Skip over the static chain slot.  */
 470                 sp += 4;
 471
 472                 /* Uncache the stack pointer.  */
 473                 cpu.asregs.regs[1] = sp;
 474               }
 475               break;
 476             case 0x05: /* add.l */
 477               {
 478                 int a = (inst >> 4) & 0xf;
 479                 int b = inst & 0xf;
 480                 unsigned av = cpu.asregs.regs[a];
 481                 unsigned bv = cpu.asregs.regs[b];
 482                 TRACE("add.l");
 483                 cpu.asregs.regs[a] = av + bv;
 484               }
 485               break;
 486             case 0x06: /* push */
 487               {
 488                 int a = (inst >> 4) & 0xf;
 489                 int b = inst & 0xf;
 490                 int sp = cpu.asregs.regs[a] - 4;
 491                 TRACE("push");
 492                 wlat (scpu, opc, sp, cpu.asregs.regs[b]);
 493                 cpu.asregs.regs[a] = sp;
 494               }
 495               break;
 496             case 0x07: /* pop */
 497               {
 498                 int a = (inst >> 4) & 0xf;
 499                 int b = inst & 0xf;
 500                 int sp = cpu.asregs.regs[a];
 501                 TRACE("pop");
 502                 cpu.asregs.regs[b] = rlat (scpu, opc, sp);
 503                 cpu.asregs.regs[a] = sp + 4;
 504               }
 505               break;
 506             case 0x08: /* lda.l */
 507               {
 508                 int reg = (inst >> 4) & 0xf;
 509                 unsigned int addr = EXTRACT_WORD(pc+2);
 510                 TRACE("lda.l");
 511                 cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
 512                 pc += 4;
 513               }
 514               break;
 515             case 0x09: /* sta.l */
 516               {
 517                 int reg = (inst >> 4) & 0xf;
 518                 unsigned int addr = EXTRACT_WORD(pc+2);
 519                 TRACE("sta.l");
 520                 wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
 521                 pc += 4;
 522               }
 523               break;
 524             case 0x0a: /* ld.l (register indirect) */
 525               {
 526                 int src  = inst & 0xf;
 527                 int dest = (inst >> 4) & 0xf;
 528                 int xv;
 529                 TRACE("ld.l");
 530                 xv = cpu.asregs.regs[src];
 531                 cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
 532               }
 533               break;
 534             case 0x0b: /* st.l */
 535               {
 536                 int dest = (inst >> 4) & 0xf;
 537                 int val  = inst & 0xf;
 538                 TRACE("st.l");
 539                 wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
 540               }
 541               break;
 542             case 0x0c: /* ldo.l */
 543               {
 544                 unsigned int addr = EXTRACT_WORD(pc+2);
 545                 int a = (inst >> 4) & 0xf;
 546                 int b = inst & 0xf;
 547                 TRACE("ldo.l");
 548                 addr += cpu.asregs.regs[b];
 549                 cpu.asregs.regs[a] = rlat (scpu, opc, addr);
 550                 pc += 4;
 551               }
 552               break;
 553             case 0x0d: /* sto.l */
 554               {
 555                 unsigned int addr = EXTRACT_WORD(pc+2);
 556                 int a = (inst >> 4) & 0xf;
 557                 int b = inst & 0xf;
 558                 TRACE("sto.l");
 559                 addr += cpu.asregs.regs[a];
 560                 wlat (scpu, opc, addr, cpu.asregs.regs[b]);
 561                 pc += 4;
 562               }
 563               break;
 564             case 0x0e: /* cmp */
 565               {
 566                 int a  = (inst >> 4) & 0xf;
 567                 int b  = inst & 0xf;
 568                 int cc = 0;
 569                 int va = cpu.asregs.regs[a];
 570                 int vb = cpu.asregs.regs[b];
 571
 572                 TRACE("cmp");
 573
 574                 if (va == vb)
 575                   cc = CC_EQ;
 576                 else
 577                   {
 578                     cc |= (va < vb ? CC_LT : 0);
 579                     cc |= (va > vb ? CC_GT : 0);
 580                     cc |= ((unsigned int) va < (unsigned int) vb ? CC_LTU : 0);
 581                     cc |= ((unsigned int) va > (unsigned int) vb ? CC_GTU : 0);
 582                   }
 583
 584                 cpu.asregs.cc = cc;
 585               }
 586               break;
 587             case 0x0f: /* nop */
 588               break;
 589             case 0x10: /* sex.b */
 590               {
 591                 int a = (inst >> 4) & 0xf;
 592                 int b = inst & 0xf;
 593                 signed char bv = cpu.asregs.regs[b];
 594                 TRACE("sex.b");
 595                 cpu.asregs.regs[a] = (int) bv;
 596               }
 597               break;
 598             case 0x11: /* sex.s */
 599               {
 600                 int a = (inst >> 4) & 0xf;
 601                 int b = inst & 0xf;
 602                 signed short bv = cpu.asregs.regs[b];
 603                 TRACE("sex.s");
 604                 cpu.asregs.regs[a] = (int) bv;
 605               }
 606               break;
 607             case 0x12: /* zex.b */
 608               {
 609                 int a = (inst >> 4) & 0xf;
 610                 int b = inst & 0xf;
 611                 signed char bv = cpu.asregs.regs[b];
 612                 TRACE("zex.b");
 613                 cpu.asregs.regs[a] = (int) bv & 0xff;
 614               }
 615               break;
 616             case 0x13: /* zex.s */
 617               {
 618                 int a = (inst >> 4) & 0xf;
 619                 int b = inst & 0xf;
 620                 signed short bv = cpu.asregs.regs[b];
 621                 TRACE("zex.s");
 622                 cpu.asregs.regs[a] = (int) bv & 0xffff;
 623               }
 624               break;
 625             case 0x14: /* bad */
 626             case 0x15: /* bad */
 627             case 0x16: /* bad */
 628             case 0x17: /* bad */
 629             case 0x18: /* bad */
 630               {
 631                 opc = opcode;
 632                 TRACE("SIGILL0");
 633                 cpu.asregs.exception = SIGILL;
 634                 break;
 635               }
 636             case 0x19: /* jsr */
 637               {
 638                 unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
 639                 unsigned int sp = cpu.asregs.regs[1];
 640
 641                 TRACE("jsr");
 642
 643                 /* Save a slot for the static chain.  */
 644                 sp -= 4;
 645
 646                 /* Push the return address.  */
 647                 sp -= 4;
 648                 wlat (scpu, opc, sp, pc + 2);
 649
 650                 /* Push the current frame pointer.  */
 651                 sp -= 4;
 652                 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
 653
 654                 /* Uncache the stack pointer and set the fp & pc.  */
 655                 cpu.asregs.regs[1] = sp;
 656                 cpu.asregs.regs[0] = sp;
 657                 pc = fn - 2;
 658               }
 659               break;
 660             case 0x1a: /* jmpa */
 661               {
 662                 unsigned int tgt = EXTRACT_WORD(pc+2);
 663                 TRACE("jmpa");
 664                 pc = tgt - 2;
 665               }
 666               break;
 667             case 0x1b: /* ldi.b (immediate) */
 668               {
 669                 int reg = (inst >> 4) & 0xf;
 670
 671                 unsigned int val = EXTRACT_WORD(pc+2);
 672                 TRACE("ldi.b");
 673                 cpu.asregs.regs[reg] = val;
 674                 pc += 4;
 675               }
 676               break;
 677             case 0x1c: /* ld.b (register indirect) */
 678               {
 679                 int src  = inst & 0xf;
 680                 int dest = (inst >> 4) & 0xf;
 681                 int xv;
 682                 TRACE("ld.b");
 683                 xv = cpu.asregs.regs[src];
 684                 cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
 685               }
 686               break;
 687             case 0x1d: /* lda.b */
 688               {
 689                 int reg = (inst >> 4) & 0xf;
 690                 unsigned int addr = EXTRACT_WORD(pc+2);
 691                 TRACE("lda.b");
 692                 cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
 693                 pc += 4;
 694               }
 695               break;
 696             case 0x1e: /* st.b */
 697               {
 698                 int dest = (inst >> 4) & 0xf;
 699                 int val  = inst & 0xf;
 700                 TRACE("st.b");
 701                 wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
 702               }
 703               break;
 704             case 0x1f: /* sta.b */
 705               {
 706                 int reg = (inst >> 4) & 0xf;
 707                 unsigned int addr = EXTRACT_WORD(pc+2);
 708                 TRACE("sta.b");
 709                 wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
 710                 pc += 4;
 711               }
 712               break;
 713             case 0x20: /* ldi.s (immediate) */
 714               {
 715                 int reg = (inst >> 4) & 0xf;
 716
 717                 unsigned int val = EXTRACT_WORD(pc+2);
 718                 TRACE("ldi.s");
 719                 cpu.asregs.regs[reg] = val;
 720                 pc += 4;
 721               }
 722               break;
 723             case 0x21: /* ld.s (register indirect) */
 724               {
 725                 int src  = inst & 0xf;
 726                 int dest = (inst >> 4) & 0xf;
 727                 int xv;
 728                 TRACE("ld.s");
 729                 xv = cpu.asregs.regs[src];
 730                 cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
 731               }
 732               break;
 733             case 0x22: /* lda.s */
 734               {
 735                 int reg = (inst >> 4) & 0xf;
 736                 unsigned int addr = EXTRACT_WORD(pc+2);
 737                 TRACE("lda.s");
 738                 cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
 739                 pc += 4;
 740               }
 741               break;
 742             case 0x23: /* st.s */
 743               {
 744                 int dest = (inst >> 4) & 0xf;
 745                 int val  = inst & 0xf;
 746                 TRACE("st.s");
 747                 wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
 748               }
 749               break;
 750             case 0x24: /* sta.s */
 751               {
 752                 int reg = (inst >> 4) & 0xf;
 753                 unsigned int addr = EXTRACT_WORD(pc+2);
 754                 TRACE("sta.s");
 755                 wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
 756                 pc += 4;
 757               }
 758               break;
 759             case 0x25: /* jmp */
 760               {
 761                 int reg = (inst >> 4) & 0xf;
 762                 TRACE("jmp");
 763                 pc = cpu.asregs.regs[reg] - 2;
 764               }
 765               break;
 766             case 0x26: /* and */
 767               {
 768                 int a = (inst >> 4) & 0xf;
 769                 int b = inst & 0xf;
 770                 int av, bv;
 771                 TRACE("and");
 772                 av = cpu.asregs.regs[a];
 773                 bv = cpu.asregs.regs[b];
 774                 cpu.asregs.regs[a] = av & bv;
 775               }
 776               break;
 777             case 0x27: /* lshr */
 778               {
 779                 int a = (inst >> 4) & 0xf;
 780                 int b = inst & 0xf;
 781                 int av = cpu.asregs.regs[a];
 782                 int bv = cpu.asregs.regs[b];
 783                 TRACE("lshr");
 784                 cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
 785               }
 786               break;
 787             case 0x28: /* ashl */
 788               {
 789                 int a = (inst >> 4) & 0xf;
 790                 int b = inst & 0xf;
 791                 int av = cpu.asregs.regs[a];
 792                 int bv = cpu.asregs.regs[b];
 793                 TRACE("ashl");
 794                 cpu.asregs.regs[a] = av << bv;
 795               }
 796               break;
 797             case 0x29: /* sub.l */
 798               {
 799                 int a = (inst >> 4) & 0xf;
 800                 int b = inst & 0xf;
 801                 unsigned av = cpu.asregs.regs[a];
 802                 unsigned bv = cpu.asregs.regs[b];
 803                 TRACE("sub.l");
 804                 cpu.asregs.regs[a] = av - bv;
 805               }
 806               break;
 807             case 0x2a: /* neg */
 808               {
 809                 int a  = (inst >> 4) & 0xf;
 810                 int b  = inst & 0xf;
 811                 int bv = cpu.asregs.regs[b];
 812                 TRACE("neg");
 813                 cpu.asregs.regs[a] = - bv;
 814               }
 815               break;
 816             case 0x2b: /* or */
 817               {
 818                 int a = (inst >> 4) & 0xf;
 819                 int b = inst & 0xf;
 820                 int av, bv;
 821                 TRACE("or");
 822                 av = cpu.asregs.regs[a];
 823                 bv = cpu.asregs.regs[b];
 824                 cpu.asregs.regs[a] = av | bv;
 825               }
 826               break;
 827             case 0x2c: /* not */
 828               {
 829                 int a = (inst >> 4) & 0xf;
 830                 int b = inst & 0xf;
 831                 int bv = cpu.asregs.regs[b];
 832                 TRACE("not");
 833                 cpu.asregs.regs[a] = 0xffffffff ^ bv;
 834               }
 835               break;
 836             case 0x2d: /* ashr */
 837               {
 838                 int a  = (inst >> 4) & 0xf;
 839                 int b  = inst & 0xf;
 840                 int av = cpu.asregs.regs[a];
 841                 int bv = cpu.asregs.regs[b];
 842                 TRACE("ashr");
 843                 cpu.asregs.regs[a] = av >> bv;
 844               }
 845               break;
 846             case 0x2e: /* xor */
 847               {
 848                 int a = (inst >> 4) & 0xf;
 849                 int b = inst & 0xf;
 850                 int av, bv;
 851                 TRACE("xor");
 852                 av = cpu.asregs.regs[a];
 853                 bv = cpu.asregs.regs[b];
 854                 cpu.asregs.regs[a] = av ^ bv;
 855               }
 856               break;
 857             case 0x2f: /* mul.l */
 858               {
 859                 int a = (inst >> 4) & 0xf;
 860                 int b = inst & 0xf;
 861                 unsigned av = cpu.asregs.regs[a];
 862                 unsigned bv = cpu.asregs.regs[b];
 863                 TRACE("mul.l");
 864                 cpu.asregs.regs[a] = av * bv;
 865               }
 866               break;
 867             case 0x30: /* swi */
 868               {
 869                 unsigned int inum = EXTRACT_WORD(pc+2);
 870                 TRACE("swi");
 871                 /* Set the special registers appropriately.  */
 872                 cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
 873                 cpu.asregs.sregs[3] = inum;
 874                 switch (inum)
 875                   {
 876                   case 0x1: /* SYS_exit */
 877                     {
 878                       cpu.asregs.exception = SIGQUIT;
 879                       break;
 880                     }
 881                   case 0x2: /* SYS_open */
 882                     {
 883                       char fname[1024];
 884                       int mode = (int) convert_target_flags ((unsigned) cpu.asregs.regs[3]);
 885                       int perm = (int) cpu.asregs.regs[4];
 886                       int fd = open (fname, mode, perm);
 887                       sim_core_read_buffer (sd, scpu, read_map, fname,
 888                                             cpu.asregs.regs[2], 1024);
 889                       /* FIXME - set errno */
 890                       cpu.asregs.regs[2] = fd;
 891                       break;
 892                     }
 893                   case 0x4: /* SYS_read */
 894                     {
 895                       int fd = cpu.asregs.regs[2];
 896                       unsigned len = (unsigned) cpu.asregs.regs[4];
 897                       char *buf = malloc (len);
 898                       cpu.asregs.regs[2] = read (fd, buf, len);
 899                       sim_core_write_buffer (sd, scpu, write_map, buf,
 900                                              cpu.asregs.regs[3], len);
 901                       free (buf);
 902                       break;
 903                     }
 904                   case 0x5: /* SYS_write */
 905                     {
 906                       char *str;
 907                       /* String length is at 0x12($fp) */
 908                       unsigned count, len = (unsigned) cpu.asregs.regs[4];
 909                       str = malloc (len);
 910                       sim_core_read_buffer (sd, scpu, read_map, str,
 911                                             cpu.asregs.regs[3], len);
 912                       count = write (cpu.asregs.regs[2], str, len);
 913                       free (str);
 914                       cpu.asregs.regs[2] = count;
 915                       break;
 916                     }
 917                   case 0xffffffff: /* Linux System Call */
 918                     {
 919                       unsigned int handler = cpu.asregs.sregs[1];
 920                       unsigned int sp = cpu.asregs.regs[1];
 921
 922                       /* Save a slot for the static chain.  */
 923                       sp -= 4;
 924
 925                       /* Push the return address.  */
 926                       sp -= 4;
 927                       wlat (scpu, opc, sp, pc + 6);
 928
 929                       /* Push the current frame pointer.  */
 930                       sp -= 4;
 931                       wlat (scpu, opc, sp, cpu.asregs.regs[0]);
 932
 933                       /* Uncache the stack pointer and set the fp & pc.  */
 934                       cpu.asregs.regs[1] = sp;
 935                       cpu.asregs.regs[0] = sp;
 936                       pc = handler - 6;
 937                     }
 938                   default:
 939                     break;
 940                   }
 941                 pc += 4;
 942               }
 943               break;
 944             case 0x31: /* div.l */
 945               {
 946                 int a = (inst >> 4) & 0xf;
 947                 int b = inst & 0xf;
 948                 int av = cpu.asregs.regs[a];
 949                 int bv = cpu.asregs.regs[b];
 950                 TRACE("div.l");
 951                 cpu.asregs.regs[a] = av / bv;
 952               }
 953               break;
 954             case 0x32: /* udiv.l */
 955               {
 956                 int a = (inst >> 4) & 0xf;
 957                 int b = inst & 0xf;
 958                 unsigned int av = cpu.asregs.regs[a];
 959                 unsigned int bv = cpu.asregs.regs[b];
 960                 TRACE("udiv.l");
 961                 cpu.asregs.regs[a] = (av / bv);
 962               }
 963               break;
 964             case 0x33: /* mod.l */
 965               {
 966                 int a = (inst >> 4) & 0xf;
 967                 int b = inst & 0xf;
 968                 int av = cpu.asregs.regs[a];
 969                 int bv = cpu.asregs.regs[b];
 970                 TRACE("mod.l");
 971                 cpu.asregs.regs[a] = av % bv;
 972               }
 973               break;
 974             case 0x34: /* umod.l */
 975               {
 976                 int a = (inst >> 4) & 0xf;
 977                 int b = inst & 0xf;
 978                 unsigned int av = cpu.asregs.regs[a];
 979                 unsigned int bv = cpu.asregs.regs[b];
 980                 TRACE("umod.l");
 981                 cpu.asregs.regs[a] = (av % bv);
 982               }
 983               break;
 984             case 0x35: /* brk */
 985               TRACE("brk");
 986               cpu.asregs.exception = SIGTRAP;
 987               pc -= 2; /* Adjust pc */
 988               break;
 989             case 0x36: /* ldo.b */
 990               {
 991                 unsigned int addr = EXTRACT_WORD(pc+2);
 992                 int a = (inst >> 4) & 0xf;
 993                 int b = inst & 0xf;
 994                 TRACE("ldo.b");
 995                 addr += cpu.asregs.regs[b];
 996                 cpu.asregs.regs[a] = rbat (scpu, opc, addr);
 997                 pc += 4;
 998               }
 999               break;
1000             case 0x37: /* sto.b */
1001               {
1002                 unsigned int addr = EXTRACT_WORD(pc+2);
1003                 int a = (inst >> 4) & 0xf;
1004                 int b = inst & 0xf;
1005                 TRACE("sto.b");
1006                 addr += cpu.asregs.regs[a];
1007                 wbat (scpu, opc, addr, cpu.asregs.regs[b]);
1008                 pc += 4;
1009               }
1010               break;
1011             case 0x38: /* ldo.s */
1012               {
1013                 unsigned int addr = EXTRACT_WORD(pc+2);
1014                 int a = (inst >> 4) & 0xf;
1015                 int b = inst & 0xf;
1016                 TRACE("ldo.s");
1017                 addr += cpu.asregs.regs[b];
1018                 cpu.asregs.regs[a] = rsat (scpu, opc, addr);
1019                 pc += 4;
1020               }
1021               break;
1022             case 0x39: /* sto.s */
1023               {
1024                 unsigned int addr = EXTRACT_WORD(pc+2);
1025                 int a = (inst >> 4) & 0xf;
1026                 int b = inst & 0xf;
1027                 TRACE("sto.s");
1028                 addr += cpu.asregs.regs[a];
1029                 wsat (scpu, opc, addr, cpu.asregs.regs[b]);
1030                 pc += 4;
1031               }
1032               break;
1033             default:
1034               opc = opcode;
1035               TRACE("SIGILL1");
1036               cpu.asregs.exception = SIGILL;
1037               break;
1038             }
1039         }
1040
1041       insts++;
1042       pc += 2;
1043
1044     } while (!cpu.asregs.exception);
1045
1046   /* Hide away the things we've cached while executing.  */
1047   cpu.asregs.regs[PC_REGNO] = pc;
1048   cpu.asregs.insts += insts;            /* instructions done ... */
1049 }
1050
1051 int
1052 sim_write (sd, addr, buffer, size)
1053      SIM_DESC sd;
1054      SIM_ADDR addr;
1055      const unsigned char * buffer;
1056      int size;
1057 {
1058   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1059
1060   sim_core_write_buffer (sd, scpu, write_map, buffer, addr, size);
1061
1062   return size;
1063 }
1064
1065 int
1066 sim_read (sd, addr, buffer, size)
1067      SIM_DESC sd;
1068      SIM_ADDR addr;
1069      unsigned char * buffer;
1070      int size;
1071 {
1072   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1073
1074   sim_core_read_buffer (sd, scpu, read_map, buffer, addr, size);
1075
1076   return size;
1077 }
1078
1079
1080 int
1081 sim_store_register (sd, rn, memory, length)
1082      SIM_DESC sd;
1083      int rn;
1084      unsigned char * memory;
1085      int length;
1086 {
1087   if (rn < NUM_MOXIE_REGS && rn >= 0)
1088     {
1089       if (length == 4)
1090         {
1091           long ival;
1092
1093           /* misalignment safe */
1094           ival = moxie_extract_unsigned_integer (memory, 4);
1095           cpu.asints[rn] = ival;
1096         }
1097
1098       return 4;
1099     }
1100   else
1101     return 0;
1102 }
1103
1104 int
1105 sim_fetch_register (sd, rn, memory, length)
1106      SIM_DESC sd;
1107      int rn;
1108      unsigned char * memory;
1109      int length;
1110 {
1111   if (rn < NUM_MOXIE_REGS && rn >= 0)
1112     {
1113       if (length == 4)
1114         {
1115           long ival = cpu.asints[rn];
1116
1117           /* misalignment-safe */
1118           moxie_store_unsigned_integer (memory, 4, ival);
1119         }
1120
1121       return 4;
1122     }
1123   else
1124     return 0;
1125 }
1126
1127
1128 int
1129 sim_trace (sd)
1130      SIM_DESC sd;
1131 {
1132   if (tracefile == 0)
1133     tracefile = fopen("trace.csv", "wb");
1134
1135   tracing = 1;
1136
1137   sim_resume (sd, 0, 0);
1138
1139   tracing = 0;
1140
1141   return 1;
1142 }
1143
1144 void
1145 sim_stop_reason (sd, reason, sigrc)
1146      SIM_DESC sd;
1147      enum sim_stop * reason;
1148      int * sigrc;
1149 {
1150   if (cpu.asregs.exception == SIGQUIT)
1151     {
1152       * reason = sim_exited;
1153       * sigrc = cpu.asregs.regs[2];
1154     }
1155   else
1156     {
1157       * reason = sim_stopped;
1158       * sigrc = cpu.asregs.exception;
1159     }
1160 }
1161
1162
1163 int
1164 sim_stop (sd)
1165      SIM_DESC sd;
1166 {
1167   cpu.asregs.exception = SIGINT;
1168   return 1;
1169 }
1170
1171
1172 void
1173 sim_info (sd, verbose)
1174      SIM_DESC sd;
1175      int verbose;
1176 {
1177   callback->printf_filtered (callback, "\n\n# instructions executed  %llu\n",
1178                              cpu.asregs.insts);
1179 }
1180
1181
1182 SIM_DESC
1183 sim_open (kind, cb, abfd, argv)
1184      SIM_OPEN_KIND kind;
1185      host_callback * cb;
1186      struct bfd * abfd;
1187      char ** argv;
1188 {
1189   SIM_DESC sd = sim_state_alloc (kind, cb);
1190   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1191
1192   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1193     return 0;
1194
1195   sim_do_command(sd," memory region 0x00000000,0x4000000") ;
1196   sim_do_command(sd," memory region 0xE0000000,0x10000") ;
1197
1198   myname = argv[0];
1199   callback = cb;
1200
1201   if (kind == SIM_OPEN_STANDALONE)
1202     issue_messages = 1;
1203
1204   set_initial_gprs ();  /* Reset the GPR registers.  */
1205
1206   /* Configure/verify the target byte order and other runtime
1207      configuration options.  */
1208   if (sim_config (sd) != SIM_RC_OK)
1209     {
1210       sim_module_uninstall (sd);
1211       return 0;
1212     }
1213
1214   if (sim_post_argv_init (sd) != SIM_RC_OK)
1215     {
1216       /* Uninstall the modules to avoid memory leaks,
1217          file descriptor leaks, etc.  */
1218       sim_module_uninstall (sd);
1219       return 0;
1220     }
1221
1222   return sd;
1223 }
1224
1225 void
1226 sim_close (sd, quitting)
1227      SIM_DESC sd;
1228      int quitting;
1229 {
1230   /* nothing to do */
1231 }
1232
1233
1234 /* Load the device tree blob.  */
1235
1236 static void
1237 load_dtb (SIM_DESC sd, const char *filename)
1238 {
1239   int size = 0;
1240   FILE *f = fopen (filename, "rb");
1241   char *buf;
1242   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1243  if (f == NULL)
1244     {
1245       printf ("WARNING: ``%s'' could not be opened.\n", filename);
1246       return;
1247     }
1248   fseek (f, 0, SEEK_END);
1249   size = ftell(f);
1250   fseek (f, 0, SEEK_SET);
1251   buf = alloca (size);
1252   if (size != fread (buf, 1, size, f))
1253     {
1254       printf ("ERROR: error reading ``%s''.\n", filename);
1255       return;
1256     }
1257   sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
1258   cpu.asregs.sregs[9] = 0xE0000000;
1259   fclose (f);
1260 }
1261
1262 SIM_RC
1263 sim_load (sd, prog, abfd, from_tty)
1264      SIM_DESC sd;
1265      const char * prog;
1266      bfd * abfd;
1267      int from_tty;
1268 {
1269
1270   /* Do the right thing for ELF executables; this turns out to be
1271      just about the right thing for any object format that:
1272        - we crack using BFD routines
1273        - follows the traditional UNIX text/data/bss layout
1274        - calls the bss section ".bss".   */
1275
1276   extern bfd * sim_load_file (); /* ??? Don't know where this should live.  */
1277   bfd * prog_bfd;
1278
1279   {
1280     bfd * handle;
1281     handle = bfd_openr (prog, 0);       /* could be "moxie" */
1282
1283     if (!handle)
1284       {
1285         printf("``%s'' could not be opened.\n", prog);
1286         return SIM_RC_FAIL;
1287       }
1288
1289     /* Makes sure that we have an object file, also cleans gets the
1290        section headers in place.  */
1291     if (!bfd_check_format (handle, bfd_object))
1292       {
1293         /* wasn't an object file */
1294         bfd_close (handle);
1295         printf ("``%s'' is not appropriate object file.\n", prog);
1296         return SIM_RC_FAIL;
1297       }
1298
1299     /* Clean up after ourselves.  */
1300     bfd_close (handle);
1301   }
1302
1303   /* from sh -- dac */
1304   prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
1305                             sim_kind == SIM_OPEN_DEBUG,
1306                             0, sim_write);
1307   if (prog_bfd == NULL)
1308     return SIM_RC_FAIL;
1309
1310   if (abfd == NULL)
1311     bfd_close (prog_bfd);
1312
1313   return SIM_RC_OK;
1314 }
1315
1316 SIM_RC
1317 sim_create_inferior (sd, prog_bfd, argv, env)
1318      SIM_DESC sd;
1319      struct bfd * prog_bfd;
1320      char ** argv;
1321      char ** env;
1322 {
1323   char ** avp;
1324   int l, argc, i, tp;
1325   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1326
1327   /* Set the initial register set.  */
1328   l = issue_messages;
1329   issue_messages = 0;
1330   set_initial_gprs ();
1331   issue_messages = l;
1332
1333   if (prog_bfd != NULL)
1334     cpu.asregs.regs[PC_REGNO] = bfd_get_start_address (prog_bfd);
1335
1336   /* Copy args into target memory.  */
1337   avp = argv;
1338   for (argc = 0; avp && *avp; avp++)
1339     argc++;
1340
1341   /* Target memory looks like this:
1342      0x00000000 zero word
1343      0x00000004 argc word
1344      0x00000008 start of argv
1345      .
1346      0x0000???? end of argv
1347      0x0000???? zero word
1348      0x0000???? start of data pointed to by argv  */
1349
1350   wlat (scpu, 0, 0, 0);
1351   wlat (scpu, 0, 4, argc);
1352
1353   /* tp is the offset of our first argv data.  */
1354   tp = 4 + 4 + argc * 4 + 4;
1355
1356   for (i = 0; i < argc; i++)
1357     {
1358       /* Set the argv value.  */
1359       wlat (scpu, 0, 4 + 4 + i * 4, tp);
1360
1361       /* Store the string.  */
1362       sim_core_write_buffer (sd, scpu, write_map, argv[i],
1363                              tp, strlen(argv[i])+1);
1364       tp += strlen (argv[i]) + 1;
1365     }
1366
1367   wlat (scpu, 0, 4 + 4 + i * 4, 0);
1368
1369   load_dtb (sd, DTB);
1370
1371   return SIM_RC_OK;
1372 }
1373
1374 void
1375 sim_kill (sd)
1376      SIM_DESC sd;
1377 {
1378   if (tracefile)
1379     fclose(tracefile);
1380 }
1381
1382 void
1383 sim_do_command (sd, cmd)
1384      SIM_DESC sd;
1385      const char *cmd;
1386 {
1387   if (sim_args_command (sd, cmd) != SIM_RC_OK)
1388     sim_io_printf (sd,
1389                    "Error: \"%s\" is not a valid moxie simulator command.\n",
1390                    cmd);
1391 }
1392
1393 void
1394 sim_set_callbacks (ptr)
1395      host_callback * ptr;
1396 {
1397   callback = ptr;
1398 }