sim/sparc/cpu32.h

   1 /* CPU family header for sparc32.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1999 Cygnus Solutions, Inc.
   6
   7 This file is part of the Cygnus Simulators.
   8
   9
  10 */
  11
  12 #ifndef CPU_SPARC32_H
  13 #define CPU_SPARC32_H
  14
  15 /* Maximum number of instructions that are fetched at a time.
  16    This is for LIW type instructions sets (e.g. m32r).  */
  17 #define MAX_LIW_INSNS 1
  18
  19 /* Maximum number of instructions that can be executed in parallel.  */
  20 #define MAX_PARALLEL_INSNS 1
  21
  22 /* CPU state information.  */
  23 typedef struct {
  24   /* Hardware elements.  */
  25   struct {
  26   /* program counter */
  27   USI h_pc;
  28 #define GET_H_PC() CPU (h_pc)
  29 #define SET_H_PC(x) (CPU (h_pc) = (x))
  30   /* next pc */
  31   SI h_npc;
  32 #define GET_H_NPC() CPU (h_npc)
  33 #define SET_H_NPC(x) (CPU (h_npc) = (x))
  34 /* GET_H_GR macro user-written */
  35 /* SET_H_GR macro user-written */
  36   /* icc carry bit */
  37   BI h_icc_c;
  38 #define GET_H_ICC_C() CPU (h_icc_c)
  39 #define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
  40   /* icc negative bit */
  41   BI h_icc_n;
  42 #define GET_H_ICC_N() CPU (h_icc_n)
  43 #define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
  44   /* icc overflow bit */
  45   BI h_icc_v;
  46 #define GET_H_ICC_V() CPU (h_icc_v)
  47 #define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
  48   /* icc zero bit */
  49   BI h_icc_z;
  50 #define GET_H_ICC_Z() CPU (h_icc_z)
  51 #define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
  52   /* xcc carry bit */
  53   BI h_xcc_c;
  54 #define GET_H_XCC_C() CPU (h_xcc_c)
  55 #define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
  56   /* xcc negative bit */
  57   BI h_xcc_n;
  58 #define GET_H_XCC_N() CPU (h_xcc_n)
  59 #define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
  60   /* xcc overflow bit */
  61   BI h_xcc_v;
  62 #define GET_H_XCC_V() CPU (h_xcc_v)
  63 #define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
  64   /* xcc zero bit */
  65   BI h_xcc_z;
  66 #define GET_H_XCC_Z() CPU (h_xcc_z)
  67 #define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
  68 /* GET_H_Y macro user-written */
  69 /* SET_H_Y macro user-written */
  70   /* ancilliary state registers */
  71   SI h_asr[32];
  72 #define GET_H_ASR(a1) CPU (h_asr)[a1]
  73 #define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
  74   /* annul next insn? - assists execution */
  75   BI h_annul_p;
  76 #define GET_H_ANNUL_P() CPU (h_annul_p)
  77 #define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
  78   /* floating point regs */
  79   SF h_fr[32];
  80 #define GET_H_FR(a1) CPU (h_fr)[a1]
  81 #define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
  82   /* psr register */
  83   USI h_psr;
  84 /* GET_H_PSR macro user-written */
  85 /* SET_H_PSR macro user-written */
  86   /* supervisor bit */
  87   BI h_s;
  88 #define GET_H_S() CPU (h_s)
  89 #define SET_H_S(x) (CPU (h_s) = (x))
  90   /* previous supervisor bit */
  91   BI h_ps;
  92 #define GET_H_PS() CPU (h_ps)
  93 #define SET_H_PS(x) (CPU (h_ps) = (x))
  94   /* processor interrupt level */
  95   UQI h_pil;
  96 #define GET_H_PIL() CPU (h_pil)
  97 #define SET_H_PIL(x) (CPU (h_pil) = (x))
  98   /* enable traps bit */
  99   BI h_et;
 100 #define GET_H_ET() CPU (h_et)
 101 #define SET_H_ET(x) (CPU (h_et) = (x))
 102   /* tbr register */
 103   SI h_tbr;
 104 /* GET_H_TBR macro user-written */
 105 /* SET_H_TBR macro user-written */
 106   /* current window pointer */
 107   UQI h_cwp;
 108 /* GET_H_CWP macro user-written */
 109 /* SET_H_CWP macro user-written */
 110   /* window invalid mask */
 111   USI h_wim;
 112 /* GET_H_WIM macro user-written */
 113 /* SET_H_WIM macro user-written */
 114   /* alternate global indicator */
 115   QI h_ag;
 116 #define GET_H_AG() CPU (h_ag)
 117 #define SET_H_AG(x) (CPU (h_ag) = (x))
 118   /* enable coprocessor bit */
 119   BI h_ec;
 120 #define GET_H_EC() CPU (h_ec)
 121 #define SET_H_EC(x) (CPU (h_ec) = (x))
 122   /* enable fpu bit */
 123   BI h_ef;
 124 #define GET_H_EF() CPU (h_ef)
 125 #define SET_H_EF(x) (CPU (h_ef) = (x))
 126   /* floating point status register */
 127   USI h_fsr;
 128 #define GET_H_FSR() CPU (h_fsr)
 129 #define SET_H_FSR(x) (CPU (h_fsr) = (x))
 130   } hardware;
 131 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 132 } SPARC32_CPU_DATA;
 133
 134 /* Cover fns for register access.  */
 135 USI sparc32_h_pc_get (SIM_CPU *);
 136 void sparc32_h_pc_set (SIM_CPU *, USI);
 137 SI sparc32_h_npc_get (SIM_CPU *);
 138 void sparc32_h_npc_set (SIM_CPU *, SI);
 139 SI sparc32_h_gr_get (SIM_CPU *, UINT);
 140 void sparc32_h_gr_set (SIM_CPU *, UINT, SI);
 141 BI sparc32_h_icc_c_get (SIM_CPU *);
 142 void sparc32_h_icc_c_set (SIM_CPU *, BI);
 143 BI sparc32_h_icc_n_get (SIM_CPU *);
 144 void sparc32_h_icc_n_set (SIM_CPU *, BI);
 145 BI sparc32_h_icc_v_get (SIM_CPU *);
 146 void sparc32_h_icc_v_set (SIM_CPU *, BI);
 147 BI sparc32_h_icc_z_get (SIM_CPU *);
 148 void sparc32_h_icc_z_set (SIM_CPU *, BI);
 149 BI sparc32_h_xcc_c_get (SIM_CPU *);
 150 void sparc32_h_xcc_c_set (SIM_CPU *, BI);
 151 BI sparc32_h_xcc_n_get (SIM_CPU *);
 152 void sparc32_h_xcc_n_set (SIM_CPU *, BI);
 153 BI sparc32_h_xcc_v_get (SIM_CPU *);
 154 void sparc32_h_xcc_v_set (SIM_CPU *, BI);
 155 BI sparc32_h_xcc_z_get (SIM_CPU *);
 156 void sparc32_h_xcc_z_set (SIM_CPU *, BI);
 157 SI sparc32_h_y_get (SIM_CPU *);
 158 void sparc32_h_y_set (SIM_CPU *, SI);
 159 SI sparc32_h_asr_get (SIM_CPU *, UINT);
 160 void sparc32_h_asr_set (SIM_CPU *, UINT, SI);
 161 BI sparc32_h_annul_p_get (SIM_CPU *);
 162 void sparc32_h_annul_p_set (SIM_CPU *, BI);
 163 SF sparc32_h_fr_get (SIM_CPU *, UINT);
 164 void sparc32_h_fr_set (SIM_CPU *, UINT, SF);
 165 USI sparc32_h_psr_get (SIM_CPU *);
 166 void sparc32_h_psr_set (SIM_CPU *, USI);
 167 BI sparc32_h_s_get (SIM_CPU *);
 168 void sparc32_h_s_set (SIM_CPU *, BI);
 169 BI sparc32_h_ps_get (SIM_CPU *);
 170 void sparc32_h_ps_set (SIM_CPU *, BI);
 171 UQI sparc32_h_pil_get (SIM_CPU *);
 172 void sparc32_h_pil_set (SIM_CPU *, UQI);
 173 BI sparc32_h_et_get (SIM_CPU *);
 174 void sparc32_h_et_set (SIM_CPU *, BI);
 175 SI sparc32_h_tbr_get (SIM_CPU *);
 176 void sparc32_h_tbr_set (SIM_CPU *, SI);
 177 UQI sparc32_h_cwp_get (SIM_CPU *);
 178 void sparc32_h_cwp_set (SIM_CPU *, UQI);
 179 USI sparc32_h_wim_get (SIM_CPU *);
 180 void sparc32_h_wim_set (SIM_CPU *, USI);
 181 QI sparc32_h_ag_get (SIM_CPU *);
 182 void sparc32_h_ag_set (SIM_CPU *, QI);
 183 BI sparc32_h_ec_get (SIM_CPU *);
 184 void sparc32_h_ec_set (SIM_CPU *, BI);
 185 BI sparc32_h_ef_get (SIM_CPU *);
 186 void sparc32_h_ef_set (SIM_CPU *, BI);
 187 USI sparc32_h_fsr_get (SIM_CPU *);
 188 void sparc32_h_fsr_set (SIM_CPU *, USI);
 189
 190 /* These must be hand-written.  */
 191 extern CPUREG_FETCH_FN sparc32_fetch_register;
 192 extern CPUREG_STORE_FN sparc32_store_register;
 193
 194 typedef struct {
 195   int empty;
 196 } MODEL_SPARC32_DEF_DATA;
 197
 198 /* The ARGBUF struct.  */
 199 struct argbuf {
 200   /* These are the baseclass definitions.  */
 201   IADDR addr;
 202   const IDESC *idesc;
 203   char trace_p;
 204   char profile_p;
 205   /* cpu specific data follows */
 206   CGEN_INSN_INT insn;
 207   int written;
 208 };
 209
 210 /* A cached insn.
 211
 212    ??? SCACHE used to contain more than just argbuf.  We could delete the
 213    type entirely and always just use ARGBUF, but for future concerns and as
 214    a level of abstraction it is left in.  */
 215
 216 struct scache {
 217   struct argbuf argbuf;
 218 };
 219
 220 /* Macros to simplify extraction, reading and semantic code.
 221    These define and assign the local vars that contain the insn's fields.  */
 222
 223 #define EXTRACT_IFMT_EMPTY_VARS \
 224   /* Instruction fields.  */ \
 225   unsigned int length;
 226 #define EXTRACT_IFMT_EMPTY_CODE \
 227   length = 0; \
 228
 229 #define EXTRACT_IFMT_RD_ASR_VARS \
 230   /* Instruction fields.  */ \
 231   INT f_simm13; \
 232   UINT f_i; \
 233   UINT f_rs1; \
 234   UINT f_op3; \
 235   UINT f_rd; \
 236   UINT f_op; \
 237   unsigned int length;
 238 #define EXTRACT_IFMT_RD_ASR_CODE \
 239   length = 4; \
 240   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 241   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 242   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 243   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 244   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 245   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 246
 247 #define EXTRACT_IFMT_WR_ASR_VARS \
 248   /* Instruction fields.  */ \
 249   UINT f_rs2; \
 250   INT f_res_asi; \
 251   UINT f_i; \
 252   UINT f_rs1; \
 253   UINT f_op3; \
 254   UINT f_rd; \
 255   UINT f_op; \
 256   unsigned int length;
 257 #define EXTRACT_IFMT_WR_ASR_CODE \
 258   length = 4; \
 259   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 260   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 261   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 262   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 263   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 264   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 265   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 266
 267 #define EXTRACT_IFMT_WR_ASR_IMM_VARS \
 268   /* Instruction fields.  */ \
 269   INT f_simm13; \
 270   UINT f_i; \
 271   UINT f_rs1; \
 272   UINT f_op3; \
 273   UINT f_rd; \
 274   UINT f_op; \
 275   unsigned int length;
 276 #define EXTRACT_IFMT_WR_ASR_IMM_CODE \
 277   length = 4; \
 278   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 279   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 280   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 281   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 282   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 283   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 284
 285 #define EXTRACT_IFMT_RD_PSR_VARS \
 286   /* Instruction fields.  */ \
 287   INT f_simm13; \
 288   UINT f_i; \
 289   UINT f_rs1; \
 290   UINT f_op3; \
 291   UINT f_rd; \
 292   UINT f_op; \
 293   unsigned int length;
 294 #define EXTRACT_IFMT_RD_PSR_CODE \
 295   length = 4; \
 296   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 297   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 298   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 299   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 300   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 301   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 302
 303 #define EXTRACT_IFMT_WR_PSR_VARS \
 304   /* Instruction fields.  */ \
 305   UINT f_rs2; \
 306   INT f_res_asi; \
 307   UINT f_i; \
 308   UINT f_rs1; \
 309   UINT f_op3; \
 310   UINT f_rd; \
 311   UINT f_op; \
 312   unsigned int length;
 313 #define EXTRACT_IFMT_WR_PSR_CODE \
 314   length = 4; \
 315   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 316   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 317   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 318   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 319   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 320   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 321   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 322
 323 #define EXTRACT_IFMT_WR_PSR_IMM_VARS \
 324   /* Instruction fields.  */ \
 325   INT f_simm13; \
 326   UINT f_i; \
 327   UINT f_rs1; \
 328   UINT f_op3; \
 329   UINT f_rd; \
 330   UINT f_op; \
 331   unsigned int length;
 332 #define EXTRACT_IFMT_WR_PSR_IMM_CODE \
 333   length = 4; \
 334   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 335   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 336   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 337   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 338   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 339   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 340
 341 #define EXTRACT_IFMT_LDSTUB_REG_REG_VARS \
 342   /* Instruction fields.  */ \
 343   UINT f_rs2; \
 344   INT f_res_asi; \
 345   UINT f_i; \
 346   UINT f_rs1; \
 347   UINT f_op3; \
 348   UINT f_rd; \
 349   UINT f_op; \
 350   unsigned int length;
 351 #define EXTRACT_IFMT_LDSTUB_REG_REG_CODE \
 352   length = 4; \
 353   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 354   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 355   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 356   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 357   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 358   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 359   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 360
 361 #define EXTRACT_IFMT_LDSTUB_REG_IMM_VARS \
 362   /* Instruction fields.  */ \
 363   INT f_simm13; \
 364   UINT f_i; \
 365   UINT f_rs1; \
 366   UINT f_op3; \
 367   UINT f_rd; \
 368   UINT f_op; \
 369   unsigned int length;
 370 #define EXTRACT_IFMT_LDSTUB_REG_IMM_CODE \
 371   length = 4; \
 372   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 373   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 374   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 375   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 376   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 377   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 378
 379 #define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS \
 380   /* Instruction fields.  */ \
 381   UINT f_rs2; \
 382   UINT f_asi; \
 383   UINT f_i; \
 384   UINT f_rs1; \
 385   UINT f_op3; \
 386   UINT f_rd; \
 387   UINT f_op; \
 388   unsigned int length;
 389 #define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE \
 390   length = 4; \
 391   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 392   f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
 393   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 394   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 395   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 396   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 397   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 398
 399 #define EXTRACT_IFMT_LDD_REG_REG_VARS \
 400   /* Instruction fields.  */ \
 401   UINT f_rs2; \
 402   INT f_res_asi; \
 403   UINT f_i; \
 404   UINT f_rs1; \
 405   UINT f_op3; \
 406   UINT f_rd; \
 407   UINT f_op; \
 408   unsigned int length;
 409 #define EXTRACT_IFMT_LDD_REG_REG_CODE \
 410   length = 4; \
 411   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 412   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 413   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 414   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 415   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 416   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 417   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 418
 419 #define EXTRACT_IFMT_LDD_REG_IMM_VARS \
 420   /* Instruction fields.  */ \
 421   INT f_simm13; \
 422   UINT f_i; \
 423   UINT f_rs1; \
 424   UINT f_op3; \
 425   UINT f_rd; \
 426   UINT f_op; \
 427   unsigned int length;
 428 #define EXTRACT_IFMT_LDD_REG_IMM_CODE \
 429   length = 4; \
 430   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 431   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 432   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 433   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 434   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 435   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 436
 437 #define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
 438   /* Instruction fields.  */ \
 439   UINT f_rs2; \
 440   UINT f_asi; \
 441   UINT f_i; \
 442   UINT f_rs1; \
 443   UINT f_op3; \
 444   UINT f_rd; \
 445   UINT f_op; \
 446   unsigned int length;
 447 #define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
 448   length = 4; \
 449   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 450   f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
 451   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 452   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 453   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 454   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 455   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 456
 457 #define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
 458   /* Instruction fields.  */ \
 459   UINT f_rs2; \
 460   INT f_res_asi; \
 461   UINT f_i; \
 462   UINT f_rs1; \
 463   UINT f_op3; \
 464   UINT f_rd; \
 465   UINT f_op; \
 466   unsigned int length;
 467 #define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
 468   length = 4; \
 469   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 470   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 471   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 472   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 473   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 474   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 475   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 476
 477 #define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
 478   /* Instruction fields.  */ \
 479   INT f_simm13; \
 480   UINT f_i; \
 481   UINT f_rs1; \
 482   UINT f_op3; \
 483   UINT f_rd; \
 484   UINT f_op; \
 485   unsigned int length;
 486 #define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
 487   length = 4; \
 488   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 489   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 490   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 491   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 492   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 493   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 494
 495 #define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
 496   /* Instruction fields.  */ \
 497   UINT f_rs2; \
 498   UINT f_asi; \
 499   UINT f_i; \
 500   UINT f_rs1; \
 501   UINT f_op3; \
 502   UINT f_rd; \
 503   UINT f_op; \
 504   unsigned int length;
 505 #define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
 506   length = 4; \
 507   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 508   f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
 509   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 510   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 511   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 512   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 513   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 514
 515 #define EXTRACT_IFMT_SETHI_VARS \
 516   /* Instruction fields.  */ \
 517   INT f_hi22; \
 518   UINT f_op2; \
 519   UINT f_rd; \
 520   UINT f_op; \
 521   unsigned int length;
 522 #define EXTRACT_IFMT_SETHI_CODE \
 523   length = 4; \
 524   f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
 525   f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
 526   f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
 527   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 528
 529 #define EXTRACT_IFMT_UNIMP_VARS \
 530   /* Instruction fields.  */ \
 531   INT f_imm22; \
 532   UINT f_op2; \
 533   UINT f_rd_res; \
 534   UINT f_op; \
 535   unsigned int length;
 536 #define EXTRACT_IFMT_UNIMP_CODE \
 537   length = 4; \
 538   f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
 539   f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
 540   f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
 541   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 542
 543 #define EXTRACT_IFMT_CALL_VARS \
 544   /* Instruction fields.  */ \
 545   SI f_disp30; \
 546   UINT f_op; \
 547   unsigned int length;
 548 #define EXTRACT_IFMT_CALL_CODE \
 549   length = 4; \
 550   f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
 551   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 552
 553 #define EXTRACT_IFMT_BA_VARS \
 554   /* Instruction fields.  */ \
 555   SI f_disp22; \
 556   UINT f_op2; \
 557   UINT f_fmt2_cond; \
 558   UINT f_a; \
 559   UINT f_op; \
 560   unsigned int length;
 561 #define EXTRACT_IFMT_BA_CODE \
 562   length = 4; \
 563   f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
 564   f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
 565   f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
 566   f_a = EXTRACT_UINT (insn, 32, 29, 1); \
 567   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 568
 569 #define EXTRACT_IFMT_TA_VARS \
 570   /* Instruction fields.  */ \
 571   UINT f_rs2; \
 572   INT f_res_asi; \
 573   UINT f_i; \
 574   UINT f_rs1; \
 575   UINT f_op3; \
 576   UINT f_fmt2_cond; \
 577   UINT f_a; \
 578   UINT f_op; \
 579   unsigned int length;
 580 #define EXTRACT_IFMT_TA_CODE \
 581   length = 4; \
 582   f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
 583   f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
 584   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 585   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 586   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 587   f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
 588   f_a = EXTRACT_UINT (insn, 32, 29, 1); \
 589   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 590
 591 #define EXTRACT_IFMT_TA_IMM_VARS \
 592   /* Instruction fields.  */ \
 593   INT f_simm13; \
 594   UINT f_i; \
 595   UINT f_rs1; \
 596   UINT f_op3; \
 597   UINT f_fmt2_cond; \
 598   UINT f_a; \
 599   UINT f_op; \
 600   unsigned int length;
 601 #define EXTRACT_IFMT_TA_IMM_CODE \
 602   length = 4; \
 603   f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
 604   f_i = EXTRACT_UINT (insn, 32, 13, 1); \
 605   f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
 606   f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
 607   f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
 608   f_a = EXTRACT_UINT (insn, 32, 29, 1); \
 609   f_op = EXTRACT_UINT (insn, 32, 31, 2); \
 610
 611 /* Collection of various things for the trace handler to use.  */
 612
 613 typedef struct trace_record {
 614   IADDR pc;
 615   /* FIXME:wip */
 616 } TRACE_RECORD;
 617
 618 #endif /* CPU_SPARC32_H */