sim/testsuite/sim/aarch64/stn_single.s

   1 # mach: aarch64
   2
   3 # Check the store single 1-element structure to one lane instructions:
   4 # st1, st2, st3, st4.
   5 # Check the addressing modes: no offset, post-index immediate offset,
   6 # post-index register offset.
   7
   8 .include "testutils.inc"
   9
  10 input:
  11         .word 0x04030201
  12         .word 0x08070605
  13         .word 0x0c0b0a09
  14         .word 0x100f0e0d
  15         .word 0x14131211
  16         .word 0x18171615
  17         .word 0x1c1b1a19
  18         .word 0x201f1e1d
  19 output:
  20         .zero 64
  21
  22         start
  23         adrp x0, input
  24         add x0, x0, :lo12:input
  25         adrp x1, output
  26         add x1, x1, :lo12:output
  27
  28         mov x2, x0
  29         ldr q0, [x2], 8
  30         ldr q1, [x2]
  31         mov x2, x0
  32         ldr q2, [x2], 8
  33         ldr q3, [x2]
  34
  35         mov x2, x1
  36         mov x3, #1
  37         mov x4, #4
  38         st1 {v0.b}[0], [x2], 1
  39         st1 {v0.b}[1], [x2], x3
  40         st1 {v0.h}[1], [x2], 2
  41         st1 {v0.s}[1], [x2], x4
  42         st1 {v0.d}[1], [x2]
  43         ldr q4, [x1]
  44         addv b4, v4.16b
  45         mov x5, v4.d[0]
  46         cmp x5, #136
  47         bne .Lfailure
  48
  49         mov x2, x1
  50         mov x3, #16
  51         mov x4, #4
  52         st2 {v0.d, v1.d}[0], [x2], x3
  53         st2 {v0.s, v1.s}[2], [x2], 8
  54         st2 {v0.h, v1.h}[6], [x2], x4
  55         st2 {v0.b, v1.b}[14], [x2], 2
  56         st2 {v0.b, v1.b}[15], [x2]
  57         mov x2, x1
  58         ldr q4, [x2], 16
  59         ldr q5, [x2]
  60         addv b4, v4.16b
  61         addv b5, v5.16b
  62         mov x5, v4.d[0]
  63         mov x6, v5.d[0]
  64         cmp x5, #136
  65         bne .Lfailure
  66         cmp x6, #8
  67         bne .Lfailure
  68
  69         mov x2, x1
  70         mov x3, #12
  71         st3 {v0.s, v1.s, v2.s}[0], [x2], 12
  72         st3 {v0.s, v1.s, v2.s}[1], [x2], x3
  73         st3 {v0.s, v1.s, v2.s}[2], [x2], 12
  74         st3 {v0.s, v1.s, v2.s}[3], [x2]
  75         mov x2, x1
  76         ldr q4, [x2], 16
  77         ldr q5, [x2], 16
  78         ldr q6, [x2]
  79         addv b4, v4.16b
  80         addv b5, v5.16b
  81         addv b6, v6.16b
  82         mov x4, v4.d[0]
  83         mov x5, v5.d[0]
  84         mov x6, v6.d[0]
  85         cmp x4, #88
  86         bne .Lfailure
  87         cmp x5, #200
  88         bne .Lfailure
  89         cmp x6, #248
  90         bne .Lfailure
  91
  92         mov x2, x1
  93         mov x3, #16
  94         st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
  95         st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3
  96         st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16
  97         st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
  98         mov x2, x1
  99         ldr q4, [x2], 16
 100         ldr q5, [x2], 16
 101         ldr q6, [x2], 16
 102         ldr q7, [x2]
 103         addv b4, v4.16b
 104         addv b5, v5.16b
 105         addv b6, v6.16b
 106         addv b7, v7.16b
 107         mov x4, v4.d[0]
 108         mov x5, v5.d[0]
 109         mov x6, v6.d[0]
 110         mov x7, v7.d[0]
 111         cmp x4, #104
 112         bne .Lfailure
 113         cmp x5, #168
 114         bne .Lfailure
 115         cmp x6, #232
 116         bne .Lfailure
 117         cmp x7, #40
 118         bne .Lfailure
 119
 120         pass
 121 .Lfailure:
 122         fail