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ALSA: hda_intel: add card number to irq description
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_SCH_HDA_DEVC 0x78
94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96 /* Define IN stream 0 FIFO size offset in VIA controller */
97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98 /* Define VIA HD Audio Device ID*/
99 #define VIA_HDAC_DEVICE_ID 0x3288
100
101 /* max number of SDs */
102 /* ICH, ATI and VIA have 4 playback and 4 capture */
103 #define ICH6_NUM_CAPTURE 4
104 #define ICH6_NUM_PLAYBACK 4
105
106 /* ULI has 6 playback and 5 capture */
107 #define ULI_NUM_CAPTURE 5
108 #define ULI_NUM_PLAYBACK 6
109
110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
111 #define ATIHDMI_NUM_CAPTURE 0
112 #define ATIHDMI_NUM_PLAYBACK 8
113
114 /* TERA has 4 playback and 3 capture */
115 #define TERA_NUM_CAPTURE 3
116 #define TERA_NUM_PLAYBACK 4
117
118
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
122 static char *model[SNDRV_CARDS];
123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int probe_only[SNDRV_CARDS];
127 static int jackpoll_ms[SNDRV_CARDS];
128 static bool single_cmd;
129 static int enable_msi = -1;
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 static char *patch[SNDRV_CARDS];
132 #endif
133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136 #endif
137
138 module_param_array(index, int, NULL, 0444);
139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
140 module_param_array(id, charp, NULL, 0444);
141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
142 module_param_array(enable, bool, NULL, 0444);
143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144 module_param_array(model, charp, NULL, 0444);
145 MODULE_PARM_DESC(model, "Use the given board model.");
146 module_param_array(position_fix, int, NULL, 0444);
147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
149 module_param_array(bdl_pos_adj, int, NULL, 0644);
150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
151 module_param_array(probe_mask, int, NULL, 0444);
152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
153 module_param_array(probe_only, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
155 module_param_array(jackpoll_ms, int, NULL, 0444);
156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
157 module_param(single_cmd, bool, 0444);
158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
160 module_param(enable_msi, bint, 0444);
161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
163 module_param_array(patch, charp, NULL, 0444);
164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165 #endif
166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
167 module_param_array(beep_mode, bool, NULL, 0444);
168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
169 "(0=off, 1=on) (default=1).");
170 #endif
171
172 #ifdef CONFIG_PM
173 static int param_set_xint(const char *val, const struct kernel_param *kp);
174 static const struct kernel_param_ops param_ops_xint = {
175 .set = param_set_xint,
176 .get = param_get_int,
177 };
178 #define param_check_xint param_check_int
179
180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
181 module_param(power_save, xint, 0644);
182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_HDMI,
263 AZX_DRIVER_ATI,
264 AZX_DRIVER_ATIHDMI,
265 AZX_DRIVER_ATIHDMI_NS,
266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
269 AZX_DRIVER_NVIDIA,
270 AZX_DRIVER_TERA,
271 AZX_DRIVER_CTX,
272 AZX_DRIVER_CTHDA,
273 AZX_DRIVER_CMEDIA,
274 AZX_DRIVER_GENERIC,
275 AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277
278 #define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
285
286 /* quirks for Intel PCH */
287 #define AZX_DCAPS_INTEL_PCH_BASE \
288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289 AZX_DCAPS_SNOOP_TYPE(SCH))
290
291 /* PCH up to IVB; no runtime PM */
292 #define AZX_DCAPS_INTEL_PCH_NOPM \
293 (AZX_DCAPS_INTEL_PCH_BASE)
294
295 /* PCH for HSW/BDW; with runtime PM */
296 #define AZX_DCAPS_INTEL_PCH \
297 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
298
299 /* HSW HDMI */
300 #define AZX_DCAPS_INTEL_HASWELL \
301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
304
305 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
306 #define AZX_DCAPS_INTEL_BROADWELL \
307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
309 AZX_DCAPS_SNOOP_TYPE(SCH))
310
311 #define AZX_DCAPS_INTEL_BAYTRAIL \
312 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
313
314 #define AZX_DCAPS_INTEL_BRASWELL \
315 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
316
317 #define AZX_DCAPS_INTEL_SKYLAKE \
318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
320
321 #define AZX_DCAPS_INTEL_BROXTON \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
324
325 /* quirks for ATI SB / AMD Hudson */
326 #define AZX_DCAPS_PRESET_ATI_SB \
327 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
328 AZX_DCAPS_SNOOP_TYPE(ATI))
329
330 /* quirks for ATI/AMD HDMI */
331 #define AZX_DCAPS_PRESET_ATI_HDMI \
332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
333 AZX_DCAPS_NO_MSI64)
334
335 /* quirks for ATI HDMI with snoop off */
336 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
337 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
338
339 /* quirks for Nvidia */
340 #define AZX_DCAPS_PRESET_NVIDIA \
341 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
342 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
343 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
344
345 #define AZX_DCAPS_PRESET_CTHDA \
346 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
347 AZX_DCAPS_NO_64BIT |\
348 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
349
350 /*
351 * vga_switcheroo support
352 */
353 #ifdef SUPPORT_VGA_SWITCHEROO
354 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
355 #else
356 #define use_vga_switcheroo(chip) 0
357 #endif
358
359 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
360 ((pci)->device == 0x0c0c) || \
361 ((pci)->device == 0x0d0c) || \
362 ((pci)->device == 0x160c))
363
364 #define IS_BROXTON(pci) ((pci)->device == 0x5a98)
365
366 static char *driver_short_names[] = {
367 [AZX_DRIVER_ICH] = "HDA Intel",
368 [AZX_DRIVER_PCH] = "HDA Intel PCH",
369 [AZX_DRIVER_SCH] = "HDA Intel MID",
370 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
371 [AZX_DRIVER_ATI] = "HDA ATI SB",
372 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
373 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
374 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
375 [AZX_DRIVER_SIS] = "HDA SIS966",
376 [AZX_DRIVER_ULI] = "HDA ULI M5461",
377 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
378 [AZX_DRIVER_TERA] = "HDA Teradici",
379 [AZX_DRIVER_CTX] = "HDA Creative",
380 [AZX_DRIVER_CTHDA] = "HDA Creative",
381 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
382 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
383 };
384
385 #ifdef CONFIG_X86
386 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
387 {
388 int pages;
389
390 if (azx_snoop(chip))
391 return;
392 if (!dmab || !dmab->area || !dmab->bytes)
393 return;
394
395 #ifdef CONFIG_SND_DMA_SGBUF
396 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
397 struct snd_sg_buf *sgbuf = dmab->private_data;
398 if (chip->driver_type == AZX_DRIVER_CMEDIA)
399 return; /* deal with only CORB/RIRB buffers */
400 if (on)
401 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
402 else
403 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
404 return;
405 }
406 #endif
407
408 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
409 if (on)
410 set_memory_wc((unsigned long)dmab->area, pages);
411 else
412 set_memory_wb((unsigned long)dmab->area, pages);
413 }
414
415 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
416 bool on)
417 {
418 __mark_pages_wc(chip, buf, on);
419 }
420 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
421 struct snd_pcm_substream *substream, bool on)
422 {
423 if (azx_dev->wc_marked != on) {
424 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
425 azx_dev->wc_marked = on;
426 }
427 }
428 #else
429 /* NOP for other archs */
430 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
431 bool on)
432 {
433 }
434 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
435 struct snd_pcm_substream *substream, bool on)
436 {
437 }
438 #endif
439
440 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
441
442 /*
443 * initialize the PCI registers
444 */
445 /* update bits in a PCI register byte */
446 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
447 unsigned char mask, unsigned char val)
448 {
449 unsigned char data;
450
451 pci_read_config_byte(pci, reg, &data);
452 data &= ~mask;
453 data |= (val & mask);
454 pci_write_config_byte(pci, reg, data);
455 }
456
457 static void azx_init_pci(struct azx *chip)
458 {
459 int snoop_type = azx_get_snoop_type(chip);
460
461 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
462 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
463 * Ensuring these bits are 0 clears playback static on some HD Audio
464 * codecs.
465 * The PCI register TCSEL is defined in the Intel manuals.
466 */
467 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
468 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
469 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
470 }
471
472 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
473 * we need to enable snoop.
474 */
475 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
476 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
477 azx_snoop(chip));
478 update_pci_byte(chip->pci,
479 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
480 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
481 }
482
483 /* For NVIDIA HDA, enable snoop */
484 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
485 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
486 azx_snoop(chip));
487 update_pci_byte(chip->pci,
488 NVIDIA_HDA_TRANSREG_ADDR,
489 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
490 update_pci_byte(chip->pci,
491 NVIDIA_HDA_ISTRM_COH,
492 0x01, NVIDIA_HDA_ENABLE_COHBIT);
493 update_pci_byte(chip->pci,
494 NVIDIA_HDA_OSTRM_COH,
495 0x01, NVIDIA_HDA_ENABLE_COHBIT);
496 }
497
498 /* Enable SCH/PCH snoop if needed */
499 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
500 unsigned short snoop;
501 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
502 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
503 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
504 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
505 if (!azx_snoop(chip))
506 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
507 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
508 pci_read_config_word(chip->pci,
509 INTEL_SCH_HDA_DEVC, &snoop);
510 }
511 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
512 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
513 "Disabled" : "Enabled");
514 }
515 }
516
517 /*
518 * In BXT-P A0, HD-Audio DMA requests is later than expected,
519 * and makes an audio stream sensitive to system latencies when
520 * 24/32 bits are playing.
521 * Adjusting threshold of DMA fifo to force the DMA request
522 * sooner to improve latency tolerance at the expense of power.
523 */
524 static void bxt_reduce_dma_latency(struct azx *chip)
525 {
526 u32 val;
527
528 val = azx_readl(chip, SKL_EM4L);
529 val &= (0x3 << 20);
530 azx_writel(chip, SKL_EM4L, val);
531 }
532
533 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
534 {
535 struct hdac_bus *bus = azx_bus(chip);
536 struct pci_dev *pci = chip->pci;
537
538 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
539 snd_hdac_set_codec_wakeup(bus, true);
540 azx_init_chip(chip, full_reset);
541 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
542 snd_hdac_set_codec_wakeup(bus, false);
543
544 /* reduce dma latency to avoid noise */
545 if (IS_BROXTON(pci))
546 bxt_reduce_dma_latency(chip);
547 }
548
549 /* calculate runtime delay from LPIB */
550 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
551 unsigned int pos)
552 {
553 struct snd_pcm_substream *substream = azx_dev->core.substream;
554 int stream = substream->stream;
555 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
556 int delay;
557
558 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
559 delay = pos - lpib_pos;
560 else
561 delay = lpib_pos - pos;
562 if (delay < 0) {
563 if (delay >= azx_dev->core.delay_negative_threshold)
564 delay = 0;
565 else
566 delay += azx_dev->core.bufsize;
567 }
568
569 if (delay >= azx_dev->core.period_bytes) {
570 dev_info(chip->card->dev,
571 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
572 delay, azx_dev->core.period_bytes);
573 delay = 0;
574 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
575 chip->get_delay[stream] = NULL;
576 }
577
578 return bytes_to_frames(substream->runtime, delay);
579 }
580
581 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
582
583 /* called from IRQ */
584 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
585 {
586 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
587 int ok;
588
589 ok = azx_position_ok(chip, azx_dev);
590 if (ok == 1) {
591 azx_dev->irq_pending = 0;
592 return ok;
593 } else if (ok == 0) {
594 /* bogus IRQ, process it later */
595 azx_dev->irq_pending = 1;
596 schedule_work(&hda->irq_pending_work);
597 }
598 return 0;
599 }
600
601 /* Enable/disable i915 display power for the link */
602 static int azx_intel_link_power(struct azx *chip, bool enable)
603 {
604 struct hdac_bus *bus = azx_bus(chip);
605
606 return snd_hdac_display_power(bus, enable);
607 }
608
609 /*
610 * Check whether the current DMA position is acceptable for updating
611 * periods. Returns non-zero if it's OK.
612 *
613 * Many HD-audio controllers appear pretty inaccurate about
614 * the update-IRQ timing. The IRQ is issued before actually the
615 * data is processed. So, we need to process it afterwords in a
616 * workqueue.
617 */
618 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
619 {
620 struct snd_pcm_substream *substream = azx_dev->core.substream;
621 int stream = substream->stream;
622 u32 wallclk;
623 unsigned int pos;
624
625 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
626 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
627 return -1; /* bogus (too early) interrupt */
628
629 if (chip->get_position[stream])
630 pos = chip->get_position[stream](chip, azx_dev);
631 else { /* use the position buffer as default */
632 pos = azx_get_pos_posbuf(chip, azx_dev);
633 if (!pos || pos == (u32)-1) {
634 dev_info(chip->card->dev,
635 "Invalid position buffer, using LPIB read method instead.\n");
636 chip->get_position[stream] = azx_get_pos_lpib;
637 if (chip->get_position[0] == azx_get_pos_lpib &&
638 chip->get_position[1] == azx_get_pos_lpib)
639 azx_bus(chip)->use_posbuf = false;
640 pos = azx_get_pos_lpib(chip, azx_dev);
641 chip->get_delay[stream] = NULL;
642 } else {
643 chip->get_position[stream] = azx_get_pos_posbuf;
644 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
645 chip->get_delay[stream] = azx_get_delay_from_lpib;
646 }
647 }
648
649 if (pos >= azx_dev->core.bufsize)
650 pos = 0;
651
652 if (WARN_ONCE(!azx_dev->core.period_bytes,
653 "hda-intel: zero azx_dev->period_bytes"))
654 return -1; /* this shouldn't happen! */
655 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
656 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
657 /* NG - it's below the first next period boundary */
658 return chip->bdl_pos_adj ? 0 : -1;
659 azx_dev->core.start_wallclk += wallclk;
660 return 1; /* OK, it's fine */
661 }
662
663 /*
664 * The work for pending PCM period updates.
665 */
666 static void azx_irq_pending_work(struct work_struct *work)
667 {
668 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
669 struct azx *chip = &hda->chip;
670 struct hdac_bus *bus = azx_bus(chip);
671 struct hdac_stream *s;
672 int pending, ok;
673
674 if (!hda->irq_pending_warned) {
675 dev_info(chip->card->dev,
676 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
677 chip->card->number);
678 hda->irq_pending_warned = 1;
679 }
680
681 for (;;) {
682 pending = 0;
683 spin_lock_irq(&bus->reg_lock);
684 list_for_each_entry(s, &bus->stream_list, list) {
685 struct azx_dev *azx_dev = stream_to_azx_dev(s);
686 if (!azx_dev->irq_pending ||
687 !s->substream ||
688 !s->running)
689 continue;
690 ok = azx_position_ok(chip, azx_dev);
691 if (ok > 0) {
692 azx_dev->irq_pending = 0;
693 spin_unlock(&bus->reg_lock);
694 snd_pcm_period_elapsed(s->substream);
695 spin_lock(&bus->reg_lock);
696 } else if (ok < 0) {
697 pending = 0; /* too early */
698 } else
699 pending++;
700 }
701 spin_unlock_irq(&bus->reg_lock);
702 if (!pending)
703 return;
704 msleep(1);
705 }
706 }
707
708 /* clear irq_pending flags and assure no on-going workq */
709 static void azx_clear_irq_pending(struct azx *chip)
710 {
711 struct hdac_bus *bus = azx_bus(chip);
712 struct hdac_stream *s;
713
714 spin_lock_irq(&bus->reg_lock);
715 list_for_each_entry(s, &bus->stream_list, list) {
716 struct azx_dev *azx_dev = stream_to_azx_dev(s);
717 azx_dev->irq_pending = 0;
718 }
719 spin_unlock_irq(&bus->reg_lock);
720 }
721
722 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
723 {
724 struct hdac_bus *bus = azx_bus(chip);
725
726 if (request_irq(chip->pci->irq, azx_interrupt,
727 chip->msi ? 0 : IRQF_SHARED,
728 chip->card->irq_descr, chip)) {
729 dev_err(chip->card->dev,
730 "unable to grab IRQ %d, disabling device\n",
731 chip->pci->irq);
732 if (do_disconnect)
733 snd_card_disconnect(chip->card);
734 return -1;
735 }
736 bus->irq = chip->pci->irq;
737 pci_intx(chip->pci, !chip->msi);
738 return 0;
739 }
740
741 /* get the current DMA position with correction on VIA chips */
742 static unsigned int azx_via_get_position(struct azx *chip,
743 struct azx_dev *azx_dev)
744 {
745 unsigned int link_pos, mini_pos, bound_pos;
746 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
747 unsigned int fifo_size;
748
749 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
750 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
751 /* Playback, no problem using link position */
752 return link_pos;
753 }
754
755 /* Capture */
756 /* For new chipset,
757 * use mod to get the DMA position just like old chipset
758 */
759 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
760 mod_dma_pos %= azx_dev->core.period_bytes;
761
762 /* azx_dev->fifo_size can't get FIFO size of in stream.
763 * Get from base address + offset.
764 */
765 fifo_size = readw(azx_bus(chip)->remap_addr +
766 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
767
768 if (azx_dev->insufficient) {
769 /* Link position never gather than FIFO size */
770 if (link_pos <= fifo_size)
771 return 0;
772
773 azx_dev->insufficient = 0;
774 }
775
776 if (link_pos <= fifo_size)
777 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
778 else
779 mini_pos = link_pos - fifo_size;
780
781 /* Find nearest previous boudary */
782 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
783 mod_link_pos = link_pos % azx_dev->core.period_bytes;
784 if (mod_link_pos >= fifo_size)
785 bound_pos = link_pos - mod_link_pos;
786 else if (mod_dma_pos >= mod_mini_pos)
787 bound_pos = mini_pos - mod_mini_pos;
788 else {
789 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
790 if (bound_pos >= azx_dev->core.bufsize)
791 bound_pos = 0;
792 }
793
794 /* Calculate real DMA position we want */
795 return bound_pos + mod_dma_pos;
796 }
797
798 #ifdef CONFIG_PM
799 static DEFINE_MUTEX(card_list_lock);
800 static LIST_HEAD(card_list);
801
802 static void azx_add_card_list(struct azx *chip)
803 {
804 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
805 mutex_lock(&card_list_lock);
806 list_add(&hda->list, &card_list);
807 mutex_unlock(&card_list_lock);
808 }
809
810 static void azx_del_card_list(struct azx *chip)
811 {
812 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
813 mutex_lock(&card_list_lock);
814 list_del_init(&hda->list);
815 mutex_unlock(&card_list_lock);
816 }
817
818 /* trigger power-save check at writing parameter */
819 static int param_set_xint(const char *val, const struct kernel_param *kp)
820 {
821 struct hda_intel *hda;
822 struct azx *chip;
823 int prev = power_save;
824 int ret = param_set_int(val, kp);
825
826 if (ret || prev == power_save)
827 return ret;
828
829 mutex_lock(&card_list_lock);
830 list_for_each_entry(hda, &card_list, list) {
831 chip = &hda->chip;
832 if (!hda->probe_continued || chip->disabled)
833 continue;
834 snd_hda_set_power_save(&chip->bus, power_save * 1000);
835 }
836 mutex_unlock(&card_list_lock);
837 return 0;
838 }
839 #else
840 #define azx_add_card_list(chip) /* NOP */
841 #define azx_del_card_list(chip) /* NOP */
842 #endif /* CONFIG_PM */
843
844 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
845 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
846 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
847 * BCLK = CDCLK * M / N
848 * The values will be lost when the display power well is disabled and need to
849 * be restored to avoid abnormal playback speed.
850 */
851 static void haswell_set_bclk(struct hda_intel *hda)
852 {
853 struct azx *chip = &hda->chip;
854 int cdclk_freq;
855 unsigned int bclk_m, bclk_n;
856
857 if (!hda->need_i915_power)
858 return;
859
860 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
861 switch (cdclk_freq) {
862 case 337500:
863 bclk_m = 16;
864 bclk_n = 225;
865 break;
866
867 case 450000:
868 default: /* default CDCLK 450MHz */
869 bclk_m = 4;
870 bclk_n = 75;
871 break;
872
873 case 540000:
874 bclk_m = 4;
875 bclk_n = 90;
876 break;
877
878 case 675000:
879 bclk_m = 8;
880 bclk_n = 225;
881 break;
882 }
883
884 azx_writew(chip, HSW_EM4, bclk_m);
885 azx_writew(chip, HSW_EM5, bclk_n);
886 }
887
888 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
889 /*
890 * power management
891 */
892 static int azx_suspend(struct device *dev)
893 {
894 struct snd_card *card = dev_get_drvdata(dev);
895 struct azx *chip;
896 struct hda_intel *hda;
897 struct hdac_bus *bus;
898
899 if (!card)
900 return 0;
901
902 chip = card->private_data;
903 hda = container_of(chip, struct hda_intel, chip);
904 if (chip->disabled || hda->init_failed || !chip->running)
905 return 0;
906
907 bus = azx_bus(chip);
908 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
909 azx_clear_irq_pending(chip);
910 azx_stop_chip(chip);
911 azx_enter_link_reset(chip);
912 if (bus->irq >= 0) {
913 free_irq(bus->irq, chip);
914 bus->irq = -1;
915 }
916
917 if (chip->msi)
918 pci_disable_msi(chip->pci);
919 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
920 && hda->need_i915_power)
921 snd_hdac_display_power(bus, false);
922
923 trace_azx_suspend(chip);
924 return 0;
925 }
926
927 static int azx_resume(struct device *dev)
928 {
929 struct pci_dev *pci = to_pci_dev(dev);
930 struct snd_card *card = dev_get_drvdata(dev);
931 struct azx *chip;
932 struct hda_intel *hda;
933
934 if (!card)
935 return 0;
936
937 chip = card->private_data;
938 hda = container_of(chip, struct hda_intel, chip);
939 if (chip->disabled || hda->init_failed || !chip->running)
940 return 0;
941
942 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
943 && hda->need_i915_power) {
944 snd_hdac_display_power(azx_bus(chip), true);
945 haswell_set_bclk(hda);
946 }
947 if (chip->msi)
948 if (pci_enable_msi(pci) < 0)
949 chip->msi = 0;
950 if (azx_acquire_irq(chip, 1) < 0)
951 return -EIO;
952 azx_init_pci(chip);
953
954 hda_intel_init_chip(chip, true);
955
956 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
957
958 trace_azx_resume(chip);
959 return 0;
960 }
961 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
962
963 #ifdef CONFIG_PM_SLEEP
964 /* put codec down to D3 at hibernation for Intel SKL+;
965 * otherwise BIOS may still access the codec and screw up the driver
966 */
967 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
968 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
969 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
970 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
971
972 static int azx_freeze_noirq(struct device *dev)
973 {
974 struct pci_dev *pci = to_pci_dev(dev);
975
976 if (IS_SKL_PLUS(pci))
977 pci_set_power_state(pci, PCI_D3hot);
978
979 return 0;
980 }
981
982 static int azx_thaw_noirq(struct device *dev)
983 {
984 struct pci_dev *pci = to_pci_dev(dev);
985
986 if (IS_SKL_PLUS(pci))
987 pci_set_power_state(pci, PCI_D0);
988
989 return 0;
990 }
991 #endif /* CONFIG_PM_SLEEP */
992
993 #ifdef CONFIG_PM
994 static int azx_runtime_suspend(struct device *dev)
995 {
996 struct snd_card *card = dev_get_drvdata(dev);
997 struct azx *chip;
998 struct hda_intel *hda;
999
1000 if (!card)
1001 return 0;
1002
1003 chip = card->private_data;
1004 hda = container_of(chip, struct hda_intel, chip);
1005 if (chip->disabled || hda->init_failed)
1006 return 0;
1007
1008 if (!azx_has_pm_runtime(chip))
1009 return 0;
1010
1011 /* enable controller wake up event */
1012 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1013 STATESTS_INT_MASK);
1014
1015 azx_stop_chip(chip);
1016 azx_enter_link_reset(chip);
1017 azx_clear_irq_pending(chip);
1018 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1019 && hda->need_i915_power)
1020 snd_hdac_display_power(azx_bus(chip), false);
1021
1022 trace_azx_runtime_suspend(chip);
1023 return 0;
1024 }
1025
1026 static int azx_runtime_resume(struct device *dev)
1027 {
1028 struct snd_card *card = dev_get_drvdata(dev);
1029 struct azx *chip;
1030 struct hda_intel *hda;
1031 struct hdac_bus *bus;
1032 struct hda_codec *codec;
1033 int status;
1034
1035 if (!card)
1036 return 0;
1037
1038 chip = card->private_data;
1039 hda = container_of(chip, struct hda_intel, chip);
1040 if (chip->disabled || hda->init_failed)
1041 return 0;
1042
1043 if (!azx_has_pm_runtime(chip))
1044 return 0;
1045
1046 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1047 bus = azx_bus(chip);
1048 if (hda->need_i915_power) {
1049 snd_hdac_display_power(bus, true);
1050 haswell_set_bclk(hda);
1051 } else {
1052 /* toggle codec wakeup bit for STATESTS read */
1053 snd_hdac_set_codec_wakeup(bus, true);
1054 snd_hdac_set_codec_wakeup(bus, false);
1055 }
1056 }
1057
1058 /* Read STATESTS before controller reset */
1059 status = azx_readw(chip, STATESTS);
1060
1061 azx_init_pci(chip);
1062 hda_intel_init_chip(chip, true);
1063
1064 if (status) {
1065 list_for_each_codec(codec, &chip->bus)
1066 if (status & (1 << codec->addr))
1067 schedule_delayed_work(&codec->jackpoll_work,
1068 codec->jackpoll_interval);
1069 }
1070
1071 /* disable controller Wake Up event*/
1072 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1073 ~STATESTS_INT_MASK);
1074
1075 trace_azx_runtime_resume(chip);
1076 return 0;
1077 }
1078
1079 static int azx_runtime_idle(struct device *dev)
1080 {
1081 struct snd_card *card = dev_get_drvdata(dev);
1082 struct azx *chip;
1083 struct hda_intel *hda;
1084
1085 if (!card)
1086 return 0;
1087
1088 chip = card->private_data;
1089 hda = container_of(chip, struct hda_intel, chip);
1090 if (chip->disabled || hda->init_failed)
1091 return 0;
1092
1093 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1094 azx_bus(chip)->codec_powered || !chip->running)
1095 return -EBUSY;
1096
1097 return 0;
1098 }
1099
1100 static const struct dev_pm_ops azx_pm = {
1101 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1102 #ifdef CONFIG_PM_SLEEP
1103 .freeze_noirq = azx_freeze_noirq,
1104 .thaw_noirq = azx_thaw_noirq,
1105 #endif
1106 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1107 };
1108
1109 #define AZX_PM_OPS &azx_pm
1110 #else
1111 #define AZX_PM_OPS NULL
1112 #endif /* CONFIG_PM */
1113
1114
1115 static int azx_probe_continue(struct azx *chip);
1116
1117 #ifdef SUPPORT_VGA_SWITCHEROO
1118 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1119
1120 static void azx_vs_set_state(struct pci_dev *pci,
1121 enum vga_switcheroo_state state)
1122 {
1123 struct snd_card *card = pci_get_drvdata(pci);
1124 struct azx *chip = card->private_data;
1125 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1126 bool disabled;
1127
1128 wait_for_completion(&hda->probe_wait);
1129 if (hda->init_failed)
1130 return;
1131
1132 disabled = (state == VGA_SWITCHEROO_OFF);
1133 if (chip->disabled == disabled)
1134 return;
1135
1136 if (!hda->probe_continued) {
1137 chip->disabled = disabled;
1138 if (!disabled) {
1139 dev_info(chip->card->dev,
1140 "Start delayed initialization\n");
1141 if (azx_probe_continue(chip) < 0) {
1142 dev_err(chip->card->dev, "initialization error\n");
1143 hda->init_failed = true;
1144 }
1145 }
1146 } else {
1147 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1148 disabled ? "Disabling" : "Enabling");
1149 if (disabled) {
1150 pm_runtime_put_sync_suspend(card->dev);
1151 azx_suspend(card->dev);
1152 /* when we get suspended by vga_switcheroo we end up in D3cold,
1153 * however we have no ACPI handle, so pci/acpi can't put us there,
1154 * put ourselves there */
1155 pci->current_state = PCI_D3cold;
1156 chip->disabled = true;
1157 if (snd_hda_lock_devices(&chip->bus))
1158 dev_warn(chip->card->dev,
1159 "Cannot lock devices!\n");
1160 } else {
1161 snd_hda_unlock_devices(&chip->bus);
1162 pm_runtime_get_noresume(card->dev);
1163 chip->disabled = false;
1164 azx_resume(card->dev);
1165 }
1166 }
1167 }
1168
1169 static bool azx_vs_can_switch(struct pci_dev *pci)
1170 {
1171 struct snd_card *card = pci_get_drvdata(pci);
1172 struct azx *chip = card->private_data;
1173 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1174
1175 wait_for_completion(&hda->probe_wait);
1176 if (hda->init_failed)
1177 return false;
1178 if (chip->disabled || !hda->probe_continued)
1179 return true;
1180 if (snd_hda_lock_devices(&chip->bus))
1181 return false;
1182 snd_hda_unlock_devices(&chip->bus);
1183 return true;
1184 }
1185
1186 static void init_vga_switcheroo(struct azx *chip)
1187 {
1188 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1189 struct pci_dev *p = get_bound_vga(chip->pci);
1190 if (p) {
1191 dev_info(chip->card->dev,
1192 "Handle vga_switcheroo audio client\n");
1193 hda->use_vga_switcheroo = 1;
1194 pci_dev_put(p);
1195 }
1196 }
1197
1198 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1199 .set_gpu_state = azx_vs_set_state,
1200 .can_switch = azx_vs_can_switch,
1201 };
1202
1203 static int register_vga_switcheroo(struct azx *chip)
1204 {
1205 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1206 int err;
1207
1208 if (!hda->use_vga_switcheroo)
1209 return 0;
1210 /* FIXME: currently only handling DIS controller
1211 * is there any machine with two switchable HDMI audio controllers?
1212 */
1213 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1214 VGA_SWITCHEROO_DIS);
1215 if (err < 0)
1216 return err;
1217 hda->vga_switcheroo_registered = 1;
1218
1219 /* register as an optimus hdmi audio power domain */
1220 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1221 &hda->hdmi_pm_domain);
1222 return 0;
1223 }
1224 #else
1225 #define init_vga_switcheroo(chip) /* NOP */
1226 #define register_vga_switcheroo(chip) 0
1227 #define check_hdmi_disabled(pci) false
1228 #endif /* SUPPORT_VGA_SWITCHER */
1229
1230 /*
1231 * destructor
1232 */
1233 static int azx_free(struct azx *chip)
1234 {
1235 struct pci_dev *pci = chip->pci;
1236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1237 struct hdac_bus *bus = azx_bus(chip);
1238
1239 if (azx_has_pm_runtime(chip) && chip->running)
1240 pm_runtime_get_noresume(&pci->dev);
1241
1242 azx_del_card_list(chip);
1243
1244 hda->init_failed = 1; /* to be sure */
1245 complete_all(&hda->probe_wait);
1246
1247 if (use_vga_switcheroo(hda)) {
1248 if (chip->disabled && hda->probe_continued)
1249 snd_hda_unlock_devices(&chip->bus);
1250 if (hda->vga_switcheroo_registered)
1251 vga_switcheroo_unregister_client(chip->pci);
1252 }
1253
1254 if (bus->chip_init) {
1255 azx_clear_irq_pending(chip);
1256 azx_stop_all_streams(chip);
1257 azx_stop_chip(chip);
1258 }
1259
1260 if (bus->irq >= 0)
1261 free_irq(bus->irq, (void*)chip);
1262 if (chip->msi)
1263 pci_disable_msi(chip->pci);
1264 iounmap(bus->remap_addr);
1265
1266 azx_free_stream_pages(chip);
1267 azx_free_streams(chip);
1268 snd_hdac_bus_exit(bus);
1269
1270 if (chip->region_requested)
1271 pci_release_regions(chip->pci);
1272
1273 pci_disable_device(chip->pci);
1274 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1275 release_firmware(chip->fw);
1276 #endif
1277
1278 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1279 if (hda->need_i915_power)
1280 snd_hdac_display_power(bus, false);
1281 snd_hdac_i915_exit(bus);
1282 }
1283 kfree(hda);
1284
1285 return 0;
1286 }
1287
1288 static int azx_dev_disconnect(struct snd_device *device)
1289 {
1290 struct azx *chip = device->device_data;
1291
1292 chip->bus.shutdown = 1;
1293 return 0;
1294 }
1295
1296 static int azx_dev_free(struct snd_device *device)
1297 {
1298 return azx_free(device->device_data);
1299 }
1300
1301 #ifdef SUPPORT_VGA_SWITCHEROO
1302 /*
1303 * Check of disabled HDMI controller by vga_switcheroo
1304 */
1305 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1306 {
1307 struct pci_dev *p;
1308
1309 /* check only discrete GPU */
1310 switch (pci->vendor) {
1311 case PCI_VENDOR_ID_ATI:
1312 case PCI_VENDOR_ID_AMD:
1313 case PCI_VENDOR_ID_NVIDIA:
1314 if (pci->devfn == 1) {
1315 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1316 pci->bus->number, 0);
1317 if (p) {
1318 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1319 return p;
1320 pci_dev_put(p);
1321 }
1322 }
1323 break;
1324 }
1325 return NULL;
1326 }
1327
1328 static bool check_hdmi_disabled(struct pci_dev *pci)
1329 {
1330 bool vga_inactive = false;
1331 struct pci_dev *p = get_bound_vga(pci);
1332
1333 if (p) {
1334 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1335 vga_inactive = true;
1336 pci_dev_put(p);
1337 }
1338 return vga_inactive;
1339 }
1340 #endif /* SUPPORT_VGA_SWITCHEROO */
1341
1342 /*
1343 * white/black-listing for position_fix
1344 */
1345 static struct snd_pci_quirk position_fix_list[] = {
1346 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1347 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1348 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1349 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1350 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1351 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1352 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1353 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1354 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1355 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1356 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1357 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1358 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1359 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1360 {}
1361 };
1362
1363 static int check_position_fix(struct azx *chip, int fix)
1364 {
1365 const struct snd_pci_quirk *q;
1366
1367 switch (fix) {
1368 case POS_FIX_AUTO:
1369 case POS_FIX_LPIB:
1370 case POS_FIX_POSBUF:
1371 case POS_FIX_VIACOMBO:
1372 case POS_FIX_COMBO:
1373 return fix;
1374 }
1375
1376 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1377 if (q) {
1378 dev_info(chip->card->dev,
1379 "position_fix set to %d for device %04x:%04x\n",
1380 q->value, q->subvendor, q->subdevice);
1381 return q->value;
1382 }
1383
1384 /* Check VIA/ATI HD Audio Controller exist */
1385 if (chip->driver_type == AZX_DRIVER_VIA) {
1386 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1387 return POS_FIX_VIACOMBO;
1388 }
1389 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1390 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1391 return POS_FIX_LPIB;
1392 }
1393 return POS_FIX_AUTO;
1394 }
1395
1396 static void assign_position_fix(struct azx *chip, int fix)
1397 {
1398 static azx_get_pos_callback_t callbacks[] = {
1399 [POS_FIX_AUTO] = NULL,
1400 [POS_FIX_LPIB] = azx_get_pos_lpib,
1401 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1402 [POS_FIX_VIACOMBO] = azx_via_get_position,
1403 [POS_FIX_COMBO] = azx_get_pos_lpib,
1404 };
1405
1406 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1407
1408 /* combo mode uses LPIB only for playback */
1409 if (fix == POS_FIX_COMBO)
1410 chip->get_position[1] = NULL;
1411
1412 if (fix == POS_FIX_POSBUF &&
1413 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1414 chip->get_delay[0] = chip->get_delay[1] =
1415 azx_get_delay_from_lpib;
1416 }
1417
1418 }
1419
1420 /*
1421 * black-lists for probe_mask
1422 */
1423 static struct snd_pci_quirk probe_mask_list[] = {
1424 /* Thinkpad often breaks the controller communication when accessing
1425 * to the non-working (or non-existing) modem codec slot.
1426 */
1427 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1428 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1429 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1430 /* broken BIOS */
1431 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1432 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1433 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1434 /* forced codec slots */
1435 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1436 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1437 /* WinFast VP200 H (Teradici) user reported broken communication */
1438 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1439 {}
1440 };
1441
1442 #define AZX_FORCE_CODEC_MASK 0x100
1443
1444 static void check_probe_mask(struct azx *chip, int dev)
1445 {
1446 const struct snd_pci_quirk *q;
1447
1448 chip->codec_probe_mask = probe_mask[dev];
1449 if (chip->codec_probe_mask == -1) {
1450 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1451 if (q) {
1452 dev_info(chip->card->dev,
1453 "probe_mask set to 0x%x for device %04x:%04x\n",
1454 q->value, q->subvendor, q->subdevice);
1455 chip->codec_probe_mask = q->value;
1456 }
1457 }
1458
1459 /* check forced option */
1460 if (chip->codec_probe_mask != -1 &&
1461 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1462 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1463 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1464 (int)azx_bus(chip)->codec_mask);
1465 }
1466 }
1467
1468 /*
1469 * white/black-list for enable_msi
1470 */
1471 static struct snd_pci_quirk msi_black_list[] = {
1472 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1473 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1474 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1475 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1476 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1477 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1478 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1479 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1480 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1481 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1482 {}
1483 };
1484
1485 static void check_msi(struct azx *chip)
1486 {
1487 const struct snd_pci_quirk *q;
1488
1489 if (enable_msi >= 0) {
1490 chip->msi = !!enable_msi;
1491 return;
1492 }
1493 chip->msi = 1; /* enable MSI as default */
1494 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1495 if (q) {
1496 dev_info(chip->card->dev,
1497 "msi for device %04x:%04x set to %d\n",
1498 q->subvendor, q->subdevice, q->value);
1499 chip->msi = q->value;
1500 return;
1501 }
1502
1503 /* NVidia chipsets seem to cause troubles with MSI */
1504 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1505 dev_info(chip->card->dev, "Disabling MSI\n");
1506 chip->msi = 0;
1507 }
1508 }
1509
1510 /* check the snoop mode availability */
1511 static void azx_check_snoop_available(struct azx *chip)
1512 {
1513 int snoop = hda_snoop;
1514
1515 if (snoop >= 0) {
1516 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1517 snoop ? "snoop" : "non-snoop");
1518 chip->snoop = snoop;
1519 return;
1520 }
1521
1522 snoop = true;
1523 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1524 chip->driver_type == AZX_DRIVER_VIA) {
1525 /* force to non-snoop mode for a new VIA controller
1526 * when BIOS is set
1527 */
1528 u8 val;
1529 pci_read_config_byte(chip->pci, 0x42, &val);
1530 if (!(val & 0x80) && chip->pci->revision == 0x30)
1531 snoop = false;
1532 }
1533
1534 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1535 snoop = false;
1536
1537 chip->snoop = snoop;
1538 if (!snoop)
1539 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1540 }
1541
1542 static void azx_probe_work(struct work_struct *work)
1543 {
1544 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1545 azx_probe_continue(&hda->chip);
1546 }
1547
1548 static int default_bdl_pos_adj(struct azx *chip)
1549 {
1550 /* some exceptions: Atoms seem problematic with value 1 */
1551 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1552 switch (chip->pci->device) {
1553 case 0x0f04: /* Baytrail */
1554 case 0x2284: /* Braswell */
1555 return 32;
1556 }
1557 }
1558
1559 switch (chip->driver_type) {
1560 case AZX_DRIVER_ICH:
1561 case AZX_DRIVER_PCH:
1562 return 1;
1563 default:
1564 return 32;
1565 }
1566 }
1567
1568 /*
1569 * constructor
1570 */
1571 static const struct hdac_io_ops pci_hda_io_ops;
1572 static const struct hda_controller_ops pci_hda_ops;
1573
1574 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1575 int dev, unsigned int driver_caps,
1576 struct azx **rchip)
1577 {
1578 static struct snd_device_ops ops = {
1579 .dev_disconnect = azx_dev_disconnect,
1580 .dev_free = azx_dev_free,
1581 };
1582 struct hda_intel *hda;
1583 struct azx *chip;
1584 int err;
1585
1586 *rchip = NULL;
1587
1588 err = pci_enable_device(pci);
1589 if (err < 0)
1590 return err;
1591
1592 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1593 if (!hda) {
1594 pci_disable_device(pci);
1595 return -ENOMEM;
1596 }
1597
1598 chip = &hda->chip;
1599 mutex_init(&chip->open_mutex);
1600 chip->card = card;
1601 chip->pci = pci;
1602 chip->ops = &pci_hda_ops;
1603 chip->driver_caps = driver_caps;
1604 chip->driver_type = driver_caps & 0xff;
1605 check_msi(chip);
1606 chip->dev_index = dev;
1607 chip->jackpoll_ms = jackpoll_ms;
1608 INIT_LIST_HEAD(&chip->pcm_list);
1609 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1610 INIT_LIST_HEAD(&hda->list);
1611 init_vga_switcheroo(chip);
1612 init_completion(&hda->probe_wait);
1613
1614 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1615
1616 check_probe_mask(chip, dev);
1617
1618 chip->single_cmd = single_cmd;
1619 azx_check_snoop_available(chip);
1620
1621 if (bdl_pos_adj[dev] < 0)
1622 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1623 else
1624 chip->bdl_pos_adj = bdl_pos_adj[dev];
1625
1626 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1627 if (err < 0) {
1628 kfree(hda);
1629 pci_disable_device(pci);
1630 return err;
1631 }
1632
1633 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1634 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1635 chip->bus.needs_damn_long_delay = 1;
1636 }
1637
1638 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1639 if (err < 0) {
1640 dev_err(card->dev, "Error creating device [card]!\n");
1641 azx_free(chip);
1642 return err;
1643 }
1644
1645 /* continue probing in work context as may trigger request module */
1646 INIT_WORK(&hda->probe_work, azx_probe_work);
1647
1648 *rchip = chip;
1649
1650 return 0;
1651 }
1652
1653 static int azx_first_init(struct azx *chip)
1654 {
1655 int dev = chip->dev_index;
1656 struct pci_dev *pci = chip->pci;
1657 struct snd_card *card = chip->card;
1658 struct hdac_bus *bus = azx_bus(chip);
1659 int err;
1660 unsigned short gcap;
1661 unsigned int dma_bits = 64;
1662
1663 #if BITS_PER_LONG != 64
1664 /* Fix up base address on ULI M5461 */
1665 if (chip->driver_type == AZX_DRIVER_ULI) {
1666 u16 tmp3;
1667 pci_read_config_word(pci, 0x40, &tmp3);
1668 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1669 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1670 }
1671 #endif
1672
1673 err = pci_request_regions(pci, "ICH HD audio");
1674 if (err < 0)
1675 return err;
1676 chip->region_requested = 1;
1677
1678 bus->addr = pci_resource_start(pci, 0);
1679 bus->remap_addr = pci_ioremap_bar(pci, 0);
1680 if (bus->remap_addr == NULL) {
1681 dev_err(card->dev, "ioremap error\n");
1682 return -ENXIO;
1683 }
1684
1685 if (chip->msi) {
1686 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1687 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1688 pci->no_64bit_msi = true;
1689 }
1690 if (pci_enable_msi(pci) < 0)
1691 chip->msi = 0;
1692 }
1693
1694 if (azx_acquire_irq(chip, 0) < 0)
1695 return -EBUSY;
1696
1697 pci_set_master(pci);
1698 synchronize_irq(bus->irq);
1699
1700 gcap = azx_readw(chip, GCAP);
1701 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1702
1703 /* AMD devices support 40 or 48bit DMA, take the safe one */
1704 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1705 dma_bits = 40;
1706
1707 /* disable SB600 64bit support for safety */
1708 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1709 struct pci_dev *p_smbus;
1710 dma_bits = 40;
1711 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1712 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1713 NULL);
1714 if (p_smbus) {
1715 if (p_smbus->revision < 0x30)
1716 gcap &= ~AZX_GCAP_64OK;
1717 pci_dev_put(p_smbus);
1718 }
1719 }
1720
1721 /* disable 64bit DMA address on some devices */
1722 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1723 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1724 gcap &= ~AZX_GCAP_64OK;
1725 }
1726
1727 /* disable buffer size rounding to 128-byte multiples if supported */
1728 if (align_buffer_size >= 0)
1729 chip->align_buffer_size = !!align_buffer_size;
1730 else {
1731 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1732 chip->align_buffer_size = 0;
1733 else
1734 chip->align_buffer_size = 1;
1735 }
1736
1737 /* allow 64bit DMA address if supported by H/W */
1738 if (!(gcap & AZX_GCAP_64OK))
1739 dma_bits = 32;
1740 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1741 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1742 } else {
1743 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1744 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1745 }
1746
1747 /* read number of streams from GCAP register instead of using
1748 * hardcoded value
1749 */
1750 chip->capture_streams = (gcap >> 8) & 0x0f;
1751 chip->playback_streams = (gcap >> 12) & 0x0f;
1752 if (!chip->playback_streams && !chip->capture_streams) {
1753 /* gcap didn't give any info, switching to old method */
1754
1755 switch (chip->driver_type) {
1756 case AZX_DRIVER_ULI:
1757 chip->playback_streams = ULI_NUM_PLAYBACK;
1758 chip->capture_streams = ULI_NUM_CAPTURE;
1759 break;
1760 case AZX_DRIVER_ATIHDMI:
1761 case AZX_DRIVER_ATIHDMI_NS:
1762 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1763 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1764 break;
1765 case AZX_DRIVER_GENERIC:
1766 default:
1767 chip->playback_streams = ICH6_NUM_PLAYBACK;
1768 chip->capture_streams = ICH6_NUM_CAPTURE;
1769 break;
1770 }
1771 }
1772 chip->capture_index_offset = 0;
1773 chip->playback_index_offset = chip->capture_streams;
1774 chip->num_streams = chip->playback_streams + chip->capture_streams;
1775
1776 /* initialize streams */
1777 err = azx_init_streams(chip);
1778 if (err < 0)
1779 return err;
1780
1781 err = azx_alloc_stream_pages(chip);
1782 if (err < 0)
1783 return err;
1784
1785 /* initialize chip */
1786 azx_init_pci(chip);
1787
1788 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1789 struct hda_intel *hda;
1790
1791 hda = container_of(chip, struct hda_intel, chip);
1792 haswell_set_bclk(hda);
1793 }
1794
1795 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1796
1797 /* codec detection */
1798 if (!azx_bus(chip)->codec_mask) {
1799 dev_err(card->dev, "no codecs found!\n");
1800 return -ENODEV;
1801 }
1802
1803 strcpy(card->driver, "HDA-Intel");
1804 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1805 sizeof(card->shortname));
1806 snprintf(card->longname, sizeof(card->longname),
1807 "%s at 0x%lx irq %i",
1808 card->shortname, bus->addr, bus->irq);
1809
1810 return 0;
1811 }
1812
1813 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1814 /* callback from request_firmware_nowait() */
1815 static void azx_firmware_cb(const struct firmware *fw, void *context)
1816 {
1817 struct snd_card *card = context;
1818 struct azx *chip = card->private_data;
1819 struct pci_dev *pci = chip->pci;
1820
1821 if (!fw) {
1822 dev_err(card->dev, "Cannot load firmware, aborting\n");
1823 goto error;
1824 }
1825
1826 chip->fw = fw;
1827 if (!chip->disabled) {
1828 /* continue probing */
1829 if (azx_probe_continue(chip))
1830 goto error;
1831 }
1832 return; /* OK */
1833
1834 error:
1835 snd_card_free(card);
1836 pci_set_drvdata(pci, NULL);
1837 }
1838 #endif
1839
1840 /*
1841 * HDA controller ops.
1842 */
1843
1844 /* PCI register access. */
1845 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1846 {
1847 writel(value, addr);
1848 }
1849
1850 static u32 pci_azx_readl(u32 __iomem *addr)
1851 {
1852 return readl(addr);
1853 }
1854
1855 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1856 {
1857 writew(value, addr);
1858 }
1859
1860 static u16 pci_azx_readw(u16 __iomem *addr)
1861 {
1862 return readw(addr);
1863 }
1864
1865 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1866 {
1867 writeb(value, addr);
1868 }
1869
1870 static u8 pci_azx_readb(u8 __iomem *addr)
1871 {
1872 return readb(addr);
1873 }
1874
1875 static int disable_msi_reset_irq(struct azx *chip)
1876 {
1877 struct hdac_bus *bus = azx_bus(chip);
1878 int err;
1879
1880 free_irq(bus->irq, chip);
1881 bus->irq = -1;
1882 pci_disable_msi(chip->pci);
1883 chip->msi = 0;
1884 err = azx_acquire_irq(chip, 1);
1885 if (err < 0)
1886 return err;
1887
1888 return 0;
1889 }
1890
1891 /* DMA page allocation helpers. */
1892 static int dma_alloc_pages(struct hdac_bus *bus,
1893 int type,
1894 size_t size,
1895 struct snd_dma_buffer *buf)
1896 {
1897 struct azx *chip = bus_to_azx(bus);
1898 int err;
1899
1900 err = snd_dma_alloc_pages(type,
1901 bus->dev,
1902 size, buf);
1903 if (err < 0)
1904 return err;
1905 mark_pages_wc(chip, buf, true);
1906 return 0;
1907 }
1908
1909 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1910 {
1911 struct azx *chip = bus_to_azx(bus);
1912
1913 mark_pages_wc(chip, buf, false);
1914 snd_dma_free_pages(buf);
1915 }
1916
1917 static int substream_alloc_pages(struct azx *chip,
1918 struct snd_pcm_substream *substream,
1919 size_t size)
1920 {
1921 struct azx_dev *azx_dev = get_azx_dev(substream);
1922 int ret;
1923
1924 mark_runtime_wc(chip, azx_dev, substream, false);
1925 ret = snd_pcm_lib_malloc_pages(substream, size);
1926 if (ret < 0)
1927 return ret;
1928 mark_runtime_wc(chip, azx_dev, substream, true);
1929 return 0;
1930 }
1931
1932 static int substream_free_pages(struct azx *chip,
1933 struct snd_pcm_substream *substream)
1934 {
1935 struct azx_dev *azx_dev = get_azx_dev(substream);
1936 mark_runtime_wc(chip, azx_dev, substream, false);
1937 return snd_pcm_lib_free_pages(substream);
1938 }
1939
1940 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1941 struct vm_area_struct *area)
1942 {
1943 #ifdef CONFIG_X86
1944 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1945 struct azx *chip = apcm->chip;
1946 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1947 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1948 #endif
1949 }
1950
1951 static const struct hdac_io_ops pci_hda_io_ops = {
1952 .reg_writel = pci_azx_writel,
1953 .reg_readl = pci_azx_readl,
1954 .reg_writew = pci_azx_writew,
1955 .reg_readw = pci_azx_readw,
1956 .reg_writeb = pci_azx_writeb,
1957 .reg_readb = pci_azx_readb,
1958 .dma_alloc_pages = dma_alloc_pages,
1959 .dma_free_pages = dma_free_pages,
1960 };
1961
1962 static const struct hda_controller_ops pci_hda_ops = {
1963 .disable_msi_reset_irq = disable_msi_reset_irq,
1964 .substream_alloc_pages = substream_alloc_pages,
1965 .substream_free_pages = substream_free_pages,
1966 .pcm_mmap_prepare = pcm_mmap_prepare,
1967 .position_check = azx_position_check,
1968 .link_power = azx_intel_link_power,
1969 };
1970
1971 static int azx_probe(struct pci_dev *pci,
1972 const struct pci_device_id *pci_id)
1973 {
1974 static int dev;
1975 struct snd_card *card;
1976 struct hda_intel *hda;
1977 struct azx *chip;
1978 bool schedule_probe;
1979 int err;
1980
1981 if (dev >= SNDRV_CARDS)
1982 return -ENODEV;
1983 if (!enable[dev]) {
1984 dev++;
1985 return -ENOENT;
1986 }
1987
1988 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1989 0, &card);
1990 if (err < 0) {
1991 dev_err(&pci->dev, "Error creating card!\n");
1992 return err;
1993 }
1994
1995 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1996 if (err < 0)
1997 goto out_free;
1998 card->private_data = chip;
1999 hda = container_of(chip, struct hda_intel, chip);
2000
2001 pci_set_drvdata(pci, card);
2002
2003 err = register_vga_switcheroo(chip);
2004 if (err < 0) {
2005 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2006 goto out_free;
2007 }
2008
2009 if (check_hdmi_disabled(pci)) {
2010 dev_info(card->dev, "VGA controller is disabled\n");
2011 dev_info(card->dev, "Delaying initialization\n");
2012 chip->disabled = true;
2013 }
2014
2015 schedule_probe = !chip->disabled;
2016
2017 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2018 if (patch[dev] && *patch[dev]) {
2019 dev_info(card->dev, "Applying patch firmware '%s'\n",
2020 patch[dev]);
2021 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2022 &pci->dev, GFP_KERNEL, card,
2023 azx_firmware_cb);
2024 if (err < 0)
2025 goto out_free;
2026 schedule_probe = false; /* continued in azx_firmware_cb() */
2027 }
2028 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2029
2030 #ifndef CONFIG_SND_HDA_I915
2031 if (CONTROLLER_IN_GPU(pci))
2032 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2033 #endif
2034
2035 if (schedule_probe)
2036 schedule_work(&hda->probe_work);
2037
2038 dev++;
2039 if (chip->disabled)
2040 complete_all(&hda->probe_wait);
2041 return 0;
2042
2043 out_free:
2044 snd_card_free(card);
2045 return err;
2046 }
2047
2048 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2049 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2050 [AZX_DRIVER_NVIDIA] = 8,
2051 [AZX_DRIVER_TERA] = 1,
2052 };
2053
2054 static int azx_probe_continue(struct azx *chip)
2055 {
2056 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2057 struct hdac_bus *bus = azx_bus(chip);
2058 struct pci_dev *pci = chip->pci;
2059 int dev = chip->dev_index;
2060 int err;
2061
2062 hda->probe_continued = 1;
2063
2064 /* Request display power well for the HDA controller or codec. For
2065 * Haswell/Broadwell, both the display HDA controller and codec need
2066 * this power. For other platforms, like Baytrail/Braswell, only the
2067 * display codec needs the power and it can be released after probe.
2068 */
2069 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2070 /* HSW/BDW controllers need this power */
2071 if (CONTROLLER_IN_GPU(pci))
2072 hda->need_i915_power = 1;
2073
2074 err = snd_hdac_i915_init(bus);
2075 if (err < 0) {
2076 /* if the controller is bound only with HDMI/DP
2077 * (for HSW and BDW), we need to abort the probe;
2078 * for other chips, still continue probing as other
2079 * codecs can be on the same link.
2080 */
2081 if (CONTROLLER_IN_GPU(pci))
2082 goto out_free;
2083 else
2084 goto skip_i915;
2085 }
2086
2087 err = snd_hdac_display_power(bus, true);
2088 if (err < 0) {
2089 dev_err(chip->card->dev,
2090 "Cannot turn on display power on i915\n");
2091 goto i915_power_fail;
2092 }
2093 }
2094
2095 skip_i915:
2096 err = azx_first_init(chip);
2097 if (err < 0)
2098 goto out_free;
2099
2100 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2101 chip->beep_mode = beep_mode[dev];
2102 #endif
2103
2104 /* create codec instances */
2105 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2106 if (err < 0)
2107 goto out_free;
2108
2109 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2110 if (chip->fw) {
2111 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2112 chip->fw->data);
2113 if (err < 0)
2114 goto out_free;
2115 #ifndef CONFIG_PM
2116 release_firmware(chip->fw); /* no longer needed */
2117 chip->fw = NULL;
2118 #endif
2119 }
2120 #endif
2121 if ((probe_only[dev] & 1) == 0) {
2122 err = azx_codec_configure(chip);
2123 if (err < 0)
2124 goto out_free;
2125 }
2126
2127 err = snd_card_register(chip->card);
2128 if (err < 0)
2129 goto out_free;
2130
2131 chip->running = 1;
2132 azx_add_card_list(chip);
2133 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2134 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2135 pm_runtime_put_noidle(&pci->dev);
2136
2137 out_free:
2138 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2139 && !hda->need_i915_power)
2140 snd_hdac_display_power(bus, false);
2141
2142 i915_power_fail:
2143 if (err < 0)
2144 hda->init_failed = 1;
2145 complete_all(&hda->probe_wait);
2146 return err;
2147 }
2148
2149 static void azx_remove(struct pci_dev *pci)
2150 {
2151 struct snd_card *card = pci_get_drvdata(pci);
2152
2153 if (card)
2154 snd_card_free(card);
2155 }
2156
2157 static void azx_shutdown(struct pci_dev *pci)
2158 {
2159 struct snd_card *card = pci_get_drvdata(pci);
2160 struct azx *chip;
2161
2162 if (!card)
2163 return;
2164 chip = card->private_data;
2165 if (chip && chip->running)
2166 azx_stop_chip(chip);
2167 }
2168
2169 /* PCI IDs */
2170 static const struct pci_device_id azx_ids[] = {
2171 /* CPT */
2172 { PCI_DEVICE(0x8086, 0x1c20),
2173 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2174 /* PBG */
2175 { PCI_DEVICE(0x8086, 0x1d20),
2176 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2177 /* Panther Point */
2178 { PCI_DEVICE(0x8086, 0x1e20),
2179 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2180 /* Lynx Point */
2181 { PCI_DEVICE(0x8086, 0x8c20),
2182 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2183 /* 9 Series */
2184 { PCI_DEVICE(0x8086, 0x8ca0),
2185 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2186 /* Wellsburg */
2187 { PCI_DEVICE(0x8086, 0x8d20),
2188 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2189 { PCI_DEVICE(0x8086, 0x8d21),
2190 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2191 /* Lewisburg */
2192 { PCI_DEVICE(0x8086, 0xa1f0),
2193 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2194 { PCI_DEVICE(0x8086, 0xa270),
2195 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2196 /* Lynx Point-LP */
2197 { PCI_DEVICE(0x8086, 0x9c20),
2198 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2199 /* Lynx Point-LP */
2200 { PCI_DEVICE(0x8086, 0x9c21),
2201 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2202 /* Wildcat Point-LP */
2203 { PCI_DEVICE(0x8086, 0x9ca0),
2204 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2205 /* Sunrise Point */
2206 { PCI_DEVICE(0x8086, 0xa170),
2207 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2208 /* Sunrise Point-LP */
2209 { PCI_DEVICE(0x8086, 0x9d70),
2210 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2211 /* Broxton-P(Apollolake) */
2212 { PCI_DEVICE(0x8086, 0x5a98),
2213 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2214 /* Haswell */
2215 { PCI_DEVICE(0x8086, 0x0a0c),
2216 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2217 { PCI_DEVICE(0x8086, 0x0c0c),
2218 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2219 { PCI_DEVICE(0x8086, 0x0d0c),
2220 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2221 /* Broadwell */
2222 { PCI_DEVICE(0x8086, 0x160c),
2223 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2224 /* 5 Series/3400 */
2225 { PCI_DEVICE(0x8086, 0x3b56),
2226 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2227 /* Poulsbo */
2228 { PCI_DEVICE(0x8086, 0x811b),
2229 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2230 /* Oaktrail */
2231 { PCI_DEVICE(0x8086, 0x080a),
2232 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2233 /* BayTrail */
2234 { PCI_DEVICE(0x8086, 0x0f04),
2235 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2236 /* Braswell */
2237 { PCI_DEVICE(0x8086, 0x2284),
2238 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2239 /* ICH6 */
2240 { PCI_DEVICE(0x8086, 0x2668),
2241 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2242 /* ICH7 */
2243 { PCI_DEVICE(0x8086, 0x27d8),
2244 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2245 /* ESB2 */
2246 { PCI_DEVICE(0x8086, 0x269a),
2247 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2248 /* ICH8 */
2249 { PCI_DEVICE(0x8086, 0x284b),
2250 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2251 /* ICH9 */
2252 { PCI_DEVICE(0x8086, 0x293e),
2253 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2254 /* ICH9 */
2255 { PCI_DEVICE(0x8086, 0x293f),
2256 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2257 /* ICH10 */
2258 { PCI_DEVICE(0x8086, 0x3a3e),
2259 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2260 /* ICH10 */
2261 { PCI_DEVICE(0x8086, 0x3a6e),
2262 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2263 /* Generic Intel */
2264 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2265 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2266 .class_mask = 0xffffff,
2267 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2268 /* ATI SB 450/600/700/800/900 */
2269 { PCI_DEVICE(0x1002, 0x437b),
2270 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2271 { PCI_DEVICE(0x1002, 0x4383),
2272 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2273 /* AMD Hudson */
2274 { PCI_DEVICE(0x1022, 0x780d),
2275 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2276 /* ATI HDMI */
2277 { PCI_DEVICE(0x1002, 0x1308),
2278 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2279 { PCI_DEVICE(0x1002, 0x157a),
2280 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2281 { PCI_DEVICE(0x1002, 0x793b),
2282 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2283 { PCI_DEVICE(0x1002, 0x7919),
2284 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2285 { PCI_DEVICE(0x1002, 0x960f),
2286 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2287 { PCI_DEVICE(0x1002, 0x970f),
2288 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2289 { PCI_DEVICE(0x1002, 0x9840),
2290 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2291 { PCI_DEVICE(0x1002, 0xaa00),
2292 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2293 { PCI_DEVICE(0x1002, 0xaa08),
2294 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2295 { PCI_DEVICE(0x1002, 0xaa10),
2296 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2297 { PCI_DEVICE(0x1002, 0xaa18),
2298 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2299 { PCI_DEVICE(0x1002, 0xaa20),
2300 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2301 { PCI_DEVICE(0x1002, 0xaa28),
2302 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2303 { PCI_DEVICE(0x1002, 0xaa30),
2304 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2305 { PCI_DEVICE(0x1002, 0xaa38),
2306 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307 { PCI_DEVICE(0x1002, 0xaa40),
2308 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309 { PCI_DEVICE(0x1002, 0xaa48),
2310 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311 { PCI_DEVICE(0x1002, 0xaa50),
2312 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313 { PCI_DEVICE(0x1002, 0xaa58),
2314 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315 { PCI_DEVICE(0x1002, 0xaa60),
2316 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317 { PCI_DEVICE(0x1002, 0xaa68),
2318 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319 { PCI_DEVICE(0x1002, 0xaa80),
2320 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321 { PCI_DEVICE(0x1002, 0xaa88),
2322 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323 { PCI_DEVICE(0x1002, 0xaa90),
2324 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325 { PCI_DEVICE(0x1002, 0xaa98),
2326 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327 { PCI_DEVICE(0x1002, 0x9902),
2328 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2329 { PCI_DEVICE(0x1002, 0xaaa0),
2330 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2331 { PCI_DEVICE(0x1002, 0xaaa8),
2332 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2333 { PCI_DEVICE(0x1002, 0xaab0),
2334 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2335 { PCI_DEVICE(0x1002, 0xaac0),
2336 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2337 { PCI_DEVICE(0x1002, 0xaac8),
2338 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2339 { PCI_DEVICE(0x1002, 0xaad8),
2340 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2341 { PCI_DEVICE(0x1002, 0xaae8),
2342 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2343 /* VIA VT8251/VT8237A */
2344 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2345 /* VIA GFX VT7122/VX900 */
2346 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2347 /* VIA GFX VT6122/VX11 */
2348 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2349 /* SIS966 */
2350 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2351 /* ULI M5461 */
2352 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2353 /* NVIDIA MCP */
2354 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2355 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2356 .class_mask = 0xffffff,
2357 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2358 /* Teradici */
2359 { PCI_DEVICE(0x6549, 0x1200),
2360 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2361 { PCI_DEVICE(0x6549, 0x2200),
2362 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2363 /* Creative X-Fi (CA0110-IBG) */
2364 /* CTHDA chips */
2365 { PCI_DEVICE(0x1102, 0x0010),
2366 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2367 { PCI_DEVICE(0x1102, 0x0012),
2368 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2369 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2370 /* the following entry conflicts with snd-ctxfi driver,
2371 * as ctxfi driver mutates from HD-audio to native mode with
2372 * a special command sequence.
2373 */
2374 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2375 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2376 .class_mask = 0xffffff,
2377 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2378 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2379 #else
2380 /* this entry seems still valid -- i.e. without emu20kx chip */
2381 { PCI_DEVICE(0x1102, 0x0009),
2382 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2383 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2384 #endif
2385 /* CM8888 */
2386 { PCI_DEVICE(0x13f6, 0x5011),
2387 .driver_data = AZX_DRIVER_CMEDIA |
2388 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2389 /* Vortex86MX */
2390 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2391 /* VMware HDAudio */
2392 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2393 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2394 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2395 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2396 .class_mask = 0xffffff,
2397 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2398 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2399 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2400 .class_mask = 0xffffff,
2401 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2402 { 0, }
2403 };
2404 MODULE_DEVICE_TABLE(pci, azx_ids);
2405
2406 /* pci_driver definition */
2407 static struct pci_driver azx_driver = {
2408 .name = KBUILD_MODNAME,
2409 .id_table = azx_ids,
2410 .probe = azx_probe,
2411 .remove = azx_remove,
2412 .shutdown = azx_shutdown,
2413 .driver = {
2414 .pm = AZX_PM_OPS,
2415 },
2416 };
2417
2418 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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