3fc259154c0b562e0d67f99bc2a55fafd590d30f
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
45 #include "hda_jack.h"
46
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
59
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
63
64 struct hdmi_spec_per_cvt {
65 hda_nid_t cvt_nid;
66 int assigned;
67 unsigned int channels_min;
68 unsigned int channels_max;
69 u32 rates;
70 u64 formats;
71 unsigned int maxbps;
72 };
73
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS 32
76
77 struct hdmi_spec_per_pin {
78 hda_nid_t pin_nid;
79 /* pin idx, different device entries on the same pin use the same idx */
80 int pin_nid_idx;
81 int num_mux_nids;
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
83 int mux_idx;
84 hda_nid_t cvt_nid;
85
86 struct hda_codec *codec;
87 struct hdmi_eld sink_eld;
88 struct mutex lock;
89 struct delayed_work work;
90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
92 int repoll_count;
93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
95 bool non_pcm;
96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 struct snd_info_entry *proc_entry;
100 #endif
101 };
102
103 /* operations used by generic code that can be overridden by patches */
104 struct hdmi_ops {
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
107
108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
110
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
113
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
116
117 };
118
119 struct hdmi_pcm {
120 struct hda_pcm *pcm;
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
123 };
124
125 struct hdmi_spec {
126 int num_cvts;
127 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids[4]; /* only for haswell fix */
129
130 int num_pins;
131 struct snd_array pins; /* struct hdmi_spec_per_pin */
132 struct hdmi_pcm pcm_rec[16];
133 struct mutex pcm_lock;
134 /* pcm_bitmap means which pcms have been assigned to pins*/
135 unsigned long pcm_bitmap;
136 int pcm_used; /* counter of pcm_rec[] */
137 /* bitmap shows whether the pcm is opened in user space
138 * bit 0 means the first playback PCM (PCM3);
139 * bit 1 means the second playback PCM, and so on.
140 */
141 unsigned long pcm_in_use;
142
143 struct hdmi_eld temp_eld;
144 struct hdmi_ops ops;
145
146 bool dyn_pin_out;
147 bool dyn_pcm_assign;
148 /*
149 * Non-generic VIA/NVIDIA specific
150 */
151 struct hda_multi_out multiout;
152 struct hda_pcm_stream pcm_playback;
153
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 struct i915_audio_component_audio_ops i915_audio_ops;
156 bool i915_bound; /* was i915 bound in this driver? */
157
158 struct hdac_chmap chmap;
159 };
160
161 #ifdef CONFIG_SND_HDA_I915
162 #define codec_has_acomp(codec) \
163 ((codec)->bus->core.audio_component != NULL)
164 #else
165 #define codec_has_acomp(codec) false
166 #endif
167
168 struct hdmi_audio_infoframe {
169 u8 type; /* 0x84 */
170 u8 ver; /* 0x01 */
171 u8 len; /* 0x0a */
172
173 u8 checksum;
174
175 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
176 u8 SS01_SF24;
177 u8 CXT04;
178 u8 CA;
179 u8 LFEPBL01_LSV36_DM_INH7;
180 };
181
182 struct dp_audio_infoframe {
183 u8 type; /* 0x84 */
184 u8 len; /* 0x1b */
185 u8 ver; /* 0x11 << 2 */
186
187 u8 CC02_CT47; /* match with HDMI infoframe from this on */
188 u8 SS01_SF24;
189 u8 CXT04;
190 u8 CA;
191 u8 LFEPBL01_LSV36_DM_INH7;
192 };
193
194 union audio_infoframe {
195 struct hdmi_audio_infoframe hdmi;
196 struct dp_audio_infoframe dp;
197 u8 bytes[0];
198 };
199
200 /*
201 * HDMI routines
202 */
203
204 #define get_pin(spec, idx) \
205 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
206 #define get_cvt(spec, idx) \
207 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
208 /* obtain hdmi_pcm object assigned to idx */
209 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
210 /* obtain hda_pcm object assigned to idx */
211 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
212
213 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
214 {
215 struct hdmi_spec *spec = codec->spec;
216 int pin_idx;
217
218 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
219 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
220 return pin_idx;
221
222 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
223 return -EINVAL;
224 }
225
226 static int hinfo_to_pcm_index(struct hda_codec *codec,
227 struct hda_pcm_stream *hinfo)
228 {
229 struct hdmi_spec *spec = codec->spec;
230 int pcm_idx;
231
232 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
233 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
234 return pcm_idx;
235
236 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
237 return -EINVAL;
238 }
239
240 static int hinfo_to_pin_index(struct hda_codec *codec,
241 struct hda_pcm_stream *hinfo)
242 {
243 struct hdmi_spec *spec = codec->spec;
244 struct hdmi_spec_per_pin *per_pin;
245 int pin_idx;
246
247 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
248 per_pin = get_pin(spec, pin_idx);
249 if (per_pin->pcm &&
250 per_pin->pcm->pcm->stream == hinfo)
251 return pin_idx;
252 }
253
254 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
255 return -EINVAL;
256 }
257
258 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
259 int pcm_idx)
260 {
261 int i;
262 struct hdmi_spec_per_pin *per_pin;
263
264 for (i = 0; i < spec->num_pins; i++) {
265 per_pin = get_pin(spec, i);
266 if (per_pin->pcm_idx == pcm_idx)
267 return per_pin;
268 }
269 return NULL;
270 }
271
272 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
273 {
274 struct hdmi_spec *spec = codec->spec;
275 int cvt_idx;
276
277 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
278 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
279 return cvt_idx;
280
281 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
282 return -EINVAL;
283 }
284
285 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
286 struct snd_ctl_elem_info *uinfo)
287 {
288 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
289 struct hdmi_spec *spec = codec->spec;
290 struct hdmi_spec_per_pin *per_pin;
291 struct hdmi_eld *eld;
292 int pcm_idx;
293
294 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
295
296 pcm_idx = kcontrol->private_value;
297 mutex_lock(&spec->pcm_lock);
298 per_pin = pcm_idx_to_pin(spec, pcm_idx);
299 if (!per_pin) {
300 /* no pin is bound to the pcm */
301 uinfo->count = 0;
302 mutex_unlock(&spec->pcm_lock);
303 return 0;
304 }
305 eld = &per_pin->sink_eld;
306 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
307 mutex_unlock(&spec->pcm_lock);
308
309 return 0;
310 }
311
312 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
314 {
315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
316 struct hdmi_spec *spec = codec->spec;
317 struct hdmi_spec_per_pin *per_pin;
318 struct hdmi_eld *eld;
319 int pcm_idx;
320
321 pcm_idx = kcontrol->private_value;
322 mutex_lock(&spec->pcm_lock);
323 per_pin = pcm_idx_to_pin(spec, pcm_idx);
324 if (!per_pin) {
325 /* no pin is bound to the pcm */
326 memset(ucontrol->value.bytes.data, 0,
327 ARRAY_SIZE(ucontrol->value.bytes.data));
328 mutex_unlock(&spec->pcm_lock);
329 return 0;
330 }
331 eld = &per_pin->sink_eld;
332
333 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
334 eld->eld_size > ELD_MAX_SIZE) {
335 mutex_unlock(&spec->pcm_lock);
336 snd_BUG();
337 return -EINVAL;
338 }
339
340 memset(ucontrol->value.bytes.data, 0,
341 ARRAY_SIZE(ucontrol->value.bytes.data));
342 if (eld->eld_valid)
343 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
344 eld->eld_size);
345 mutex_unlock(&spec->pcm_lock);
346
347 return 0;
348 }
349
350 static struct snd_kcontrol_new eld_bytes_ctl = {
351 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
352 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
353 .name = "ELD",
354 .info = hdmi_eld_ctl_info,
355 .get = hdmi_eld_ctl_get,
356 };
357
358 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
359 int device)
360 {
361 struct snd_kcontrol *kctl;
362 struct hdmi_spec *spec = codec->spec;
363 int err;
364
365 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
366 if (!kctl)
367 return -ENOMEM;
368 kctl->private_value = pcm_idx;
369 kctl->id.device = device;
370
371 /* no pin nid is associated with the kctl now
372 * tbd: associate pin nid to eld ctl later
373 */
374 err = snd_hda_ctl_add(codec, 0, kctl);
375 if (err < 0)
376 return err;
377
378 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
379 return 0;
380 }
381
382 #ifdef BE_PARANOID
383 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
384 int *packet_index, int *byte_index)
385 {
386 int val;
387
388 val = snd_hda_codec_read(codec, pin_nid, 0,
389 AC_VERB_GET_HDMI_DIP_INDEX, 0);
390
391 *packet_index = val >> 5;
392 *byte_index = val & 0x1f;
393 }
394 #endif
395
396 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
397 int packet_index, int byte_index)
398 {
399 int val;
400
401 val = (packet_index << 5) | (byte_index & 0x1f);
402
403 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
404 }
405
406 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
407 unsigned char val)
408 {
409 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
410 }
411
412 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
413 {
414 struct hdmi_spec *spec = codec->spec;
415 int pin_out;
416
417 /* Unmute */
418 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
419 snd_hda_codec_write(codec, pin_nid, 0,
420 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
421
422 if (spec->dyn_pin_out)
423 /* Disable pin out until stream is active */
424 pin_out = 0;
425 else
426 /* Enable pin out: some machines with GM965 gets broken output
427 * when the pin is disabled or changed while using with HDMI
428 */
429 pin_out = PIN_OUT;
430
431 snd_hda_codec_write(codec, pin_nid, 0,
432 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
433 }
434
435 /*
436 * ELD proc files
437 */
438
439 #ifdef CONFIG_SND_PROC_FS
440 static void print_eld_info(struct snd_info_entry *entry,
441 struct snd_info_buffer *buffer)
442 {
443 struct hdmi_spec_per_pin *per_pin = entry->private_data;
444
445 mutex_lock(&per_pin->lock);
446 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
447 mutex_unlock(&per_pin->lock);
448 }
449
450 static void write_eld_info(struct snd_info_entry *entry,
451 struct snd_info_buffer *buffer)
452 {
453 struct hdmi_spec_per_pin *per_pin = entry->private_data;
454
455 mutex_lock(&per_pin->lock);
456 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
457 mutex_unlock(&per_pin->lock);
458 }
459
460 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
461 {
462 char name[32];
463 struct hda_codec *codec = per_pin->codec;
464 struct snd_info_entry *entry;
465 int err;
466
467 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
468 err = snd_card_proc_new(codec->card, name, &entry);
469 if (err < 0)
470 return err;
471
472 snd_info_set_text_ops(entry, per_pin, print_eld_info);
473 entry->c.text.write = write_eld_info;
474 entry->mode |= S_IWUSR;
475 per_pin->proc_entry = entry;
476
477 return 0;
478 }
479
480 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
481 {
482 if (!per_pin->codec->bus->shutdown) {
483 snd_info_free_entry(per_pin->proc_entry);
484 per_pin->proc_entry = NULL;
485 }
486 }
487 #else
488 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
489 int index)
490 {
491 return 0;
492 }
493 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
494 {
495 }
496 #endif
497
498 /*
499 * Audio InfoFrame routines
500 */
501
502 /*
503 * Enable Audio InfoFrame Transmission
504 */
505 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
506 hda_nid_t pin_nid)
507 {
508 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
509 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
510 AC_DIPXMIT_BEST);
511 }
512
513 /*
514 * Disable Audio InfoFrame Transmission
515 */
516 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
517 hda_nid_t pin_nid)
518 {
519 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
520 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
521 AC_DIPXMIT_DISABLE);
522 }
523
524 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
525 {
526 #ifdef CONFIG_SND_DEBUG_VERBOSE
527 int i;
528 int size;
529
530 size = snd_hdmi_get_eld_size(codec, pin_nid);
531 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
532
533 for (i = 0; i < 8; i++) {
534 size = snd_hda_codec_read(codec, pin_nid, 0,
535 AC_VERB_GET_HDMI_DIP_SIZE, i);
536 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
537 }
538 #endif
539 }
540
541 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
542 {
543 #ifdef BE_PARANOID
544 int i, j;
545 int size;
546 int pi, bi;
547 for (i = 0; i < 8; i++) {
548 size = snd_hda_codec_read(codec, pin_nid, 0,
549 AC_VERB_GET_HDMI_DIP_SIZE, i);
550 if (size == 0)
551 continue;
552
553 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
554 for (j = 1; j < 1000; j++) {
555 hdmi_write_dip_byte(codec, pin_nid, 0x0);
556 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
557 if (pi != i)
558 codec_dbg(codec, "dip index %d: %d != %d\n",
559 bi, pi, i);
560 if (bi == 0) /* byte index wrapped around */
561 break;
562 }
563 codec_dbg(codec,
564 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
565 i, size, j);
566 }
567 #endif
568 }
569
570 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
571 {
572 u8 *bytes = (u8 *)hdmi_ai;
573 u8 sum = 0;
574 int i;
575
576 hdmi_ai->checksum = 0;
577
578 for (i = 0; i < sizeof(*hdmi_ai); i++)
579 sum += bytes[i];
580
581 hdmi_ai->checksum = -sum;
582 }
583
584 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
585 hda_nid_t pin_nid,
586 u8 *dip, int size)
587 {
588 int i;
589
590 hdmi_debug_dip_size(codec, pin_nid);
591 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
592
593 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
594 for (i = 0; i < size; i++)
595 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
596 }
597
598 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
599 u8 *dip, int size)
600 {
601 u8 val;
602 int i;
603
604 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
605 != AC_DIPXMIT_BEST)
606 return false;
607
608 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
609 for (i = 0; i < size; i++) {
610 val = snd_hda_codec_read(codec, pin_nid, 0,
611 AC_VERB_GET_HDMI_DIP_DATA, 0);
612 if (val != dip[i])
613 return false;
614 }
615
616 return true;
617 }
618
619 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
620 hda_nid_t pin_nid,
621 int ca, int active_channels,
622 int conn_type)
623 {
624 union audio_infoframe ai;
625
626 memset(&ai, 0, sizeof(ai));
627 if (conn_type == 0) { /* HDMI */
628 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
629
630 hdmi_ai->type = 0x84;
631 hdmi_ai->ver = 0x01;
632 hdmi_ai->len = 0x0a;
633 hdmi_ai->CC02_CT47 = active_channels - 1;
634 hdmi_ai->CA = ca;
635 hdmi_checksum_audio_infoframe(hdmi_ai);
636 } else if (conn_type == 1) { /* DisplayPort */
637 struct dp_audio_infoframe *dp_ai = &ai.dp;
638
639 dp_ai->type = 0x84;
640 dp_ai->len = 0x1b;
641 dp_ai->ver = 0x11 << 2;
642 dp_ai->CC02_CT47 = active_channels - 1;
643 dp_ai->CA = ca;
644 } else {
645 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
646 pin_nid);
647 return;
648 }
649
650 /*
651 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
652 * sizeof(*dp_ai) to avoid partial match/update problems when
653 * the user switches between HDMI/DP monitors.
654 */
655 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
656 sizeof(ai))) {
657 codec_dbg(codec,
658 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
659 pin_nid,
660 active_channels, ca);
661 hdmi_stop_infoframe_trans(codec, pin_nid);
662 hdmi_fill_audio_infoframe(codec, pin_nid,
663 ai.bytes, sizeof(ai));
664 hdmi_start_infoframe_trans(codec, pin_nid);
665 }
666 }
667
668 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
669 struct hdmi_spec_per_pin *per_pin,
670 bool non_pcm)
671 {
672 struct hdmi_spec *spec = codec->spec;
673 struct hdac_chmap *chmap = &spec->chmap;
674 hda_nid_t pin_nid = per_pin->pin_nid;
675 int channels = per_pin->channels;
676 int active_channels;
677 struct hdmi_eld *eld;
678 int ca;
679
680 if (!channels)
681 return;
682
683 if (is_haswell_plus(codec))
684 snd_hda_codec_write(codec, pin_nid, 0,
685 AC_VERB_SET_AMP_GAIN_MUTE,
686 AMP_OUT_UNMUTE);
687
688 eld = &per_pin->sink_eld;
689
690 ca = snd_hdac_channel_allocation(&codec->core,
691 eld->info.spk_alloc, channels,
692 per_pin->chmap_set, non_pcm, per_pin->chmap);
693
694 active_channels = snd_hdac_get_active_channels(ca);
695
696 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
697 active_channels);
698
699 /*
700 * always configure channel mapping, it may have been changed by the
701 * user in the meantime
702 */
703 snd_hdac_setup_channel_mapping(&spec->chmap,
704 pin_nid, non_pcm, ca, channels,
705 per_pin->chmap, per_pin->chmap_set);
706
707 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
708 eld->info.conn_type);
709
710 per_pin->non_pcm = non_pcm;
711 }
712
713 /*
714 * Unsolicited events
715 */
716
717 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
718
719 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
720 {
721 struct hdmi_spec *spec = codec->spec;
722 int pin_idx = pin_nid_to_pin_index(codec, nid);
723
724 if (pin_idx < 0)
725 return;
726 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
727 snd_hda_jack_report_sync(codec);
728 }
729
730 static void jack_callback(struct hda_codec *codec,
731 struct hda_jack_callback *jack)
732 {
733 check_presence_and_report(codec, jack->nid);
734 }
735
736 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
737 {
738 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
739 struct hda_jack_tbl *jack;
740 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
741
742 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
743 if (!jack)
744 return;
745 jack->jack_dirty = 1;
746
747 codec_dbg(codec,
748 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
749 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
750 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
751
752 check_presence_and_report(codec, jack->nid);
753 }
754
755 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
756 {
757 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
758 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
759 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
760 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
761
762 codec_info(codec,
763 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
764 codec->addr,
765 tag,
766 subtag,
767 cp_state,
768 cp_ready);
769
770 /* TODO */
771 if (cp_state)
772 ;
773 if (cp_ready)
774 ;
775 }
776
777
778 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
779 {
780 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
781 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
782
783 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
784 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
785 return;
786 }
787
788 if (subtag == 0)
789 hdmi_intrinsic_event(codec, res);
790 else
791 hdmi_non_intrinsic_event(codec, res);
792 }
793
794 static void haswell_verify_D0(struct hda_codec *codec,
795 hda_nid_t cvt_nid, hda_nid_t nid)
796 {
797 int pwr;
798
799 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
800 * thus pins could only choose converter 0 for use. Make sure the
801 * converters are in correct power state */
802 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
803 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
804
805 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
806 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
807 AC_PWRST_D0);
808 msleep(40);
809 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
810 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
811 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
812 }
813 }
814
815 /*
816 * Callbacks
817 */
818
819 /* HBR should be Non-PCM, 8 channels */
820 #define is_hbr_format(format) \
821 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
822
823 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
824 bool hbr)
825 {
826 int pinctl, new_pinctl;
827
828 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
829 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
830 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
831
832 if (pinctl < 0)
833 return hbr ? -EINVAL : 0;
834
835 new_pinctl = pinctl & ~AC_PINCTL_EPT;
836 if (hbr)
837 new_pinctl |= AC_PINCTL_EPT_HBR;
838 else
839 new_pinctl |= AC_PINCTL_EPT_NATIVE;
840
841 codec_dbg(codec,
842 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
843 pin_nid,
844 pinctl == new_pinctl ? "" : "new-",
845 new_pinctl);
846
847 if (pinctl != new_pinctl)
848 snd_hda_codec_write(codec, pin_nid, 0,
849 AC_VERB_SET_PIN_WIDGET_CONTROL,
850 new_pinctl);
851 } else if (hbr)
852 return -EINVAL;
853
854 return 0;
855 }
856
857 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
858 hda_nid_t pin_nid, u32 stream_tag, int format)
859 {
860 struct hdmi_spec *spec = codec->spec;
861 int err;
862
863 if (is_haswell_plus(codec))
864 haswell_verify_D0(codec, cvt_nid, pin_nid);
865
866 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
867
868 if (err) {
869 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
870 return err;
871 }
872
873 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
874 return 0;
875 }
876
877 /* Try to find an available converter
878 * If pin_idx is less then zero, just try to find an available converter.
879 * Otherwise, try to find an available converter and get the cvt mux index
880 * of the pin.
881 */
882 static int hdmi_choose_cvt(struct hda_codec *codec,
883 int pin_idx, int *cvt_id, int *mux_id)
884 {
885 struct hdmi_spec *spec = codec->spec;
886 struct hdmi_spec_per_pin *per_pin;
887 struct hdmi_spec_per_cvt *per_cvt = NULL;
888 int cvt_idx, mux_idx = 0;
889
890 /* pin_idx < 0 means no pin will be bound to the converter */
891 if (pin_idx < 0)
892 per_pin = NULL;
893 else
894 per_pin = get_pin(spec, pin_idx);
895
896 /* Dynamically assign converter to stream */
897 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
898 per_cvt = get_cvt(spec, cvt_idx);
899
900 /* Must not already be assigned */
901 if (per_cvt->assigned)
902 continue;
903 if (per_pin == NULL)
904 break;
905 /* Must be in pin's mux's list of converters */
906 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
907 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
908 break;
909 /* Not in mux list */
910 if (mux_idx == per_pin->num_mux_nids)
911 continue;
912 break;
913 }
914
915 /* No free converters */
916 if (cvt_idx == spec->num_cvts)
917 return -EBUSY;
918
919 if (per_pin != NULL)
920 per_pin->mux_idx = mux_idx;
921
922 if (cvt_id)
923 *cvt_id = cvt_idx;
924 if (mux_id)
925 *mux_id = mux_idx;
926
927 return 0;
928 }
929
930 /* Assure the pin select the right convetor */
931 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
932 struct hdmi_spec_per_pin *per_pin)
933 {
934 hda_nid_t pin_nid = per_pin->pin_nid;
935 int mux_idx, curr;
936
937 mux_idx = per_pin->mux_idx;
938 curr = snd_hda_codec_read(codec, pin_nid, 0,
939 AC_VERB_GET_CONNECT_SEL, 0);
940 if (curr != mux_idx)
941 snd_hda_codec_write_cache(codec, pin_nid, 0,
942 AC_VERB_SET_CONNECT_SEL,
943 mux_idx);
944 }
945
946 /* get the mux index for the converter of the pins
947 * converter's mux index is the same for all pins on Intel platform
948 */
949 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
950 hda_nid_t cvt_nid)
951 {
952 int i;
953
954 for (i = 0; i < spec->num_cvts; i++)
955 if (spec->cvt_nids[i] == cvt_nid)
956 return i;
957 return -EINVAL;
958 }
959
960 /* Intel HDMI workaround to fix audio routing issue:
961 * For some Intel display codecs, pins share the same connection list.
962 * So a conveter can be selected by multiple pins and playback on any of these
963 * pins will generate sound on the external display, because audio flows from
964 * the same converter to the display pipeline. Also muting one pin may make
965 * other pins have no sound output.
966 * So this function assures that an assigned converter for a pin is not selected
967 * by any other pins.
968 */
969 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
970 hda_nid_t pin_nid, int mux_idx)
971 {
972 struct hdmi_spec *spec = codec->spec;
973 hda_nid_t nid;
974 int cvt_idx, curr;
975 struct hdmi_spec_per_cvt *per_cvt;
976
977 /* configure all pins, including "no physical connection" ones */
978 for_each_hda_codec_node(nid, codec) {
979 unsigned int wid_caps = get_wcaps(codec, nid);
980 unsigned int wid_type = get_wcaps_type(wid_caps);
981
982 if (wid_type != AC_WID_PIN)
983 continue;
984
985 if (nid == pin_nid)
986 continue;
987
988 curr = snd_hda_codec_read(codec, nid, 0,
989 AC_VERB_GET_CONNECT_SEL, 0);
990 if (curr != mux_idx)
991 continue;
992
993 /* choose an unassigned converter. The conveters in the
994 * connection list are in the same order as in the codec.
995 */
996 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
997 per_cvt = get_cvt(spec, cvt_idx);
998 if (!per_cvt->assigned) {
999 codec_dbg(codec,
1000 "choose cvt %d for pin nid %d\n",
1001 cvt_idx, nid);
1002 snd_hda_codec_write_cache(codec, nid, 0,
1003 AC_VERB_SET_CONNECT_SEL,
1004 cvt_idx);
1005 break;
1006 }
1007 }
1008 }
1009 }
1010
1011 /* A wrapper of intel_not_share_asigned_cvt() */
1012 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1013 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1014 {
1015 int mux_idx;
1016 struct hdmi_spec *spec = codec->spec;
1017
1018 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1019 return;
1020
1021 /* On Intel platform, the mapping of converter nid to
1022 * mux index of the pins are always the same.
1023 * The pin nid may be 0, this means all pins will not
1024 * share the converter.
1025 */
1026 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1027 if (mux_idx >= 0)
1028 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1029 }
1030
1031 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1032 * in dyn_pcm_assign mode.
1033 */
1034 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1035 struct hda_codec *codec,
1036 struct snd_pcm_substream *substream)
1037 {
1038 struct hdmi_spec *spec = codec->spec;
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 int cvt_idx, pcm_idx;
1041 struct hdmi_spec_per_cvt *per_cvt = NULL;
1042 int err;
1043
1044 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1045 if (pcm_idx < 0)
1046 return -EINVAL;
1047
1048 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1049 if (err)
1050 return err;
1051
1052 per_cvt = get_cvt(spec, cvt_idx);
1053 per_cvt->assigned = 1;
1054 hinfo->nid = per_cvt->cvt_nid;
1055
1056 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1057
1058 set_bit(pcm_idx, &spec->pcm_in_use);
1059 /* todo: setup spdif ctls assign */
1060
1061 /* Initially set the converter's capabilities */
1062 hinfo->channels_min = per_cvt->channels_min;
1063 hinfo->channels_max = per_cvt->channels_max;
1064 hinfo->rates = per_cvt->rates;
1065 hinfo->formats = per_cvt->formats;
1066 hinfo->maxbps = per_cvt->maxbps;
1067
1068 /* Store the updated parameters */
1069 runtime->hw.channels_min = hinfo->channels_min;
1070 runtime->hw.channels_max = hinfo->channels_max;
1071 runtime->hw.formats = hinfo->formats;
1072 runtime->hw.rates = hinfo->rates;
1073
1074 snd_pcm_hw_constraint_step(substream->runtime, 0,
1075 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1076 return 0;
1077 }
1078
1079 /*
1080 * HDA PCM callbacks
1081 */
1082 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1083 struct hda_codec *codec,
1084 struct snd_pcm_substream *substream)
1085 {
1086 struct hdmi_spec *spec = codec->spec;
1087 struct snd_pcm_runtime *runtime = substream->runtime;
1088 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
1089 struct hdmi_spec_per_pin *per_pin;
1090 struct hdmi_eld *eld;
1091 struct hdmi_spec_per_cvt *per_cvt = NULL;
1092 int err;
1093
1094 /* Validate hinfo */
1095 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1096 if (pcm_idx < 0)
1097 return -EINVAL;
1098
1099 mutex_lock(&spec->pcm_lock);
1100 pin_idx = hinfo_to_pin_index(codec, hinfo);
1101 if (!spec->dyn_pcm_assign) {
1102 if (snd_BUG_ON(pin_idx < 0)) {
1103 mutex_unlock(&spec->pcm_lock);
1104 return -EINVAL;
1105 }
1106 } else {
1107 /* no pin is assigned to the PCM
1108 * PA need pcm open successfully when probe
1109 */
1110 if (pin_idx < 0) {
1111 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1112 mutex_unlock(&spec->pcm_lock);
1113 return err;
1114 }
1115 }
1116
1117 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1118 if (err < 0) {
1119 mutex_unlock(&spec->pcm_lock);
1120 return err;
1121 }
1122
1123 per_cvt = get_cvt(spec, cvt_idx);
1124 /* Claim converter */
1125 per_cvt->assigned = 1;
1126
1127 set_bit(pcm_idx, &spec->pcm_in_use);
1128 per_pin = get_pin(spec, pin_idx);
1129 per_pin->cvt_nid = per_cvt->cvt_nid;
1130 hinfo->nid = per_cvt->cvt_nid;
1131
1132 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1133 AC_VERB_SET_CONNECT_SEL,
1134 mux_idx);
1135
1136 /* configure unused pins to choose other converters */
1137 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1138 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1139
1140 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1141
1142 /* Initially set the converter's capabilities */
1143 hinfo->channels_min = per_cvt->channels_min;
1144 hinfo->channels_max = per_cvt->channels_max;
1145 hinfo->rates = per_cvt->rates;
1146 hinfo->formats = per_cvt->formats;
1147 hinfo->maxbps = per_cvt->maxbps;
1148
1149 eld = &per_pin->sink_eld;
1150 /* Restrict capabilities by ELD if this isn't disabled */
1151 if (!static_hdmi_pcm && eld->eld_valid) {
1152 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1153 if (hinfo->channels_min > hinfo->channels_max ||
1154 !hinfo->rates || !hinfo->formats) {
1155 per_cvt->assigned = 0;
1156 hinfo->nid = 0;
1157 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1158 mutex_unlock(&spec->pcm_lock);
1159 return -ENODEV;
1160 }
1161 }
1162
1163 mutex_unlock(&spec->pcm_lock);
1164 /* Store the updated parameters */
1165 runtime->hw.channels_min = hinfo->channels_min;
1166 runtime->hw.channels_max = hinfo->channels_max;
1167 runtime->hw.formats = hinfo->formats;
1168 runtime->hw.rates = hinfo->rates;
1169
1170 snd_pcm_hw_constraint_step(substream->runtime, 0,
1171 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1172 return 0;
1173 }
1174
1175 /*
1176 * HDA/HDMI auto parsing
1177 */
1178 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1179 {
1180 struct hdmi_spec *spec = codec->spec;
1181 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1182 hda_nid_t pin_nid = per_pin->pin_nid;
1183
1184 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1185 codec_warn(codec,
1186 "HDMI: pin %d wcaps %#x does not support connection list\n",
1187 pin_nid, get_wcaps(codec, pin_nid));
1188 return -EINVAL;
1189 }
1190
1191 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1192 per_pin->mux_nids,
1193 HDA_MAX_CONNECTIONS);
1194
1195 return 0;
1196 }
1197
1198 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1199 struct hdmi_spec_per_pin *per_pin)
1200 {
1201 int i;
1202
1203 /* try the prefer PCM */
1204 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1205 return per_pin->pin_nid_idx;
1206
1207 /* have a second try; check the "reserved area" over num_pins */
1208 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1209 if (!test_bit(i, &spec->pcm_bitmap))
1210 return i;
1211 }
1212
1213 /* the last try; check the empty slots in pins */
1214 for (i = 0; i < spec->num_pins; i++) {
1215 if (!test_bit(i, &spec->pcm_bitmap))
1216 return i;
1217 }
1218 return -EBUSY;
1219 }
1220
1221 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1222 struct hdmi_spec_per_pin *per_pin)
1223 {
1224 int idx;
1225
1226 /* pcm already be attached to the pin */
1227 if (per_pin->pcm)
1228 return;
1229 idx = hdmi_find_pcm_slot(spec, per_pin);
1230 if (idx == -EBUSY)
1231 return;
1232 per_pin->pcm_idx = idx;
1233 per_pin->pcm = get_hdmi_pcm(spec, idx);
1234 set_bit(idx, &spec->pcm_bitmap);
1235 }
1236
1237 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1238 struct hdmi_spec_per_pin *per_pin)
1239 {
1240 int idx;
1241
1242 /* pcm already be detached from the pin */
1243 if (!per_pin->pcm)
1244 return;
1245 idx = per_pin->pcm_idx;
1246 per_pin->pcm_idx = -1;
1247 per_pin->pcm = NULL;
1248 if (idx >= 0 && idx < spec->pcm_used)
1249 clear_bit(idx, &spec->pcm_bitmap);
1250 }
1251
1252 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1253 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1254 {
1255 int mux_idx;
1256
1257 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1258 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1259 break;
1260 return mux_idx;
1261 }
1262
1263 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1264
1265 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1266 struct hdmi_spec_per_pin *per_pin)
1267 {
1268 struct hda_codec *codec = per_pin->codec;
1269 struct hda_pcm *pcm;
1270 struct hda_pcm_stream *hinfo;
1271 struct snd_pcm_substream *substream;
1272 int mux_idx;
1273 bool non_pcm;
1274
1275 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1276 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1277 else
1278 return;
1279 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1280 return;
1281
1282 /* hdmi audio only uses playback and one substream */
1283 hinfo = pcm->stream;
1284 substream = pcm->pcm->streams[0].substream;
1285
1286 per_pin->cvt_nid = hinfo->nid;
1287
1288 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1289 if (mux_idx < per_pin->num_mux_nids)
1290 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1291 AC_VERB_SET_CONNECT_SEL,
1292 mux_idx);
1293 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1294
1295 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1296 if (substream->runtime)
1297 per_pin->channels = substream->runtime->channels;
1298 per_pin->setup = true;
1299 per_pin->mux_idx = mux_idx;
1300
1301 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1302 }
1303
1304 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1305 struct hdmi_spec_per_pin *per_pin)
1306 {
1307 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1308 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1309
1310 per_pin->chmap_set = false;
1311 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1312
1313 per_pin->setup = false;
1314 per_pin->channels = 0;
1315 }
1316
1317 /* update per_pin ELD from the given new ELD;
1318 * setup info frame and notification accordingly
1319 */
1320 static void update_eld(struct hda_codec *codec,
1321 struct hdmi_spec_per_pin *per_pin,
1322 struct hdmi_eld *eld)
1323 {
1324 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1325 struct hdmi_spec *spec = codec->spec;
1326 bool old_eld_valid = pin_eld->eld_valid;
1327 bool eld_changed;
1328 int pcm_idx = -1;
1329
1330 /* for monitor disconnection, save pcm_idx firstly */
1331 pcm_idx = per_pin->pcm_idx;
1332 if (spec->dyn_pcm_assign) {
1333 if (eld->eld_valid) {
1334 hdmi_attach_hda_pcm(spec, per_pin);
1335 hdmi_pcm_setup_pin(spec, per_pin);
1336 } else {
1337 hdmi_pcm_reset_pin(spec, per_pin);
1338 hdmi_detach_hda_pcm(spec, per_pin);
1339 }
1340 }
1341 /* if pcm_idx == -1, it means this is in monitor connection event
1342 * we can get the correct pcm_idx now.
1343 */
1344 if (pcm_idx == -1)
1345 pcm_idx = per_pin->pcm_idx;
1346
1347 if (eld->eld_valid)
1348 snd_hdmi_show_eld(codec, &eld->info);
1349
1350 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1351 if (eld->eld_valid && pin_eld->eld_valid)
1352 if (pin_eld->eld_size != eld->eld_size ||
1353 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1354 eld->eld_size) != 0)
1355 eld_changed = true;
1356
1357 pin_eld->eld_valid = eld->eld_valid;
1358 pin_eld->eld_size = eld->eld_size;
1359 if (eld->eld_valid)
1360 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1361 pin_eld->info = eld->info;
1362
1363 /*
1364 * Re-setup pin and infoframe. This is needed e.g. when
1365 * - sink is first plugged-in
1366 * - transcoder can change during stream playback on Haswell
1367 * and this can make HW reset converter selection on a pin.
1368 */
1369 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1370 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1371 intel_verify_pin_cvt_connect(codec, per_pin);
1372 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1373 per_pin->mux_idx);
1374 }
1375
1376 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1377 }
1378
1379 if (eld_changed && pcm_idx >= 0)
1380 snd_ctl_notify(codec->card,
1381 SNDRV_CTL_EVENT_MASK_VALUE |
1382 SNDRV_CTL_EVENT_MASK_INFO,
1383 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1384 }
1385
1386 /* update ELD and jack state via HD-audio verbs */
1387 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1388 int repoll)
1389 {
1390 struct hda_jack_tbl *jack;
1391 struct hda_codec *codec = per_pin->codec;
1392 struct hdmi_spec *spec = codec->spec;
1393 struct hdmi_eld *eld = &spec->temp_eld;
1394 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1395 hda_nid_t pin_nid = per_pin->pin_nid;
1396 /*
1397 * Always execute a GetPinSense verb here, even when called from
1398 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1399 * response's PD bit is not the real PD value, but indicates that
1400 * the real PD value changed. An older version of the HD-audio
1401 * specification worked this way. Hence, we just ignore the data in
1402 * the unsolicited response to avoid custom WARs.
1403 */
1404 int present;
1405 bool ret;
1406 bool do_repoll = false;
1407
1408 snd_hda_power_up_pm(codec);
1409 present = snd_hda_pin_sense(codec, pin_nid);
1410
1411 mutex_lock(&per_pin->lock);
1412 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1413 if (pin_eld->monitor_present)
1414 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1415 else
1416 eld->eld_valid = false;
1417
1418 codec_dbg(codec,
1419 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1420 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1421
1422 if (eld->eld_valid) {
1423 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1424 &eld->eld_size) < 0)
1425 eld->eld_valid = false;
1426 else {
1427 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1428 eld->eld_size) < 0)
1429 eld->eld_valid = false;
1430 }
1431 if (!eld->eld_valid && repoll)
1432 do_repoll = true;
1433 }
1434
1435 if (do_repoll)
1436 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1437 else
1438 update_eld(codec, per_pin, eld);
1439
1440 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1441
1442 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1443 if (jack)
1444 jack->block_report = !ret;
1445
1446 mutex_unlock(&per_pin->lock);
1447 snd_hda_power_down_pm(codec);
1448 return ret;
1449 }
1450
1451 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1452 struct hdmi_spec_per_pin *per_pin)
1453 {
1454 struct hdmi_spec *spec = codec->spec;
1455 struct snd_jack *jack = NULL;
1456 struct hda_jack_tbl *jack_tbl;
1457
1458 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1459 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1460 * NULL even after snd_hda_jack_tbl_clear() is called to
1461 * free snd_jack. This may cause access invalid memory
1462 * when calling snd_jack_report
1463 */
1464 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1465 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1466 else if (!spec->dyn_pcm_assign) {
1467 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1468 if (jack_tbl)
1469 jack = jack_tbl->jack;
1470 }
1471 return jack;
1472 }
1473
1474 /* update ELD and jack state via audio component */
1475 static void sync_eld_via_acomp(struct hda_codec *codec,
1476 struct hdmi_spec_per_pin *per_pin)
1477 {
1478 struct hdmi_spec *spec = codec->spec;
1479 struct hdmi_eld *eld = &spec->temp_eld;
1480 struct snd_jack *jack = NULL;
1481 int size;
1482
1483 mutex_lock(&per_pin->lock);
1484 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1485 &eld->monitor_present, eld->eld_buffer,
1486 ELD_MAX_SIZE);
1487 if (size < 0)
1488 goto unlock;
1489 if (size > 0) {
1490 size = min(size, ELD_MAX_SIZE);
1491 if (snd_hdmi_parse_eld(codec, &eld->info,
1492 eld->eld_buffer, size) < 0)
1493 size = -EINVAL;
1494 }
1495
1496 if (size > 0) {
1497 eld->eld_valid = true;
1498 eld->eld_size = size;
1499 } else {
1500 eld->eld_valid = false;
1501 eld->eld_size = 0;
1502 }
1503
1504 /* pcm_idx >=0 before update_eld() means it is in monitor
1505 * disconnected event. Jack must be fetched before update_eld()
1506 */
1507 jack = pin_idx_to_jack(codec, per_pin);
1508 update_eld(codec, per_pin, eld);
1509 if (jack == NULL)
1510 jack = pin_idx_to_jack(codec, per_pin);
1511 if (jack == NULL)
1512 goto unlock;
1513 snd_jack_report(jack,
1514 eld->monitor_present ? SND_JACK_AVOUT : 0);
1515 unlock:
1516 mutex_unlock(&per_pin->lock);
1517 }
1518
1519 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1520 {
1521 struct hda_codec *codec = per_pin->codec;
1522 struct hdmi_spec *spec = codec->spec;
1523 int ret;
1524
1525 mutex_lock(&spec->pcm_lock);
1526 if (codec_has_acomp(codec)) {
1527 sync_eld_via_acomp(codec, per_pin);
1528 ret = false; /* don't call snd_hda_jack_report_sync() */
1529 } else {
1530 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1531 }
1532 mutex_unlock(&spec->pcm_lock);
1533
1534 return ret;
1535 }
1536
1537 static void hdmi_repoll_eld(struct work_struct *work)
1538 {
1539 struct hdmi_spec_per_pin *per_pin =
1540 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1541
1542 if (per_pin->repoll_count++ > 6)
1543 per_pin->repoll_count = 0;
1544
1545 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1546 snd_hda_jack_report_sync(per_pin->codec);
1547 }
1548
1549 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1550 hda_nid_t nid);
1551
1552 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1553 {
1554 struct hdmi_spec *spec = codec->spec;
1555 unsigned int caps, config;
1556 int pin_idx;
1557 struct hdmi_spec_per_pin *per_pin;
1558 int err;
1559
1560 caps = snd_hda_query_pin_caps(codec, pin_nid);
1561 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1562 return 0;
1563
1564 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1565 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1566 return 0;
1567
1568 if (is_haswell_plus(codec))
1569 intel_haswell_fixup_connect_list(codec, pin_nid);
1570
1571 pin_idx = spec->num_pins;
1572 per_pin = snd_array_new(&spec->pins);
1573 if (!per_pin)
1574 return -ENOMEM;
1575
1576 per_pin->pin_nid = pin_nid;
1577 per_pin->non_pcm = false;
1578 if (spec->dyn_pcm_assign)
1579 per_pin->pcm_idx = -1;
1580 else {
1581 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1582 per_pin->pcm_idx = pin_idx;
1583 }
1584 per_pin->pin_nid_idx = pin_idx;
1585
1586 err = hdmi_read_pin_conn(codec, pin_idx);
1587 if (err < 0)
1588 return err;
1589
1590 spec->num_pins++;
1591
1592 return 0;
1593 }
1594
1595 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1596 {
1597 struct hdmi_spec *spec = codec->spec;
1598 struct hdmi_spec_per_cvt *per_cvt;
1599 unsigned int chans;
1600 int err;
1601
1602 chans = get_wcaps(codec, cvt_nid);
1603 chans = get_wcaps_channels(chans);
1604
1605 per_cvt = snd_array_new(&spec->cvts);
1606 if (!per_cvt)
1607 return -ENOMEM;
1608
1609 per_cvt->cvt_nid = cvt_nid;
1610 per_cvt->channels_min = 2;
1611 if (chans <= 16) {
1612 per_cvt->channels_max = chans;
1613 if (chans > spec->chmap.channels_max)
1614 spec->chmap.channels_max = chans;
1615 }
1616
1617 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1618 &per_cvt->rates,
1619 &per_cvt->formats,
1620 &per_cvt->maxbps);
1621 if (err < 0)
1622 return err;
1623
1624 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1625 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1626 spec->num_cvts++;
1627
1628 return 0;
1629 }
1630
1631 static int hdmi_parse_codec(struct hda_codec *codec)
1632 {
1633 hda_nid_t nid;
1634 int i, nodes;
1635
1636 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1637 if (!nid || nodes < 0) {
1638 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1639 return -EINVAL;
1640 }
1641
1642 for (i = 0; i < nodes; i++, nid++) {
1643 unsigned int caps;
1644 unsigned int type;
1645
1646 caps = get_wcaps(codec, nid);
1647 type = get_wcaps_type(caps);
1648
1649 if (!(caps & AC_WCAP_DIGITAL))
1650 continue;
1651
1652 switch (type) {
1653 case AC_WID_AUD_OUT:
1654 hdmi_add_cvt(codec, nid);
1655 break;
1656 case AC_WID_PIN:
1657 hdmi_add_pin(codec, nid);
1658 break;
1659 }
1660 }
1661
1662 return 0;
1663 }
1664
1665 /*
1666 */
1667 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1668 {
1669 struct hda_spdif_out *spdif;
1670 bool non_pcm;
1671
1672 mutex_lock(&codec->spdif_mutex);
1673 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1674 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1675 mutex_unlock(&codec->spdif_mutex);
1676 return non_pcm;
1677 }
1678
1679 /*
1680 * HDMI callbacks
1681 */
1682
1683 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1684 struct hda_codec *codec,
1685 unsigned int stream_tag,
1686 unsigned int format,
1687 struct snd_pcm_substream *substream)
1688 {
1689 hda_nid_t cvt_nid = hinfo->nid;
1690 struct hdmi_spec *spec = codec->spec;
1691 int pin_idx;
1692 struct hdmi_spec_per_pin *per_pin;
1693 hda_nid_t pin_nid;
1694 struct snd_pcm_runtime *runtime = substream->runtime;
1695 bool non_pcm;
1696 int pinctl;
1697 int err;
1698
1699 mutex_lock(&spec->pcm_lock);
1700 pin_idx = hinfo_to_pin_index(codec, hinfo);
1701 if (spec->dyn_pcm_assign && pin_idx < 0) {
1702 /* when dyn_pcm_assign and pcm is not bound to a pin
1703 * skip pin setup and return 0 to make audio playback
1704 * be ongoing
1705 */
1706 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
1707 snd_hda_codec_setup_stream(codec, cvt_nid,
1708 stream_tag, 0, format);
1709 mutex_unlock(&spec->pcm_lock);
1710 return 0;
1711 }
1712
1713 if (snd_BUG_ON(pin_idx < 0)) {
1714 mutex_unlock(&spec->pcm_lock);
1715 return -EINVAL;
1716 }
1717 per_pin = get_pin(spec, pin_idx);
1718 pin_nid = per_pin->pin_nid;
1719 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1720 /* Verify pin:cvt selections to avoid silent audio after S3.
1721 * After S3, the audio driver restores pin:cvt selections
1722 * but this can happen before gfx is ready and such selection
1723 * is overlooked by HW. Thus multiple pins can share a same
1724 * default convertor and mute control will affect each other,
1725 * which can cause a resumed audio playback become silent
1726 * after S3.
1727 */
1728 intel_verify_pin_cvt_connect(codec, per_pin);
1729 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1730 }
1731
1732 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1733 /* Todo: add DP1.2 MST audio support later */
1734 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
1735
1736 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1737 mutex_lock(&per_pin->lock);
1738 per_pin->channels = substream->runtime->channels;
1739 per_pin->setup = true;
1740
1741 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1742 mutex_unlock(&per_pin->lock);
1743 if (spec->dyn_pin_out) {
1744 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1745 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1746 snd_hda_codec_write(codec, pin_nid, 0,
1747 AC_VERB_SET_PIN_WIDGET_CONTROL,
1748 pinctl | PIN_OUT);
1749 }
1750
1751 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1752 stream_tag, format);
1753 mutex_unlock(&spec->pcm_lock);
1754 return err;
1755 }
1756
1757 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1758 struct hda_codec *codec,
1759 struct snd_pcm_substream *substream)
1760 {
1761 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1762 return 0;
1763 }
1764
1765 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1766 struct hda_codec *codec,
1767 struct snd_pcm_substream *substream)
1768 {
1769 struct hdmi_spec *spec = codec->spec;
1770 int cvt_idx, pin_idx, pcm_idx;
1771 struct hdmi_spec_per_cvt *per_cvt;
1772 struct hdmi_spec_per_pin *per_pin;
1773 int pinctl;
1774
1775 if (hinfo->nid) {
1776 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1777 if (snd_BUG_ON(pcm_idx < 0))
1778 return -EINVAL;
1779 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1780 if (snd_BUG_ON(cvt_idx < 0))
1781 return -EINVAL;
1782 per_cvt = get_cvt(spec, cvt_idx);
1783
1784 snd_BUG_ON(!per_cvt->assigned);
1785 per_cvt->assigned = 0;
1786 hinfo->nid = 0;
1787
1788 mutex_lock(&spec->pcm_lock);
1789 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1790 clear_bit(pcm_idx, &spec->pcm_in_use);
1791 pin_idx = hinfo_to_pin_index(codec, hinfo);
1792 if (spec->dyn_pcm_assign && pin_idx < 0) {
1793 mutex_unlock(&spec->pcm_lock);
1794 return 0;
1795 }
1796
1797 if (snd_BUG_ON(pin_idx < 0)) {
1798 mutex_unlock(&spec->pcm_lock);
1799 return -EINVAL;
1800 }
1801 per_pin = get_pin(spec, pin_idx);
1802
1803 if (spec->dyn_pin_out) {
1804 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1805 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1806 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1807 AC_VERB_SET_PIN_WIDGET_CONTROL,
1808 pinctl & ~PIN_OUT);
1809 }
1810
1811 mutex_lock(&per_pin->lock);
1812 per_pin->chmap_set = false;
1813 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1814
1815 per_pin->setup = false;
1816 per_pin->channels = 0;
1817 mutex_unlock(&per_pin->lock);
1818 mutex_unlock(&spec->pcm_lock);
1819 }
1820
1821 return 0;
1822 }
1823
1824 static const struct hda_pcm_ops generic_ops = {
1825 .open = hdmi_pcm_open,
1826 .close = hdmi_pcm_close,
1827 .prepare = generic_hdmi_playback_pcm_prepare,
1828 .cleanup = generic_hdmi_playback_pcm_cleanup,
1829 };
1830
1831 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1832 unsigned char *chmap)
1833 {
1834 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1835 struct hdmi_spec *spec = codec->spec;
1836 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1837
1838 /* chmap is already set to 0 in caller */
1839 if (!per_pin)
1840 return;
1841
1842 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1843 }
1844
1845 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1846 unsigned char *chmap, int prepared)
1847 {
1848 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1849 struct hdmi_spec *spec = codec->spec;
1850 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1851
1852 mutex_lock(&per_pin->lock);
1853 per_pin->chmap_set = true;
1854 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1855 if (prepared)
1856 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1857 mutex_unlock(&per_pin->lock);
1858 }
1859
1860 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1861 {
1862 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1863 struct hdmi_spec *spec = codec->spec;
1864 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1865
1866 return per_pin ? true:false;
1867 }
1868
1869 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1870 {
1871 struct hdmi_spec *spec = codec->spec;
1872 int pin_idx;
1873
1874 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1875 struct hda_pcm *info;
1876 struct hda_pcm_stream *pstr;
1877
1878 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1879 if (!info)
1880 return -ENOMEM;
1881
1882 spec->pcm_rec[pin_idx].pcm = info;
1883 spec->pcm_used++;
1884 info->pcm_type = HDA_PCM_TYPE_HDMI;
1885 info->own_chmap = true;
1886
1887 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1888 pstr->substreams = 1;
1889 pstr->ops = generic_ops;
1890 /* other pstr fields are set in open */
1891 }
1892
1893 return 0;
1894 }
1895
1896 static void free_hdmi_jack_priv(struct snd_jack *jack)
1897 {
1898 struct hdmi_pcm *pcm = jack->private_data;
1899
1900 pcm->jack = NULL;
1901 }
1902
1903 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1904 struct hdmi_spec *spec,
1905 int pcm_idx,
1906 const char *name)
1907 {
1908 struct snd_jack *jack;
1909 int err;
1910
1911 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1912 true, false);
1913 if (err < 0)
1914 return err;
1915
1916 spec->pcm_rec[pcm_idx].jack = jack;
1917 jack->private_data = &spec->pcm_rec[pcm_idx];
1918 jack->private_free = free_hdmi_jack_priv;
1919 return 0;
1920 }
1921
1922 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1923 {
1924 char hdmi_str[32] = "HDMI/DP";
1925 struct hdmi_spec *spec = codec->spec;
1926 struct hdmi_spec_per_pin *per_pin;
1927 struct hda_jack_tbl *jack;
1928 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1929 bool phantom_jack;
1930 int ret;
1931
1932 if (pcmdev > 0)
1933 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1934
1935 if (spec->dyn_pcm_assign)
1936 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1937
1938 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1939 /* if !dyn_pcm_assign, it must be non-MST mode.
1940 * This means pcms and pins are statically mapped.
1941 * And pcm_idx is pin_idx.
1942 */
1943 per_pin = get_pin(spec, pcm_idx);
1944 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1945 if (phantom_jack)
1946 strncat(hdmi_str, " Phantom",
1947 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1948 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1949 phantom_jack);
1950 if (ret < 0)
1951 return ret;
1952 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1953 if (jack == NULL)
1954 return 0;
1955 /* assign jack->jack to pcm_rec[].jack to
1956 * align with dyn_pcm_assign mode
1957 */
1958 spec->pcm_rec[pcm_idx].jack = jack->jack;
1959 return 0;
1960 }
1961
1962 static int generic_hdmi_build_controls(struct hda_codec *codec)
1963 {
1964 struct hdmi_spec *spec = codec->spec;
1965 int err;
1966 int pin_idx, pcm_idx;
1967
1968
1969 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1970 err = generic_hdmi_build_jack(codec, pcm_idx);
1971 if (err < 0)
1972 return err;
1973
1974 /* create the spdif for each pcm
1975 * pin will be bound when monitor is connected
1976 */
1977 if (spec->dyn_pcm_assign)
1978 err = snd_hda_create_dig_out_ctls(codec,
1979 0, spec->cvt_nids[0],
1980 HDA_PCM_TYPE_HDMI);
1981 else {
1982 struct hdmi_spec_per_pin *per_pin =
1983 get_pin(spec, pcm_idx);
1984 err = snd_hda_create_dig_out_ctls(codec,
1985 per_pin->pin_nid,
1986 per_pin->mux_nids[0],
1987 HDA_PCM_TYPE_HDMI);
1988 }
1989 if (err < 0)
1990 return err;
1991 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1992
1993 /* add control for ELD Bytes */
1994 err = hdmi_create_eld_ctl(codec, pcm_idx,
1995 get_pcm_rec(spec, pcm_idx)->device);
1996 if (err < 0)
1997 return err;
1998 }
1999
2000 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2001 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2002
2003 hdmi_present_sense(per_pin, 0);
2004 }
2005
2006 /* add channel maps */
2007 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2008 struct hda_pcm *pcm;
2009
2010 pcm = get_pcm_rec(spec, pcm_idx);
2011 if (!pcm || !pcm->pcm)
2012 break;
2013 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2014 if (err < 0)
2015 return err;
2016 }
2017
2018 return 0;
2019 }
2020
2021 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2022 {
2023 struct hdmi_spec *spec = codec->spec;
2024 int pin_idx;
2025
2026 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2027 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2028
2029 per_pin->codec = codec;
2030 mutex_init(&per_pin->lock);
2031 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2032 eld_proc_new(per_pin, pin_idx);
2033 }
2034 return 0;
2035 }
2036
2037 static int generic_hdmi_init(struct hda_codec *codec)
2038 {
2039 struct hdmi_spec *spec = codec->spec;
2040 int pin_idx;
2041
2042 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2043 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2044 hda_nid_t pin_nid = per_pin->pin_nid;
2045
2046 hdmi_init_pin(codec, pin_nid);
2047 if (!codec_has_acomp(codec))
2048 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2049 codec->jackpoll_interval > 0 ?
2050 jack_callback : NULL);
2051 }
2052 return 0;
2053 }
2054
2055 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2056 {
2057 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2058 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2059 }
2060
2061 static void hdmi_array_free(struct hdmi_spec *spec)
2062 {
2063 snd_array_free(&spec->pins);
2064 snd_array_free(&spec->cvts);
2065 }
2066
2067 static void generic_hdmi_free(struct hda_codec *codec)
2068 {
2069 struct hdmi_spec *spec = codec->spec;
2070 int pin_idx, pcm_idx;
2071
2072 if (codec_has_acomp(codec))
2073 snd_hdac_i915_register_notifier(NULL);
2074
2075 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2076 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2077 cancel_delayed_work_sync(&per_pin->work);
2078 eld_proc_free(per_pin);
2079 }
2080
2081 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2082 if (spec->pcm_rec[pcm_idx].jack == NULL)
2083 continue;
2084 if (spec->dyn_pcm_assign)
2085 snd_device_free(codec->card,
2086 spec->pcm_rec[pcm_idx].jack);
2087 else
2088 spec->pcm_rec[pcm_idx].jack = NULL;
2089 }
2090
2091 if (spec->i915_bound)
2092 snd_hdac_i915_exit(&codec->bus->core);
2093 hdmi_array_free(spec);
2094 kfree(spec);
2095 }
2096
2097 #ifdef CONFIG_PM
2098 static int generic_hdmi_resume(struct hda_codec *codec)
2099 {
2100 struct hdmi_spec *spec = codec->spec;
2101 int pin_idx;
2102
2103 codec->patch_ops.init(codec);
2104 regcache_sync(codec->core.regmap);
2105
2106 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2107 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2108 hdmi_present_sense(per_pin, 1);
2109 }
2110 return 0;
2111 }
2112 #endif
2113
2114 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2115 .init = generic_hdmi_init,
2116 .free = generic_hdmi_free,
2117 .build_pcms = generic_hdmi_build_pcms,
2118 .build_controls = generic_hdmi_build_controls,
2119 .unsol_event = hdmi_unsol_event,
2120 #ifdef CONFIG_PM
2121 .resume = generic_hdmi_resume,
2122 #endif
2123 };
2124
2125 static const struct hdmi_ops generic_standard_hdmi_ops = {
2126 .pin_get_eld = snd_hdmi_get_eld,
2127 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2128 .pin_hbr_setup = hdmi_pin_hbr_setup,
2129 .setup_stream = hdmi_setup_stream,
2130 };
2131
2132 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2133 hda_nid_t nid)
2134 {
2135 struct hdmi_spec *spec = codec->spec;
2136 hda_nid_t conns[4];
2137 int nconns;
2138
2139 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2140 if (nconns == spec->num_cvts &&
2141 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2142 return;
2143
2144 /* override pins connection list */
2145 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2146 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2147 }
2148
2149 #define INTEL_VENDOR_NID 0x08
2150 #define INTEL_GET_VENDOR_VERB 0xf81
2151 #define INTEL_SET_VENDOR_VERB 0x781
2152 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2153 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2154
2155 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2156 bool update_tree)
2157 {
2158 unsigned int vendor_param;
2159
2160 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2161 INTEL_GET_VENDOR_VERB, 0);
2162 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2163 return;
2164
2165 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2166 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2167 INTEL_SET_VENDOR_VERB, vendor_param);
2168 if (vendor_param == -1)
2169 return;
2170
2171 if (update_tree)
2172 snd_hda_codec_update_widgets(codec);
2173 }
2174
2175 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2176 {
2177 unsigned int vendor_param;
2178
2179 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2180 INTEL_GET_VENDOR_VERB, 0);
2181 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2182 return;
2183
2184 /* enable DP1.2 mode */
2185 vendor_param |= INTEL_EN_DP12;
2186 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2187 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2188 INTEL_SET_VENDOR_VERB, vendor_param);
2189 }
2190
2191 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2192 * Otherwise you may get severe h/w communication errors.
2193 */
2194 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2195 unsigned int power_state)
2196 {
2197 if (power_state == AC_PWRST_D0) {
2198 intel_haswell_enable_all_pins(codec, false);
2199 intel_haswell_fixup_enable_dp12(codec);
2200 }
2201
2202 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2203 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2204 }
2205
2206 static void intel_pin_eld_notify(void *audio_ptr, int port)
2207 {
2208 struct hda_codec *codec = audio_ptr;
2209 int pin_nid = port + 0x04;
2210
2211 /* we assume only from port-B to port-D */
2212 if (port < 1 || port > 3)
2213 return;
2214
2215 /* skip notification during system suspend (but not in runtime PM);
2216 * the state will be updated at resume
2217 */
2218 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2219 return;
2220 /* ditto during suspend/resume process itself */
2221 if (atomic_read(&(codec)->core.in_pm))
2222 return;
2223
2224 check_presence_and_report(codec, pin_nid);
2225 }
2226
2227 static int patch_generic_hdmi(struct hda_codec *codec)
2228 {
2229 struct hdmi_spec *spec;
2230
2231 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2232 if (spec == NULL)
2233 return -ENOMEM;
2234
2235 spec->ops = generic_standard_hdmi_ops;
2236 mutex_init(&spec->pcm_lock);
2237 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2238
2239 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2240 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2241 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2242
2243 codec->spec = spec;
2244 hdmi_array_init(spec, 4);
2245
2246 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2247 if (!codec_has_acomp(codec) &&
2248 (codec->core.vendor_id >> 16) == 0x8086)
2249 if (!snd_hdac_i915_init(&codec->bus->core))
2250 spec->i915_bound = true;
2251
2252 if (is_haswell_plus(codec)) {
2253 intel_haswell_enable_all_pins(codec, true);
2254 intel_haswell_fixup_enable_dp12(codec);
2255 }
2256
2257 /* For Valleyview/Cherryview, only the display codec is in the display
2258 * power well and can use link_power ops to request/release the power.
2259 * For Haswell/Broadwell, the controller is also in the power well and
2260 * can cover the codec power request, and so need not set this flag.
2261 * For previous platforms, there is no such power well feature.
2262 */
2263 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2264 is_broxton(codec))
2265 codec->core.link_power_control = 1;
2266
2267 if (hdmi_parse_codec(codec) < 0) {
2268 if (spec->i915_bound)
2269 snd_hdac_i915_exit(&codec->bus->core);
2270 codec->spec = NULL;
2271 kfree(spec);
2272 return -EINVAL;
2273 }
2274 codec->patch_ops = generic_hdmi_patch_ops;
2275 if (is_haswell_plus(codec)) {
2276 codec->patch_ops.set_power_state = haswell_set_power_state;
2277 codec->dp_mst = true;
2278 }
2279
2280 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2281 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2282 codec->auto_runtime_pm = 1;
2283
2284 generic_hdmi_init_per_pins(codec);
2285
2286
2287 if (codec_has_acomp(codec)) {
2288 codec->depop_delay = 0;
2289 spec->i915_audio_ops.audio_ptr = codec;
2290 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2291 * will call pin_eld_notify with using audio_ptr pointer
2292 * We need make sure audio_ptr is really setup
2293 */
2294 wmb();
2295 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2296 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2297 }
2298
2299 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
2300 return 0;
2301 }
2302
2303 /*
2304 * Shared non-generic implementations
2305 */
2306
2307 static int simple_playback_build_pcms(struct hda_codec *codec)
2308 {
2309 struct hdmi_spec *spec = codec->spec;
2310 struct hda_pcm *info;
2311 unsigned int chans;
2312 struct hda_pcm_stream *pstr;
2313 struct hdmi_spec_per_cvt *per_cvt;
2314
2315 per_cvt = get_cvt(spec, 0);
2316 chans = get_wcaps(codec, per_cvt->cvt_nid);
2317 chans = get_wcaps_channels(chans);
2318
2319 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2320 if (!info)
2321 return -ENOMEM;
2322 spec->pcm_rec[0].pcm = info;
2323 info->pcm_type = HDA_PCM_TYPE_HDMI;
2324 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2325 *pstr = spec->pcm_playback;
2326 pstr->nid = per_cvt->cvt_nid;
2327 if (pstr->channels_max <= 2 && chans && chans <= 16)
2328 pstr->channels_max = chans;
2329
2330 return 0;
2331 }
2332
2333 /* unsolicited event for jack sensing */
2334 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2335 unsigned int res)
2336 {
2337 snd_hda_jack_set_dirty_all(codec);
2338 snd_hda_jack_report_sync(codec);
2339 }
2340
2341 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2342 * as long as spec->pins[] is set correctly
2343 */
2344 #define simple_hdmi_build_jack generic_hdmi_build_jack
2345
2346 static int simple_playback_build_controls(struct hda_codec *codec)
2347 {
2348 struct hdmi_spec *spec = codec->spec;
2349 struct hdmi_spec_per_cvt *per_cvt;
2350 int err;
2351
2352 per_cvt = get_cvt(spec, 0);
2353 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2354 per_cvt->cvt_nid,
2355 HDA_PCM_TYPE_HDMI);
2356 if (err < 0)
2357 return err;
2358 return simple_hdmi_build_jack(codec, 0);
2359 }
2360
2361 static int simple_playback_init(struct hda_codec *codec)
2362 {
2363 struct hdmi_spec *spec = codec->spec;
2364 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2365 hda_nid_t pin = per_pin->pin_nid;
2366
2367 snd_hda_codec_write(codec, pin, 0,
2368 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2369 /* some codecs require to unmute the pin */
2370 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2371 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2372 AMP_OUT_UNMUTE);
2373 snd_hda_jack_detect_enable(codec, pin);
2374 return 0;
2375 }
2376
2377 static void simple_playback_free(struct hda_codec *codec)
2378 {
2379 struct hdmi_spec *spec = codec->spec;
2380
2381 hdmi_array_free(spec);
2382 kfree(spec);
2383 }
2384
2385 /*
2386 * Nvidia specific implementations
2387 */
2388
2389 #define Nv_VERB_SET_Channel_Allocation 0xF79
2390 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2391 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2392 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2393
2394 #define nvhdmi_master_con_nid_7x 0x04
2395 #define nvhdmi_master_pin_nid_7x 0x05
2396
2397 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2398 /*front, rear, clfe, rear_surr */
2399 0x6, 0x8, 0xa, 0xc,
2400 };
2401
2402 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2403 /* set audio protect on */
2404 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2405 /* enable digital output on pin widget */
2406 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2407 {} /* terminator */
2408 };
2409
2410 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2411 /* set audio protect on */
2412 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2413 /* enable digital output on pin widget */
2414 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2415 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2416 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2417 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2418 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2419 {} /* terminator */
2420 };
2421
2422 #ifdef LIMITED_RATE_FMT_SUPPORT
2423 /* support only the safe format and rate */
2424 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2425 #define SUPPORTED_MAXBPS 16
2426 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2427 #else
2428 /* support all rates and formats */
2429 #define SUPPORTED_RATES \
2430 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2431 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2432 SNDRV_PCM_RATE_192000)
2433 #define SUPPORTED_MAXBPS 24
2434 #define SUPPORTED_FORMATS \
2435 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2436 #endif
2437
2438 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2439 {
2440 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2441 return 0;
2442 }
2443
2444 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2445 {
2446 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2447 return 0;
2448 }
2449
2450 static unsigned int channels_2_6_8[] = {
2451 2, 6, 8
2452 };
2453
2454 static unsigned int channels_2_8[] = {
2455 2, 8
2456 };
2457
2458 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2459 .count = ARRAY_SIZE(channels_2_6_8),
2460 .list = channels_2_6_8,
2461 .mask = 0,
2462 };
2463
2464 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2465 .count = ARRAY_SIZE(channels_2_8),
2466 .list = channels_2_8,
2467 .mask = 0,
2468 };
2469
2470 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2471 struct hda_codec *codec,
2472 struct snd_pcm_substream *substream)
2473 {
2474 struct hdmi_spec *spec = codec->spec;
2475 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2476
2477 switch (codec->preset->vendor_id) {
2478 case 0x10de0002:
2479 case 0x10de0003:
2480 case 0x10de0005:
2481 case 0x10de0006:
2482 hw_constraints_channels = &hw_constraints_2_8_channels;
2483 break;
2484 case 0x10de0007:
2485 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2486 break;
2487 default:
2488 break;
2489 }
2490
2491 if (hw_constraints_channels != NULL) {
2492 snd_pcm_hw_constraint_list(substream->runtime, 0,
2493 SNDRV_PCM_HW_PARAM_CHANNELS,
2494 hw_constraints_channels);
2495 } else {
2496 snd_pcm_hw_constraint_step(substream->runtime, 0,
2497 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2498 }
2499
2500 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2501 }
2502
2503 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2504 struct hda_codec *codec,
2505 struct snd_pcm_substream *substream)
2506 {
2507 struct hdmi_spec *spec = codec->spec;
2508 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2509 }
2510
2511 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2512 struct hda_codec *codec,
2513 unsigned int stream_tag,
2514 unsigned int format,
2515 struct snd_pcm_substream *substream)
2516 {
2517 struct hdmi_spec *spec = codec->spec;
2518 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2519 stream_tag, format, substream);
2520 }
2521
2522 static const struct hda_pcm_stream simple_pcm_playback = {
2523 .substreams = 1,
2524 .channels_min = 2,
2525 .channels_max = 2,
2526 .ops = {
2527 .open = simple_playback_pcm_open,
2528 .close = simple_playback_pcm_close,
2529 .prepare = simple_playback_pcm_prepare
2530 },
2531 };
2532
2533 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2534 .build_controls = simple_playback_build_controls,
2535 .build_pcms = simple_playback_build_pcms,
2536 .init = simple_playback_init,
2537 .free = simple_playback_free,
2538 .unsol_event = simple_hdmi_unsol_event,
2539 };
2540
2541 static int patch_simple_hdmi(struct hda_codec *codec,
2542 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2543 {
2544 struct hdmi_spec *spec;
2545 struct hdmi_spec_per_cvt *per_cvt;
2546 struct hdmi_spec_per_pin *per_pin;
2547
2548 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2549 if (!spec)
2550 return -ENOMEM;
2551
2552 codec->spec = spec;
2553 hdmi_array_init(spec, 1);
2554
2555 spec->multiout.num_dacs = 0; /* no analog */
2556 spec->multiout.max_channels = 2;
2557 spec->multiout.dig_out_nid = cvt_nid;
2558 spec->num_cvts = 1;
2559 spec->num_pins = 1;
2560 per_pin = snd_array_new(&spec->pins);
2561 per_cvt = snd_array_new(&spec->cvts);
2562 if (!per_pin || !per_cvt) {
2563 simple_playback_free(codec);
2564 return -ENOMEM;
2565 }
2566 per_cvt->cvt_nid = cvt_nid;
2567 per_pin->pin_nid = pin_nid;
2568 spec->pcm_playback = simple_pcm_playback;
2569
2570 codec->patch_ops = simple_hdmi_patch_ops;
2571
2572 return 0;
2573 }
2574
2575 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2576 int channels)
2577 {
2578 unsigned int chanmask;
2579 int chan = channels ? (channels - 1) : 1;
2580
2581 switch (channels) {
2582 default:
2583 case 0:
2584 case 2:
2585 chanmask = 0x00;
2586 break;
2587 case 4:
2588 chanmask = 0x08;
2589 break;
2590 case 6:
2591 chanmask = 0x0b;
2592 break;
2593 case 8:
2594 chanmask = 0x13;
2595 break;
2596 }
2597
2598 /* Set the audio infoframe channel allocation and checksum fields. The
2599 * channel count is computed implicitly by the hardware. */
2600 snd_hda_codec_write(codec, 0x1, 0,
2601 Nv_VERB_SET_Channel_Allocation, chanmask);
2602
2603 snd_hda_codec_write(codec, 0x1, 0,
2604 Nv_VERB_SET_Info_Frame_Checksum,
2605 (0x71 - chan - chanmask));
2606 }
2607
2608 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2609 struct hda_codec *codec,
2610 struct snd_pcm_substream *substream)
2611 {
2612 struct hdmi_spec *spec = codec->spec;
2613 int i;
2614
2615 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2616 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2617 for (i = 0; i < 4; i++) {
2618 /* set the stream id */
2619 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2620 AC_VERB_SET_CHANNEL_STREAMID, 0);
2621 /* set the stream format */
2622 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2623 AC_VERB_SET_STREAM_FORMAT, 0);
2624 }
2625
2626 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2627 * streams are disabled. */
2628 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2629
2630 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2631 }
2632
2633 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2634 struct hda_codec *codec,
2635 unsigned int stream_tag,
2636 unsigned int format,
2637 struct snd_pcm_substream *substream)
2638 {
2639 int chs;
2640 unsigned int dataDCC2, channel_id;
2641 int i;
2642 struct hdmi_spec *spec = codec->spec;
2643 struct hda_spdif_out *spdif;
2644 struct hdmi_spec_per_cvt *per_cvt;
2645
2646 mutex_lock(&codec->spdif_mutex);
2647 per_cvt = get_cvt(spec, 0);
2648 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2649
2650 chs = substream->runtime->channels;
2651
2652 dataDCC2 = 0x2;
2653
2654 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2655 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2656 snd_hda_codec_write(codec,
2657 nvhdmi_master_con_nid_7x,
2658 0,
2659 AC_VERB_SET_DIGI_CONVERT_1,
2660 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2661
2662 /* set the stream id */
2663 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2664 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2665
2666 /* set the stream format */
2667 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2668 AC_VERB_SET_STREAM_FORMAT, format);
2669
2670 /* turn on again (if needed) */
2671 /* enable and set the channel status audio/data flag */
2672 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2673 snd_hda_codec_write(codec,
2674 nvhdmi_master_con_nid_7x,
2675 0,
2676 AC_VERB_SET_DIGI_CONVERT_1,
2677 spdif->ctls & 0xff);
2678 snd_hda_codec_write(codec,
2679 nvhdmi_master_con_nid_7x,
2680 0,
2681 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2682 }
2683
2684 for (i = 0; i < 4; i++) {
2685 if (chs == 2)
2686 channel_id = 0;
2687 else
2688 channel_id = i * 2;
2689
2690 /* turn off SPDIF once;
2691 *otherwise the IEC958 bits won't be updated
2692 */
2693 if (codec->spdif_status_reset &&
2694 (spdif->ctls & AC_DIG1_ENABLE))
2695 snd_hda_codec_write(codec,
2696 nvhdmi_con_nids_7x[i],
2697 0,
2698 AC_VERB_SET_DIGI_CONVERT_1,
2699 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2700 /* set the stream id */
2701 snd_hda_codec_write(codec,
2702 nvhdmi_con_nids_7x[i],
2703 0,
2704 AC_VERB_SET_CHANNEL_STREAMID,
2705 (stream_tag << 4) | channel_id);
2706 /* set the stream format */
2707 snd_hda_codec_write(codec,
2708 nvhdmi_con_nids_7x[i],
2709 0,
2710 AC_VERB_SET_STREAM_FORMAT,
2711 format);
2712 /* turn on again (if needed) */
2713 /* enable and set the channel status audio/data flag */
2714 if (codec->spdif_status_reset &&
2715 (spdif->ctls & AC_DIG1_ENABLE)) {
2716 snd_hda_codec_write(codec,
2717 nvhdmi_con_nids_7x[i],
2718 0,
2719 AC_VERB_SET_DIGI_CONVERT_1,
2720 spdif->ctls & 0xff);
2721 snd_hda_codec_write(codec,
2722 nvhdmi_con_nids_7x[i],
2723 0,
2724 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2725 }
2726 }
2727
2728 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2729
2730 mutex_unlock(&codec->spdif_mutex);
2731 return 0;
2732 }
2733
2734 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2735 .substreams = 1,
2736 .channels_min = 2,
2737 .channels_max = 8,
2738 .nid = nvhdmi_master_con_nid_7x,
2739 .rates = SUPPORTED_RATES,
2740 .maxbps = SUPPORTED_MAXBPS,
2741 .formats = SUPPORTED_FORMATS,
2742 .ops = {
2743 .open = simple_playback_pcm_open,
2744 .close = nvhdmi_8ch_7x_pcm_close,
2745 .prepare = nvhdmi_8ch_7x_pcm_prepare
2746 },
2747 };
2748
2749 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2750 {
2751 struct hdmi_spec *spec;
2752 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2753 nvhdmi_master_pin_nid_7x);
2754 if (err < 0)
2755 return err;
2756
2757 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2758 /* override the PCM rates, etc, as the codec doesn't give full list */
2759 spec = codec->spec;
2760 spec->pcm_playback.rates = SUPPORTED_RATES;
2761 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2762 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2763 return 0;
2764 }
2765
2766 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2767 {
2768 struct hdmi_spec *spec = codec->spec;
2769 int err = simple_playback_build_pcms(codec);
2770 if (!err) {
2771 struct hda_pcm *info = get_pcm_rec(spec, 0);
2772 info->own_chmap = true;
2773 }
2774 return err;
2775 }
2776
2777 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2778 {
2779 struct hdmi_spec *spec = codec->spec;
2780 struct hda_pcm *info;
2781 struct snd_pcm_chmap *chmap;
2782 int err;
2783
2784 err = simple_playback_build_controls(codec);
2785 if (err < 0)
2786 return err;
2787
2788 /* add channel maps */
2789 info = get_pcm_rec(spec, 0);
2790 err = snd_pcm_add_chmap_ctls(info->pcm,
2791 SNDRV_PCM_STREAM_PLAYBACK,
2792 snd_pcm_alt_chmaps, 8, 0, &chmap);
2793 if (err < 0)
2794 return err;
2795 switch (codec->preset->vendor_id) {
2796 case 0x10de0002:
2797 case 0x10de0003:
2798 case 0x10de0005:
2799 case 0x10de0006:
2800 chmap->channel_mask = (1U << 2) | (1U << 8);
2801 break;
2802 case 0x10de0007:
2803 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2804 }
2805 return 0;
2806 }
2807
2808 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2809 {
2810 struct hdmi_spec *spec;
2811 int err = patch_nvhdmi_2ch(codec);
2812 if (err < 0)
2813 return err;
2814 spec = codec->spec;
2815 spec->multiout.max_channels = 8;
2816 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2817 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2818 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2819 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2820
2821 /* Initialize the audio infoframe channel mask and checksum to something
2822 * valid */
2823 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2824
2825 return 0;
2826 }
2827
2828 /*
2829 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2830 * - 0x10de0015
2831 * - 0x10de0040
2832 */
2833 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
2834 struct hdac_cea_channel_speaker_allocation *cap, int channels)
2835 {
2836 if (cap->ca_index == 0x00 && channels == 2)
2837 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2838
2839 /* If the speaker allocation matches the channel count, it is OK. */
2840 if (cap->channels != channels)
2841 return -1;
2842
2843 /* all channels are remappable freely */
2844 return SNDRV_CTL_TLVT_CHMAP_VAR;
2845 }
2846
2847 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
2848 int ca, int chs, unsigned char *map)
2849 {
2850 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2851 return -EINVAL;
2852
2853 return 0;
2854 }
2855
2856 static int patch_nvhdmi(struct hda_codec *codec)
2857 {
2858 struct hdmi_spec *spec;
2859 int err;
2860
2861 err = patch_generic_hdmi(codec);
2862 if (err)
2863 return err;
2864
2865 spec = codec->spec;
2866 spec->dyn_pin_out = true;
2867
2868 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
2869 nvhdmi_chmap_cea_alloc_validate_get_type;
2870 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
2871
2872 return 0;
2873 }
2874
2875 /*
2876 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2877 * accessed using vendor-defined verbs. These registers can be used for
2878 * interoperability between the HDA and HDMI drivers.
2879 */
2880
2881 /* Audio Function Group node */
2882 #define NVIDIA_AFG_NID 0x01
2883
2884 /*
2885 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2886 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2887 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2888 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2889 * additional bit (at position 30) to signal the validity of the format.
2890 *
2891 * | 31 | 30 | 29 16 | 15 0 |
2892 * +---------+-------+--------+--------+
2893 * | TRIGGER | VALID | UNUSED | FORMAT |
2894 * +-----------------------------------|
2895 *
2896 * Note that for the trigger bit to take effect it needs to change value
2897 * (i.e. it needs to be toggled).
2898 */
2899 #define NVIDIA_GET_SCRATCH0 0xfa6
2900 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2901 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2902 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2903 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2904 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2905 #define NVIDIA_SCRATCH_VALID (1 << 6)
2906
2907 #define NVIDIA_GET_SCRATCH1 0xfab
2908 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2909 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2910 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2911 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2912
2913 /*
2914 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2915 * the format is invalidated so that the HDMI codec can be disabled.
2916 */
2917 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2918 {
2919 unsigned int value;
2920
2921 /* bits [31:30] contain the trigger and valid bits */
2922 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
2923 NVIDIA_GET_SCRATCH0, 0);
2924 value = (value >> 24) & 0xff;
2925
2926 /* bits [15:0] are used to store the HDA format */
2927 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2928 NVIDIA_SET_SCRATCH0_BYTE0,
2929 (format >> 0) & 0xff);
2930 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2931 NVIDIA_SET_SCRATCH0_BYTE1,
2932 (format >> 8) & 0xff);
2933
2934 /* bits [16:24] are unused */
2935 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2936 NVIDIA_SET_SCRATCH0_BYTE2, 0);
2937
2938 /*
2939 * Bit 30 signals that the data is valid and hence that HDMI audio can
2940 * be enabled.
2941 */
2942 if (format == 0)
2943 value &= ~NVIDIA_SCRATCH_VALID;
2944 else
2945 value |= NVIDIA_SCRATCH_VALID;
2946
2947 /*
2948 * Whenever the trigger bit is toggled, an interrupt is raised in the
2949 * HDMI codec. The HDMI driver will use that as trigger to update its
2950 * configuration.
2951 */
2952 value ^= NVIDIA_SCRATCH_TRIGGER;
2953
2954 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2955 NVIDIA_SET_SCRATCH0_BYTE3, value);
2956 }
2957
2958 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
2959 struct hda_codec *codec,
2960 unsigned int stream_tag,
2961 unsigned int format,
2962 struct snd_pcm_substream *substream)
2963 {
2964 int err;
2965
2966 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
2967 format, substream);
2968 if (err < 0)
2969 return err;
2970
2971 /* notify the HDMI codec of the format change */
2972 tegra_hdmi_set_format(codec, format);
2973
2974 return 0;
2975 }
2976
2977 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
2978 struct hda_codec *codec,
2979 struct snd_pcm_substream *substream)
2980 {
2981 /* invalidate the format in the HDMI codec */
2982 tegra_hdmi_set_format(codec, 0);
2983
2984 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
2985 }
2986
2987 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
2988 {
2989 struct hdmi_spec *spec = codec->spec;
2990 unsigned int i;
2991
2992 for (i = 0; i < spec->num_pins; i++) {
2993 struct hda_pcm *pcm = get_pcm_rec(spec, i);
2994
2995 if (pcm->pcm_type == type)
2996 return pcm;
2997 }
2998
2999 return NULL;
3000 }
3001
3002 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3003 {
3004 struct hda_pcm_stream *stream;
3005 struct hda_pcm *pcm;
3006 int err;
3007
3008 err = generic_hdmi_build_pcms(codec);
3009 if (err < 0)
3010 return err;
3011
3012 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3013 if (!pcm)
3014 return -ENODEV;
3015
3016 /*
3017 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3018 * codec about format changes.
3019 */
3020 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3021 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3022 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3023
3024 return 0;
3025 }
3026
3027 static int patch_tegra_hdmi(struct hda_codec *codec)
3028 {
3029 int err;
3030
3031 err = patch_generic_hdmi(codec);
3032 if (err)
3033 return err;
3034
3035 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3036
3037 return 0;
3038 }
3039
3040 /*
3041 * ATI/AMD-specific implementations
3042 */
3043
3044 #define is_amdhdmi_rev3_or_later(codec) \
3045 ((codec)->core.vendor_id == 0x1002aa01 && \
3046 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3047 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3048
3049 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3050 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3051 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3052 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3053 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3054 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3055 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3056 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3057 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3058 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3059 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3060 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3061 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3062 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3063 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3064 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3065 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3066 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3067 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3068 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3069 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3070 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3071 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3072 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3073 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3074
3075 /* AMD specific HDA cvt verbs */
3076 #define ATI_VERB_SET_RAMP_RATE 0x770
3077 #define ATI_VERB_GET_RAMP_RATE 0xf70
3078
3079 #define ATI_OUT_ENABLE 0x1
3080
3081 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3082 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3083
3084 #define ATI_HBR_CAPABLE 0x01
3085 #define ATI_HBR_ENABLE 0x10
3086
3087 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3088 unsigned char *buf, int *eld_size)
3089 {
3090 /* call hda_eld.c ATI/AMD-specific function */
3091 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3092 is_amdhdmi_rev3_or_later(codec));
3093 }
3094
3095 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3096 int active_channels, int conn_type)
3097 {
3098 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3099 }
3100
3101 static int atihdmi_paired_swap_fc_lfe(int pos)
3102 {
3103 /*
3104 * ATI/AMD have automatic FC/LFE swap built-in
3105 * when in pairwise mapping mode.
3106 */
3107
3108 switch (pos) {
3109 /* see channel_allocations[].speakers[] */
3110 case 2: return 3;
3111 case 3: return 2;
3112 default: break;
3113 }
3114
3115 return pos;
3116 }
3117
3118 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3119 int ca, int chs, unsigned char *map)
3120 {
3121 struct hdac_cea_channel_speaker_allocation *cap;
3122 int i, j;
3123
3124 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3125
3126 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3127 for (i = 0; i < chs; ++i) {
3128 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3129 bool ok = false;
3130 bool companion_ok = false;
3131
3132 if (!mask)
3133 continue;
3134
3135 for (j = 0 + i % 2; j < 8; j += 2) {
3136 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3137 if (cap->speakers[chan_idx] == mask) {
3138 /* channel is in a supported position */
3139 ok = true;
3140
3141 if (i % 2 == 0 && i + 1 < chs) {
3142 /* even channel, check the odd companion */
3143 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3144 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3145 int comp_mask_act = cap->speakers[comp_chan_idx];
3146
3147 if (comp_mask_req == comp_mask_act)
3148 companion_ok = true;
3149 else
3150 return -EINVAL;
3151 }
3152 break;
3153 }
3154 }
3155
3156 if (!ok)
3157 return -EINVAL;
3158
3159 if (companion_ok)
3160 i++; /* companion channel already checked */
3161 }
3162
3163 return 0;
3164 }
3165
3166 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3167 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3168 {
3169 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3170 int verb;
3171 int ati_channel_setup = 0;
3172
3173 if (hdmi_slot > 7)
3174 return -EINVAL;
3175
3176 if (!has_amd_full_remap_support(codec)) {
3177 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3178
3179 /* In case this is an odd slot but without stream channel, do not
3180 * disable the slot since the corresponding even slot could have a
3181 * channel. In case neither have a channel, the slot pair will be
3182 * disabled when this function is called for the even slot. */
3183 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3184 return 0;
3185
3186 hdmi_slot -= hdmi_slot % 2;
3187
3188 if (stream_channel != 0xf)
3189 stream_channel -= stream_channel % 2;
3190 }
3191
3192 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3193
3194 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3195
3196 if (stream_channel != 0xf)
3197 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3198
3199 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3200 }
3201
3202 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3203 hda_nid_t pin_nid, int asp_slot)
3204 {
3205 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3206 bool was_odd = false;
3207 int ati_asp_slot = asp_slot;
3208 int verb;
3209 int ati_channel_setup;
3210
3211 if (asp_slot > 7)
3212 return -EINVAL;
3213
3214 if (!has_amd_full_remap_support(codec)) {
3215 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3216 if (ati_asp_slot % 2 != 0) {
3217 ati_asp_slot -= 1;
3218 was_odd = true;
3219 }
3220 }
3221
3222 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3223
3224 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3225
3226 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3227 return 0xf;
3228
3229 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3230 }
3231
3232 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3233 struct hdac_chmap *chmap,
3234 struct hdac_cea_channel_speaker_allocation *cap,
3235 int channels)
3236 {
3237 int c;
3238
3239 /*
3240 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3241 * we need to take that into account (a single channel may take 2
3242 * channel slots if we need to carry a silent channel next to it).
3243 * On Rev3+ AMD codecs this function is not used.
3244 */
3245 int chanpairs = 0;
3246
3247 /* We only produce even-numbered channel count TLVs */
3248 if ((channels % 2) != 0)
3249 return -1;
3250
3251 for (c = 0; c < 7; c += 2) {
3252 if (cap->speakers[c] || cap->speakers[c+1])
3253 chanpairs++;
3254 }
3255
3256 if (chanpairs * 2 != channels)
3257 return -1;
3258
3259 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3260 }
3261
3262 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3263 struct hdac_cea_channel_speaker_allocation *cap,
3264 unsigned int *chmap, int channels)
3265 {
3266 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3267 int count = 0;
3268 int c;
3269
3270 for (c = 7; c >= 0; c--) {
3271 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3272 int spk = cap->speakers[chan];
3273 if (!spk) {
3274 /* add N/A channel if the companion channel is occupied */
3275 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3276 chmap[count++] = SNDRV_CHMAP_NA;
3277
3278 continue;
3279 }
3280
3281 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3282 }
3283
3284 WARN_ON(count != channels);
3285 }
3286
3287 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3288 bool hbr)
3289 {
3290 int hbr_ctl, hbr_ctl_new;
3291
3292 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3293 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3294 if (hbr)
3295 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3296 else
3297 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3298
3299 codec_dbg(codec,
3300 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3301 pin_nid,
3302 hbr_ctl == hbr_ctl_new ? "" : "new-",
3303 hbr_ctl_new);
3304
3305 if (hbr_ctl != hbr_ctl_new)
3306 snd_hda_codec_write(codec, pin_nid, 0,
3307 ATI_VERB_SET_HBR_CONTROL,
3308 hbr_ctl_new);
3309
3310 } else if (hbr)
3311 return -EINVAL;
3312
3313 return 0;
3314 }
3315
3316 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3317 hda_nid_t pin_nid, u32 stream_tag, int format)
3318 {
3319
3320 if (is_amdhdmi_rev3_or_later(codec)) {
3321 int ramp_rate = 180; /* default as per AMD spec */
3322 /* disable ramp-up/down for non-pcm as per AMD spec */
3323 if (format & AC_FMT_TYPE_NON_PCM)
3324 ramp_rate = 0;
3325
3326 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3327 }
3328
3329 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3330 }
3331
3332
3333 static int atihdmi_init(struct hda_codec *codec)
3334 {
3335 struct hdmi_spec *spec = codec->spec;
3336 int pin_idx, err;
3337
3338 err = generic_hdmi_init(codec);
3339
3340 if (err)
3341 return err;
3342
3343 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3344 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3345
3346 /* make sure downmix information in infoframe is zero */
3347 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3348
3349 /* enable channel-wise remap mode if supported */
3350 if (has_amd_full_remap_support(codec))
3351 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3352 ATI_VERB_SET_MULTICHANNEL_MODE,
3353 ATI_MULTICHANNEL_MODE_SINGLE);
3354 }
3355
3356 return 0;
3357 }
3358
3359 static int patch_atihdmi(struct hda_codec *codec)
3360 {
3361 struct hdmi_spec *spec;
3362 struct hdmi_spec_per_cvt *per_cvt;
3363 int err, cvt_idx;
3364
3365 err = patch_generic_hdmi(codec);
3366
3367 if (err)
3368 return err;
3369
3370 codec->patch_ops.init = atihdmi_init;
3371
3372 spec = codec->spec;
3373
3374 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3375 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3376 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3377 spec->ops.setup_stream = atihdmi_setup_stream;
3378
3379 if (!has_amd_full_remap_support(codec)) {
3380 /* override to ATI/AMD-specific versions with pairwise mapping */
3381 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3382 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3383 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3384 atihdmi_paired_cea_alloc_to_tlv_chmap;
3385 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3386 spec->chmap.ops.pin_get_slot_channel =
3387 atihdmi_pin_get_slot_channel;
3388 spec->chmap.ops.pin_set_slot_channel =
3389 atihdmi_pin_set_slot_channel;
3390 }
3391
3392 /* ATI/AMD converters do not advertise all of their capabilities */
3393 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3394 per_cvt = get_cvt(spec, cvt_idx);
3395 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3396 per_cvt->rates |= SUPPORTED_RATES;
3397 per_cvt->formats |= SUPPORTED_FORMATS;
3398 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3399 }
3400
3401 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3402
3403 return 0;
3404 }
3405
3406 /* VIA HDMI Implementation */
3407 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3408 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3409
3410 static int patch_via_hdmi(struct hda_codec *codec)
3411 {
3412 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3413 }
3414
3415 /*
3416 * patch entries
3417 */
3418 static const struct hda_device_id snd_hda_id_hdmi[] = {
3419 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3420 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3421 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3422 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3423 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3424 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3425 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3426 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3427 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3428 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3429 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3430 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3431 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3432 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3433 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3434 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3435 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3436 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3437 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3438 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3439 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3440 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3441 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3442 /* 17 is known to be absent */
3443 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3444 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3445 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3446 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3447 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3448 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3449 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3450 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3451 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3452 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3453 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3454 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3455 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3456 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3457 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3458 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3459 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3460 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3461 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3462 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3463 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3464 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3465 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3466 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3467 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3468 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3469 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3470 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3471 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3472 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3473 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3474 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3475 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3476 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3477 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3478 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3479 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3480 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3481 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3482 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
3483 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3484 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3485 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3486 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3487 /* special ID for generic HDMI */
3488 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3489 {} /* terminator */
3490 };
3491 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3492
3493 MODULE_LICENSE("GPL");
3494 MODULE_DESCRIPTION("HDMI HD-audio codec");
3495 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3496 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3497 MODULE_ALIAS("snd-hda-codec-atihdmi");
3498
3499 static struct hda_codec_driver hdmi_driver = {
3500 .id = snd_hda_id_hdmi,
3501 };
3502
3503 module_hda_codec_driver(hdmi_driver);
This page took 0.134683 seconds and 4 git commands to generate.