3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm
;
48 module_param(static_hdmi_pcm
, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm
, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
64 struct hdmi_spec_per_cvt
{
67 unsigned int channels_min
;
68 unsigned int channels_max
;
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS 32
77 struct hdmi_spec_per_pin
{
79 /* pin idx, different device entries on the same pin use the same idx */
82 hda_nid_t mux_nids
[HDA_MAX_CONNECTIONS
];
86 struct hda_codec
*codec
;
87 struct hdmi_eld sink_eld
;
89 struct delayed_work work
;
90 struct hdmi_pcm
*pcm
; /* pointer to spec->pcm_rec[n] dynamically*/
91 int pcm_idx
; /* which pcm is attached. -1 means no pcm is attached */
93 bool setup
; /* the stream has been set up by prepare callback */
94 int channels
; /* current number of channels */
96 bool chmap_set
; /* channel-map override by ALSA API? */
97 unsigned char chmap
[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 struct snd_info_entry
*proc_entry
;
103 /* operations used by generic code that can be overridden by patches */
105 int (*pin_get_eld
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
106 unsigned char *buf
, int *eld_size
);
108 void (*pin_setup_infoframe
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
109 int ca
, int active_channels
, int conn_type
);
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup
)(struct hda_codec
*codec
, hda_nid_t pin_nid
, bool hbr
);
114 int (*setup_stream
)(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
115 hda_nid_t pin_nid
, u32 stream_tag
, int format
);
121 struct snd_jack
*jack
;
122 struct snd_kcontrol
*eld_ctl
;
127 struct snd_array cvts
; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids
[4]; /* only for haswell fix */
131 struct snd_array pins
; /* struct hdmi_spec_per_pin */
132 struct hdmi_pcm pcm_rec
[16];
133 struct mutex pcm_lock
;
134 /* pcm_bitmap means which pcms have been assigned to pins*/
135 unsigned long pcm_bitmap
;
136 int pcm_used
; /* counter of pcm_rec[] */
137 /* bitmap shows whether the pcm is opened in user space
138 * bit 0 means the first playback PCM (PCM3);
139 * bit 1 means the second playback PCM, and so on.
141 unsigned long pcm_in_use
;
143 struct hdmi_eld temp_eld
;
149 * Non-generic VIA/NVIDIA specific
151 struct hda_multi_out multiout
;
152 struct hda_pcm_stream pcm_playback
;
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 bool use_acomp_notifier
; /* use i915 eld_notify callback for hotplug */
156 struct i915_audio_component_audio_ops i915_audio_ops
;
157 bool i915_bound
; /* was i915 bound in this driver? */
159 struct hdac_chmap chmap
;
162 #ifdef CONFIG_SND_HDA_I915
163 static inline bool codec_has_acomp(struct hda_codec
*codec
)
165 struct hdmi_spec
*spec
= codec
->spec
;
166 return spec
->use_acomp_notifier
;
169 #define codec_has_acomp(codec) false
172 struct hdmi_audio_infoframe
{
179 u8 CC02_CT47
; /* CC in bits 0:2, CT in 4:7 */
183 u8 LFEPBL01_LSV36_DM_INH7
;
186 struct dp_audio_infoframe
{
189 u8 ver
; /* 0x11 << 2 */
191 u8 CC02_CT47
; /* match with HDMI infoframe from this on */
195 u8 LFEPBL01_LSV36_DM_INH7
;
198 union audio_infoframe
{
199 struct hdmi_audio_infoframe hdmi
;
200 struct dp_audio_infoframe dp
;
208 #define get_pin(spec, idx) \
209 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
210 #define get_cvt(spec, idx) \
211 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
212 /* obtain hdmi_pcm object assigned to idx */
213 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
214 /* obtain hda_pcm object assigned to idx */
215 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
217 static int pin_nid_to_pin_index(struct hda_codec
*codec
, hda_nid_t pin_nid
)
219 struct hdmi_spec
*spec
= codec
->spec
;
222 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++)
223 if (get_pin(spec
, pin_idx
)->pin_nid
== pin_nid
)
226 codec_warn(codec
, "HDMI: pin nid %d not registered\n", pin_nid
);
230 static int hinfo_to_pcm_index(struct hda_codec
*codec
,
231 struct hda_pcm_stream
*hinfo
)
233 struct hdmi_spec
*spec
= codec
->spec
;
236 for (pcm_idx
= 0; pcm_idx
< spec
->pcm_used
; pcm_idx
++)
237 if (get_pcm_rec(spec
, pcm_idx
)->stream
== hinfo
)
240 codec_warn(codec
, "HDMI: hinfo %p not registered\n", hinfo
);
244 static int hinfo_to_pin_index(struct hda_codec
*codec
,
245 struct hda_pcm_stream
*hinfo
)
247 struct hdmi_spec
*spec
= codec
->spec
;
248 struct hdmi_spec_per_pin
*per_pin
;
251 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
252 per_pin
= get_pin(spec
, pin_idx
);
254 per_pin
->pcm
->pcm
->stream
== hinfo
)
258 codec_dbg(codec
, "HDMI: hinfo %p not registered\n", hinfo
);
262 static struct hdmi_spec_per_pin
*pcm_idx_to_pin(struct hdmi_spec
*spec
,
266 struct hdmi_spec_per_pin
*per_pin
;
268 for (i
= 0; i
< spec
->num_pins
; i
++) {
269 per_pin
= get_pin(spec
, i
);
270 if (per_pin
->pcm_idx
== pcm_idx
)
276 static int cvt_nid_to_cvt_index(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
278 struct hdmi_spec
*spec
= codec
->spec
;
281 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++)
282 if (get_cvt(spec
, cvt_idx
)->cvt_nid
== cvt_nid
)
285 codec_warn(codec
, "HDMI: cvt nid %d not registered\n", cvt_nid
);
289 static int hdmi_eld_ctl_info(struct snd_kcontrol
*kcontrol
,
290 struct snd_ctl_elem_info
*uinfo
)
292 struct hda_codec
*codec
= snd_kcontrol_chip(kcontrol
);
293 struct hdmi_spec
*spec
= codec
->spec
;
294 struct hdmi_spec_per_pin
*per_pin
;
295 struct hdmi_eld
*eld
;
298 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
300 pcm_idx
= kcontrol
->private_value
;
301 mutex_lock(&spec
->pcm_lock
);
302 per_pin
= pcm_idx_to_pin(spec
, pcm_idx
);
304 /* no pin is bound to the pcm */
306 mutex_unlock(&spec
->pcm_lock
);
309 eld
= &per_pin
->sink_eld
;
310 uinfo
->count
= eld
->eld_valid
? eld
->eld_size
: 0;
311 mutex_unlock(&spec
->pcm_lock
);
316 static int hdmi_eld_ctl_get(struct snd_kcontrol
*kcontrol
,
317 struct snd_ctl_elem_value
*ucontrol
)
319 struct hda_codec
*codec
= snd_kcontrol_chip(kcontrol
);
320 struct hdmi_spec
*spec
= codec
->spec
;
321 struct hdmi_spec_per_pin
*per_pin
;
322 struct hdmi_eld
*eld
;
325 pcm_idx
= kcontrol
->private_value
;
326 mutex_lock(&spec
->pcm_lock
);
327 per_pin
= pcm_idx_to_pin(spec
, pcm_idx
);
329 /* no pin is bound to the pcm */
330 memset(ucontrol
->value
.bytes
.data
, 0,
331 ARRAY_SIZE(ucontrol
->value
.bytes
.data
));
332 mutex_unlock(&spec
->pcm_lock
);
335 eld
= &per_pin
->sink_eld
;
337 if (eld
->eld_size
> ARRAY_SIZE(ucontrol
->value
.bytes
.data
) ||
338 eld
->eld_size
> ELD_MAX_SIZE
) {
339 mutex_unlock(&spec
->pcm_lock
);
344 memset(ucontrol
->value
.bytes
.data
, 0,
345 ARRAY_SIZE(ucontrol
->value
.bytes
.data
));
347 memcpy(ucontrol
->value
.bytes
.data
, eld
->eld_buffer
,
349 mutex_unlock(&spec
->pcm_lock
);
354 static struct snd_kcontrol_new eld_bytes_ctl
= {
355 .access
= SNDRV_CTL_ELEM_ACCESS_READ
| SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
356 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
358 .info
= hdmi_eld_ctl_info
,
359 .get
= hdmi_eld_ctl_get
,
362 static int hdmi_create_eld_ctl(struct hda_codec
*codec
, int pcm_idx
,
365 struct snd_kcontrol
*kctl
;
366 struct hdmi_spec
*spec
= codec
->spec
;
369 kctl
= snd_ctl_new1(&eld_bytes_ctl
, codec
);
372 kctl
->private_value
= pcm_idx
;
373 kctl
->id
.device
= device
;
375 /* no pin nid is associated with the kctl now
376 * tbd: associate pin nid to eld ctl later
378 err
= snd_hda_ctl_add(codec
, 0, kctl
);
382 get_hdmi_pcm(spec
, pcm_idx
)->eld_ctl
= kctl
;
387 static void hdmi_get_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
388 int *packet_index
, int *byte_index
)
392 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
393 AC_VERB_GET_HDMI_DIP_INDEX
, 0);
395 *packet_index
= val
>> 5;
396 *byte_index
= val
& 0x1f;
400 static void hdmi_set_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
401 int packet_index
, int byte_index
)
405 val
= (packet_index
<< 5) | (byte_index
& 0x1f);
407 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_INDEX
, val
);
410 static void hdmi_write_dip_byte(struct hda_codec
*codec
, hda_nid_t pin_nid
,
413 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_DATA
, val
);
416 static void hdmi_init_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
418 struct hdmi_spec
*spec
= codec
->spec
;
422 if (get_wcaps(codec
, pin_nid
) & AC_WCAP_OUT_AMP
)
423 snd_hda_codec_write(codec
, pin_nid
, 0,
424 AC_VERB_SET_AMP_GAIN_MUTE
, AMP_OUT_UNMUTE
);
426 if (spec
->dyn_pin_out
)
427 /* Disable pin out until stream is active */
430 /* Enable pin out: some machines with GM965 gets broken output
431 * when the pin is disabled or changed while using with HDMI
435 snd_hda_codec_write(codec
, pin_nid
, 0,
436 AC_VERB_SET_PIN_WIDGET_CONTROL
, pin_out
);
443 #ifdef CONFIG_SND_PROC_FS
444 static void print_eld_info(struct snd_info_entry
*entry
,
445 struct snd_info_buffer
*buffer
)
447 struct hdmi_spec_per_pin
*per_pin
= entry
->private_data
;
449 mutex_lock(&per_pin
->lock
);
450 snd_hdmi_print_eld_info(&per_pin
->sink_eld
, buffer
);
451 mutex_unlock(&per_pin
->lock
);
454 static void write_eld_info(struct snd_info_entry
*entry
,
455 struct snd_info_buffer
*buffer
)
457 struct hdmi_spec_per_pin
*per_pin
= entry
->private_data
;
459 mutex_lock(&per_pin
->lock
);
460 snd_hdmi_write_eld_info(&per_pin
->sink_eld
, buffer
);
461 mutex_unlock(&per_pin
->lock
);
464 static int eld_proc_new(struct hdmi_spec_per_pin
*per_pin
, int index
)
467 struct hda_codec
*codec
= per_pin
->codec
;
468 struct snd_info_entry
*entry
;
471 snprintf(name
, sizeof(name
), "eld#%d.%d", codec
->addr
, index
);
472 err
= snd_card_proc_new(codec
->card
, name
, &entry
);
476 snd_info_set_text_ops(entry
, per_pin
, print_eld_info
);
477 entry
->c
.text
.write
= write_eld_info
;
478 entry
->mode
|= S_IWUSR
;
479 per_pin
->proc_entry
= entry
;
484 static void eld_proc_free(struct hdmi_spec_per_pin
*per_pin
)
486 if (!per_pin
->codec
->bus
->shutdown
) {
487 snd_info_free_entry(per_pin
->proc_entry
);
488 per_pin
->proc_entry
= NULL
;
492 static inline int eld_proc_new(struct hdmi_spec_per_pin
*per_pin
,
497 static inline void eld_proc_free(struct hdmi_spec_per_pin
*per_pin
)
503 * Audio InfoFrame routines
507 * Enable Audio InfoFrame Transmission
509 static void hdmi_start_infoframe_trans(struct hda_codec
*codec
,
512 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
513 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
518 * Disable Audio InfoFrame Transmission
520 static void hdmi_stop_infoframe_trans(struct hda_codec
*codec
,
523 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
524 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
528 static void hdmi_debug_dip_size(struct hda_codec
*codec
, hda_nid_t pin_nid
)
530 #ifdef CONFIG_SND_DEBUG_VERBOSE
534 size
= snd_hdmi_get_eld_size(codec
, pin_nid
);
535 codec_dbg(codec
, "HDMI: ELD buf size is %d\n", size
);
537 for (i
= 0; i
< 8; i
++) {
538 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
539 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
540 codec_dbg(codec
, "HDMI: DIP GP[%d] buf size is %d\n", i
, size
);
545 static void hdmi_clear_dip_buffers(struct hda_codec
*codec
, hda_nid_t pin_nid
)
551 for (i
= 0; i
< 8; i
++) {
552 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
553 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
557 hdmi_set_dip_index(codec
, pin_nid
, i
, 0x0);
558 for (j
= 1; j
< 1000; j
++) {
559 hdmi_write_dip_byte(codec
, pin_nid
, 0x0);
560 hdmi_get_dip_index(codec
, pin_nid
, &pi
, &bi
);
562 codec_dbg(codec
, "dip index %d: %d != %d\n",
564 if (bi
== 0) /* byte index wrapped around */
568 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
574 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe
*hdmi_ai
)
576 u8
*bytes
= (u8
*)hdmi_ai
;
580 hdmi_ai
->checksum
= 0;
582 for (i
= 0; i
< sizeof(*hdmi_ai
); i
++)
585 hdmi_ai
->checksum
= -sum
;
588 static void hdmi_fill_audio_infoframe(struct hda_codec
*codec
,
594 hdmi_debug_dip_size(codec
, pin_nid
);
595 hdmi_clear_dip_buffers(codec
, pin_nid
); /* be paranoid */
597 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
598 for (i
= 0; i
< size
; i
++)
599 hdmi_write_dip_byte(codec
, pin_nid
, dip
[i
]);
602 static bool hdmi_infoframe_uptodate(struct hda_codec
*codec
, hda_nid_t pin_nid
,
608 if (snd_hda_codec_read(codec
, pin_nid
, 0, AC_VERB_GET_HDMI_DIP_XMIT
, 0)
612 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
613 for (i
= 0; i
< size
; i
++) {
614 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
615 AC_VERB_GET_HDMI_DIP_DATA
, 0);
623 static void hdmi_pin_setup_infoframe(struct hda_codec
*codec
,
625 int ca
, int active_channels
,
628 union audio_infoframe ai
;
630 memset(&ai
, 0, sizeof(ai
));
631 if (conn_type
== 0) { /* HDMI */
632 struct hdmi_audio_infoframe
*hdmi_ai
= &ai
.hdmi
;
634 hdmi_ai
->type
= 0x84;
637 hdmi_ai
->CC02_CT47
= active_channels
- 1;
639 hdmi_checksum_audio_infoframe(hdmi_ai
);
640 } else if (conn_type
== 1) { /* DisplayPort */
641 struct dp_audio_infoframe
*dp_ai
= &ai
.dp
;
645 dp_ai
->ver
= 0x11 << 2;
646 dp_ai
->CC02_CT47
= active_channels
- 1;
649 codec_dbg(codec
, "HDMI: unknown connection type at pin %d\n",
655 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
656 * sizeof(*dp_ai) to avoid partial match/update problems when
657 * the user switches between HDMI/DP monitors.
659 if (!hdmi_infoframe_uptodate(codec
, pin_nid
, ai
.bytes
,
662 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
664 active_channels
, ca
);
665 hdmi_stop_infoframe_trans(codec
, pin_nid
);
666 hdmi_fill_audio_infoframe(codec
, pin_nid
,
667 ai
.bytes
, sizeof(ai
));
668 hdmi_start_infoframe_trans(codec
, pin_nid
);
672 static void hdmi_setup_audio_infoframe(struct hda_codec
*codec
,
673 struct hdmi_spec_per_pin
*per_pin
,
676 struct hdmi_spec
*spec
= codec
->spec
;
677 struct hdac_chmap
*chmap
= &spec
->chmap
;
678 hda_nid_t pin_nid
= per_pin
->pin_nid
;
679 int channels
= per_pin
->channels
;
681 struct hdmi_eld
*eld
;
687 if (is_haswell_plus(codec
))
688 snd_hda_codec_write(codec
, pin_nid
, 0,
689 AC_VERB_SET_AMP_GAIN_MUTE
,
692 eld
= &per_pin
->sink_eld
;
694 ca
= snd_hdac_channel_allocation(&codec
->core
,
695 eld
->info
.spk_alloc
, channels
,
696 per_pin
->chmap_set
, non_pcm
, per_pin
->chmap
);
698 active_channels
= snd_hdac_get_active_channels(ca
);
700 chmap
->ops
.set_channel_count(&codec
->core
, per_pin
->cvt_nid
,
704 * always configure channel mapping, it may have been changed by the
705 * user in the meantime
707 snd_hdac_setup_channel_mapping(&spec
->chmap
,
708 pin_nid
, non_pcm
, ca
, channels
,
709 per_pin
->chmap
, per_pin
->chmap_set
);
711 spec
->ops
.pin_setup_infoframe(codec
, pin_nid
, ca
, active_channels
,
712 eld
->info
.conn_type
);
714 per_pin
->non_pcm
= non_pcm
;
721 static bool hdmi_present_sense(struct hdmi_spec_per_pin
*per_pin
, int repoll
);
723 static void check_presence_and_report(struct hda_codec
*codec
, hda_nid_t nid
)
725 struct hdmi_spec
*spec
= codec
->spec
;
726 int pin_idx
= pin_nid_to_pin_index(codec
, nid
);
730 if (hdmi_present_sense(get_pin(spec
, pin_idx
), 1))
731 snd_hda_jack_report_sync(codec
);
734 static void jack_callback(struct hda_codec
*codec
,
735 struct hda_jack_callback
*jack
)
737 check_presence_and_report(codec
, jack
->nid
);
740 static void hdmi_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
742 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
743 struct hda_jack_tbl
*jack
;
744 int dev_entry
= (res
& AC_UNSOL_RES_DE
) >> AC_UNSOL_RES_DE_SHIFT
;
746 jack
= snd_hda_jack_tbl_get_from_tag(codec
, tag
);
749 jack
->jack_dirty
= 1;
752 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
753 codec
->addr
, jack
->nid
, dev_entry
, !!(res
& AC_UNSOL_RES_IA
),
754 !!(res
& AC_UNSOL_RES_PD
), !!(res
& AC_UNSOL_RES_ELDV
));
756 check_presence_and_report(codec
, jack
->nid
);
759 static void hdmi_non_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
761 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
762 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
763 int cp_state
= !!(res
& AC_UNSOL_RES_CP_STATE
);
764 int cp_ready
= !!(res
& AC_UNSOL_RES_CP_READY
);
767 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
782 static void hdmi_unsol_event(struct hda_codec
*codec
, unsigned int res
)
784 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
785 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
787 if (!snd_hda_jack_tbl_get_from_tag(codec
, tag
)) {
788 codec_dbg(codec
, "Unexpected HDMI event tag 0x%x\n", tag
);
793 hdmi_intrinsic_event(codec
, res
);
795 hdmi_non_intrinsic_event(codec
, res
);
798 static void haswell_verify_D0(struct hda_codec
*codec
,
799 hda_nid_t cvt_nid
, hda_nid_t nid
)
803 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
804 * thus pins could only choose converter 0 for use. Make sure the
805 * converters are in correct power state */
806 if (!snd_hda_check_power_state(codec
, cvt_nid
, AC_PWRST_D0
))
807 snd_hda_codec_write(codec
, cvt_nid
, 0, AC_VERB_SET_POWER_STATE
, AC_PWRST_D0
);
809 if (!snd_hda_check_power_state(codec
, nid
, AC_PWRST_D0
)) {
810 snd_hda_codec_write(codec
, nid
, 0, AC_VERB_SET_POWER_STATE
,
813 pwr
= snd_hda_codec_read(codec
, nid
, 0, AC_VERB_GET_POWER_STATE
, 0);
814 pwr
= (pwr
& AC_PWRST_ACTUAL
) >> AC_PWRST_ACTUAL_SHIFT
;
815 codec_dbg(codec
, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid
, pwr
);
823 /* HBR should be Non-PCM, 8 channels */
824 #define is_hbr_format(format) \
825 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
827 static int hdmi_pin_hbr_setup(struct hda_codec
*codec
, hda_nid_t pin_nid
,
830 int pinctl
, new_pinctl
;
832 if (snd_hda_query_pin_caps(codec
, pin_nid
) & AC_PINCAP_HBR
) {
833 pinctl
= snd_hda_codec_read(codec
, pin_nid
, 0,
834 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
837 return hbr
? -EINVAL
: 0;
839 new_pinctl
= pinctl
& ~AC_PINCTL_EPT
;
841 new_pinctl
|= AC_PINCTL_EPT_HBR
;
843 new_pinctl
|= AC_PINCTL_EPT_NATIVE
;
846 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
848 pinctl
== new_pinctl
? "" : "new-",
851 if (pinctl
!= new_pinctl
)
852 snd_hda_codec_write(codec
, pin_nid
, 0,
853 AC_VERB_SET_PIN_WIDGET_CONTROL
,
861 static int hdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
862 hda_nid_t pin_nid
, u32 stream_tag
, int format
)
864 struct hdmi_spec
*spec
= codec
->spec
;
867 if (is_haswell_plus(codec
))
868 haswell_verify_D0(codec
, cvt_nid
, pin_nid
);
870 err
= spec
->ops
.pin_hbr_setup(codec
, pin_nid
, is_hbr_format(format
));
873 codec_dbg(codec
, "hdmi_setup_stream: HBR is not supported\n");
877 snd_hda_codec_setup_stream(codec
, cvt_nid
, stream_tag
, 0, format
);
881 /* Try to find an available converter
882 * If pin_idx is less then zero, just try to find an available converter.
883 * Otherwise, try to find an available converter and get the cvt mux index
886 static int hdmi_choose_cvt(struct hda_codec
*codec
,
887 int pin_idx
, int *cvt_id
, int *mux_id
)
889 struct hdmi_spec
*spec
= codec
->spec
;
890 struct hdmi_spec_per_pin
*per_pin
;
891 struct hdmi_spec_per_cvt
*per_cvt
= NULL
;
892 int cvt_idx
, mux_idx
= 0;
894 /* pin_idx < 0 means no pin will be bound to the converter */
898 per_pin
= get_pin(spec
, pin_idx
);
900 /* Dynamically assign converter to stream */
901 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
902 per_cvt
= get_cvt(spec
, cvt_idx
);
904 /* Must not already be assigned */
905 if (per_cvt
->assigned
)
909 /* Must be in pin's mux's list of converters */
910 for (mux_idx
= 0; mux_idx
< per_pin
->num_mux_nids
; mux_idx
++)
911 if (per_pin
->mux_nids
[mux_idx
] == per_cvt
->cvt_nid
)
913 /* Not in mux list */
914 if (mux_idx
== per_pin
->num_mux_nids
)
919 /* No free converters */
920 if (cvt_idx
== spec
->num_cvts
)
924 per_pin
->mux_idx
= mux_idx
;
934 /* Assure the pin select the right convetor */
935 static void intel_verify_pin_cvt_connect(struct hda_codec
*codec
,
936 struct hdmi_spec_per_pin
*per_pin
)
938 hda_nid_t pin_nid
= per_pin
->pin_nid
;
941 mux_idx
= per_pin
->mux_idx
;
942 curr
= snd_hda_codec_read(codec
, pin_nid
, 0,
943 AC_VERB_GET_CONNECT_SEL
, 0);
945 snd_hda_codec_write_cache(codec
, pin_nid
, 0,
946 AC_VERB_SET_CONNECT_SEL
,
950 /* get the mux index for the converter of the pins
951 * converter's mux index is the same for all pins on Intel platform
953 static int intel_cvt_id_to_mux_idx(struct hdmi_spec
*spec
,
958 for (i
= 0; i
< spec
->num_cvts
; i
++)
959 if (spec
->cvt_nids
[i
] == cvt_nid
)
964 /* Intel HDMI workaround to fix audio routing issue:
965 * For some Intel display codecs, pins share the same connection list.
966 * So a conveter can be selected by multiple pins and playback on any of these
967 * pins will generate sound on the external display, because audio flows from
968 * the same converter to the display pipeline. Also muting one pin may make
969 * other pins have no sound output.
970 * So this function assures that an assigned converter for a pin is not selected
973 static void intel_not_share_assigned_cvt(struct hda_codec
*codec
,
974 hda_nid_t pin_nid
, int mux_idx
)
976 struct hdmi_spec
*spec
= codec
->spec
;
979 struct hdmi_spec_per_cvt
*per_cvt
;
981 /* configure all pins, including "no physical connection" ones */
982 for_each_hda_codec_node(nid
, codec
) {
983 unsigned int wid_caps
= get_wcaps(codec
, nid
);
984 unsigned int wid_type
= get_wcaps_type(wid_caps
);
986 if (wid_type
!= AC_WID_PIN
)
992 curr
= snd_hda_codec_read(codec
, nid
, 0,
993 AC_VERB_GET_CONNECT_SEL
, 0);
997 /* choose an unassigned converter. The conveters in the
998 * connection list are in the same order as in the codec.
1000 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
1001 per_cvt
= get_cvt(spec
, cvt_idx
);
1002 if (!per_cvt
->assigned
) {
1004 "choose cvt %d for pin nid %d\n",
1006 snd_hda_codec_write_cache(codec
, nid
, 0,
1007 AC_VERB_SET_CONNECT_SEL
,
1015 /* A wrapper of intel_not_share_asigned_cvt() */
1016 static void intel_not_share_assigned_cvt_nid(struct hda_codec
*codec
,
1017 hda_nid_t pin_nid
, hda_nid_t cvt_nid
)
1020 struct hdmi_spec
*spec
= codec
->spec
;
1022 if (!is_haswell_plus(codec
) && !is_valleyview_plus(codec
))
1025 /* On Intel platform, the mapping of converter nid to
1026 * mux index of the pins are always the same.
1027 * The pin nid may be 0, this means all pins will not
1028 * share the converter.
1030 mux_idx
= intel_cvt_id_to_mux_idx(spec
, cvt_nid
);
1032 intel_not_share_assigned_cvt(codec
, pin_nid
, mux_idx
);
1035 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1036 * in dyn_pcm_assign mode.
1038 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream
*hinfo
,
1039 struct hda_codec
*codec
,
1040 struct snd_pcm_substream
*substream
)
1042 struct hdmi_spec
*spec
= codec
->spec
;
1043 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1044 int cvt_idx
, pcm_idx
;
1045 struct hdmi_spec_per_cvt
*per_cvt
= NULL
;
1048 pcm_idx
= hinfo_to_pcm_index(codec
, hinfo
);
1052 err
= hdmi_choose_cvt(codec
, -1, &cvt_idx
, NULL
);
1056 per_cvt
= get_cvt(spec
, cvt_idx
);
1057 per_cvt
->assigned
= 1;
1058 hinfo
->nid
= per_cvt
->cvt_nid
;
1060 intel_not_share_assigned_cvt_nid(codec
, 0, per_cvt
->cvt_nid
);
1062 set_bit(pcm_idx
, &spec
->pcm_in_use
);
1063 /* todo: setup spdif ctls assign */
1065 /* Initially set the converter's capabilities */
1066 hinfo
->channels_min
= per_cvt
->channels_min
;
1067 hinfo
->channels_max
= per_cvt
->channels_max
;
1068 hinfo
->rates
= per_cvt
->rates
;
1069 hinfo
->formats
= per_cvt
->formats
;
1070 hinfo
->maxbps
= per_cvt
->maxbps
;
1072 /* Store the updated parameters */
1073 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1074 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1075 runtime
->hw
.formats
= hinfo
->formats
;
1076 runtime
->hw
.rates
= hinfo
->rates
;
1078 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
1079 SNDRV_PCM_HW_PARAM_CHANNELS
, 2);
1086 static int hdmi_pcm_open(struct hda_pcm_stream
*hinfo
,
1087 struct hda_codec
*codec
,
1088 struct snd_pcm_substream
*substream
)
1090 struct hdmi_spec
*spec
= codec
->spec
;
1091 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1092 int pin_idx
, cvt_idx
, pcm_idx
, mux_idx
= 0;
1093 struct hdmi_spec_per_pin
*per_pin
;
1094 struct hdmi_eld
*eld
;
1095 struct hdmi_spec_per_cvt
*per_cvt
= NULL
;
1098 /* Validate hinfo */
1099 pcm_idx
= hinfo_to_pcm_index(codec
, hinfo
);
1103 mutex_lock(&spec
->pcm_lock
);
1104 pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1105 if (!spec
->dyn_pcm_assign
) {
1106 if (snd_BUG_ON(pin_idx
< 0)) {
1107 mutex_unlock(&spec
->pcm_lock
);
1111 /* no pin is assigned to the PCM
1112 * PA need pcm open successfully when probe
1115 err
= hdmi_pcm_open_no_pin(hinfo
, codec
, substream
);
1116 mutex_unlock(&spec
->pcm_lock
);
1121 err
= hdmi_choose_cvt(codec
, pin_idx
, &cvt_idx
, &mux_idx
);
1123 mutex_unlock(&spec
->pcm_lock
);
1127 per_cvt
= get_cvt(spec
, cvt_idx
);
1128 /* Claim converter */
1129 per_cvt
->assigned
= 1;
1131 set_bit(pcm_idx
, &spec
->pcm_in_use
);
1132 per_pin
= get_pin(spec
, pin_idx
);
1133 per_pin
->cvt_nid
= per_cvt
->cvt_nid
;
1134 hinfo
->nid
= per_cvt
->cvt_nid
;
1136 snd_hda_codec_write_cache(codec
, per_pin
->pin_nid
, 0,
1137 AC_VERB_SET_CONNECT_SEL
,
1140 /* configure unused pins to choose other converters */
1141 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
))
1142 intel_not_share_assigned_cvt(codec
, per_pin
->pin_nid
, mux_idx
);
1144 snd_hda_spdif_ctls_assign(codec
, pcm_idx
, per_cvt
->cvt_nid
);
1146 /* Initially set the converter's capabilities */
1147 hinfo
->channels_min
= per_cvt
->channels_min
;
1148 hinfo
->channels_max
= per_cvt
->channels_max
;
1149 hinfo
->rates
= per_cvt
->rates
;
1150 hinfo
->formats
= per_cvt
->formats
;
1151 hinfo
->maxbps
= per_cvt
->maxbps
;
1153 eld
= &per_pin
->sink_eld
;
1154 /* Restrict capabilities by ELD if this isn't disabled */
1155 if (!static_hdmi_pcm
&& eld
->eld_valid
) {
1156 snd_hdmi_eld_update_pcm_info(&eld
->info
, hinfo
);
1157 if (hinfo
->channels_min
> hinfo
->channels_max
||
1158 !hinfo
->rates
|| !hinfo
->formats
) {
1159 per_cvt
->assigned
= 0;
1161 snd_hda_spdif_ctls_unassign(codec
, pcm_idx
);
1162 mutex_unlock(&spec
->pcm_lock
);
1167 mutex_unlock(&spec
->pcm_lock
);
1168 /* Store the updated parameters */
1169 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1170 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1171 runtime
->hw
.formats
= hinfo
->formats
;
1172 runtime
->hw
.rates
= hinfo
->rates
;
1174 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
1175 SNDRV_PCM_HW_PARAM_CHANNELS
, 2);
1180 * HDA/HDMI auto parsing
1182 static int hdmi_read_pin_conn(struct hda_codec
*codec
, int pin_idx
)
1184 struct hdmi_spec
*spec
= codec
->spec
;
1185 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
1186 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1188 if (!(get_wcaps(codec
, pin_nid
) & AC_WCAP_CONN_LIST
)) {
1190 "HDMI: pin %d wcaps %#x does not support connection list\n",
1191 pin_nid
, get_wcaps(codec
, pin_nid
));
1195 per_pin
->num_mux_nids
= snd_hda_get_connections(codec
, pin_nid
,
1197 HDA_MAX_CONNECTIONS
);
1202 static int hdmi_find_pcm_slot(struct hdmi_spec
*spec
,
1203 struct hdmi_spec_per_pin
*per_pin
)
1207 /* try the prefer PCM */
1208 if (!test_bit(per_pin
->pin_nid_idx
, &spec
->pcm_bitmap
))
1209 return per_pin
->pin_nid_idx
;
1211 /* have a second try; check the "reserved area" over num_pins */
1212 for (i
= spec
->num_pins
; i
< spec
->pcm_used
; i
++) {
1213 if (!test_bit(i
, &spec
->pcm_bitmap
))
1217 /* the last try; check the empty slots in pins */
1218 for (i
= 0; i
< spec
->num_pins
; i
++) {
1219 if (!test_bit(i
, &spec
->pcm_bitmap
))
1225 static void hdmi_attach_hda_pcm(struct hdmi_spec
*spec
,
1226 struct hdmi_spec_per_pin
*per_pin
)
1230 /* pcm already be attached to the pin */
1233 idx
= hdmi_find_pcm_slot(spec
, per_pin
);
1236 per_pin
->pcm_idx
= idx
;
1237 per_pin
->pcm
= get_hdmi_pcm(spec
, idx
);
1238 set_bit(idx
, &spec
->pcm_bitmap
);
1241 static void hdmi_detach_hda_pcm(struct hdmi_spec
*spec
,
1242 struct hdmi_spec_per_pin
*per_pin
)
1246 /* pcm already be detached from the pin */
1249 idx
= per_pin
->pcm_idx
;
1250 per_pin
->pcm_idx
= -1;
1251 per_pin
->pcm
= NULL
;
1252 if (idx
>= 0 && idx
< spec
->pcm_used
)
1253 clear_bit(idx
, &spec
->pcm_bitmap
);
1256 static int hdmi_get_pin_cvt_mux(struct hdmi_spec
*spec
,
1257 struct hdmi_spec_per_pin
*per_pin
, hda_nid_t cvt_nid
)
1261 for (mux_idx
= 0; mux_idx
< per_pin
->num_mux_nids
; mux_idx
++)
1262 if (per_pin
->mux_nids
[mux_idx
] == cvt_nid
)
1267 static bool check_non_pcm_per_cvt(struct hda_codec
*codec
, hda_nid_t cvt_nid
);
1269 static void hdmi_pcm_setup_pin(struct hdmi_spec
*spec
,
1270 struct hdmi_spec_per_pin
*per_pin
)
1272 struct hda_codec
*codec
= per_pin
->codec
;
1273 struct hda_pcm
*pcm
;
1274 struct hda_pcm_stream
*hinfo
;
1275 struct snd_pcm_substream
*substream
;
1279 if (per_pin
->pcm_idx
>= 0 && per_pin
->pcm_idx
< spec
->pcm_used
)
1280 pcm
= get_pcm_rec(spec
, per_pin
->pcm_idx
);
1283 if (!test_bit(per_pin
->pcm_idx
, &spec
->pcm_in_use
))
1286 /* hdmi audio only uses playback and one substream */
1287 hinfo
= pcm
->stream
;
1288 substream
= pcm
->pcm
->streams
[0].substream
;
1290 per_pin
->cvt_nid
= hinfo
->nid
;
1292 mux_idx
= hdmi_get_pin_cvt_mux(spec
, per_pin
, hinfo
->nid
);
1293 if (mux_idx
< per_pin
->num_mux_nids
)
1294 snd_hda_codec_write_cache(codec
, per_pin
->pin_nid
, 0,
1295 AC_VERB_SET_CONNECT_SEL
,
1297 snd_hda_spdif_ctls_assign(codec
, per_pin
->pcm_idx
, hinfo
->nid
);
1299 non_pcm
= check_non_pcm_per_cvt(codec
, hinfo
->nid
);
1300 if (substream
->runtime
)
1301 per_pin
->channels
= substream
->runtime
->channels
;
1302 per_pin
->setup
= true;
1303 per_pin
->mux_idx
= mux_idx
;
1305 hdmi_setup_audio_infoframe(codec
, per_pin
, non_pcm
);
1308 static void hdmi_pcm_reset_pin(struct hdmi_spec
*spec
,
1309 struct hdmi_spec_per_pin
*per_pin
)
1311 if (per_pin
->pcm_idx
>= 0 && per_pin
->pcm_idx
< spec
->pcm_used
)
1312 snd_hda_spdif_ctls_unassign(per_pin
->codec
, per_pin
->pcm_idx
);
1314 per_pin
->chmap_set
= false;
1315 memset(per_pin
->chmap
, 0, sizeof(per_pin
->chmap
));
1317 per_pin
->setup
= false;
1318 per_pin
->channels
= 0;
1321 /* update per_pin ELD from the given new ELD;
1322 * setup info frame and notification accordingly
1324 static void update_eld(struct hda_codec
*codec
,
1325 struct hdmi_spec_per_pin
*per_pin
,
1326 struct hdmi_eld
*eld
)
1328 struct hdmi_eld
*pin_eld
= &per_pin
->sink_eld
;
1329 struct hdmi_spec
*spec
= codec
->spec
;
1330 bool old_eld_valid
= pin_eld
->eld_valid
;
1334 /* for monitor disconnection, save pcm_idx firstly */
1335 pcm_idx
= per_pin
->pcm_idx
;
1336 if (spec
->dyn_pcm_assign
) {
1337 if (eld
->eld_valid
) {
1338 hdmi_attach_hda_pcm(spec
, per_pin
);
1339 hdmi_pcm_setup_pin(spec
, per_pin
);
1341 hdmi_pcm_reset_pin(spec
, per_pin
);
1342 hdmi_detach_hda_pcm(spec
, per_pin
);
1345 /* if pcm_idx == -1, it means this is in monitor connection event
1346 * we can get the correct pcm_idx now.
1349 pcm_idx
= per_pin
->pcm_idx
;
1352 snd_hdmi_show_eld(codec
, &eld
->info
);
1354 eld_changed
= (pin_eld
->eld_valid
!= eld
->eld_valid
);
1355 if (eld
->eld_valid
&& pin_eld
->eld_valid
)
1356 if (pin_eld
->eld_size
!= eld
->eld_size
||
1357 memcmp(pin_eld
->eld_buffer
, eld
->eld_buffer
,
1358 eld
->eld_size
) != 0)
1361 pin_eld
->monitor_present
= eld
->monitor_present
;
1362 pin_eld
->eld_valid
= eld
->eld_valid
;
1363 pin_eld
->eld_size
= eld
->eld_size
;
1365 memcpy(pin_eld
->eld_buffer
, eld
->eld_buffer
, eld
->eld_size
);
1366 pin_eld
->info
= eld
->info
;
1369 * Re-setup pin and infoframe. This is needed e.g. when
1370 * - sink is first plugged-in
1371 * - transcoder can change during stream playback on Haswell
1372 * and this can make HW reset converter selection on a pin.
1374 if (eld
->eld_valid
&& !old_eld_valid
&& per_pin
->setup
) {
1375 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
)) {
1376 intel_verify_pin_cvt_connect(codec
, per_pin
);
1377 intel_not_share_assigned_cvt(codec
, per_pin
->pin_nid
,
1381 hdmi_setup_audio_infoframe(codec
, per_pin
, per_pin
->non_pcm
);
1384 if (eld_changed
&& pcm_idx
>= 0)
1385 snd_ctl_notify(codec
->card
,
1386 SNDRV_CTL_EVENT_MASK_VALUE
|
1387 SNDRV_CTL_EVENT_MASK_INFO
,
1388 &get_hdmi_pcm(spec
, pcm_idx
)->eld_ctl
->id
);
1391 /* update ELD and jack state via HD-audio verbs */
1392 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin
*per_pin
,
1395 struct hda_jack_tbl
*jack
;
1396 struct hda_codec
*codec
= per_pin
->codec
;
1397 struct hdmi_spec
*spec
= codec
->spec
;
1398 struct hdmi_eld
*eld
= &spec
->temp_eld
;
1399 struct hdmi_eld
*pin_eld
= &per_pin
->sink_eld
;
1400 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1402 * Always execute a GetPinSense verb here, even when called from
1403 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1404 * response's PD bit is not the real PD value, but indicates that
1405 * the real PD value changed. An older version of the HD-audio
1406 * specification worked this way. Hence, we just ignore the data in
1407 * the unsolicited response to avoid custom WARs.
1411 bool do_repoll
= false;
1413 present
= snd_hda_pin_sense(codec
, pin_nid
);
1415 mutex_lock(&per_pin
->lock
);
1416 pin_eld
->monitor_present
= !!(present
& AC_PINSENSE_PRESENCE
);
1417 if (pin_eld
->monitor_present
)
1418 eld
->eld_valid
= !!(present
& AC_PINSENSE_ELDV
);
1420 eld
->eld_valid
= false;
1423 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1424 codec
->addr
, pin_nid
, pin_eld
->monitor_present
, eld
->eld_valid
);
1426 if (eld
->eld_valid
) {
1427 if (spec
->ops
.pin_get_eld(codec
, pin_nid
, eld
->eld_buffer
,
1428 &eld
->eld_size
) < 0)
1429 eld
->eld_valid
= false;
1431 if (snd_hdmi_parse_eld(codec
, &eld
->info
, eld
->eld_buffer
,
1433 eld
->eld_valid
= false;
1435 if (!eld
->eld_valid
&& repoll
)
1440 schedule_delayed_work(&per_pin
->work
, msecs_to_jiffies(300));
1442 update_eld(codec
, per_pin
, eld
);
1444 ret
= !repoll
|| !pin_eld
->monitor_present
|| pin_eld
->eld_valid
;
1446 jack
= snd_hda_jack_tbl_get(codec
, pin_nid
);
1448 jack
->block_report
= !ret
;
1450 mutex_unlock(&per_pin
->lock
);
1454 static struct snd_jack
*pin_idx_to_jack(struct hda_codec
*codec
,
1455 struct hdmi_spec_per_pin
*per_pin
)
1457 struct hdmi_spec
*spec
= codec
->spec
;
1458 struct snd_jack
*jack
= NULL
;
1459 struct hda_jack_tbl
*jack_tbl
;
1461 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1462 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1463 * NULL even after snd_hda_jack_tbl_clear() is called to
1464 * free snd_jack. This may cause access invalid memory
1465 * when calling snd_jack_report
1467 if (per_pin
->pcm_idx
>= 0 && spec
->dyn_pcm_assign
)
1468 jack
= spec
->pcm_rec
[per_pin
->pcm_idx
].jack
;
1469 else if (!spec
->dyn_pcm_assign
) {
1470 jack_tbl
= snd_hda_jack_tbl_get(codec
, per_pin
->pin_nid
);
1472 jack
= jack_tbl
->jack
;
1477 /* update ELD and jack state via audio component */
1478 static void sync_eld_via_acomp(struct hda_codec
*codec
,
1479 struct hdmi_spec_per_pin
*per_pin
)
1481 struct hdmi_spec
*spec
= codec
->spec
;
1482 struct hdmi_eld
*eld
= &spec
->temp_eld
;
1483 struct snd_jack
*jack
= NULL
;
1486 mutex_lock(&per_pin
->lock
);
1487 size
= snd_hdac_acomp_get_eld(&codec
->bus
->core
, per_pin
->pin_nid
,
1488 &eld
->monitor_present
, eld
->eld_buffer
,
1493 size
= min(size
, ELD_MAX_SIZE
);
1494 if (snd_hdmi_parse_eld(codec
, &eld
->info
,
1495 eld
->eld_buffer
, size
) < 0)
1500 eld
->eld_valid
= true;
1501 eld
->eld_size
= size
;
1503 eld
->eld_valid
= false;
1507 /* pcm_idx >=0 before update_eld() means it is in monitor
1508 * disconnected event. Jack must be fetched before update_eld()
1510 jack
= pin_idx_to_jack(codec
, per_pin
);
1511 update_eld(codec
, per_pin
, eld
);
1513 jack
= pin_idx_to_jack(codec
, per_pin
);
1516 snd_jack_report(jack
,
1517 eld
->monitor_present
? SND_JACK_AVOUT
: 0);
1519 mutex_unlock(&per_pin
->lock
);
1522 static bool hdmi_present_sense(struct hdmi_spec_per_pin
*per_pin
, int repoll
)
1524 struct hda_codec
*codec
= per_pin
->codec
;
1525 struct hdmi_spec
*spec
= codec
->spec
;
1528 /* no temporary power up/down needed for component notifier */
1529 if (!codec_has_acomp(codec
))
1530 snd_hda_power_up_pm(codec
);
1532 mutex_lock(&spec
->pcm_lock
);
1533 if (codec_has_acomp(codec
)) {
1534 sync_eld_via_acomp(codec
, per_pin
);
1535 ret
= false; /* don't call snd_hda_jack_report_sync() */
1537 ret
= hdmi_present_sense_via_verbs(per_pin
, repoll
);
1539 mutex_unlock(&spec
->pcm_lock
);
1541 if (!codec_has_acomp(codec
))
1542 snd_hda_power_down_pm(codec
);
1547 static void hdmi_repoll_eld(struct work_struct
*work
)
1549 struct hdmi_spec_per_pin
*per_pin
=
1550 container_of(to_delayed_work(work
), struct hdmi_spec_per_pin
, work
);
1552 if (per_pin
->repoll_count
++ > 6)
1553 per_pin
->repoll_count
= 0;
1555 if (hdmi_present_sense(per_pin
, per_pin
->repoll_count
))
1556 snd_hda_jack_report_sync(per_pin
->codec
);
1559 static void intel_haswell_fixup_connect_list(struct hda_codec
*codec
,
1562 static int hdmi_add_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
1564 struct hdmi_spec
*spec
= codec
->spec
;
1565 unsigned int caps
, config
;
1567 struct hdmi_spec_per_pin
*per_pin
;
1570 caps
= snd_hda_query_pin_caps(codec
, pin_nid
);
1571 if (!(caps
& (AC_PINCAP_HDMI
| AC_PINCAP_DP
)))
1574 config
= snd_hda_codec_get_pincfg(codec
, pin_nid
);
1575 if (get_defcfg_connect(config
) == AC_JACK_PORT_NONE
)
1578 if (is_haswell_plus(codec
))
1579 intel_haswell_fixup_connect_list(codec
, pin_nid
);
1581 pin_idx
= spec
->num_pins
;
1582 per_pin
= snd_array_new(&spec
->pins
);
1586 per_pin
->pin_nid
= pin_nid
;
1587 per_pin
->non_pcm
= false;
1588 if (spec
->dyn_pcm_assign
)
1589 per_pin
->pcm_idx
= -1;
1591 per_pin
->pcm
= get_hdmi_pcm(spec
, pin_idx
);
1592 per_pin
->pcm_idx
= pin_idx
;
1594 per_pin
->pin_nid_idx
= pin_idx
;
1596 err
= hdmi_read_pin_conn(codec
, pin_idx
);
1605 static int hdmi_add_cvt(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
1607 struct hdmi_spec
*spec
= codec
->spec
;
1608 struct hdmi_spec_per_cvt
*per_cvt
;
1612 chans
= get_wcaps(codec
, cvt_nid
);
1613 chans
= get_wcaps_channels(chans
);
1615 per_cvt
= snd_array_new(&spec
->cvts
);
1619 per_cvt
->cvt_nid
= cvt_nid
;
1620 per_cvt
->channels_min
= 2;
1622 per_cvt
->channels_max
= chans
;
1623 if (chans
> spec
->chmap
.channels_max
)
1624 spec
->chmap
.channels_max
= chans
;
1627 err
= snd_hda_query_supported_pcm(codec
, cvt_nid
,
1634 if (spec
->num_cvts
< ARRAY_SIZE(spec
->cvt_nids
))
1635 spec
->cvt_nids
[spec
->num_cvts
] = cvt_nid
;
1641 static int hdmi_parse_codec(struct hda_codec
*codec
)
1646 nodes
= snd_hda_get_sub_nodes(codec
, codec
->core
.afg
, &nid
);
1647 if (!nid
|| nodes
< 0) {
1648 codec_warn(codec
, "HDMI: failed to get afg sub nodes\n");
1652 for (i
= 0; i
< nodes
; i
++, nid
++) {
1656 caps
= get_wcaps(codec
, nid
);
1657 type
= get_wcaps_type(caps
);
1659 if (!(caps
& AC_WCAP_DIGITAL
))
1663 case AC_WID_AUD_OUT
:
1664 hdmi_add_cvt(codec
, nid
);
1667 hdmi_add_pin(codec
, nid
);
1677 static bool check_non_pcm_per_cvt(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
1679 struct hda_spdif_out
*spdif
;
1682 mutex_lock(&codec
->spdif_mutex
);
1683 spdif
= snd_hda_spdif_out_of_nid(codec
, cvt_nid
);
1684 non_pcm
= !!(spdif
->status
& IEC958_AES0_NONAUDIO
);
1685 mutex_unlock(&codec
->spdif_mutex
);
1693 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1694 struct hda_codec
*codec
,
1695 unsigned int stream_tag
,
1696 unsigned int format
,
1697 struct snd_pcm_substream
*substream
)
1699 hda_nid_t cvt_nid
= hinfo
->nid
;
1700 struct hdmi_spec
*spec
= codec
->spec
;
1702 struct hdmi_spec_per_pin
*per_pin
;
1704 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1709 mutex_lock(&spec
->pcm_lock
);
1710 pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1711 if (spec
->dyn_pcm_assign
&& pin_idx
< 0) {
1712 /* when dyn_pcm_assign and pcm is not bound to a pin
1713 * skip pin setup and return 0 to make audio playback
1716 intel_not_share_assigned_cvt_nid(codec
, 0, cvt_nid
);
1717 snd_hda_codec_setup_stream(codec
, cvt_nid
,
1718 stream_tag
, 0, format
);
1719 mutex_unlock(&spec
->pcm_lock
);
1723 if (snd_BUG_ON(pin_idx
< 0)) {
1724 mutex_unlock(&spec
->pcm_lock
);
1727 per_pin
= get_pin(spec
, pin_idx
);
1728 pin_nid
= per_pin
->pin_nid
;
1729 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
)) {
1730 /* Verify pin:cvt selections to avoid silent audio after S3.
1731 * After S3, the audio driver restores pin:cvt selections
1732 * but this can happen before gfx is ready and such selection
1733 * is overlooked by HW. Thus multiple pins can share a same
1734 * default convertor and mute control will affect each other,
1735 * which can cause a resumed audio playback become silent
1738 intel_verify_pin_cvt_connect(codec
, per_pin
);
1739 intel_not_share_assigned_cvt(codec
, pin_nid
, per_pin
->mux_idx
);
1742 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1743 /* Todo: add DP1.2 MST audio support later */
1744 snd_hdac_sync_audio_rate(&codec
->bus
->core
, pin_nid
, runtime
->rate
);
1746 non_pcm
= check_non_pcm_per_cvt(codec
, cvt_nid
);
1747 mutex_lock(&per_pin
->lock
);
1748 per_pin
->channels
= substream
->runtime
->channels
;
1749 per_pin
->setup
= true;
1751 hdmi_setup_audio_infoframe(codec
, per_pin
, non_pcm
);
1752 mutex_unlock(&per_pin
->lock
);
1753 if (spec
->dyn_pin_out
) {
1754 pinctl
= snd_hda_codec_read(codec
, pin_nid
, 0,
1755 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
1756 snd_hda_codec_write(codec
, pin_nid
, 0,
1757 AC_VERB_SET_PIN_WIDGET_CONTROL
,
1761 err
= spec
->ops
.setup_stream(codec
, cvt_nid
, pin_nid
,
1762 stream_tag
, format
);
1763 mutex_unlock(&spec
->pcm_lock
);
1767 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream
*hinfo
,
1768 struct hda_codec
*codec
,
1769 struct snd_pcm_substream
*substream
)
1771 snd_hda_codec_cleanup_stream(codec
, hinfo
->nid
);
1775 static int hdmi_pcm_close(struct hda_pcm_stream
*hinfo
,
1776 struct hda_codec
*codec
,
1777 struct snd_pcm_substream
*substream
)
1779 struct hdmi_spec
*spec
= codec
->spec
;
1780 int cvt_idx
, pin_idx
, pcm_idx
;
1781 struct hdmi_spec_per_cvt
*per_cvt
;
1782 struct hdmi_spec_per_pin
*per_pin
;
1786 pcm_idx
= hinfo_to_pcm_index(codec
, hinfo
);
1787 if (snd_BUG_ON(pcm_idx
< 0))
1789 cvt_idx
= cvt_nid_to_cvt_index(codec
, hinfo
->nid
);
1790 if (snd_BUG_ON(cvt_idx
< 0))
1792 per_cvt
= get_cvt(spec
, cvt_idx
);
1794 snd_BUG_ON(!per_cvt
->assigned
);
1795 per_cvt
->assigned
= 0;
1798 mutex_lock(&spec
->pcm_lock
);
1799 snd_hda_spdif_ctls_unassign(codec
, pcm_idx
);
1800 clear_bit(pcm_idx
, &spec
->pcm_in_use
);
1801 pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1802 if (spec
->dyn_pcm_assign
&& pin_idx
< 0) {
1803 mutex_unlock(&spec
->pcm_lock
);
1807 if (snd_BUG_ON(pin_idx
< 0)) {
1808 mutex_unlock(&spec
->pcm_lock
);
1811 per_pin
= get_pin(spec
, pin_idx
);
1813 if (spec
->dyn_pin_out
) {
1814 pinctl
= snd_hda_codec_read(codec
, per_pin
->pin_nid
, 0,
1815 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
1816 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0,
1817 AC_VERB_SET_PIN_WIDGET_CONTROL
,
1821 mutex_lock(&per_pin
->lock
);
1822 per_pin
->chmap_set
= false;
1823 memset(per_pin
->chmap
, 0, sizeof(per_pin
->chmap
));
1825 per_pin
->setup
= false;
1826 per_pin
->channels
= 0;
1827 mutex_unlock(&per_pin
->lock
);
1828 mutex_unlock(&spec
->pcm_lock
);
1834 static const struct hda_pcm_ops generic_ops
= {
1835 .open
= hdmi_pcm_open
,
1836 .close
= hdmi_pcm_close
,
1837 .prepare
= generic_hdmi_playback_pcm_prepare
,
1838 .cleanup
= generic_hdmi_playback_pcm_cleanup
,
1841 static void hdmi_get_chmap(struct hdac_device
*hdac
, int pcm_idx
,
1842 unsigned char *chmap
)
1844 struct hda_codec
*codec
= container_of(hdac
, struct hda_codec
, core
);
1845 struct hdmi_spec
*spec
= codec
->spec
;
1846 struct hdmi_spec_per_pin
*per_pin
= pcm_idx_to_pin(spec
, pcm_idx
);
1848 /* chmap is already set to 0 in caller */
1852 memcpy(chmap
, per_pin
->chmap
, ARRAY_SIZE(per_pin
->chmap
));
1855 static void hdmi_set_chmap(struct hdac_device
*hdac
, int pcm_idx
,
1856 unsigned char *chmap
, int prepared
)
1858 struct hda_codec
*codec
= container_of(hdac
, struct hda_codec
, core
);
1859 struct hdmi_spec
*spec
= codec
->spec
;
1860 struct hdmi_spec_per_pin
*per_pin
= pcm_idx_to_pin(spec
, pcm_idx
);
1862 mutex_lock(&per_pin
->lock
);
1863 per_pin
->chmap_set
= true;
1864 memcpy(per_pin
->chmap
, chmap
, ARRAY_SIZE(per_pin
->chmap
));
1866 hdmi_setup_audio_infoframe(codec
, per_pin
, per_pin
->non_pcm
);
1867 mutex_unlock(&per_pin
->lock
);
1870 static bool is_hdmi_pcm_attached(struct hdac_device
*hdac
, int pcm_idx
)
1872 struct hda_codec
*codec
= container_of(hdac
, struct hda_codec
, core
);
1873 struct hdmi_spec
*spec
= codec
->spec
;
1874 struct hdmi_spec_per_pin
*per_pin
= pcm_idx_to_pin(spec
, pcm_idx
);
1876 return per_pin
? true:false;
1879 static int generic_hdmi_build_pcms(struct hda_codec
*codec
)
1881 struct hdmi_spec
*spec
= codec
->spec
;
1884 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
1885 struct hda_pcm
*info
;
1886 struct hda_pcm_stream
*pstr
;
1888 info
= snd_hda_codec_pcm_new(codec
, "HDMI %d", pin_idx
);
1892 spec
->pcm_rec
[pin_idx
].pcm
= info
;
1894 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
1895 info
->own_chmap
= true;
1897 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
1898 pstr
->substreams
= 1;
1899 pstr
->ops
= generic_ops
;
1900 /* other pstr fields are set in open */
1906 static void free_hdmi_jack_priv(struct snd_jack
*jack
)
1908 struct hdmi_pcm
*pcm
= jack
->private_data
;
1913 static int add_hdmi_jack_kctl(struct hda_codec
*codec
,
1914 struct hdmi_spec
*spec
,
1918 struct snd_jack
*jack
;
1921 err
= snd_jack_new(codec
->card
, name
, SND_JACK_AVOUT
, &jack
,
1926 spec
->pcm_rec
[pcm_idx
].jack
= jack
;
1927 jack
->private_data
= &spec
->pcm_rec
[pcm_idx
];
1928 jack
->private_free
= free_hdmi_jack_priv
;
1932 static int generic_hdmi_build_jack(struct hda_codec
*codec
, int pcm_idx
)
1934 char hdmi_str
[32] = "HDMI/DP";
1935 struct hdmi_spec
*spec
= codec
->spec
;
1936 struct hdmi_spec_per_pin
*per_pin
;
1937 struct hda_jack_tbl
*jack
;
1938 int pcmdev
= get_pcm_rec(spec
, pcm_idx
)->device
;
1943 sprintf(hdmi_str
+ strlen(hdmi_str
), ",pcm=%d", pcmdev
);
1945 if (spec
->dyn_pcm_assign
)
1946 return add_hdmi_jack_kctl(codec
, spec
, pcm_idx
, hdmi_str
);
1948 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1949 /* if !dyn_pcm_assign, it must be non-MST mode.
1950 * This means pcms and pins are statically mapped.
1951 * And pcm_idx is pin_idx.
1953 per_pin
= get_pin(spec
, pcm_idx
);
1954 phantom_jack
= !is_jack_detectable(codec
, per_pin
->pin_nid
);
1956 strncat(hdmi_str
, " Phantom",
1957 sizeof(hdmi_str
) - strlen(hdmi_str
) - 1);
1958 ret
= snd_hda_jack_add_kctl(codec
, per_pin
->pin_nid
, hdmi_str
,
1962 jack
= snd_hda_jack_tbl_get(codec
, per_pin
->pin_nid
);
1965 /* assign jack->jack to pcm_rec[].jack to
1966 * align with dyn_pcm_assign mode
1968 spec
->pcm_rec
[pcm_idx
].jack
= jack
->jack
;
1972 static int generic_hdmi_build_controls(struct hda_codec
*codec
)
1974 struct hdmi_spec
*spec
= codec
->spec
;
1976 int pin_idx
, pcm_idx
;
1979 for (pcm_idx
= 0; pcm_idx
< spec
->pcm_used
; pcm_idx
++) {
1980 err
= generic_hdmi_build_jack(codec
, pcm_idx
);
1984 /* create the spdif for each pcm
1985 * pin will be bound when monitor is connected
1987 if (spec
->dyn_pcm_assign
)
1988 err
= snd_hda_create_dig_out_ctls(codec
,
1989 0, spec
->cvt_nids
[0],
1992 struct hdmi_spec_per_pin
*per_pin
=
1993 get_pin(spec
, pcm_idx
);
1994 err
= snd_hda_create_dig_out_ctls(codec
,
1996 per_pin
->mux_nids
[0],
2001 snd_hda_spdif_ctls_unassign(codec
, pcm_idx
);
2003 /* add control for ELD Bytes */
2004 err
= hdmi_create_eld_ctl(codec
, pcm_idx
,
2005 get_pcm_rec(spec
, pcm_idx
)->device
);
2010 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2011 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2013 hdmi_present_sense(per_pin
, 0);
2016 /* add channel maps */
2017 for (pcm_idx
= 0; pcm_idx
< spec
->pcm_used
; pcm_idx
++) {
2018 struct hda_pcm
*pcm
;
2020 pcm
= get_pcm_rec(spec
, pcm_idx
);
2021 if (!pcm
|| !pcm
->pcm
)
2023 err
= snd_hdac_add_chmap_ctls(pcm
->pcm
, pcm_idx
, &spec
->chmap
);
2031 static int generic_hdmi_init_per_pins(struct hda_codec
*codec
)
2033 struct hdmi_spec
*spec
= codec
->spec
;
2036 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2037 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2039 per_pin
->codec
= codec
;
2040 mutex_init(&per_pin
->lock
);
2041 INIT_DELAYED_WORK(&per_pin
->work
, hdmi_repoll_eld
);
2042 eld_proc_new(per_pin
, pin_idx
);
2047 static int generic_hdmi_init(struct hda_codec
*codec
)
2049 struct hdmi_spec
*spec
= codec
->spec
;
2052 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2053 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2054 hda_nid_t pin_nid
= per_pin
->pin_nid
;
2056 hdmi_init_pin(codec
, pin_nid
);
2057 if (!codec_has_acomp(codec
))
2058 snd_hda_jack_detect_enable_callback(codec
, pin_nid
,
2059 codec
->jackpoll_interval
> 0 ?
2060 jack_callback
: NULL
);
2065 static void hdmi_array_init(struct hdmi_spec
*spec
, int nums
)
2067 snd_array_init(&spec
->pins
, sizeof(struct hdmi_spec_per_pin
), nums
);
2068 snd_array_init(&spec
->cvts
, sizeof(struct hdmi_spec_per_cvt
), nums
);
2071 static void hdmi_array_free(struct hdmi_spec
*spec
)
2073 snd_array_free(&spec
->pins
);
2074 snd_array_free(&spec
->cvts
);
2077 static void generic_hdmi_free(struct hda_codec
*codec
)
2079 struct hdmi_spec
*spec
= codec
->spec
;
2080 int pin_idx
, pcm_idx
;
2082 if (codec_has_acomp(codec
))
2083 snd_hdac_i915_register_notifier(NULL
);
2085 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2086 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2087 cancel_delayed_work_sync(&per_pin
->work
);
2088 eld_proc_free(per_pin
);
2091 for (pcm_idx
= 0; pcm_idx
< spec
->pcm_used
; pcm_idx
++) {
2092 if (spec
->pcm_rec
[pcm_idx
].jack
== NULL
)
2094 if (spec
->dyn_pcm_assign
)
2095 snd_device_free(codec
->card
,
2096 spec
->pcm_rec
[pcm_idx
].jack
);
2098 spec
->pcm_rec
[pcm_idx
].jack
= NULL
;
2101 if (spec
->i915_bound
)
2102 snd_hdac_i915_exit(&codec
->bus
->core
);
2103 hdmi_array_free(spec
);
2108 static int generic_hdmi_resume(struct hda_codec
*codec
)
2110 struct hdmi_spec
*spec
= codec
->spec
;
2113 codec
->patch_ops
.init(codec
);
2114 regcache_sync(codec
->core
.regmap
);
2116 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2117 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2118 hdmi_present_sense(per_pin
, 1);
2124 static const struct hda_codec_ops generic_hdmi_patch_ops
= {
2125 .init
= generic_hdmi_init
,
2126 .free
= generic_hdmi_free
,
2127 .build_pcms
= generic_hdmi_build_pcms
,
2128 .build_controls
= generic_hdmi_build_controls
,
2129 .unsol_event
= hdmi_unsol_event
,
2131 .resume
= generic_hdmi_resume
,
2135 static const struct hdmi_ops generic_standard_hdmi_ops
= {
2136 .pin_get_eld
= snd_hdmi_get_eld
,
2137 .pin_setup_infoframe
= hdmi_pin_setup_infoframe
,
2138 .pin_hbr_setup
= hdmi_pin_hbr_setup
,
2139 .setup_stream
= hdmi_setup_stream
,
2142 static void intel_haswell_fixup_connect_list(struct hda_codec
*codec
,
2145 struct hdmi_spec
*spec
= codec
->spec
;
2149 nconns
= snd_hda_get_connections(codec
, nid
, conns
, ARRAY_SIZE(conns
));
2150 if (nconns
== spec
->num_cvts
&&
2151 !memcmp(conns
, spec
->cvt_nids
, spec
->num_cvts
* sizeof(hda_nid_t
)))
2154 /* override pins connection list */
2155 codec_dbg(codec
, "hdmi: haswell: override pin connection 0x%x\n", nid
);
2156 snd_hda_override_conn_list(codec
, nid
, spec
->num_cvts
, spec
->cvt_nids
);
2159 #define INTEL_VENDOR_NID 0x08
2160 #define INTEL_GET_VENDOR_VERB 0xf81
2161 #define INTEL_SET_VENDOR_VERB 0x781
2162 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2163 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2165 static void intel_haswell_enable_all_pins(struct hda_codec
*codec
,
2168 unsigned int vendor_param
;
2170 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2171 INTEL_GET_VENDOR_VERB
, 0);
2172 if (vendor_param
== -1 || vendor_param
& INTEL_EN_ALL_PIN_CVTS
)
2175 vendor_param
|= INTEL_EN_ALL_PIN_CVTS
;
2176 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2177 INTEL_SET_VENDOR_VERB
, vendor_param
);
2178 if (vendor_param
== -1)
2182 snd_hda_codec_update_widgets(codec
);
2185 static void intel_haswell_fixup_enable_dp12(struct hda_codec
*codec
)
2187 unsigned int vendor_param
;
2189 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2190 INTEL_GET_VENDOR_VERB
, 0);
2191 if (vendor_param
== -1 || vendor_param
& INTEL_EN_DP12
)
2194 /* enable DP1.2 mode */
2195 vendor_param
|= INTEL_EN_DP12
;
2196 snd_hdac_regmap_add_vendor_verb(&codec
->core
, INTEL_SET_VENDOR_VERB
);
2197 snd_hda_codec_write_cache(codec
, INTEL_VENDOR_NID
, 0,
2198 INTEL_SET_VENDOR_VERB
, vendor_param
);
2201 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2202 * Otherwise you may get severe h/w communication errors.
2204 static void haswell_set_power_state(struct hda_codec
*codec
, hda_nid_t fg
,
2205 unsigned int power_state
)
2207 if (power_state
== AC_PWRST_D0
) {
2208 intel_haswell_enable_all_pins(codec
, false);
2209 intel_haswell_fixup_enable_dp12(codec
);
2212 snd_hda_codec_read(codec
, fg
, 0, AC_VERB_SET_POWER_STATE
, power_state
);
2213 snd_hda_codec_set_power_to_all(codec
, fg
, power_state
);
2216 static void intel_pin_eld_notify(void *audio_ptr
, int port
)
2218 struct hda_codec
*codec
= audio_ptr
;
2219 int pin_nid
= port
+ 0x04;
2221 /* we assume only from port-B to port-D */
2222 if (port
< 1 || port
> 3)
2225 /* skip notification during system suspend (but not in runtime PM);
2226 * the state will be updated at resume
2228 if (snd_power_get_state(codec
->card
) != SNDRV_CTL_POWER_D0
)
2230 /* ditto during suspend/resume process itself */
2231 if (atomic_read(&(codec
)->core
.in_pm
))
2234 check_presence_and_report(codec
, pin_nid
);
2237 static int patch_generic_hdmi(struct hda_codec
*codec
)
2239 struct hdmi_spec
*spec
;
2241 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
2245 spec
->ops
= generic_standard_hdmi_ops
;
2246 mutex_init(&spec
->pcm_lock
);
2247 snd_hdac_register_chmap_ops(&codec
->core
, &spec
->chmap
);
2249 spec
->chmap
.ops
.get_chmap
= hdmi_get_chmap
;
2250 spec
->chmap
.ops
.set_chmap
= hdmi_set_chmap
;
2251 spec
->chmap
.ops
.is_pcm_attached
= is_hdmi_pcm_attached
;
2254 hdmi_array_init(spec
, 4);
2256 #ifdef CONFIG_SND_HDA_I915
2257 /* Try to bind with i915 for Intel HSW+ codecs (if not done yet) */
2258 if ((codec
->core
.vendor_id
>> 16) == 0x8086 &&
2259 is_haswell_plus(codec
)) {
2260 if (!codec
->bus
->core
.audio_component
)
2261 if (!snd_hdac_i915_init(&codec
->bus
->core
))
2262 spec
->i915_bound
= true;
2263 /* use i915 audio component notifier for hotplug */
2264 if (codec
->bus
->core
.audio_component
)
2265 spec
->use_acomp_notifier
= true;
2269 if (is_haswell_plus(codec
)) {
2270 intel_haswell_enable_all_pins(codec
, true);
2271 intel_haswell_fixup_enable_dp12(codec
);
2274 /* For Valleyview/Cherryview, only the display codec is in the display
2275 * power well and can use link_power ops to request/release the power.
2276 * For Haswell/Broadwell, the controller is also in the power well and
2277 * can cover the codec power request, and so need not set this flag.
2278 * For previous platforms, there is no such power well feature.
2280 if (is_valleyview_plus(codec
) || is_skylake(codec
) ||
2282 codec
->core
.link_power_control
= 1;
2284 if (hdmi_parse_codec(codec
) < 0) {
2285 if (spec
->i915_bound
)
2286 snd_hdac_i915_exit(&codec
->bus
->core
);
2291 codec
->patch_ops
= generic_hdmi_patch_ops
;
2292 if (is_haswell_plus(codec
)) {
2293 codec
->patch_ops
.set_power_state
= haswell_set_power_state
;
2294 codec
->dp_mst
= true;
2297 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2298 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
))
2299 codec
->auto_runtime_pm
= 1;
2301 generic_hdmi_init_per_pins(codec
);
2304 if (codec_has_acomp(codec
)) {
2305 codec
->depop_delay
= 0;
2306 spec
->i915_audio_ops
.audio_ptr
= codec
;
2307 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2308 * will call pin_eld_notify with using audio_ptr pointer
2309 * We need make sure audio_ptr is really setup
2312 spec
->i915_audio_ops
.pin_eld_notify
= intel_pin_eld_notify
;
2313 snd_hdac_i915_register_notifier(&spec
->i915_audio_ops
);
2316 WARN_ON(spec
->dyn_pcm_assign
&& !codec_has_acomp(codec
));
2321 * Shared non-generic implementations
2324 static int simple_playback_build_pcms(struct hda_codec
*codec
)
2326 struct hdmi_spec
*spec
= codec
->spec
;
2327 struct hda_pcm
*info
;
2329 struct hda_pcm_stream
*pstr
;
2330 struct hdmi_spec_per_cvt
*per_cvt
;
2332 per_cvt
= get_cvt(spec
, 0);
2333 chans
= get_wcaps(codec
, per_cvt
->cvt_nid
);
2334 chans
= get_wcaps_channels(chans
);
2336 info
= snd_hda_codec_pcm_new(codec
, "HDMI 0");
2339 spec
->pcm_rec
[0].pcm
= info
;
2340 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
2341 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
2342 *pstr
= spec
->pcm_playback
;
2343 pstr
->nid
= per_cvt
->cvt_nid
;
2344 if (pstr
->channels_max
<= 2 && chans
&& chans
<= 16)
2345 pstr
->channels_max
= chans
;
2350 /* unsolicited event for jack sensing */
2351 static void simple_hdmi_unsol_event(struct hda_codec
*codec
,
2354 snd_hda_jack_set_dirty_all(codec
);
2355 snd_hda_jack_report_sync(codec
);
2358 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2359 * as long as spec->pins[] is set correctly
2361 #define simple_hdmi_build_jack generic_hdmi_build_jack
2363 static int simple_playback_build_controls(struct hda_codec
*codec
)
2365 struct hdmi_spec
*spec
= codec
->spec
;
2366 struct hdmi_spec_per_cvt
*per_cvt
;
2369 per_cvt
= get_cvt(spec
, 0);
2370 err
= snd_hda_create_dig_out_ctls(codec
, per_cvt
->cvt_nid
,
2375 return simple_hdmi_build_jack(codec
, 0);
2378 static int simple_playback_init(struct hda_codec
*codec
)
2380 struct hdmi_spec
*spec
= codec
->spec
;
2381 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, 0);
2382 hda_nid_t pin
= per_pin
->pin_nid
;
2384 snd_hda_codec_write(codec
, pin
, 0,
2385 AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
);
2386 /* some codecs require to unmute the pin */
2387 if (get_wcaps(codec
, pin
) & AC_WCAP_OUT_AMP
)
2388 snd_hda_codec_write(codec
, pin
, 0, AC_VERB_SET_AMP_GAIN_MUTE
,
2390 snd_hda_jack_detect_enable(codec
, pin
);
2394 static void simple_playback_free(struct hda_codec
*codec
)
2396 struct hdmi_spec
*spec
= codec
->spec
;
2398 hdmi_array_free(spec
);
2403 * Nvidia specific implementations
2406 #define Nv_VERB_SET_Channel_Allocation 0xF79
2407 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2408 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2409 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2411 #define nvhdmi_master_con_nid_7x 0x04
2412 #define nvhdmi_master_pin_nid_7x 0x05
2414 static const hda_nid_t nvhdmi_con_nids_7x
[4] = {
2415 /*front, rear, clfe, rear_surr */
2419 static const struct hda_verb nvhdmi_basic_init_7x_2ch
[] = {
2420 /* set audio protect on */
2421 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
2422 /* enable digital output on pin widget */
2423 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2427 static const struct hda_verb nvhdmi_basic_init_7x_8ch
[] = {
2428 /* set audio protect on */
2429 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
2430 /* enable digital output on pin widget */
2431 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2432 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2433 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2434 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2435 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2439 #ifdef LIMITED_RATE_FMT_SUPPORT
2440 /* support only the safe format and rate */
2441 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2442 #define SUPPORTED_MAXBPS 16
2443 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2445 /* support all rates and formats */
2446 #define SUPPORTED_RATES \
2447 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2448 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2449 SNDRV_PCM_RATE_192000)
2450 #define SUPPORTED_MAXBPS 24
2451 #define SUPPORTED_FORMATS \
2452 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2455 static int nvhdmi_7x_init_2ch(struct hda_codec
*codec
)
2457 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x_2ch
);
2461 static int nvhdmi_7x_init_8ch(struct hda_codec
*codec
)
2463 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x_8ch
);
2467 static unsigned int channels_2_6_8
[] = {
2471 static unsigned int channels_2_8
[] = {
2475 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels
= {
2476 .count
= ARRAY_SIZE(channels_2_6_8
),
2477 .list
= channels_2_6_8
,
2481 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels
= {
2482 .count
= ARRAY_SIZE(channels_2_8
),
2483 .list
= channels_2_8
,
2487 static int simple_playback_pcm_open(struct hda_pcm_stream
*hinfo
,
2488 struct hda_codec
*codec
,
2489 struct snd_pcm_substream
*substream
)
2491 struct hdmi_spec
*spec
= codec
->spec
;
2492 struct snd_pcm_hw_constraint_list
*hw_constraints_channels
= NULL
;
2494 switch (codec
->preset
->vendor_id
) {
2499 hw_constraints_channels
= &hw_constraints_2_8_channels
;
2502 hw_constraints_channels
= &hw_constraints_2_6_8_channels
;
2508 if (hw_constraints_channels
!= NULL
) {
2509 snd_pcm_hw_constraint_list(substream
->runtime
, 0,
2510 SNDRV_PCM_HW_PARAM_CHANNELS
,
2511 hw_constraints_channels
);
2513 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
2514 SNDRV_PCM_HW_PARAM_CHANNELS
, 2);
2517 return snd_hda_multi_out_dig_open(codec
, &spec
->multiout
);
2520 static int simple_playback_pcm_close(struct hda_pcm_stream
*hinfo
,
2521 struct hda_codec
*codec
,
2522 struct snd_pcm_substream
*substream
)
2524 struct hdmi_spec
*spec
= codec
->spec
;
2525 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
2528 static int simple_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
2529 struct hda_codec
*codec
,
2530 unsigned int stream_tag
,
2531 unsigned int format
,
2532 struct snd_pcm_substream
*substream
)
2534 struct hdmi_spec
*spec
= codec
->spec
;
2535 return snd_hda_multi_out_dig_prepare(codec
, &spec
->multiout
,
2536 stream_tag
, format
, substream
);
2539 static const struct hda_pcm_stream simple_pcm_playback
= {
2544 .open
= simple_playback_pcm_open
,
2545 .close
= simple_playback_pcm_close
,
2546 .prepare
= simple_playback_pcm_prepare
2550 static const struct hda_codec_ops simple_hdmi_patch_ops
= {
2551 .build_controls
= simple_playback_build_controls
,
2552 .build_pcms
= simple_playback_build_pcms
,
2553 .init
= simple_playback_init
,
2554 .free
= simple_playback_free
,
2555 .unsol_event
= simple_hdmi_unsol_event
,
2558 static int patch_simple_hdmi(struct hda_codec
*codec
,
2559 hda_nid_t cvt_nid
, hda_nid_t pin_nid
)
2561 struct hdmi_spec
*spec
;
2562 struct hdmi_spec_per_cvt
*per_cvt
;
2563 struct hdmi_spec_per_pin
*per_pin
;
2565 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
2570 hdmi_array_init(spec
, 1);
2572 spec
->multiout
.num_dacs
= 0; /* no analog */
2573 spec
->multiout
.max_channels
= 2;
2574 spec
->multiout
.dig_out_nid
= cvt_nid
;
2577 per_pin
= snd_array_new(&spec
->pins
);
2578 per_cvt
= snd_array_new(&spec
->cvts
);
2579 if (!per_pin
|| !per_cvt
) {
2580 simple_playback_free(codec
);
2583 per_cvt
->cvt_nid
= cvt_nid
;
2584 per_pin
->pin_nid
= pin_nid
;
2585 spec
->pcm_playback
= simple_pcm_playback
;
2587 codec
->patch_ops
= simple_hdmi_patch_ops
;
2592 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec
*codec
,
2595 unsigned int chanmask
;
2596 int chan
= channels
? (channels
- 1) : 1;
2615 /* Set the audio infoframe channel allocation and checksum fields. The
2616 * channel count is computed implicitly by the hardware. */
2617 snd_hda_codec_write(codec
, 0x1, 0,
2618 Nv_VERB_SET_Channel_Allocation
, chanmask
);
2620 snd_hda_codec_write(codec
, 0x1, 0,
2621 Nv_VERB_SET_Info_Frame_Checksum
,
2622 (0x71 - chan
- chanmask
));
2625 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream
*hinfo
,
2626 struct hda_codec
*codec
,
2627 struct snd_pcm_substream
*substream
)
2629 struct hdmi_spec
*spec
= codec
->spec
;
2632 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
,
2633 0, AC_VERB_SET_CHANNEL_STREAMID
, 0);
2634 for (i
= 0; i
< 4; i
++) {
2635 /* set the stream id */
2636 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
2637 AC_VERB_SET_CHANNEL_STREAMID
, 0);
2638 /* set the stream format */
2639 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
2640 AC_VERB_SET_STREAM_FORMAT
, 0);
2643 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2644 * streams are disabled. */
2645 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, 8);
2647 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
2650 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream
*hinfo
,
2651 struct hda_codec
*codec
,
2652 unsigned int stream_tag
,
2653 unsigned int format
,
2654 struct snd_pcm_substream
*substream
)
2657 unsigned int dataDCC2
, channel_id
;
2659 struct hdmi_spec
*spec
= codec
->spec
;
2660 struct hda_spdif_out
*spdif
;
2661 struct hdmi_spec_per_cvt
*per_cvt
;
2663 mutex_lock(&codec
->spdif_mutex
);
2664 per_cvt
= get_cvt(spec
, 0);
2665 spdif
= snd_hda_spdif_out_of_nid(codec
, per_cvt
->cvt_nid
);
2667 chs
= substream
->runtime
->channels
;
2671 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2672 if (codec
->spdif_status_reset
&& (spdif
->ctls
& AC_DIG1_ENABLE
))
2673 snd_hda_codec_write(codec
,
2674 nvhdmi_master_con_nid_7x
,
2676 AC_VERB_SET_DIGI_CONVERT_1
,
2677 spdif
->ctls
& ~AC_DIG1_ENABLE
& 0xff);
2679 /* set the stream id */
2680 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
2681 AC_VERB_SET_CHANNEL_STREAMID
, (stream_tag
<< 4) | 0x0);
2683 /* set the stream format */
2684 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
2685 AC_VERB_SET_STREAM_FORMAT
, format
);
2687 /* turn on again (if needed) */
2688 /* enable and set the channel status audio/data flag */
2689 if (codec
->spdif_status_reset
&& (spdif
->ctls
& AC_DIG1_ENABLE
)) {
2690 snd_hda_codec_write(codec
,
2691 nvhdmi_master_con_nid_7x
,
2693 AC_VERB_SET_DIGI_CONVERT_1
,
2694 spdif
->ctls
& 0xff);
2695 snd_hda_codec_write(codec
,
2696 nvhdmi_master_con_nid_7x
,
2698 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
2701 for (i
= 0; i
< 4; i
++) {
2707 /* turn off SPDIF once;
2708 *otherwise the IEC958 bits won't be updated
2710 if (codec
->spdif_status_reset
&&
2711 (spdif
->ctls
& AC_DIG1_ENABLE
))
2712 snd_hda_codec_write(codec
,
2713 nvhdmi_con_nids_7x
[i
],
2715 AC_VERB_SET_DIGI_CONVERT_1
,
2716 spdif
->ctls
& ~AC_DIG1_ENABLE
& 0xff);
2717 /* set the stream id */
2718 snd_hda_codec_write(codec
,
2719 nvhdmi_con_nids_7x
[i
],
2721 AC_VERB_SET_CHANNEL_STREAMID
,
2722 (stream_tag
<< 4) | channel_id
);
2723 /* set the stream format */
2724 snd_hda_codec_write(codec
,
2725 nvhdmi_con_nids_7x
[i
],
2727 AC_VERB_SET_STREAM_FORMAT
,
2729 /* turn on again (if needed) */
2730 /* enable and set the channel status audio/data flag */
2731 if (codec
->spdif_status_reset
&&
2732 (spdif
->ctls
& AC_DIG1_ENABLE
)) {
2733 snd_hda_codec_write(codec
,
2734 nvhdmi_con_nids_7x
[i
],
2736 AC_VERB_SET_DIGI_CONVERT_1
,
2737 spdif
->ctls
& 0xff);
2738 snd_hda_codec_write(codec
,
2739 nvhdmi_con_nids_7x
[i
],
2741 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
2745 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, chs
);
2747 mutex_unlock(&codec
->spdif_mutex
);
2751 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x
= {
2755 .nid
= nvhdmi_master_con_nid_7x
,
2756 .rates
= SUPPORTED_RATES
,
2757 .maxbps
= SUPPORTED_MAXBPS
,
2758 .formats
= SUPPORTED_FORMATS
,
2760 .open
= simple_playback_pcm_open
,
2761 .close
= nvhdmi_8ch_7x_pcm_close
,
2762 .prepare
= nvhdmi_8ch_7x_pcm_prepare
2766 static int patch_nvhdmi_2ch(struct hda_codec
*codec
)
2768 struct hdmi_spec
*spec
;
2769 int err
= patch_simple_hdmi(codec
, nvhdmi_master_con_nid_7x
,
2770 nvhdmi_master_pin_nid_7x
);
2774 codec
->patch_ops
.init
= nvhdmi_7x_init_2ch
;
2775 /* override the PCM rates, etc, as the codec doesn't give full list */
2777 spec
->pcm_playback
.rates
= SUPPORTED_RATES
;
2778 spec
->pcm_playback
.maxbps
= SUPPORTED_MAXBPS
;
2779 spec
->pcm_playback
.formats
= SUPPORTED_FORMATS
;
2783 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec
*codec
)
2785 struct hdmi_spec
*spec
= codec
->spec
;
2786 int err
= simple_playback_build_pcms(codec
);
2788 struct hda_pcm
*info
= get_pcm_rec(spec
, 0);
2789 info
->own_chmap
= true;
2794 static int nvhdmi_7x_8ch_build_controls(struct hda_codec
*codec
)
2796 struct hdmi_spec
*spec
= codec
->spec
;
2797 struct hda_pcm
*info
;
2798 struct snd_pcm_chmap
*chmap
;
2801 err
= simple_playback_build_controls(codec
);
2805 /* add channel maps */
2806 info
= get_pcm_rec(spec
, 0);
2807 err
= snd_pcm_add_chmap_ctls(info
->pcm
,
2808 SNDRV_PCM_STREAM_PLAYBACK
,
2809 snd_pcm_alt_chmaps
, 8, 0, &chmap
);
2812 switch (codec
->preset
->vendor_id
) {
2817 chmap
->channel_mask
= (1U << 2) | (1U << 8);
2820 chmap
->channel_mask
= (1U << 2) | (1U << 6) | (1U << 8);
2825 static int patch_nvhdmi_8ch_7x(struct hda_codec
*codec
)
2827 struct hdmi_spec
*spec
;
2828 int err
= patch_nvhdmi_2ch(codec
);
2832 spec
->multiout
.max_channels
= 8;
2833 spec
->pcm_playback
= nvhdmi_pcm_playback_8ch_7x
;
2834 codec
->patch_ops
.init
= nvhdmi_7x_init_8ch
;
2835 codec
->patch_ops
.build_pcms
= nvhdmi_7x_8ch_build_pcms
;
2836 codec
->patch_ops
.build_controls
= nvhdmi_7x_8ch_build_controls
;
2838 /* Initialize the audio infoframe channel mask and checksum to something
2840 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, 8);
2846 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2850 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap
*chmap
,
2851 struct hdac_cea_channel_speaker_allocation
*cap
, int channels
)
2853 if (cap
->ca_index
== 0x00 && channels
== 2)
2854 return SNDRV_CTL_TLVT_CHMAP_FIXED
;
2856 /* If the speaker allocation matches the channel count, it is OK. */
2857 if (cap
->channels
!= channels
)
2860 /* all channels are remappable freely */
2861 return SNDRV_CTL_TLVT_CHMAP_VAR
;
2864 static int nvhdmi_chmap_validate(struct hdac_chmap
*chmap
,
2865 int ca
, int chs
, unsigned char *map
)
2867 if (ca
== 0x00 && (map
[0] != SNDRV_CHMAP_FL
|| map
[1] != SNDRV_CHMAP_FR
))
2873 static int patch_nvhdmi(struct hda_codec
*codec
)
2875 struct hdmi_spec
*spec
;
2878 err
= patch_generic_hdmi(codec
);
2883 spec
->dyn_pin_out
= true;
2885 spec
->chmap
.ops
.chmap_cea_alloc_validate_get_type
=
2886 nvhdmi_chmap_cea_alloc_validate_get_type
;
2887 spec
->chmap
.ops
.chmap_validate
= nvhdmi_chmap_validate
;
2893 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2894 * accessed using vendor-defined verbs. These registers can be used for
2895 * interoperability between the HDA and HDMI drivers.
2898 /* Audio Function Group node */
2899 #define NVIDIA_AFG_NID 0x01
2902 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2903 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2904 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2905 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2906 * additional bit (at position 30) to signal the validity of the format.
2908 * | 31 | 30 | 29 16 | 15 0 |
2909 * +---------+-------+--------+--------+
2910 * | TRIGGER | VALID | UNUSED | FORMAT |
2911 * +-----------------------------------|
2913 * Note that for the trigger bit to take effect it needs to change value
2914 * (i.e. it needs to be toggled).
2916 #define NVIDIA_GET_SCRATCH0 0xfa6
2917 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2918 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2919 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2920 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2921 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2922 #define NVIDIA_SCRATCH_VALID (1 << 6)
2924 #define NVIDIA_GET_SCRATCH1 0xfab
2925 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2926 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2927 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2928 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2931 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2932 * the format is invalidated so that the HDMI codec can be disabled.
2934 static void tegra_hdmi_set_format(struct hda_codec
*codec
, unsigned int format
)
2938 /* bits [31:30] contain the trigger and valid bits */
2939 value
= snd_hda_codec_read(codec
, NVIDIA_AFG_NID
, 0,
2940 NVIDIA_GET_SCRATCH0
, 0);
2941 value
= (value
>> 24) & 0xff;
2943 /* bits [15:0] are used to store the HDA format */
2944 snd_hda_codec_write(codec
, NVIDIA_AFG_NID
, 0,
2945 NVIDIA_SET_SCRATCH0_BYTE0
,
2946 (format
>> 0) & 0xff);
2947 snd_hda_codec_write(codec
, NVIDIA_AFG_NID
, 0,
2948 NVIDIA_SET_SCRATCH0_BYTE1
,
2949 (format
>> 8) & 0xff);
2951 /* bits [16:24] are unused */
2952 snd_hda_codec_write(codec
, NVIDIA_AFG_NID
, 0,
2953 NVIDIA_SET_SCRATCH0_BYTE2
, 0);
2956 * Bit 30 signals that the data is valid and hence that HDMI audio can
2960 value
&= ~NVIDIA_SCRATCH_VALID
;
2962 value
|= NVIDIA_SCRATCH_VALID
;
2965 * Whenever the trigger bit is toggled, an interrupt is raised in the
2966 * HDMI codec. The HDMI driver will use that as trigger to update its
2969 value
^= NVIDIA_SCRATCH_TRIGGER
;
2971 snd_hda_codec_write(codec
, NVIDIA_AFG_NID
, 0,
2972 NVIDIA_SET_SCRATCH0_BYTE3
, value
);
2975 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream
*hinfo
,
2976 struct hda_codec
*codec
,
2977 unsigned int stream_tag
,
2978 unsigned int format
,
2979 struct snd_pcm_substream
*substream
)
2983 err
= generic_hdmi_playback_pcm_prepare(hinfo
, codec
, stream_tag
,
2988 /* notify the HDMI codec of the format change */
2989 tegra_hdmi_set_format(codec
, format
);
2994 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream
*hinfo
,
2995 struct hda_codec
*codec
,
2996 struct snd_pcm_substream
*substream
)
2998 /* invalidate the format in the HDMI codec */
2999 tegra_hdmi_set_format(codec
, 0);
3001 return generic_hdmi_playback_pcm_cleanup(hinfo
, codec
, substream
);
3004 static struct hda_pcm
*hda_find_pcm_by_type(struct hda_codec
*codec
, int type
)
3006 struct hdmi_spec
*spec
= codec
->spec
;
3009 for (i
= 0; i
< spec
->num_pins
; i
++) {
3010 struct hda_pcm
*pcm
= get_pcm_rec(spec
, i
);
3012 if (pcm
->pcm_type
== type
)
3019 static int tegra_hdmi_build_pcms(struct hda_codec
*codec
)
3021 struct hda_pcm_stream
*stream
;
3022 struct hda_pcm
*pcm
;
3025 err
= generic_hdmi_build_pcms(codec
);
3029 pcm
= hda_find_pcm_by_type(codec
, HDA_PCM_TYPE_HDMI
);
3034 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3035 * codec about format changes.
3037 stream
= &pcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
3038 stream
->ops
.prepare
= tegra_hdmi_pcm_prepare
;
3039 stream
->ops
.cleanup
= tegra_hdmi_pcm_cleanup
;
3044 static int patch_tegra_hdmi(struct hda_codec
*codec
)
3048 err
= patch_generic_hdmi(codec
);
3052 codec
->patch_ops
.build_pcms
= tegra_hdmi_build_pcms
;
3058 * ATI/AMD-specific implementations
3061 #define is_amdhdmi_rev3_or_later(codec) \
3062 ((codec)->core.vendor_id == 0x1002aa01 && \
3063 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3064 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3066 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3067 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3068 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3069 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3070 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3071 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3072 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3073 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3074 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3075 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3076 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3077 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3078 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3079 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3080 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3081 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3082 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3083 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3084 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3085 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3086 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3087 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3088 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3089 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3090 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3092 /* AMD specific HDA cvt verbs */
3093 #define ATI_VERB_SET_RAMP_RATE 0x770
3094 #define ATI_VERB_GET_RAMP_RATE 0xf70
3096 #define ATI_OUT_ENABLE 0x1
3098 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3099 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3101 #define ATI_HBR_CAPABLE 0x01
3102 #define ATI_HBR_ENABLE 0x10
3104 static int atihdmi_pin_get_eld(struct hda_codec
*codec
, hda_nid_t nid
,
3105 unsigned char *buf
, int *eld_size
)
3107 /* call hda_eld.c ATI/AMD-specific function */
3108 return snd_hdmi_get_eld_ati(codec
, nid
, buf
, eld_size
,
3109 is_amdhdmi_rev3_or_later(codec
));
3112 static void atihdmi_pin_setup_infoframe(struct hda_codec
*codec
, hda_nid_t pin_nid
, int ca
,
3113 int active_channels
, int conn_type
)
3115 snd_hda_codec_write(codec
, pin_nid
, 0, ATI_VERB_SET_CHANNEL_ALLOCATION
, ca
);
3118 static int atihdmi_paired_swap_fc_lfe(int pos
)
3121 * ATI/AMD have automatic FC/LFE swap built-in
3122 * when in pairwise mapping mode.
3126 /* see channel_allocations[].speakers[] */
3135 static int atihdmi_paired_chmap_validate(struct hdac_chmap
*chmap
,
3136 int ca
, int chs
, unsigned char *map
)
3138 struct hdac_cea_channel_speaker_allocation
*cap
;
3141 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3143 cap
= snd_hdac_get_ch_alloc_from_ca(ca
);
3144 for (i
= 0; i
< chs
; ++i
) {
3145 int mask
= snd_hdac_chmap_to_spk_mask(map
[i
]);
3147 bool companion_ok
= false;
3152 for (j
= 0 + i
% 2; j
< 8; j
+= 2) {
3153 int chan_idx
= 7 - atihdmi_paired_swap_fc_lfe(j
);
3154 if (cap
->speakers
[chan_idx
] == mask
) {
3155 /* channel is in a supported position */
3158 if (i
% 2 == 0 && i
+ 1 < chs
) {
3159 /* even channel, check the odd companion */
3160 int comp_chan_idx
= 7 - atihdmi_paired_swap_fc_lfe(j
+ 1);
3161 int comp_mask_req
= snd_hdac_chmap_to_spk_mask(map
[i
+1]);
3162 int comp_mask_act
= cap
->speakers
[comp_chan_idx
];
3164 if (comp_mask_req
== comp_mask_act
)
3165 companion_ok
= true;
3177 i
++; /* companion channel already checked */
3183 static int atihdmi_pin_set_slot_channel(struct hdac_device
*hdac
,
3184 hda_nid_t pin_nid
, int hdmi_slot
, int stream_channel
)
3186 struct hda_codec
*codec
= container_of(hdac
, struct hda_codec
, core
);
3188 int ati_channel_setup
= 0;
3193 if (!has_amd_full_remap_support(codec
)) {
3194 hdmi_slot
= atihdmi_paired_swap_fc_lfe(hdmi_slot
);
3196 /* In case this is an odd slot but without stream channel, do not
3197 * disable the slot since the corresponding even slot could have a
3198 * channel. In case neither have a channel, the slot pair will be
3199 * disabled when this function is called for the even slot. */
3200 if (hdmi_slot
% 2 != 0 && stream_channel
== 0xf)
3203 hdmi_slot
-= hdmi_slot
% 2;
3205 if (stream_channel
!= 0xf)
3206 stream_channel
-= stream_channel
% 2;
3209 verb
= ATI_VERB_SET_MULTICHANNEL_01
+ hdmi_slot
/2 + (hdmi_slot
% 2) * 0x00e;
3211 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3213 if (stream_channel
!= 0xf)
3214 ati_channel_setup
= (stream_channel
<< 4) | ATI_OUT_ENABLE
;
3216 return snd_hda_codec_write(codec
, pin_nid
, 0, verb
, ati_channel_setup
);
3219 static int atihdmi_pin_get_slot_channel(struct hdac_device
*hdac
,
3220 hda_nid_t pin_nid
, int asp_slot
)
3222 struct hda_codec
*codec
= container_of(hdac
, struct hda_codec
, core
);
3223 bool was_odd
= false;
3224 int ati_asp_slot
= asp_slot
;
3226 int ati_channel_setup
;
3231 if (!has_amd_full_remap_support(codec
)) {
3232 ati_asp_slot
= atihdmi_paired_swap_fc_lfe(asp_slot
);
3233 if (ati_asp_slot
% 2 != 0) {
3239 verb
= ATI_VERB_GET_MULTICHANNEL_01
+ ati_asp_slot
/2 + (ati_asp_slot
% 2) * 0x00e;
3241 ati_channel_setup
= snd_hda_codec_read(codec
, pin_nid
, 0, verb
, 0);
3243 if (!(ati_channel_setup
& ATI_OUT_ENABLE
))
3246 return ((ati_channel_setup
& 0xf0) >> 4) + !!was_odd
;
3249 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3250 struct hdac_chmap
*chmap
,
3251 struct hdac_cea_channel_speaker_allocation
*cap
,
3257 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3258 * we need to take that into account (a single channel may take 2
3259 * channel slots if we need to carry a silent channel next to it).
3260 * On Rev3+ AMD codecs this function is not used.
3264 /* We only produce even-numbered channel count TLVs */
3265 if ((channels
% 2) != 0)
3268 for (c
= 0; c
< 7; c
+= 2) {
3269 if (cap
->speakers
[c
] || cap
->speakers
[c
+1])
3273 if (chanpairs
* 2 != channels
)
3276 return SNDRV_CTL_TLVT_CHMAP_PAIRED
;
3279 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap
*hchmap
,
3280 struct hdac_cea_channel_speaker_allocation
*cap
,
3281 unsigned int *chmap
, int channels
)
3283 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3287 for (c
= 7; c
>= 0; c
--) {
3288 int chan
= 7 - atihdmi_paired_swap_fc_lfe(7 - c
);
3289 int spk
= cap
->speakers
[chan
];
3291 /* add N/A channel if the companion channel is occupied */
3292 if (cap
->speakers
[chan
+ (chan
% 2 ? -1 : 1)])
3293 chmap
[count
++] = SNDRV_CHMAP_NA
;
3298 chmap
[count
++] = snd_hdac_spk_to_chmap(spk
);
3301 WARN_ON(count
!= channels
);
3304 static int atihdmi_pin_hbr_setup(struct hda_codec
*codec
, hda_nid_t pin_nid
,
3307 int hbr_ctl
, hbr_ctl_new
;
3309 hbr_ctl
= snd_hda_codec_read(codec
, pin_nid
, 0, ATI_VERB_GET_HBR_CONTROL
, 0);
3310 if (hbr_ctl
>= 0 && (hbr_ctl
& ATI_HBR_CAPABLE
)) {
3312 hbr_ctl_new
= hbr_ctl
| ATI_HBR_ENABLE
;
3314 hbr_ctl_new
= hbr_ctl
& ~ATI_HBR_ENABLE
;
3317 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3319 hbr_ctl
== hbr_ctl_new
? "" : "new-",
3322 if (hbr_ctl
!= hbr_ctl_new
)
3323 snd_hda_codec_write(codec
, pin_nid
, 0,
3324 ATI_VERB_SET_HBR_CONTROL
,
3333 static int atihdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
3334 hda_nid_t pin_nid
, u32 stream_tag
, int format
)
3337 if (is_amdhdmi_rev3_or_later(codec
)) {
3338 int ramp_rate
= 180; /* default as per AMD spec */
3339 /* disable ramp-up/down for non-pcm as per AMD spec */
3340 if (format
& AC_FMT_TYPE_NON_PCM
)
3343 snd_hda_codec_write(codec
, cvt_nid
, 0, ATI_VERB_SET_RAMP_RATE
, ramp_rate
);
3346 return hdmi_setup_stream(codec
, cvt_nid
, pin_nid
, stream_tag
, format
);
3350 static int atihdmi_init(struct hda_codec
*codec
)
3352 struct hdmi_spec
*spec
= codec
->spec
;
3355 err
= generic_hdmi_init(codec
);
3360 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
3361 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
3363 /* make sure downmix information in infoframe is zero */
3364 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0, ATI_VERB_SET_DOWNMIX_INFO
, 0);
3366 /* enable channel-wise remap mode if supported */
3367 if (has_amd_full_remap_support(codec
))
3368 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0,
3369 ATI_VERB_SET_MULTICHANNEL_MODE
,
3370 ATI_MULTICHANNEL_MODE_SINGLE
);
3376 static int patch_atihdmi(struct hda_codec
*codec
)
3378 struct hdmi_spec
*spec
;
3379 struct hdmi_spec_per_cvt
*per_cvt
;
3382 err
= patch_generic_hdmi(codec
);
3387 codec
->patch_ops
.init
= atihdmi_init
;
3391 spec
->ops
.pin_get_eld
= atihdmi_pin_get_eld
;
3392 spec
->ops
.pin_setup_infoframe
= atihdmi_pin_setup_infoframe
;
3393 spec
->ops
.pin_hbr_setup
= atihdmi_pin_hbr_setup
;
3394 spec
->ops
.setup_stream
= atihdmi_setup_stream
;
3396 if (!has_amd_full_remap_support(codec
)) {
3397 /* override to ATI/AMD-specific versions with pairwise mapping */
3398 spec
->chmap
.ops
.chmap_cea_alloc_validate_get_type
=
3399 atihdmi_paired_chmap_cea_alloc_validate_get_type
;
3400 spec
->chmap
.ops
.cea_alloc_to_tlv_chmap
=
3401 atihdmi_paired_cea_alloc_to_tlv_chmap
;
3402 spec
->chmap
.ops
.chmap_validate
= atihdmi_paired_chmap_validate
;
3403 spec
->chmap
.ops
.pin_get_slot_channel
=
3404 atihdmi_pin_get_slot_channel
;
3405 spec
->chmap
.ops
.pin_set_slot_channel
=
3406 atihdmi_pin_set_slot_channel
;
3409 /* ATI/AMD converters do not advertise all of their capabilities */
3410 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
3411 per_cvt
= get_cvt(spec
, cvt_idx
);
3412 per_cvt
->channels_max
= max(per_cvt
->channels_max
, 8u);
3413 per_cvt
->rates
|= SUPPORTED_RATES
;
3414 per_cvt
->formats
|= SUPPORTED_FORMATS
;
3415 per_cvt
->maxbps
= max(per_cvt
->maxbps
, 24u);
3418 spec
->chmap
.channels_max
= max(spec
->chmap
.channels_max
, 8u);
3423 /* VIA HDMI Implementation */
3424 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3425 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3427 static int patch_via_hdmi(struct hda_codec
*codec
)
3429 return patch_simple_hdmi(codec
, VIAHDMI_CVT_NID
, VIAHDMI_PIN_NID
);
3435 static const struct hda_device_id snd_hda_id_hdmi
[] = {
3436 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi
),
3437 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi
),
3438 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi
),
3439 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi
),
3440 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi
),
3441 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi
),
3442 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi
),
3443 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x
),
3444 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x
),
3445 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x
),
3446 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x
),
3447 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x
),
3448 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi
),
3449 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi
),
3450 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi
),
3451 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi
),
3452 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi
),
3453 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi
),
3454 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi
),
3455 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi
),
3456 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi
),
3457 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi
),
3458 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi
),
3459 /* 17 is known to be absent */
3460 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi
),
3461 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi
),
3462 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi
),
3463 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi
),
3464 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi
),
3465 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi
),
3466 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi
),
3467 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi
),
3468 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi
),
3469 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi
),
3470 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi
),
3471 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi
),
3472 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi
),
3473 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi
),
3474 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi
),
3475 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi
),
3476 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch
),
3477 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi
),
3478 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi
),
3479 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi
),
3480 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi
),
3481 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi
),
3482 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi
),
3483 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch
),
3484 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi
),
3485 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi
),
3486 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi
),
3487 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi
),
3488 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi
),
3489 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi
),
3490 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi
),
3491 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi
),
3492 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi
),
3493 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi
),
3494 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi
),
3495 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi
),
3496 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi
),
3497 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi
),
3498 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi
),
3499 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi
),
3500 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi
),
3501 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi
),
3502 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi
),
3503 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi
),
3504 /* special ID for generic HDMI */
3505 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI
, "Generic HDMI", patch_generic_hdmi
),
3508 MODULE_DEVICE_TABLE(hdaudio
, snd_hda_id_hdmi
);
3510 MODULE_LICENSE("GPL");
3511 MODULE_DESCRIPTION("HDMI HD-audio codec");
3512 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3513 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3514 MODULE_ALIAS("snd-hda-codec-atihdmi");
3516 static struct hda_codec_driver hdmi_driver
= {
3517 .id
= snd_hda_id_hdmi
,
3520 module_hda_codec_driver(hdmi_driver
);