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fb: adv7393: off by one in probe function
[deliverable/linux.git] / sound / pci / rme96.c
1 /*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/module.h>
31 #include <linux/vmalloc.h>
32 #include <linux/io.h>
33
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
41
42 /* note, two last pcis should be equal, it is not a bug */
43
44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46 "Digi96/8 PAD");
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49 "{RME,Digi96/8},"
50 "{RME,Digi96/8 PRO},"
51 "{RME,Digi96/8 PST},"
52 "{RME,Digi96/8 PAD}}");
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
56 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
57
58 module_param_array(index, int, NULL, 0444);
59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60 module_param_array(id, charp, NULL, 0444);
61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62 module_param_array(enable, bool, NULL, 0444);
63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64
65 /*
66 * Defines for RME Digi96 series, from internal RME reference documents
67 * dated 12.01.00
68 */
69
70 #define RME96_SPDIF_NCHANNELS 2
71
72 /* Playback and capture buffer size */
73 #define RME96_BUFFER_SIZE 0x10000
74
75 /* IO area size */
76 #define RME96_IO_SIZE 0x60000
77
78 /* IO area offsets */
79 #define RME96_IO_PLAY_BUFFER 0x0
80 #define RME96_IO_REC_BUFFER 0x10000
81 #define RME96_IO_CONTROL_REGISTER 0x20000
82 #define RME96_IO_ADDITIONAL_REG 0x20004
83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85 #define RME96_IO_SET_PLAY_POS 0x40000
86 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
87 #define RME96_IO_SET_REC_POS 0x50000
88 #define RME96_IO_RESET_REC_POS 0x5FFFC
89 #define RME96_IO_GET_PLAY_POS 0x20000
90 #define RME96_IO_GET_REC_POS 0x30000
91
92 /* Write control register bits */
93 #define RME96_WCR_START (1 << 0)
94 #define RME96_WCR_START_2 (1 << 1)
95 #define RME96_WCR_GAIN_0 (1 << 2)
96 #define RME96_WCR_GAIN_1 (1 << 3)
97 #define RME96_WCR_MODE24 (1 << 4)
98 #define RME96_WCR_MODE24_2 (1 << 5)
99 #define RME96_WCR_BM (1 << 6)
100 #define RME96_WCR_BM_2 (1 << 7)
101 #define RME96_WCR_ADAT (1 << 8)
102 #define RME96_WCR_FREQ_0 (1 << 9)
103 #define RME96_WCR_FREQ_1 (1 << 10)
104 #define RME96_WCR_DS (1 << 11)
105 #define RME96_WCR_PRO (1 << 12)
106 #define RME96_WCR_EMP (1 << 13)
107 #define RME96_WCR_SEL (1 << 14)
108 #define RME96_WCR_MASTER (1 << 15)
109 #define RME96_WCR_PD (1 << 16)
110 #define RME96_WCR_INP_0 (1 << 17)
111 #define RME96_WCR_INP_1 (1 << 18)
112 #define RME96_WCR_THRU_0 (1 << 19)
113 #define RME96_WCR_THRU_1 (1 << 20)
114 #define RME96_WCR_THRU_2 (1 << 21)
115 #define RME96_WCR_THRU_3 (1 << 22)
116 #define RME96_WCR_THRU_4 (1 << 23)
117 #define RME96_WCR_THRU_5 (1 << 24)
118 #define RME96_WCR_THRU_6 (1 << 25)
119 #define RME96_WCR_THRU_7 (1 << 26)
120 #define RME96_WCR_DOLBY (1 << 27)
121 #define RME96_WCR_MONITOR_0 (1 << 28)
122 #define RME96_WCR_MONITOR_1 (1 << 29)
123 #define RME96_WCR_ISEL (1 << 30)
124 #define RME96_WCR_IDIS (1 << 31)
125
126 #define RME96_WCR_BITPOS_GAIN_0 2
127 #define RME96_WCR_BITPOS_GAIN_1 3
128 #define RME96_WCR_BITPOS_FREQ_0 9
129 #define RME96_WCR_BITPOS_FREQ_1 10
130 #define RME96_WCR_BITPOS_INP_0 17
131 #define RME96_WCR_BITPOS_INP_1 18
132 #define RME96_WCR_BITPOS_MONITOR_0 28
133 #define RME96_WCR_BITPOS_MONITOR_1 29
134
135 /* Read control register bits */
136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137 #define RME96_RCR_IRQ_2 (1 << 16)
138 #define RME96_RCR_T_OUT (1 << 17)
139 #define RME96_RCR_DEV_ID_0 (1 << 21)
140 #define RME96_RCR_DEV_ID_1 (1 << 22)
141 #define RME96_RCR_LOCK (1 << 23)
142 #define RME96_RCR_VERF (1 << 26)
143 #define RME96_RCR_F0 (1 << 27)
144 #define RME96_RCR_F1 (1 << 28)
145 #define RME96_RCR_F2 (1 << 29)
146 #define RME96_RCR_AUTOSYNC (1 << 30)
147 #define RME96_RCR_IRQ (1 << 31)
148
149 #define RME96_RCR_BITPOS_F0 27
150 #define RME96_RCR_BITPOS_F1 28
151 #define RME96_RCR_BITPOS_F2 29
152
153 /* Additional register bits */
154 #define RME96_AR_WSEL (1 << 0)
155 #define RME96_AR_ANALOG (1 << 1)
156 #define RME96_AR_FREQPAD_0 (1 << 2)
157 #define RME96_AR_FREQPAD_1 (1 << 3)
158 #define RME96_AR_FREQPAD_2 (1 << 4)
159 #define RME96_AR_PD2 (1 << 5)
160 #define RME96_AR_DAC_EN (1 << 6)
161 #define RME96_AR_CLATCH (1 << 7)
162 #define RME96_AR_CCLK (1 << 8)
163 #define RME96_AR_CDATA (1 << 9)
164
165 #define RME96_AR_BITPOS_F0 2
166 #define RME96_AR_BITPOS_F1 3
167 #define RME96_AR_BITPOS_F2 4
168
169 /* Monitor tracks */
170 #define RME96_MONITOR_TRACKS_1_2 0
171 #define RME96_MONITOR_TRACKS_3_4 1
172 #define RME96_MONITOR_TRACKS_5_6 2
173 #define RME96_MONITOR_TRACKS_7_8 3
174
175 /* Attenuation */
176 #define RME96_ATTENUATION_0 0
177 #define RME96_ATTENUATION_6 1
178 #define RME96_ATTENUATION_12 2
179 #define RME96_ATTENUATION_18 3
180
181 /* Input types */
182 #define RME96_INPUT_OPTICAL 0
183 #define RME96_INPUT_COAXIAL 1
184 #define RME96_INPUT_INTERNAL 2
185 #define RME96_INPUT_XLR 3
186 #define RME96_INPUT_ANALOG 4
187
188 /* Clock modes */
189 #define RME96_CLOCKMODE_SLAVE 0
190 #define RME96_CLOCKMODE_MASTER 1
191 #define RME96_CLOCKMODE_WORDCLOCK 2
192
193 /* Block sizes in bytes */
194 #define RME96_SMALL_BLOCK_SIZE 2048
195 #define RME96_LARGE_BLOCK_SIZE 8192
196
197 /* Volume control */
198 #define RME96_AD1852_VOL_BITS 14
199 #define RME96_AD1855_VOL_BITS 10
200
201 /* Defines for snd_rme96_trigger */
202 #define RME96_TB_START_PLAYBACK 1
203 #define RME96_TB_START_CAPTURE 2
204 #define RME96_TB_STOP_PLAYBACK 4
205 #define RME96_TB_STOP_CAPTURE 8
206 #define RME96_TB_RESET_PLAYPOS 16
207 #define RME96_TB_RESET_CAPTUREPOS 32
208 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
209 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
210 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
211 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
212 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
213 | RME96_RESUME_CAPTURE)
214 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
215 | RME96_TB_RESET_PLAYPOS)
216 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
217 | RME96_TB_RESET_CAPTUREPOS)
218 #define RME96_START_BOTH (RME96_START_PLAYBACK \
219 | RME96_START_CAPTURE)
220 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
221 | RME96_TB_CLEAR_PLAYBACK_IRQ)
222 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
223 | RME96_TB_CLEAR_CAPTURE_IRQ)
224 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
225 | RME96_STOP_CAPTURE)
226
227 struct rme96 {
228 spinlock_t lock;
229 int irq;
230 unsigned long port;
231 void __iomem *iobase;
232
233 u32 wcreg; /* cached write control register value */
234 u32 wcreg_spdif; /* S/PDIF setup */
235 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
236 u32 rcreg; /* cached read control register value */
237 u32 areg; /* cached additional register value */
238 u16 vol[2]; /* cached volume of analog output */
239
240 u8 rev; /* card revision number */
241
242 #ifdef CONFIG_PM_SLEEP
243 u32 playback_pointer;
244 u32 capture_pointer;
245 void *playback_suspend_buffer;
246 void *capture_suspend_buffer;
247 #endif
248
249 struct snd_pcm_substream *playback_substream;
250 struct snd_pcm_substream *capture_substream;
251
252 int playback_frlog; /* log2 of framesize */
253 int capture_frlog;
254
255 size_t playback_periodsize; /* in bytes, zero if not used */
256 size_t capture_periodsize; /* in bytes, zero if not used */
257
258 struct snd_card *card;
259 struct snd_pcm *spdif_pcm;
260 struct snd_pcm *adat_pcm;
261 struct pci_dev *pci;
262 struct snd_kcontrol *spdif_ctl;
263 };
264
265 static const struct pci_device_id snd_rme96_ids[] = {
266 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
270 { 0, }
271 };
272
273 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
274
275 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
276 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
277 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
278 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
279 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
280 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
281 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
282 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
283 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
284
285 static int
286 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
287
288 static int
289 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
290
291 static int
292 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
293 int cmd);
294
295 static int
296 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
297 int cmd);
298
299 static snd_pcm_uframes_t
300 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
301
302 static snd_pcm_uframes_t
303 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
304
305 static void snd_rme96_proc_init(struct rme96 *rme96);
306
307 static int
308 snd_rme96_create_switches(struct snd_card *card,
309 struct rme96 *rme96);
310
311 static int
312 snd_rme96_getinputtype(struct rme96 *rme96);
313
314 static inline unsigned int
315 snd_rme96_playback_ptr(struct rme96 *rme96)
316 {
317 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
318 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
319 }
320
321 static inline unsigned int
322 snd_rme96_capture_ptr(struct rme96 *rme96)
323 {
324 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
325 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
326 }
327
328 static int
329 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
330 int channel, /* not used (interleaved data) */
331 snd_pcm_uframes_t pos,
332 snd_pcm_uframes_t count)
333 {
334 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
335 count <<= rme96->playback_frlog;
336 pos <<= rme96->playback_frlog;
337 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
338 0, count);
339 return 0;
340 }
341
342 static int
343 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
344 int channel, /* not used (interleaved data) */
345 snd_pcm_uframes_t pos,
346 void __user *src,
347 snd_pcm_uframes_t count)
348 {
349 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
350 count <<= rme96->playback_frlog;
351 pos <<= rme96->playback_frlog;
352 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
353 count);
354 }
355
356 static int
357 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
358 int channel, /* not used (interleaved data) */
359 snd_pcm_uframes_t pos,
360 void __user *dst,
361 snd_pcm_uframes_t count)
362 {
363 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
364 count <<= rme96->capture_frlog;
365 pos <<= rme96->capture_frlog;
366 return copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
367 count);
368 }
369
370 /*
371 * Digital output capabilities (S/PDIF)
372 */
373 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
374 {
375 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
376 SNDRV_PCM_INFO_MMAP_VALID |
377 SNDRV_PCM_INFO_SYNC_START |
378 SNDRV_PCM_INFO_RESUME |
379 SNDRV_PCM_INFO_INTERLEAVED |
380 SNDRV_PCM_INFO_PAUSE),
381 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
382 SNDRV_PCM_FMTBIT_S32_LE),
383 .rates = (SNDRV_PCM_RATE_32000 |
384 SNDRV_PCM_RATE_44100 |
385 SNDRV_PCM_RATE_48000 |
386 SNDRV_PCM_RATE_64000 |
387 SNDRV_PCM_RATE_88200 |
388 SNDRV_PCM_RATE_96000),
389 .rate_min = 32000,
390 .rate_max = 96000,
391 .channels_min = 2,
392 .channels_max = 2,
393 .buffer_bytes_max = RME96_BUFFER_SIZE,
394 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
395 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
396 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
397 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
398 .fifo_size = 0,
399 };
400
401 /*
402 * Digital input capabilities (S/PDIF)
403 */
404 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
405 {
406 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
407 SNDRV_PCM_INFO_MMAP_VALID |
408 SNDRV_PCM_INFO_SYNC_START |
409 SNDRV_PCM_INFO_RESUME |
410 SNDRV_PCM_INFO_INTERLEAVED |
411 SNDRV_PCM_INFO_PAUSE),
412 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
413 SNDRV_PCM_FMTBIT_S32_LE),
414 .rates = (SNDRV_PCM_RATE_32000 |
415 SNDRV_PCM_RATE_44100 |
416 SNDRV_PCM_RATE_48000 |
417 SNDRV_PCM_RATE_64000 |
418 SNDRV_PCM_RATE_88200 |
419 SNDRV_PCM_RATE_96000),
420 .rate_min = 32000,
421 .rate_max = 96000,
422 .channels_min = 2,
423 .channels_max = 2,
424 .buffer_bytes_max = RME96_BUFFER_SIZE,
425 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
426 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
427 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
428 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
429 .fifo_size = 0,
430 };
431
432 /*
433 * Digital output capabilities (ADAT)
434 */
435 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
436 {
437 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
438 SNDRV_PCM_INFO_MMAP_VALID |
439 SNDRV_PCM_INFO_SYNC_START |
440 SNDRV_PCM_INFO_RESUME |
441 SNDRV_PCM_INFO_INTERLEAVED |
442 SNDRV_PCM_INFO_PAUSE),
443 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
444 SNDRV_PCM_FMTBIT_S32_LE),
445 .rates = (SNDRV_PCM_RATE_44100 |
446 SNDRV_PCM_RATE_48000),
447 .rate_min = 44100,
448 .rate_max = 48000,
449 .channels_min = 8,
450 .channels_max = 8,
451 .buffer_bytes_max = RME96_BUFFER_SIZE,
452 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
453 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
454 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
455 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
456 .fifo_size = 0,
457 };
458
459 /*
460 * Digital input capabilities (ADAT)
461 */
462 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
463 {
464 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
465 SNDRV_PCM_INFO_MMAP_VALID |
466 SNDRV_PCM_INFO_SYNC_START |
467 SNDRV_PCM_INFO_RESUME |
468 SNDRV_PCM_INFO_INTERLEAVED |
469 SNDRV_PCM_INFO_PAUSE),
470 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
471 SNDRV_PCM_FMTBIT_S32_LE),
472 .rates = (SNDRV_PCM_RATE_44100 |
473 SNDRV_PCM_RATE_48000),
474 .rate_min = 44100,
475 .rate_max = 48000,
476 .channels_min = 8,
477 .channels_max = 8,
478 .buffer_bytes_max = RME96_BUFFER_SIZE,
479 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
480 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
481 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
482 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
483 .fifo_size = 0,
484 };
485
486 /*
487 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
488 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
489 * on the falling edge of CCLK and be stable on the rising edge. The rising
490 * edge of CLATCH after the last data bit clocks in the whole data word.
491 * A fast processor could probably drive the SPI interface faster than the
492 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
493 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
494 *
495 * NOTE: increased delay from 1 to 10, since there where problems setting
496 * the volume.
497 */
498 static void
499 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
500 {
501 int i;
502
503 for (i = 0; i < 16; i++) {
504 if (val & 0x8000) {
505 rme96->areg |= RME96_AR_CDATA;
506 } else {
507 rme96->areg &= ~RME96_AR_CDATA;
508 }
509 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
510 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
511 udelay(10);
512 rme96->areg |= RME96_AR_CCLK;
513 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
514 udelay(10);
515 val <<= 1;
516 }
517 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
518 rme96->areg |= RME96_AR_CLATCH;
519 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
520 udelay(10);
521 rme96->areg &= ~RME96_AR_CLATCH;
522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
523 }
524
525 static void
526 snd_rme96_apply_dac_volume(struct rme96 *rme96)
527 {
528 if (RME96_DAC_IS_1852(rme96)) {
529 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
530 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
531 } else if (RME96_DAC_IS_1855(rme96)) {
532 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
533 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
534 }
535 }
536
537 static void
538 snd_rme96_reset_dac(struct rme96 *rme96)
539 {
540 writel(rme96->wcreg | RME96_WCR_PD,
541 rme96->iobase + RME96_IO_CONTROL_REGISTER);
542 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
543 }
544
545 static int
546 snd_rme96_getmontracks(struct rme96 *rme96)
547 {
548 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
549 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
550 }
551
552 static int
553 snd_rme96_setmontracks(struct rme96 *rme96,
554 int montracks)
555 {
556 if (montracks & 1) {
557 rme96->wcreg |= RME96_WCR_MONITOR_0;
558 } else {
559 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
560 }
561 if (montracks & 2) {
562 rme96->wcreg |= RME96_WCR_MONITOR_1;
563 } else {
564 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
565 }
566 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
567 return 0;
568 }
569
570 static int
571 snd_rme96_getattenuation(struct rme96 *rme96)
572 {
573 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
574 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
575 }
576
577 static int
578 snd_rme96_setattenuation(struct rme96 *rme96,
579 int attenuation)
580 {
581 switch (attenuation) {
582 case 0:
583 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
584 ~RME96_WCR_GAIN_1;
585 break;
586 case 1:
587 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
588 ~RME96_WCR_GAIN_1;
589 break;
590 case 2:
591 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
592 RME96_WCR_GAIN_1;
593 break;
594 case 3:
595 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
596 RME96_WCR_GAIN_1;
597 break;
598 default:
599 return -EINVAL;
600 }
601 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
602 return 0;
603 }
604
605 static int
606 snd_rme96_capture_getrate(struct rme96 *rme96,
607 int *is_adat)
608 {
609 int n, rate;
610
611 *is_adat = 0;
612 if (rme96->areg & RME96_AR_ANALOG) {
613 /* Analog input, overrides S/PDIF setting */
614 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
615 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
616 switch (n) {
617 case 1:
618 rate = 32000;
619 break;
620 case 2:
621 rate = 44100;
622 break;
623 case 3:
624 rate = 48000;
625 break;
626 default:
627 return -1;
628 }
629 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
630 }
631
632 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
633 if (rme96->rcreg & RME96_RCR_LOCK) {
634 /* ADAT rate */
635 *is_adat = 1;
636 if (rme96->rcreg & RME96_RCR_T_OUT) {
637 return 48000;
638 }
639 return 44100;
640 }
641
642 if (rme96->rcreg & RME96_RCR_VERF) {
643 return -1;
644 }
645
646 /* S/PDIF rate */
647 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
648 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
649 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
650
651 switch (n) {
652 case 0:
653 if (rme96->rcreg & RME96_RCR_T_OUT) {
654 return 64000;
655 }
656 return -1;
657 case 3: return 96000;
658 case 4: return 88200;
659 case 5: return 48000;
660 case 6: return 44100;
661 case 7: return 32000;
662 default:
663 break;
664 }
665 return -1;
666 }
667
668 static int
669 snd_rme96_playback_getrate(struct rme96 *rme96)
670 {
671 int rate, dummy;
672
673 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
674 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
675 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
676 {
677 /* slave clock */
678 return rate;
679 }
680 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
681 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
682 switch (rate) {
683 case 1:
684 rate = 32000;
685 break;
686 case 2:
687 rate = 44100;
688 break;
689 case 3:
690 rate = 48000;
691 break;
692 default:
693 return -1;
694 }
695 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
696 }
697
698 static int
699 snd_rme96_playback_setrate(struct rme96 *rme96,
700 int rate)
701 {
702 int ds;
703
704 ds = rme96->wcreg & RME96_WCR_DS;
705 switch (rate) {
706 case 32000:
707 rme96->wcreg &= ~RME96_WCR_DS;
708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
709 ~RME96_WCR_FREQ_1;
710 break;
711 case 44100:
712 rme96->wcreg &= ~RME96_WCR_DS;
713 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
714 ~RME96_WCR_FREQ_0;
715 break;
716 case 48000:
717 rme96->wcreg &= ~RME96_WCR_DS;
718 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
719 RME96_WCR_FREQ_1;
720 break;
721 case 64000:
722 rme96->wcreg |= RME96_WCR_DS;
723 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
724 ~RME96_WCR_FREQ_1;
725 break;
726 case 88200:
727 rme96->wcreg |= RME96_WCR_DS;
728 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
729 ~RME96_WCR_FREQ_0;
730 break;
731 case 96000:
732 rme96->wcreg |= RME96_WCR_DS;
733 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
734 RME96_WCR_FREQ_1;
735 break;
736 default:
737 return -EINVAL;
738 }
739 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
740 (ds && !(rme96->wcreg & RME96_WCR_DS)))
741 {
742 /* change to/from double-speed: reset the DAC (if available) */
743 snd_rme96_reset_dac(rme96);
744 return 1; /* need to restore volume */
745 } else {
746 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
747 return 0;
748 }
749 }
750
751 static int
752 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
753 int rate)
754 {
755 switch (rate) {
756 case 32000:
757 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
758 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
759 break;
760 case 44100:
761 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
762 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
763 break;
764 case 48000:
765 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
766 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
767 break;
768 case 64000:
769 if (rme96->rev < 4) {
770 return -EINVAL;
771 }
772 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
773 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
774 break;
775 case 88200:
776 if (rme96->rev < 4) {
777 return -EINVAL;
778 }
779 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
780 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
781 break;
782 case 96000:
783 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
784 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
785 break;
786 default:
787 return -EINVAL;
788 }
789 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
790 return 0;
791 }
792
793 static int
794 snd_rme96_setclockmode(struct rme96 *rme96,
795 int mode)
796 {
797 switch (mode) {
798 case RME96_CLOCKMODE_SLAVE:
799 /* AutoSync */
800 rme96->wcreg &= ~RME96_WCR_MASTER;
801 rme96->areg &= ~RME96_AR_WSEL;
802 break;
803 case RME96_CLOCKMODE_MASTER:
804 /* Internal */
805 rme96->wcreg |= RME96_WCR_MASTER;
806 rme96->areg &= ~RME96_AR_WSEL;
807 break;
808 case RME96_CLOCKMODE_WORDCLOCK:
809 /* Word clock is a master mode */
810 rme96->wcreg |= RME96_WCR_MASTER;
811 rme96->areg |= RME96_AR_WSEL;
812 break;
813 default:
814 return -EINVAL;
815 }
816 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
817 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
818 return 0;
819 }
820
821 static int
822 snd_rme96_getclockmode(struct rme96 *rme96)
823 {
824 if (rme96->areg & RME96_AR_WSEL) {
825 return RME96_CLOCKMODE_WORDCLOCK;
826 }
827 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
828 RME96_CLOCKMODE_SLAVE;
829 }
830
831 static int
832 snd_rme96_setinputtype(struct rme96 *rme96,
833 int type)
834 {
835 int n;
836
837 switch (type) {
838 case RME96_INPUT_OPTICAL:
839 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
840 ~RME96_WCR_INP_1;
841 break;
842 case RME96_INPUT_COAXIAL:
843 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
844 ~RME96_WCR_INP_1;
845 break;
846 case RME96_INPUT_INTERNAL:
847 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
848 RME96_WCR_INP_1;
849 break;
850 case RME96_INPUT_XLR:
851 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
852 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
853 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
854 rme96->rev > 4))
855 {
856 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
857 return -EINVAL;
858 }
859 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
860 RME96_WCR_INP_1;
861 break;
862 case RME96_INPUT_ANALOG:
863 if (!RME96_HAS_ANALOG_IN(rme96)) {
864 return -EINVAL;
865 }
866 rme96->areg |= RME96_AR_ANALOG;
867 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
868 if (rme96->rev < 4) {
869 /*
870 * Revision less than 004 does not support 64 and
871 * 88.2 kHz
872 */
873 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
874 snd_rme96_capture_analog_setrate(rme96, 44100);
875 }
876 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
877 snd_rme96_capture_analog_setrate(rme96, 32000);
878 }
879 }
880 return 0;
881 default:
882 return -EINVAL;
883 }
884 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
885 rme96->areg &= ~RME96_AR_ANALOG;
886 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
887 }
888 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
889 return 0;
890 }
891
892 static int
893 snd_rme96_getinputtype(struct rme96 *rme96)
894 {
895 if (rme96->areg & RME96_AR_ANALOG) {
896 return RME96_INPUT_ANALOG;
897 }
898 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
899 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
900 }
901
902 static void
903 snd_rme96_setframelog(struct rme96 *rme96,
904 int n_channels,
905 int is_playback)
906 {
907 int frlog;
908
909 if (n_channels == 2) {
910 frlog = 1;
911 } else {
912 /* assume 8 channels */
913 frlog = 3;
914 }
915 if (is_playback) {
916 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
917 rme96->playback_frlog = frlog;
918 } else {
919 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
920 rme96->capture_frlog = frlog;
921 }
922 }
923
924 static int
925 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
926 {
927 switch (format) {
928 case SNDRV_PCM_FORMAT_S16_LE:
929 rme96->wcreg &= ~RME96_WCR_MODE24;
930 break;
931 case SNDRV_PCM_FORMAT_S32_LE:
932 rme96->wcreg |= RME96_WCR_MODE24;
933 break;
934 default:
935 return -EINVAL;
936 }
937 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
938 return 0;
939 }
940
941 static int
942 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
943 {
944 switch (format) {
945 case SNDRV_PCM_FORMAT_S16_LE:
946 rme96->wcreg &= ~RME96_WCR_MODE24_2;
947 break;
948 case SNDRV_PCM_FORMAT_S32_LE:
949 rme96->wcreg |= RME96_WCR_MODE24_2;
950 break;
951 default:
952 return -EINVAL;
953 }
954 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
955 return 0;
956 }
957
958 static void
959 snd_rme96_set_period_properties(struct rme96 *rme96,
960 size_t period_bytes)
961 {
962 switch (period_bytes) {
963 case RME96_LARGE_BLOCK_SIZE:
964 rme96->wcreg &= ~RME96_WCR_ISEL;
965 break;
966 case RME96_SMALL_BLOCK_SIZE:
967 rme96->wcreg |= RME96_WCR_ISEL;
968 break;
969 default:
970 snd_BUG();
971 break;
972 }
973 rme96->wcreg &= ~RME96_WCR_IDIS;
974 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
975 }
976
977 static int
978 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
979 struct snd_pcm_hw_params *params)
980 {
981 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
982 struct snd_pcm_runtime *runtime = substream->runtime;
983 int err, rate, dummy;
984 bool apply_dac_volume = false;
985
986 runtime->dma_area = (void __force *)(rme96->iobase +
987 RME96_IO_PLAY_BUFFER);
988 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
989 runtime->dma_bytes = RME96_BUFFER_SIZE;
990
991 spin_lock_irq(&rme96->lock);
992 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
993 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
994 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
995 {
996 /* slave clock */
997 if ((int)params_rate(params) != rate) {
998 err = -EIO;
999 goto error;
1000 }
1001 } else {
1002 err = snd_rme96_playback_setrate(rme96, params_rate(params));
1003 if (err < 0)
1004 goto error;
1005 apply_dac_volume = err > 0; /* need to restore volume later? */
1006 }
1007
1008 err = snd_rme96_playback_setformat(rme96, params_format(params));
1009 if (err < 0)
1010 goto error;
1011 snd_rme96_setframelog(rme96, params_channels(params), 1);
1012 if (rme96->capture_periodsize != 0) {
1013 if (params_period_size(params) << rme96->playback_frlog !=
1014 rme96->capture_periodsize)
1015 {
1016 err = -EBUSY;
1017 goto error;
1018 }
1019 }
1020 rme96->playback_periodsize =
1021 params_period_size(params) << rme96->playback_frlog;
1022 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1023 /* S/PDIF setup */
1024 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1027 }
1028
1029 err = 0;
1030 error:
1031 spin_unlock_irq(&rme96->lock);
1032 if (apply_dac_volume) {
1033 usleep_range(3000, 10000);
1034 snd_rme96_apply_dac_volume(rme96);
1035 }
1036
1037 return err;
1038 }
1039
1040 static int
1041 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1042 struct snd_pcm_hw_params *params)
1043 {
1044 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1045 struct snd_pcm_runtime *runtime = substream->runtime;
1046 int err, isadat, rate;
1047
1048 runtime->dma_area = (void __force *)(rme96->iobase +
1049 RME96_IO_REC_BUFFER);
1050 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1051 runtime->dma_bytes = RME96_BUFFER_SIZE;
1052
1053 spin_lock_irq(&rme96->lock);
1054 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1055 spin_unlock_irq(&rme96->lock);
1056 return err;
1057 }
1058 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1059 if ((err = snd_rme96_capture_analog_setrate(rme96,
1060 params_rate(params))) < 0)
1061 {
1062 spin_unlock_irq(&rme96->lock);
1063 return err;
1064 }
1065 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1066 if ((int)params_rate(params) != rate) {
1067 spin_unlock_irq(&rme96->lock);
1068 return -EIO;
1069 }
1070 if ((isadat && runtime->hw.channels_min == 2) ||
1071 (!isadat && runtime->hw.channels_min == 8))
1072 {
1073 spin_unlock_irq(&rme96->lock);
1074 return -EIO;
1075 }
1076 }
1077 snd_rme96_setframelog(rme96, params_channels(params), 0);
1078 if (rme96->playback_periodsize != 0) {
1079 if (params_period_size(params) << rme96->capture_frlog !=
1080 rme96->playback_periodsize)
1081 {
1082 spin_unlock_irq(&rme96->lock);
1083 return -EBUSY;
1084 }
1085 }
1086 rme96->capture_periodsize =
1087 params_period_size(params) << rme96->capture_frlog;
1088 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1089 spin_unlock_irq(&rme96->lock);
1090
1091 return 0;
1092 }
1093
1094 static void
1095 snd_rme96_trigger(struct rme96 *rme96,
1096 int op)
1097 {
1098 if (op & RME96_TB_RESET_PLAYPOS)
1099 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1100 if (op & RME96_TB_RESET_CAPTUREPOS)
1101 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1102 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1103 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1104 if (rme96->rcreg & RME96_RCR_IRQ)
1105 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1106 }
1107 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1108 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1109 if (rme96->rcreg & RME96_RCR_IRQ_2)
1110 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1111 }
1112 if (op & RME96_TB_START_PLAYBACK)
1113 rme96->wcreg |= RME96_WCR_START;
1114 if (op & RME96_TB_STOP_PLAYBACK)
1115 rme96->wcreg &= ~RME96_WCR_START;
1116 if (op & RME96_TB_START_CAPTURE)
1117 rme96->wcreg |= RME96_WCR_START_2;
1118 if (op & RME96_TB_STOP_CAPTURE)
1119 rme96->wcreg &= ~RME96_WCR_START_2;
1120 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1121 }
1122
1123
1124
1125 static irqreturn_t
1126 snd_rme96_interrupt(int irq,
1127 void *dev_id)
1128 {
1129 struct rme96 *rme96 = (struct rme96 *)dev_id;
1130
1131 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1132 /* fastpath out, to ease interrupt sharing */
1133 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1134 (rme96->rcreg & RME96_RCR_IRQ_2)))
1135 {
1136 return IRQ_NONE;
1137 }
1138
1139 if (rme96->rcreg & RME96_RCR_IRQ) {
1140 /* playback */
1141 snd_pcm_period_elapsed(rme96->playback_substream);
1142 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1143 }
1144 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1145 /* capture */
1146 snd_pcm_period_elapsed(rme96->capture_substream);
1147 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1148 }
1149 return IRQ_HANDLED;
1150 }
1151
1152 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1153
1154 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1155 .count = ARRAY_SIZE(period_bytes),
1156 .list = period_bytes,
1157 .mask = 0
1158 };
1159
1160 static void
1161 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1162 struct snd_pcm_runtime *runtime)
1163 {
1164 unsigned int size;
1165
1166 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1167 RME96_BUFFER_SIZE);
1168 if ((size = rme96->playback_periodsize) != 0 ||
1169 (size = rme96->capture_periodsize) != 0)
1170 snd_pcm_hw_constraint_single(runtime,
1171 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1172 size);
1173 else
1174 snd_pcm_hw_constraint_list(runtime, 0,
1175 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1176 &hw_constraints_period_bytes);
1177 }
1178
1179 static int
1180 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1181 {
1182 int rate, dummy;
1183 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1184 struct snd_pcm_runtime *runtime = substream->runtime;
1185
1186 snd_pcm_set_sync(substream);
1187 spin_lock_irq(&rme96->lock);
1188 if (rme96->playback_substream != NULL) {
1189 spin_unlock_irq(&rme96->lock);
1190 return -EBUSY;
1191 }
1192 rme96->wcreg &= ~RME96_WCR_ADAT;
1193 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1194 rme96->playback_substream = substream;
1195 spin_unlock_irq(&rme96->lock);
1196
1197 runtime->hw = snd_rme96_playback_spdif_info;
1198 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1199 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1200 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1201 {
1202 /* slave clock */
1203 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1204 runtime->hw.rate_min = rate;
1205 runtime->hw.rate_max = rate;
1206 }
1207 rme96_set_buffer_size_constraint(rme96, runtime);
1208
1209 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1210 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1211 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1212 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1213 return 0;
1214 }
1215
1216 static int
1217 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1218 {
1219 int isadat, rate;
1220 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1221 struct snd_pcm_runtime *runtime = substream->runtime;
1222
1223 snd_pcm_set_sync(substream);
1224 runtime->hw = snd_rme96_capture_spdif_info;
1225 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1226 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1227 {
1228 if (isadat) {
1229 return -EIO;
1230 }
1231 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1232 runtime->hw.rate_min = rate;
1233 runtime->hw.rate_max = rate;
1234 }
1235
1236 spin_lock_irq(&rme96->lock);
1237 if (rme96->capture_substream != NULL) {
1238 spin_unlock_irq(&rme96->lock);
1239 return -EBUSY;
1240 }
1241 rme96->capture_substream = substream;
1242 spin_unlock_irq(&rme96->lock);
1243
1244 rme96_set_buffer_size_constraint(rme96, runtime);
1245 return 0;
1246 }
1247
1248 static int
1249 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1250 {
1251 int rate, dummy;
1252 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1253 struct snd_pcm_runtime *runtime = substream->runtime;
1254
1255 snd_pcm_set_sync(substream);
1256 spin_lock_irq(&rme96->lock);
1257 if (rme96->playback_substream != NULL) {
1258 spin_unlock_irq(&rme96->lock);
1259 return -EBUSY;
1260 }
1261 rme96->wcreg |= RME96_WCR_ADAT;
1262 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1263 rme96->playback_substream = substream;
1264 spin_unlock_irq(&rme96->lock);
1265
1266 runtime->hw = snd_rme96_playback_adat_info;
1267 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1268 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1269 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1270 {
1271 /* slave clock */
1272 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1273 runtime->hw.rate_min = rate;
1274 runtime->hw.rate_max = rate;
1275 }
1276 rme96_set_buffer_size_constraint(rme96, runtime);
1277 return 0;
1278 }
1279
1280 static int
1281 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1282 {
1283 int isadat, rate;
1284 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1285 struct snd_pcm_runtime *runtime = substream->runtime;
1286
1287 snd_pcm_set_sync(substream);
1288 runtime->hw = snd_rme96_capture_adat_info;
1289 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1290 /* makes no sense to use analog input. Note that analog
1291 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1292 return -EIO;
1293 }
1294 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1295 if (!isadat) {
1296 return -EIO;
1297 }
1298 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1299 runtime->hw.rate_min = rate;
1300 runtime->hw.rate_max = rate;
1301 }
1302
1303 spin_lock_irq(&rme96->lock);
1304 if (rme96->capture_substream != NULL) {
1305 spin_unlock_irq(&rme96->lock);
1306 return -EBUSY;
1307 }
1308 rme96->capture_substream = substream;
1309 spin_unlock_irq(&rme96->lock);
1310
1311 rme96_set_buffer_size_constraint(rme96, runtime);
1312 return 0;
1313 }
1314
1315 static int
1316 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1317 {
1318 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1319 int spdif = 0;
1320
1321 spin_lock_irq(&rme96->lock);
1322 if (RME96_ISPLAYING(rme96)) {
1323 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1324 }
1325 rme96->playback_substream = NULL;
1326 rme96->playback_periodsize = 0;
1327 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1328 spin_unlock_irq(&rme96->lock);
1329 if (spdif) {
1330 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1331 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1332 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1333 }
1334 return 0;
1335 }
1336
1337 static int
1338 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1339 {
1340 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1341
1342 spin_lock_irq(&rme96->lock);
1343 if (RME96_ISRECORDING(rme96)) {
1344 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1345 }
1346 rme96->capture_substream = NULL;
1347 rme96->capture_periodsize = 0;
1348 spin_unlock_irq(&rme96->lock);
1349 return 0;
1350 }
1351
1352 static int
1353 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1354 {
1355 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1356
1357 spin_lock_irq(&rme96->lock);
1358 if (RME96_ISPLAYING(rme96)) {
1359 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1360 }
1361 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1362 spin_unlock_irq(&rme96->lock);
1363 return 0;
1364 }
1365
1366 static int
1367 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1368 {
1369 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1370
1371 spin_lock_irq(&rme96->lock);
1372 if (RME96_ISRECORDING(rme96)) {
1373 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1374 }
1375 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1376 spin_unlock_irq(&rme96->lock);
1377 return 0;
1378 }
1379
1380 static int
1381 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1382 int cmd)
1383 {
1384 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1385 struct snd_pcm_substream *s;
1386 bool sync;
1387
1388 snd_pcm_group_for_each_entry(s, substream) {
1389 if (snd_pcm_substream_chip(s) == rme96)
1390 snd_pcm_trigger_done(s, substream);
1391 }
1392
1393 sync = (rme96->playback_substream && rme96->capture_substream) &&
1394 (rme96->playback_substream->group ==
1395 rme96->capture_substream->group);
1396
1397 switch (cmd) {
1398 case SNDRV_PCM_TRIGGER_START:
1399 if (!RME96_ISPLAYING(rme96)) {
1400 if (substream != rme96->playback_substream)
1401 return -EBUSY;
1402 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1403 : RME96_START_PLAYBACK);
1404 }
1405 break;
1406
1407 case SNDRV_PCM_TRIGGER_SUSPEND:
1408 case SNDRV_PCM_TRIGGER_STOP:
1409 if (RME96_ISPLAYING(rme96)) {
1410 if (substream != rme96->playback_substream)
1411 return -EBUSY;
1412 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1413 : RME96_STOP_PLAYBACK);
1414 }
1415 break;
1416
1417 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1418 if (RME96_ISPLAYING(rme96))
1419 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1420 : RME96_STOP_PLAYBACK);
1421 break;
1422
1423 case SNDRV_PCM_TRIGGER_RESUME:
1424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1425 if (!RME96_ISPLAYING(rme96))
1426 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1427 : RME96_RESUME_PLAYBACK);
1428 break;
1429
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 return 0;
1435 }
1436
1437 static int
1438 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1439 int cmd)
1440 {
1441 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1442 struct snd_pcm_substream *s;
1443 bool sync;
1444
1445 snd_pcm_group_for_each_entry(s, substream) {
1446 if (snd_pcm_substream_chip(s) == rme96)
1447 snd_pcm_trigger_done(s, substream);
1448 }
1449
1450 sync = (rme96->playback_substream && rme96->capture_substream) &&
1451 (rme96->playback_substream->group ==
1452 rme96->capture_substream->group);
1453
1454 switch (cmd) {
1455 case SNDRV_PCM_TRIGGER_START:
1456 if (!RME96_ISRECORDING(rme96)) {
1457 if (substream != rme96->capture_substream)
1458 return -EBUSY;
1459 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1460 : RME96_START_CAPTURE);
1461 }
1462 break;
1463
1464 case SNDRV_PCM_TRIGGER_SUSPEND:
1465 case SNDRV_PCM_TRIGGER_STOP:
1466 if (RME96_ISRECORDING(rme96)) {
1467 if (substream != rme96->capture_substream)
1468 return -EBUSY;
1469 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1470 : RME96_STOP_CAPTURE);
1471 }
1472 break;
1473
1474 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1475 if (RME96_ISRECORDING(rme96))
1476 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1477 : RME96_STOP_CAPTURE);
1478 break;
1479
1480 case SNDRV_PCM_TRIGGER_RESUME:
1481 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1482 if (!RME96_ISRECORDING(rme96))
1483 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1484 : RME96_RESUME_CAPTURE);
1485 break;
1486
1487 default:
1488 return -EINVAL;
1489 }
1490
1491 return 0;
1492 }
1493
1494 static snd_pcm_uframes_t
1495 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1496 {
1497 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1498 return snd_rme96_playback_ptr(rme96);
1499 }
1500
1501 static snd_pcm_uframes_t
1502 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1503 {
1504 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1505 return snd_rme96_capture_ptr(rme96);
1506 }
1507
1508 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1509 .open = snd_rme96_playback_spdif_open,
1510 .close = snd_rme96_playback_close,
1511 .ioctl = snd_pcm_lib_ioctl,
1512 .hw_params = snd_rme96_playback_hw_params,
1513 .prepare = snd_rme96_playback_prepare,
1514 .trigger = snd_rme96_playback_trigger,
1515 .pointer = snd_rme96_playback_pointer,
1516 .copy = snd_rme96_playback_copy,
1517 .silence = snd_rme96_playback_silence,
1518 .mmap = snd_pcm_lib_mmap_iomem,
1519 };
1520
1521 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1522 .open = snd_rme96_capture_spdif_open,
1523 .close = snd_rme96_capture_close,
1524 .ioctl = snd_pcm_lib_ioctl,
1525 .hw_params = snd_rme96_capture_hw_params,
1526 .prepare = snd_rme96_capture_prepare,
1527 .trigger = snd_rme96_capture_trigger,
1528 .pointer = snd_rme96_capture_pointer,
1529 .copy = snd_rme96_capture_copy,
1530 .mmap = snd_pcm_lib_mmap_iomem,
1531 };
1532
1533 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1534 .open = snd_rme96_playback_adat_open,
1535 .close = snd_rme96_playback_close,
1536 .ioctl = snd_pcm_lib_ioctl,
1537 .hw_params = snd_rme96_playback_hw_params,
1538 .prepare = snd_rme96_playback_prepare,
1539 .trigger = snd_rme96_playback_trigger,
1540 .pointer = snd_rme96_playback_pointer,
1541 .copy = snd_rme96_playback_copy,
1542 .silence = snd_rme96_playback_silence,
1543 .mmap = snd_pcm_lib_mmap_iomem,
1544 };
1545
1546 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1547 .open = snd_rme96_capture_adat_open,
1548 .close = snd_rme96_capture_close,
1549 .ioctl = snd_pcm_lib_ioctl,
1550 .hw_params = snd_rme96_capture_hw_params,
1551 .prepare = snd_rme96_capture_prepare,
1552 .trigger = snd_rme96_capture_trigger,
1553 .pointer = snd_rme96_capture_pointer,
1554 .copy = snd_rme96_capture_copy,
1555 .mmap = snd_pcm_lib_mmap_iomem,
1556 };
1557
1558 static void
1559 snd_rme96_free(void *private_data)
1560 {
1561 struct rme96 *rme96 = (struct rme96 *)private_data;
1562
1563 if (rme96 == NULL) {
1564 return;
1565 }
1566 if (rme96->irq >= 0) {
1567 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1568 rme96->areg &= ~RME96_AR_DAC_EN;
1569 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1570 free_irq(rme96->irq, (void *)rme96);
1571 rme96->irq = -1;
1572 }
1573 if (rme96->iobase) {
1574 iounmap(rme96->iobase);
1575 rme96->iobase = NULL;
1576 }
1577 if (rme96->port) {
1578 pci_release_regions(rme96->pci);
1579 rme96->port = 0;
1580 }
1581 #ifdef CONFIG_PM_SLEEP
1582 vfree(rme96->playback_suspend_buffer);
1583 vfree(rme96->capture_suspend_buffer);
1584 #endif
1585 pci_disable_device(rme96->pci);
1586 }
1587
1588 static void
1589 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1590 {
1591 struct rme96 *rme96 = pcm->private_data;
1592 rme96->spdif_pcm = NULL;
1593 }
1594
1595 static void
1596 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1597 {
1598 struct rme96 *rme96 = pcm->private_data;
1599 rme96->adat_pcm = NULL;
1600 }
1601
1602 static int
1603 snd_rme96_create(struct rme96 *rme96)
1604 {
1605 struct pci_dev *pci = rme96->pci;
1606 int err;
1607
1608 rme96->irq = -1;
1609 spin_lock_init(&rme96->lock);
1610
1611 if ((err = pci_enable_device(pci)) < 0)
1612 return err;
1613
1614 if ((err = pci_request_regions(pci, "RME96")) < 0)
1615 return err;
1616 rme96->port = pci_resource_start(rme96->pci, 0);
1617
1618 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1619 if (!rme96->iobase) {
1620 dev_err(rme96->card->dev,
1621 "unable to remap memory region 0x%lx-0x%lx\n",
1622 rme96->port, rme96->port + RME96_IO_SIZE - 1);
1623 return -ENOMEM;
1624 }
1625
1626 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1627 KBUILD_MODNAME, rme96)) {
1628 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1629 return -EBUSY;
1630 }
1631 rme96->irq = pci->irq;
1632
1633 /* read the card's revision number */
1634 pci_read_config_byte(pci, 8, &rme96->rev);
1635
1636 /* set up ALSA pcm device for S/PDIF */
1637 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1638 1, 1, &rme96->spdif_pcm)) < 0)
1639 {
1640 return err;
1641 }
1642 rme96->spdif_pcm->private_data = rme96;
1643 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1644 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1645 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1646 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1647
1648 rme96->spdif_pcm->info_flags = 0;
1649
1650 /* set up ALSA pcm device for ADAT */
1651 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1652 /* ADAT is not available on the base model */
1653 rme96->adat_pcm = NULL;
1654 } else {
1655 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1656 1, 1, &rme96->adat_pcm)) < 0)
1657 {
1658 return err;
1659 }
1660 rme96->adat_pcm->private_data = rme96;
1661 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1662 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1663 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1664 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1665
1666 rme96->adat_pcm->info_flags = 0;
1667 }
1668
1669 rme96->playback_periodsize = 0;
1670 rme96->capture_periodsize = 0;
1671
1672 /* make sure playback/capture is stopped, if by some reason active */
1673 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1674
1675 /* set default values in registers */
1676 rme96->wcreg =
1677 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1678 RME96_WCR_SEL | /* normal playback */
1679 RME96_WCR_MASTER | /* set to master clock mode */
1680 RME96_WCR_INP_0; /* set coaxial input */
1681
1682 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1683
1684 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1685 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1686
1687 /* reset the ADC */
1688 writel(rme96->areg | RME96_AR_PD2,
1689 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1690 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1691
1692 /* reset and enable the DAC (order is important). */
1693 snd_rme96_reset_dac(rme96);
1694 rme96->areg |= RME96_AR_DAC_EN;
1695 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1696
1697 /* reset playback and record buffer pointers */
1698 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1699 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1700
1701 /* reset volume */
1702 rme96->vol[0] = rme96->vol[1] = 0;
1703 if (RME96_HAS_ANALOG_OUT(rme96)) {
1704 snd_rme96_apply_dac_volume(rme96);
1705 }
1706
1707 /* init switch interface */
1708 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1709 return err;
1710 }
1711
1712 /* init proc interface */
1713 snd_rme96_proc_init(rme96);
1714
1715 return 0;
1716 }
1717
1718 /*
1719 * proc interface
1720 */
1721
1722 static void
1723 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1724 {
1725 int n;
1726 struct rme96 *rme96 = entry->private_data;
1727
1728 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1729
1730 snd_iprintf(buffer, rme96->card->longname);
1731 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1732
1733 snd_iprintf(buffer, "\nGeneral settings\n");
1734 if (rme96->wcreg & RME96_WCR_IDIS) {
1735 snd_iprintf(buffer, " period size: N/A (interrupts "
1736 "disabled)\n");
1737 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1738 snd_iprintf(buffer, " period size: 2048 bytes\n");
1739 } else {
1740 snd_iprintf(buffer, " period size: 8192 bytes\n");
1741 }
1742 snd_iprintf(buffer, "\nInput settings\n");
1743 switch (snd_rme96_getinputtype(rme96)) {
1744 case RME96_INPUT_OPTICAL:
1745 snd_iprintf(buffer, " input: optical");
1746 break;
1747 case RME96_INPUT_COAXIAL:
1748 snd_iprintf(buffer, " input: coaxial");
1749 break;
1750 case RME96_INPUT_INTERNAL:
1751 snd_iprintf(buffer, " input: internal");
1752 break;
1753 case RME96_INPUT_XLR:
1754 snd_iprintf(buffer, " input: XLR");
1755 break;
1756 case RME96_INPUT_ANALOG:
1757 snd_iprintf(buffer, " input: analog");
1758 break;
1759 }
1760 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1761 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1762 } else {
1763 if (n) {
1764 snd_iprintf(buffer, " (8 channels)\n");
1765 } else {
1766 snd_iprintf(buffer, " (2 channels)\n");
1767 }
1768 snd_iprintf(buffer, " sample rate: %d Hz\n",
1769 snd_rme96_capture_getrate(rme96, &n));
1770 }
1771 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1772 snd_iprintf(buffer, " sample format: 24 bit\n");
1773 } else {
1774 snd_iprintf(buffer, " sample format: 16 bit\n");
1775 }
1776
1777 snd_iprintf(buffer, "\nOutput settings\n");
1778 if (rme96->wcreg & RME96_WCR_SEL) {
1779 snd_iprintf(buffer, " output signal: normal playback\n");
1780 } else {
1781 snd_iprintf(buffer, " output signal: same as input\n");
1782 }
1783 snd_iprintf(buffer, " sample rate: %d Hz\n",
1784 snd_rme96_playback_getrate(rme96));
1785 if (rme96->wcreg & RME96_WCR_MODE24) {
1786 snd_iprintf(buffer, " sample format: 24 bit\n");
1787 } else {
1788 snd_iprintf(buffer, " sample format: 16 bit\n");
1789 }
1790 if (rme96->areg & RME96_AR_WSEL) {
1791 snd_iprintf(buffer, " sample clock source: word clock\n");
1792 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1793 snd_iprintf(buffer, " sample clock source: internal\n");
1794 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1795 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1796 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1797 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1798 } else {
1799 snd_iprintf(buffer, " sample clock source: autosync\n");
1800 }
1801 if (rme96->wcreg & RME96_WCR_PRO) {
1802 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1803 } else {
1804 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1805 }
1806 if (rme96->wcreg & RME96_WCR_EMP) {
1807 snd_iprintf(buffer, " emphasis: on\n");
1808 } else {
1809 snd_iprintf(buffer, " emphasis: off\n");
1810 }
1811 if (rme96->wcreg & RME96_WCR_DOLBY) {
1812 snd_iprintf(buffer, " non-audio (dolby): on\n");
1813 } else {
1814 snd_iprintf(buffer, " non-audio (dolby): off\n");
1815 }
1816 if (RME96_HAS_ANALOG_IN(rme96)) {
1817 snd_iprintf(buffer, "\nAnalog output settings\n");
1818 switch (snd_rme96_getmontracks(rme96)) {
1819 case RME96_MONITOR_TRACKS_1_2:
1820 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1821 break;
1822 case RME96_MONITOR_TRACKS_3_4:
1823 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1824 break;
1825 case RME96_MONITOR_TRACKS_5_6:
1826 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1827 break;
1828 case RME96_MONITOR_TRACKS_7_8:
1829 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1830 break;
1831 }
1832 switch (snd_rme96_getattenuation(rme96)) {
1833 case RME96_ATTENUATION_0:
1834 snd_iprintf(buffer, " attenuation: 0 dB\n");
1835 break;
1836 case RME96_ATTENUATION_6:
1837 snd_iprintf(buffer, " attenuation: -6 dB\n");
1838 break;
1839 case RME96_ATTENUATION_12:
1840 snd_iprintf(buffer, " attenuation: -12 dB\n");
1841 break;
1842 case RME96_ATTENUATION_18:
1843 snd_iprintf(buffer, " attenuation: -18 dB\n");
1844 break;
1845 }
1846 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1847 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1848 }
1849 }
1850
1851 static void snd_rme96_proc_init(struct rme96 *rme96)
1852 {
1853 struct snd_info_entry *entry;
1854
1855 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1856 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1857 }
1858
1859 /*
1860 * control interface
1861 */
1862
1863 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1864
1865 static int
1866 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1867 {
1868 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1869
1870 spin_lock_irq(&rme96->lock);
1871 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1872 spin_unlock_irq(&rme96->lock);
1873 return 0;
1874 }
1875 static int
1876 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1877 {
1878 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1879 unsigned int val;
1880 int change;
1881
1882 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1883 spin_lock_irq(&rme96->lock);
1884 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1885 change = val != rme96->wcreg;
1886 rme96->wcreg = val;
1887 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1888 spin_unlock_irq(&rme96->lock);
1889 return change;
1890 }
1891
1892 static int
1893 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1894 {
1895 static const char * const _texts[5] = {
1896 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1897 };
1898 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1899 const char *texts[5] = {
1900 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1901 };
1902 int num_items;
1903
1904 switch (rme96->pci->device) {
1905 case PCI_DEVICE_ID_RME_DIGI96:
1906 case PCI_DEVICE_ID_RME_DIGI96_8:
1907 num_items = 3;
1908 break;
1909 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1910 num_items = 4;
1911 break;
1912 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1913 if (rme96->rev > 4) {
1914 /* PST */
1915 num_items = 4;
1916 texts[3] = _texts[4]; /* Analog instead of XLR */
1917 } else {
1918 /* PAD */
1919 num_items = 5;
1920 }
1921 break;
1922 default:
1923 snd_BUG();
1924 return -EINVAL;
1925 }
1926 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1927 }
1928 static int
1929 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1930 {
1931 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1932 unsigned int items = 3;
1933
1934 spin_lock_irq(&rme96->lock);
1935 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1936
1937 switch (rme96->pci->device) {
1938 case PCI_DEVICE_ID_RME_DIGI96:
1939 case PCI_DEVICE_ID_RME_DIGI96_8:
1940 items = 3;
1941 break;
1942 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1943 items = 4;
1944 break;
1945 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1946 if (rme96->rev > 4) {
1947 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1948 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1949 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1950 }
1951 items = 4;
1952 } else {
1953 items = 5;
1954 }
1955 break;
1956 default:
1957 snd_BUG();
1958 break;
1959 }
1960 if (ucontrol->value.enumerated.item[0] >= items) {
1961 ucontrol->value.enumerated.item[0] = items - 1;
1962 }
1963
1964 spin_unlock_irq(&rme96->lock);
1965 return 0;
1966 }
1967 static int
1968 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1969 {
1970 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1971 unsigned int val;
1972 int change, items = 3;
1973
1974 switch (rme96->pci->device) {
1975 case PCI_DEVICE_ID_RME_DIGI96:
1976 case PCI_DEVICE_ID_RME_DIGI96_8:
1977 items = 3;
1978 break;
1979 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1980 items = 4;
1981 break;
1982 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1983 if (rme96->rev > 4) {
1984 items = 4;
1985 } else {
1986 items = 5;
1987 }
1988 break;
1989 default:
1990 snd_BUG();
1991 break;
1992 }
1993 val = ucontrol->value.enumerated.item[0] % items;
1994
1995 /* special case for PST */
1996 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1997 if (val == RME96_INPUT_XLR) {
1998 val = RME96_INPUT_ANALOG;
1999 }
2000 }
2001
2002 spin_lock_irq(&rme96->lock);
2003 change = (int)val != snd_rme96_getinputtype(rme96);
2004 snd_rme96_setinputtype(rme96, val);
2005 spin_unlock_irq(&rme96->lock);
2006 return change;
2007 }
2008
2009 static int
2010 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2011 {
2012 static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
2013
2014 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2015 }
2016 static int
2017 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2018 {
2019 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2020
2021 spin_lock_irq(&rme96->lock);
2022 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2023 spin_unlock_irq(&rme96->lock);
2024 return 0;
2025 }
2026 static int
2027 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2028 {
2029 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2030 unsigned int val;
2031 int change;
2032
2033 val = ucontrol->value.enumerated.item[0] % 3;
2034 spin_lock_irq(&rme96->lock);
2035 change = (int)val != snd_rme96_getclockmode(rme96);
2036 snd_rme96_setclockmode(rme96, val);
2037 spin_unlock_irq(&rme96->lock);
2038 return change;
2039 }
2040
2041 static int
2042 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2043 {
2044 static const char * const texts[4] = {
2045 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2046 };
2047
2048 return snd_ctl_enum_info(uinfo, 1, 4, texts);
2049 }
2050 static int
2051 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2052 {
2053 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2054
2055 spin_lock_irq(&rme96->lock);
2056 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2057 spin_unlock_irq(&rme96->lock);
2058 return 0;
2059 }
2060 static int
2061 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2062 {
2063 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2064 unsigned int val;
2065 int change;
2066
2067 val = ucontrol->value.enumerated.item[0] % 4;
2068 spin_lock_irq(&rme96->lock);
2069
2070 change = (int)val != snd_rme96_getattenuation(rme96);
2071 snd_rme96_setattenuation(rme96, val);
2072 spin_unlock_irq(&rme96->lock);
2073 return change;
2074 }
2075
2076 static int
2077 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2078 {
2079 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2080
2081 return snd_ctl_enum_info(uinfo, 1, 4, texts);
2082 }
2083 static int
2084 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2085 {
2086 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2087
2088 spin_lock_irq(&rme96->lock);
2089 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2090 spin_unlock_irq(&rme96->lock);
2091 return 0;
2092 }
2093 static int
2094 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2095 {
2096 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2097 unsigned int val;
2098 int change;
2099
2100 val = ucontrol->value.enumerated.item[0] % 4;
2101 spin_lock_irq(&rme96->lock);
2102 change = (int)val != snd_rme96_getmontracks(rme96);
2103 snd_rme96_setmontracks(rme96, val);
2104 spin_unlock_irq(&rme96->lock);
2105 return change;
2106 }
2107
2108 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2109 {
2110 u32 val = 0;
2111 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2112 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2113 if (val & RME96_WCR_PRO)
2114 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2115 else
2116 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2117 return val;
2118 }
2119
2120 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2121 {
2122 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2123 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2124 if (val & RME96_WCR_PRO)
2125 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2126 else
2127 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2128 }
2129
2130 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2131 {
2132 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2133 uinfo->count = 1;
2134 return 0;
2135 }
2136
2137 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 {
2139 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2140
2141 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2142 return 0;
2143 }
2144
2145 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2146 {
2147 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2148 int change;
2149 u32 val;
2150
2151 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2152 spin_lock_irq(&rme96->lock);
2153 change = val != rme96->wcreg_spdif;
2154 rme96->wcreg_spdif = val;
2155 spin_unlock_irq(&rme96->lock);
2156 return change;
2157 }
2158
2159 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2160 {
2161 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2162 uinfo->count = 1;
2163 return 0;
2164 }
2165
2166 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2167 {
2168 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2169
2170 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2171 return 0;
2172 }
2173
2174 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2175 {
2176 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2177 int change;
2178 u32 val;
2179
2180 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2181 spin_lock_irq(&rme96->lock);
2182 change = val != rme96->wcreg_spdif_stream;
2183 rme96->wcreg_spdif_stream = val;
2184 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2185 rme96->wcreg |= val;
2186 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2187 spin_unlock_irq(&rme96->lock);
2188 return change;
2189 }
2190
2191 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2192 {
2193 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2194 uinfo->count = 1;
2195 return 0;
2196 }
2197
2198 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2199 {
2200 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2201 return 0;
2202 }
2203
2204 static int
2205 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2206 {
2207 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2208
2209 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2210 uinfo->count = 2;
2211 uinfo->value.integer.min = 0;
2212 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2213 return 0;
2214 }
2215
2216 static int
2217 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2218 {
2219 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2220
2221 spin_lock_irq(&rme96->lock);
2222 u->value.integer.value[0] = rme96->vol[0];
2223 u->value.integer.value[1] = rme96->vol[1];
2224 spin_unlock_irq(&rme96->lock);
2225
2226 return 0;
2227 }
2228
2229 static int
2230 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2231 {
2232 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2233 int change = 0;
2234 unsigned int vol, maxvol;
2235
2236
2237 if (!RME96_HAS_ANALOG_OUT(rme96))
2238 return -EINVAL;
2239 maxvol = RME96_185X_MAX_OUT(rme96);
2240 spin_lock_irq(&rme96->lock);
2241 vol = u->value.integer.value[0];
2242 if (vol != rme96->vol[0] && vol <= maxvol) {
2243 rme96->vol[0] = vol;
2244 change = 1;
2245 }
2246 vol = u->value.integer.value[1];
2247 if (vol != rme96->vol[1] && vol <= maxvol) {
2248 rme96->vol[1] = vol;
2249 change = 1;
2250 }
2251 if (change)
2252 snd_rme96_apply_dac_volume(rme96);
2253 spin_unlock_irq(&rme96->lock);
2254
2255 return change;
2256 }
2257
2258 static struct snd_kcontrol_new snd_rme96_controls[] = {
2259 {
2260 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2261 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2262 .info = snd_rme96_control_spdif_info,
2263 .get = snd_rme96_control_spdif_get,
2264 .put = snd_rme96_control_spdif_put
2265 },
2266 {
2267 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2268 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2269 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2270 .info = snd_rme96_control_spdif_stream_info,
2271 .get = snd_rme96_control_spdif_stream_get,
2272 .put = snd_rme96_control_spdif_stream_put
2273 },
2274 {
2275 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2276 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2277 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2278 .info = snd_rme96_control_spdif_mask_info,
2279 .get = snd_rme96_control_spdif_mask_get,
2280 .private_value = IEC958_AES0_NONAUDIO |
2281 IEC958_AES0_PROFESSIONAL |
2282 IEC958_AES0_CON_EMPHASIS
2283 },
2284 {
2285 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2286 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2287 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2288 .info = snd_rme96_control_spdif_mask_info,
2289 .get = snd_rme96_control_spdif_mask_get,
2290 .private_value = IEC958_AES0_NONAUDIO |
2291 IEC958_AES0_PROFESSIONAL |
2292 IEC958_AES0_PRO_EMPHASIS
2293 },
2294 {
2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2296 .name = "Input Connector",
2297 .info = snd_rme96_info_inputtype_control,
2298 .get = snd_rme96_get_inputtype_control,
2299 .put = snd_rme96_put_inputtype_control
2300 },
2301 {
2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2303 .name = "Loopback Input",
2304 .info = snd_rme96_info_loopback_control,
2305 .get = snd_rme96_get_loopback_control,
2306 .put = snd_rme96_put_loopback_control
2307 },
2308 {
2309 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2310 .name = "Sample Clock Source",
2311 .info = snd_rme96_info_clockmode_control,
2312 .get = snd_rme96_get_clockmode_control,
2313 .put = snd_rme96_put_clockmode_control
2314 },
2315 {
2316 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2317 .name = "Monitor Tracks",
2318 .info = snd_rme96_info_montracks_control,
2319 .get = snd_rme96_get_montracks_control,
2320 .put = snd_rme96_put_montracks_control
2321 },
2322 {
2323 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2324 .name = "Attenuation",
2325 .info = snd_rme96_info_attenuation_control,
2326 .get = snd_rme96_get_attenuation_control,
2327 .put = snd_rme96_put_attenuation_control
2328 },
2329 {
2330 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2331 .name = "DAC Playback Volume",
2332 .info = snd_rme96_dac_volume_info,
2333 .get = snd_rme96_dac_volume_get,
2334 .put = snd_rme96_dac_volume_put
2335 }
2336 };
2337
2338 static int
2339 snd_rme96_create_switches(struct snd_card *card,
2340 struct rme96 *rme96)
2341 {
2342 int idx, err;
2343 struct snd_kcontrol *kctl;
2344
2345 for (idx = 0; idx < 7; idx++) {
2346 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2347 return err;
2348 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2349 rme96->spdif_ctl = kctl;
2350 }
2351
2352 if (RME96_HAS_ANALOG_OUT(rme96)) {
2353 for (idx = 7; idx < 10; idx++)
2354 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2355 return err;
2356 }
2357
2358 return 0;
2359 }
2360
2361 /*
2362 * Card initialisation
2363 */
2364
2365 #ifdef CONFIG_PM_SLEEP
2366
2367 static int rme96_suspend(struct device *dev)
2368 {
2369 struct snd_card *card = dev_get_drvdata(dev);
2370 struct rme96 *rme96 = card->private_data;
2371
2372 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2373 snd_pcm_suspend(rme96->playback_substream);
2374 snd_pcm_suspend(rme96->capture_substream);
2375
2376 /* save capture & playback pointers */
2377 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2378 & RME96_RCR_AUDIO_ADDR_MASK;
2379 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2380 & RME96_RCR_AUDIO_ADDR_MASK;
2381
2382 /* save playback and capture buffers */
2383 memcpy_fromio(rme96->playback_suspend_buffer,
2384 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2385 memcpy_fromio(rme96->capture_suspend_buffer,
2386 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2387
2388 /* disable the DAC */
2389 rme96->areg &= ~RME96_AR_DAC_EN;
2390 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2391 return 0;
2392 }
2393
2394 static int rme96_resume(struct device *dev)
2395 {
2396 struct snd_card *card = dev_get_drvdata(dev);
2397 struct rme96 *rme96 = card->private_data;
2398
2399 /* reset playback and record buffer pointers */
2400 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2401 + rme96->playback_pointer);
2402 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2403 + rme96->capture_pointer);
2404
2405 /* restore playback and capture buffers */
2406 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2407 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2408 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2409 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2410
2411 /* reset the ADC */
2412 writel(rme96->areg | RME96_AR_PD2,
2413 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2414 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2415
2416 /* reset and enable DAC, restore analog volume */
2417 snd_rme96_reset_dac(rme96);
2418 rme96->areg |= RME96_AR_DAC_EN;
2419 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2420 if (RME96_HAS_ANALOG_OUT(rme96)) {
2421 usleep_range(3000, 10000);
2422 snd_rme96_apply_dac_volume(rme96);
2423 }
2424
2425 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2426
2427 return 0;
2428 }
2429
2430 static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2431 #define RME96_PM_OPS &rme96_pm
2432 #else
2433 #define RME96_PM_OPS NULL
2434 #endif /* CONFIG_PM_SLEEP */
2435
2436 static void snd_rme96_card_free(struct snd_card *card)
2437 {
2438 snd_rme96_free(card->private_data);
2439 }
2440
2441 static int
2442 snd_rme96_probe(struct pci_dev *pci,
2443 const struct pci_device_id *pci_id)
2444 {
2445 static int dev;
2446 struct rme96 *rme96;
2447 struct snd_card *card;
2448 int err;
2449 u8 val;
2450
2451 if (dev >= SNDRV_CARDS) {
2452 return -ENODEV;
2453 }
2454 if (!enable[dev]) {
2455 dev++;
2456 return -ENOENT;
2457 }
2458 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2459 sizeof(struct rme96), &card);
2460 if (err < 0)
2461 return err;
2462 card->private_free = snd_rme96_card_free;
2463 rme96 = card->private_data;
2464 rme96->card = card;
2465 rme96->pci = pci;
2466 if ((err = snd_rme96_create(rme96)) < 0) {
2467 snd_card_free(card);
2468 return err;
2469 }
2470
2471 #ifdef CONFIG_PM_SLEEP
2472 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2473 if (!rme96->playback_suspend_buffer) {
2474 dev_err(card->dev,
2475 "Failed to allocate playback suspend buffer!\n");
2476 snd_card_free(card);
2477 return -ENOMEM;
2478 }
2479 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2480 if (!rme96->capture_suspend_buffer) {
2481 dev_err(card->dev,
2482 "Failed to allocate capture suspend buffer!\n");
2483 snd_card_free(card);
2484 return -ENOMEM;
2485 }
2486 #endif
2487
2488 strcpy(card->driver, "Digi96");
2489 switch (rme96->pci->device) {
2490 case PCI_DEVICE_ID_RME_DIGI96:
2491 strcpy(card->shortname, "RME Digi96");
2492 break;
2493 case PCI_DEVICE_ID_RME_DIGI96_8:
2494 strcpy(card->shortname, "RME Digi96/8");
2495 break;
2496 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2497 strcpy(card->shortname, "RME Digi96/8 PRO");
2498 break;
2499 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2500 pci_read_config_byte(rme96->pci, 8, &val);
2501 if (val < 5) {
2502 strcpy(card->shortname, "RME Digi96/8 PAD");
2503 } else {
2504 strcpy(card->shortname, "RME Digi96/8 PST");
2505 }
2506 break;
2507 }
2508 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2509 rme96->port, rme96->irq);
2510
2511 if ((err = snd_card_register(card)) < 0) {
2512 snd_card_free(card);
2513 return err;
2514 }
2515 pci_set_drvdata(pci, card);
2516 dev++;
2517 return 0;
2518 }
2519
2520 static void snd_rme96_remove(struct pci_dev *pci)
2521 {
2522 snd_card_free(pci_get_drvdata(pci));
2523 }
2524
2525 static struct pci_driver rme96_driver = {
2526 .name = KBUILD_MODNAME,
2527 .id_table = snd_rme96_ids,
2528 .probe = snd_rme96_probe,
2529 .remove = snd_rme96_remove,
2530 .driver = {
2531 .pm = RME96_PM_OPS,
2532 },
2533 };
2534
2535 module_pci_driver(rme96_driver);
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