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Merge branch 'pm-cpufreq-fixes'
[deliverable/linux.git] / sound / soc / codecs / nau8825.c
1 /*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/jack.h>
29
30
31 #include "nau8825.h"
32
33 #define NAU_FREF_MAX 13500000
34 #define NAU_FVCO_MAX 100000000
35 #define NAU_FVCO_MIN 90000000
36
37 struct nau8825_fll {
38 int mclk_src;
39 int ratio;
40 int fll_frac;
41 int fll_int;
42 int clk_ref_div;
43 };
44
45 struct nau8825_fll_attr {
46 unsigned int param;
47 unsigned int val;
48 };
49
50 /* scaling for mclk from sysclk_src output */
51 static const struct nau8825_fll_attr mclk_src_scaling[] = {
52 { 1, 0x0 },
53 { 2, 0x2 },
54 { 4, 0x3 },
55 { 8, 0x4 },
56 { 16, 0x5 },
57 { 32, 0x6 },
58 { 3, 0x7 },
59 { 6, 0xa },
60 { 12, 0xb },
61 { 24, 0xc },
62 { 48, 0xd },
63 { 96, 0xe },
64 { 5, 0xf },
65 };
66
67 /* ratio for input clk freq */
68 static const struct nau8825_fll_attr fll_ratio[] = {
69 { 512000, 0x01 },
70 { 256000, 0x02 },
71 { 128000, 0x04 },
72 { 64000, 0x08 },
73 { 32000, 0x10 },
74 { 8000, 0x20 },
75 { 4000, 0x40 },
76 };
77
78 static const struct nau8825_fll_attr fll_pre_scalar[] = {
79 { 1, 0x0 },
80 { 2, 0x1 },
81 { 4, 0x2 },
82 { 8, 0x3 },
83 };
84
85 static const struct reg_default nau8825_reg_defaults[] = {
86 { NAU8825_REG_ENA_CTRL, 0x00ff },
87 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
88 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
89 { NAU8825_REG_FLL1, 0x0 },
90 { NAU8825_REG_FLL2, 0x3126 },
91 { NAU8825_REG_FLL3, 0x0008 },
92 { NAU8825_REG_FLL4, 0x0010 },
93 { NAU8825_REG_FLL5, 0x0 },
94 { NAU8825_REG_FLL6, 0x6000 },
95 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
96 { NAU8825_REG_HSD_CTRL, 0x000c },
97 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
98 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
99 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
100 { NAU8825_REG_SAR_CTRL, 0x0015 },
101 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
102 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
103 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
104 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
105 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
106 { NAU8825_REG_GPIO34_CTRL, 0x0 },
107 { NAU8825_REG_GPIO12_CTRL, 0x0 },
108 { NAU8825_REG_TDM_CTRL, 0x0 },
109 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
110 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
111 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
112 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
113 { NAU8825_REG_BIQ_CTRL, 0x0 },
114 { NAU8825_REG_BIQ_COF1, 0x0 },
115 { NAU8825_REG_BIQ_COF2, 0x0 },
116 { NAU8825_REG_BIQ_COF3, 0x0 },
117 { NAU8825_REG_BIQ_COF4, 0x0 },
118 { NAU8825_REG_BIQ_COF5, 0x0 },
119 { NAU8825_REG_BIQ_COF6, 0x0 },
120 { NAU8825_REG_BIQ_COF7, 0x0 },
121 { NAU8825_REG_BIQ_COF8, 0x0 },
122 { NAU8825_REG_BIQ_COF9, 0x0 },
123 { NAU8825_REG_BIQ_COF10, 0x0 },
124 { NAU8825_REG_ADC_RATE, 0x0010 },
125 { NAU8825_REG_DAC_CTRL1, 0x0001 },
126 { NAU8825_REG_DAC_CTRL2, 0x0 },
127 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
128 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
129 { NAU8825_REG_MUTE_CTRL, 0x0 },
130 { NAU8825_REG_HSVOL_CTRL, 0x0 },
131 { NAU8825_REG_DACL_CTRL, 0x02cf },
132 { NAU8825_REG_DACR_CTRL, 0x00cf },
133 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
134 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
135 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
136 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
137 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
138 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
139 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
140 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
141 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
142 { NAU8825_REG_CLASSG_CTRL, 0x0 },
143 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
144 { NAU8825_REG_MISC_CTRL, 0x0 },
145 { NAU8825_REG_BIAS_ADJ, 0x0 },
146 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
147 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
148 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
149 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
150 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
151 { NAU8825_REG_RDAC, 0x0008 },
152 { NAU8825_REG_MIC_BIAS, 0x0006 },
153 { NAU8825_REG_BOOST, 0x0 },
154 { NAU8825_REG_FEPGA, 0x0 },
155 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
156 { NAU8825_REG_CHARGE_PUMP, 0x0 },
157 };
158
159 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
160 {
161 switch (reg) {
162 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
163 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
164 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
165 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
166 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
167 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
168 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
169 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
170 case NAU8825_REG_MISC_CTRL:
171 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
172 case NAU8825_REG_BIAS_ADJ:
173 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
174 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
175 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
176 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
177 return true;
178 default:
179 return false;
180 }
181
182 }
183
184 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
185 {
186 switch (reg) {
187 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
188 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
189 case NAU8825_REG_INTERRUPT_MASK:
190 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
191 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
192 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
193 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
194 case NAU8825_REG_IMM_MODE_CTRL:
195 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
196 case NAU8825_REG_MISC_CTRL:
197 case NAU8825_REG_BIAS_ADJ:
198 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
199 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
200 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
201 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
202 return true;
203 default:
204 return false;
205 }
206 }
207
208 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
209 {
210 switch (reg) {
211 case NAU8825_REG_RESET:
212 case NAU8825_REG_IRQ_STATUS:
213 case NAU8825_REG_INT_CLR_KEY_STATUS:
214 case NAU8825_REG_IMM_RMS_L:
215 case NAU8825_REG_IMM_RMS_R:
216 case NAU8825_REG_I2C_DEVICE_ID:
217 case NAU8825_REG_SARDOUT_RAM_STATUS:
218 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
219 case NAU8825_REG_GENERAL_STATUS:
220 return true;
221 default:
222 return false;
223 }
224 }
225
226 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
227 struct snd_kcontrol *kcontrol, int event)
228 {
229 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
230 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
231
232 switch (event) {
233 case SND_SOC_DAPM_POST_PMU:
234 /* Prevent startup click by letting charge pump to ramp up */
235 msleep(10);
236 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
237 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
238 break;
239 case SND_SOC_DAPM_PRE_PMD:
240 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
241 NAU8825_JAMNODCLOW, 0);
242 break;
243 default:
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
250 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
251 struct snd_kcontrol *kcontrol, int event)
252 {
253 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
254 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
255
256 switch (event) {
257 case SND_SOC_DAPM_PRE_PMU:
258 /* Disables the TESTDAC to let DAC signal pass through. */
259 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
260 NAU8825_BIAS_TESTDAC_EN, 0);
261 break;
262 case SND_SOC_DAPM_POST_PMD:
263 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
264 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 return 0;
271 }
272
273 static const char * const nau8825_adc_decimation[] = {
274 "32", "64", "128", "256"
275 };
276
277 static const struct soc_enum nau8825_adc_decimation_enum =
278 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
279 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
280
281 static const char * const nau8825_dac_oversampl[] = {
282 "64", "256", "128", "", "32"
283 };
284
285 static const struct soc_enum nau8825_dac_oversampl_enum =
286 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
287 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
288
289 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
290 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
291 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
292 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
293 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
294
295 static const struct snd_kcontrol_new nau8825_controls[] = {
296 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
297 0, 0xff, 0, adc_vol_tlv),
298 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
299 12, 8, 0x0f, 0, sidetone_vol_tlv),
300 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
301 6, 0, 0x3f, 1, dac_vol_tlv),
302 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
303 8, 37, 0, fepga_gain_tlv),
304 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
305 0, 8, 0xff, 0, crosstalk_vol_tlv),
306
307 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
308 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
309 };
310
311 /* DAC Mux 0x33[9] and 0x34[9] */
312 static const char * const nau8825_dac_src[] = {
313 "DACL", "DACR",
314 };
315
316 static SOC_ENUM_SINGLE_DECL(
317 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
318 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
319
320 static SOC_ENUM_SINGLE_DECL(
321 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
322 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
323
324 static const struct snd_kcontrol_new nau8825_dacl_mux =
325 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
326
327 static const struct snd_kcontrol_new nau8825_dacr_mux =
328 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
329
330
331 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
332 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
333 15, 1),
334
335 SND_SOC_DAPM_INPUT("MIC"),
336 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
337
338 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
339 NULL, 0),
340
341 SND_SOC_DAPM_ADC("ADC", NULL, NAU8825_REG_ENA_CTRL, 8, 0),
342 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
343 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
344 0),
345
346 /* ADC for button press detection */
347 SND_SOC_DAPM_ADC("SAR", NULL, NAU8825_REG_SAR_CTRL,
348 NAU8825_SAR_ADC_EN_SFT, 0),
349
350 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
351 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
352 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
353 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
354
355 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
356 NAU8825_ENABLE_DACR_SFT, 0),
357 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
358 NAU8825_ENABLE_DACL_SFT, 0),
359 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
360
361 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
362 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
363
364 SND_SOC_DAPM_PGA_S("HP amp L", 0,
365 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
366 SND_SOC_DAPM_PGA_S("HP amp R", 0,
367 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
368
369 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
370 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
371 SND_SOC_DAPM_PRE_PMD),
372
373 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
374 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
375 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
376 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
377 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
378 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
379 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
380 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
381 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
382 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
383 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
384 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
385
386 SND_SOC_DAPM_PGA_S("Output DACL", 7,
387 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
388 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
389 SND_SOC_DAPM_PGA_S("Output DACR", 7,
390 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
392
393 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
394 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
395 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
396 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
397 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
398
399 /* High current HPOL/R boost driver */
400 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
401 NAU8825_REG_BOOST, 9, 1, NULL, 0),
402
403 /* Class G operation control*/
404 SND_SOC_DAPM_PGA_S("Class G", 10,
405 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
406
407 SND_SOC_DAPM_OUTPUT("HPOL"),
408 SND_SOC_DAPM_OUTPUT("HPOR"),
409 };
410
411 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
412 {"Frontend PGA", NULL, "MIC"},
413 {"ADC", NULL, "Frontend PGA"},
414 {"ADC", NULL, "ADC Clock"},
415 {"ADC", NULL, "ADC Power"},
416 {"AIFTX", NULL, "ADC"},
417
418 {"DDACL", NULL, "Playback"},
419 {"DDACR", NULL, "Playback"},
420 {"DDACL", NULL, "DDAC Clock"},
421 {"DDACR", NULL, "DDAC Clock"},
422 {"DACL Mux", "DACL", "DDACL"},
423 {"DACL Mux", "DACR", "DDACR"},
424 {"DACR Mux", "DACL", "DDACL"},
425 {"DACR Mux", "DACR", "DDACR"},
426 {"HP amp L", NULL, "DACL Mux"},
427 {"HP amp R", NULL, "DACR Mux"},
428 {"Charge Pump", NULL, "HP amp L"},
429 {"Charge Pump", NULL, "HP amp R"},
430 {"ADACL", NULL, "Charge Pump"},
431 {"ADACR", NULL, "Charge Pump"},
432 {"ADACL Clock", NULL, "ADACL"},
433 {"ADACR Clock", NULL, "ADACR"},
434 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
435 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
436 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
437 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
438 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
439 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
440 {"Output DACL", NULL, "Output Driver L Stage 3"},
441 {"Output DACR", NULL, "Output Driver R Stage 3"},
442 {"HPOL Pulldown", NULL, "Output DACL"},
443 {"HPOR Pulldown", NULL, "Output DACR"},
444 {"HP Boost Driver", NULL, "HPOL Pulldown"},
445 {"HP Boost Driver", NULL, "HPOR Pulldown"},
446 {"Class G", NULL, "HP Boost Driver"},
447 {"HPOL", NULL, "Class G"},
448 {"HPOR", NULL, "Class G"},
449 };
450
451 static int nau8825_hw_params(struct snd_pcm_substream *substream,
452 struct snd_pcm_hw_params *params,
453 struct snd_soc_dai *dai)
454 {
455 struct snd_soc_codec *codec = dai->codec;
456 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
457 unsigned int val_len = 0;
458
459 switch (params_width(params)) {
460 case 16:
461 val_len |= NAU8825_I2S_DL_16;
462 break;
463 case 20:
464 val_len |= NAU8825_I2S_DL_20;
465 break;
466 case 24:
467 val_len |= NAU8825_I2S_DL_24;
468 break;
469 case 32:
470 val_len |= NAU8825_I2S_DL_32;
471 break;
472 default:
473 return -EINVAL;
474 }
475
476 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
477 NAU8825_I2S_DL_MASK, val_len);
478
479 return 0;
480 }
481
482 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
483 {
484 struct snd_soc_codec *codec = codec_dai->codec;
485 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
486 unsigned int ctrl1_val = 0, ctrl2_val = 0;
487
488 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
489 case SND_SOC_DAIFMT_CBM_CFM:
490 ctrl2_val |= NAU8825_I2S_MS_MASTER;
491 break;
492 case SND_SOC_DAIFMT_CBS_CFS:
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 case SND_SOC_DAIFMT_NB_NF:
500 break;
501 case SND_SOC_DAIFMT_IB_NF:
502 ctrl1_val |= NAU8825_I2S_BP_INV;
503 break;
504 default:
505 return -EINVAL;
506 }
507
508 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
509 case SND_SOC_DAIFMT_I2S:
510 ctrl1_val |= NAU8825_I2S_DF_I2S;
511 break;
512 case SND_SOC_DAIFMT_LEFT_J:
513 ctrl1_val |= NAU8825_I2S_DF_LEFT;
514 break;
515 case SND_SOC_DAIFMT_RIGHT_J:
516 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
517 break;
518 case SND_SOC_DAIFMT_DSP_A:
519 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
520 break;
521 case SND_SOC_DAIFMT_DSP_B:
522 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
523 ctrl1_val |= NAU8825_I2S_PCMB_EN;
524 break;
525 default:
526 return -EINVAL;
527 }
528
529 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
530 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
531 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
532 ctrl1_val);
533 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
534 NAU8825_I2S_MS_MASK, ctrl2_val);
535
536 return 0;
537 }
538
539 static const struct snd_soc_dai_ops nau8825_dai_ops = {
540 .hw_params = nau8825_hw_params,
541 .set_fmt = nau8825_set_dai_fmt,
542 };
543
544 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
545 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
546 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
547
548 static struct snd_soc_dai_driver nau8825_dai = {
549 .name = "nau8825-hifi",
550 .playback = {
551 .stream_name = "Playback",
552 .channels_min = 1,
553 .channels_max = 2,
554 .rates = NAU8825_RATES,
555 .formats = NAU8825_FORMATS,
556 },
557 .capture = {
558 .stream_name = "Capture",
559 .channels_min = 1,
560 .channels_max = 1,
561 .rates = NAU8825_RATES,
562 .formats = NAU8825_FORMATS,
563 },
564 .ops = &nau8825_dai_ops,
565 };
566
567 /**
568 * nau8825_enable_jack_detect - Specify a jack for event reporting
569 *
570 * @component: component to register the jack with
571 * @jack: jack to use to report headset and button events on
572 *
573 * After this function has been called the headset insert/remove and button
574 * events will be routed to the given jack. Jack can be null to stop
575 * reporting.
576 */
577 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
578 struct snd_soc_jack *jack)
579 {
580 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
581 struct regmap *regmap = nau8825->regmap;
582
583 nau8825->jack = jack;
584
585 /* Ground HP Outputs[1:0], needed for headset auto detection
586 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
587 */
588 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
589 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
590 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
591
592 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
593 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
594
595 return 0;
596 }
597 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
598
599
600 static bool nau8825_is_jack_inserted(struct regmap *regmap)
601 {
602 int status;
603
604 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
605 return !(status & NAU8825_GPIO2JD1);
606 }
607
608 static void nau8825_restart_jack_detection(struct regmap *regmap)
609 {
610 /* this will restart the entire jack detection process including MIC/GND
611 * switching and create interrupts. We have to go from 0 to 1 and back
612 * to 0 to restart.
613 */
614 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
615 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
616 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
617 NAU8825_JACK_DET_RESTART, 0);
618 }
619
620 static void nau8825_eject_jack(struct nau8825 *nau8825)
621 {
622 struct snd_soc_dapm_context *dapm = nau8825->dapm;
623 struct regmap *regmap = nau8825->regmap;
624
625 snd_soc_dapm_disable_pin(dapm, "SAR");
626 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
627 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
628 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
629 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
630 /* ground HPL/HPR, MICGRND1/2 */
631 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
632
633 snd_soc_dapm_sync(dapm);
634 }
635
636 static int nau8825_button_decode(int value)
637 {
638 int buttons = 0;
639
640 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
641 if (value & BIT(0))
642 buttons |= SND_JACK_BTN_0;
643 if (value & BIT(1))
644 buttons |= SND_JACK_BTN_1;
645 if (value & BIT(2))
646 buttons |= SND_JACK_BTN_2;
647 if (value & BIT(3))
648 buttons |= SND_JACK_BTN_3;
649 if (value & BIT(4))
650 buttons |= SND_JACK_BTN_4;
651 if (value & BIT(5))
652 buttons |= SND_JACK_BTN_5;
653
654 return buttons;
655 }
656
657 static int nau8825_jack_insert(struct nau8825 *nau8825)
658 {
659 struct regmap *regmap = nau8825->regmap;
660 struct snd_soc_dapm_context *dapm = nau8825->dapm;
661 int jack_status_reg, mic_detected;
662 int type = 0;
663
664 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
665 mic_detected = (jack_status_reg >> 10) & 3;
666
667 switch (mic_detected) {
668 case 0:
669 /* no mic */
670 type = SND_JACK_HEADPHONE;
671 break;
672 case 1:
673 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
674 type = SND_JACK_HEADSET;
675
676 /* Unground MICGND1 */
677 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
678 1 << 2);
679 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
680 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
681 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
682 NAU8825_MICBIAS_JKR2);
683 /* Attach SARADC to MICGND1 */
684 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
685 NAU8825_SAR_INPUT_MASK,
686 NAU8825_SAR_INPUT_JKR2);
687
688 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
689 snd_soc_dapm_force_enable_pin(dapm, "SAR");
690 snd_soc_dapm_sync(dapm);
691 break;
692 case 2:
693 case 3:
694 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
695 type = SND_JACK_HEADSET;
696
697 /* Unground MICGND2 */
698 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
699 2 << 2);
700 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
701 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
702 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
703 NAU8825_MICBIAS_JKSLV);
704 /* Attach SARADC to MICGND2 */
705 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
706 NAU8825_SAR_INPUT_MASK,
707 NAU8825_SAR_INPUT_JKSLV);
708
709 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
710 snd_soc_dapm_force_enable_pin(dapm, "SAR");
711 snd_soc_dapm_sync(dapm);
712 break;
713 }
714
715 /* Leaving HPOL/R grounded after jack insert by default. They will be
716 * ungrounded as part of the widget power up sequence at the beginning
717 * of playback to reduce pop.
718 */
719 return type;
720 }
721
722 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
723 SND_JACK_BTN_2 | SND_JACK_BTN_3)
724
725 static irqreturn_t nau8825_interrupt(int irq, void *data)
726 {
727 struct nau8825 *nau8825 = (struct nau8825 *)data;
728 struct regmap *regmap = nau8825->regmap;
729 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
730
731 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
732
733 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
734 NAU8825_JACK_EJECTION_DETECTED) {
735
736 nau8825_eject_jack(nau8825);
737 event_mask |= SND_JACK_HEADSET;
738 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
739 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
740 int key_status;
741
742 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
743 &key_status);
744
745 /* upper 8 bits of the register are for short pressed keys,
746 * lower 8 bits - for long pressed buttons
747 */
748 nau8825->button_pressed = nau8825_button_decode(
749 key_status >> 8);
750
751 event |= nau8825->button_pressed;
752 event_mask |= NAU8825_BUTTONS;
753 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
754 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
755 event_mask = NAU8825_BUTTONS;
756 clear_irq = NAU8825_KEY_RELEASE_IRQ;
757 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
758 if (nau8825_is_jack_inserted(regmap)) {
759 event |= nau8825_jack_insert(nau8825);
760 } else {
761 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
762 nau8825_eject_jack(nau8825);
763 }
764
765 event_mask |= SND_JACK_HEADSET;
766 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
767 }
768
769 if (!clear_irq)
770 clear_irq = active_irq;
771 /* clears the rightmost interruption */
772 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
773
774 if (event_mask)
775 snd_soc_jack_report(nau8825->jack, event, event_mask);
776
777 return IRQ_HANDLED;
778 }
779
780 static void nau8825_setup_buttons(struct nau8825 *nau8825)
781 {
782 struct regmap *regmap = nau8825->regmap;
783
784 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
785 NAU8825_SAR_TRACKING_GAIN_MASK,
786 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
787 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
788 NAU8825_SAR_COMPARE_TIME_MASK,
789 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
790 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
791 NAU8825_SAR_SAMPLING_TIME_MASK,
792 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
793
794 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
795 NAU8825_KEYDET_LEVELS_NR_MASK,
796 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
797 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
798 NAU8825_KEYDET_HYSTERESIS_MASK,
799 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
800 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
801 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
802 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
803
804 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
805 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
806 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
807 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
808 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
809 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
810 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
811 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
812
813 /* Enable short press and release interruptions */
814 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
815 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
816 0);
817 }
818
819 static void nau8825_init_regs(struct nau8825 *nau8825)
820 {
821 struct regmap *regmap = nau8825->regmap;
822
823 /* Latch IIC LSB value */
824 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
825 /* Enable Bias/Vmid */
826 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
827 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
828 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
829 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
830
831 /* VMID Tieoff */
832 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
833 NAU8825_BIAS_VMID_SEL_MASK,
834 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
835 /* Disable Boost Driver, Automatic Short circuit protection enable */
836 regmap_update_bits(regmap, NAU8825_REG_BOOST,
837 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
838 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
839 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
840 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
841
842 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
843 NAU8825_JKDET_OUTPUT_EN,
844 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
845 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
846 NAU8825_JKDET_PULL_EN,
847 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
848 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
849 NAU8825_JKDET_PULL_UP,
850 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
851 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
852 NAU8825_JACK_POLARITY,
853 /* jkdet_polarity - 1 is for active-low */
854 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
855
856 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
857 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
858 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
859 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
860 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
861 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
862
863 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
864 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
865
866 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
867 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
868
869 if (nau8825->sar_threshold_num)
870 nau8825_setup_buttons(nau8825);
871
872 /* Default oversampling/decimations settings are unusable
873 * (audible hiss). Set it to something better.
874 */
875 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
876 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
877 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
878 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
879 /* Disable DACR/L power */
880 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
881 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
882 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
883 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
884 * signal to avoid any glitches due to power up transients in both
885 * the analog and digital DAC circuit.
886 */
887 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
888 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
889 /* CICCLP off */
890 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
891 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
892
893 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
894 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
895 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
896 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
897 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
898 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
899 /* Class G timer 64ms */
900 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
901 NAU8825_CLASSG_TIMER_MASK,
902 0x20 << NAU8825_CLASSG_TIMER_SFT);
903 /* DAC clock delay 2ns, VREF */
904 regmap_update_bits(regmap, NAU8825_REG_RDAC,
905 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
906 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
907 (0x3 << NAU8825_RDAC_VREF_SFT));
908 }
909
910 static const struct regmap_config nau8825_regmap_config = {
911 .val_bits = 16,
912 .reg_bits = 16,
913
914 .max_register = NAU8825_REG_MAX,
915 .readable_reg = nau8825_readable_reg,
916 .writeable_reg = nau8825_writeable_reg,
917 .volatile_reg = nau8825_volatile_reg,
918
919 .cache_type = REGCACHE_RBTREE,
920 .reg_defaults = nau8825_reg_defaults,
921 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
922 };
923
924 static int nau8825_codec_probe(struct snd_soc_codec *codec)
925 {
926 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
927 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
928
929 nau8825->dapm = dapm;
930
931 /* The interrupt clock is gated by x1[10:8],
932 * one of them needs to be enabled all the time for
933 * interrupts to happen.
934 */
935 snd_soc_dapm_force_enable_pin(dapm, "DDACR");
936 snd_soc_dapm_sync(dapm);
937
938 /* Unmask interruptions. Handler uses dapm object so we can enable
939 * interruptions only after dapm is fully initialized.
940 */
941 regmap_write(nau8825->regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
942 nau8825_restart_jack_detection(nau8825->regmap);
943
944 return 0;
945 }
946
947 /**
948 * nau8825_calc_fll_param - Calculate FLL parameters.
949 * @fll_in: external clock provided to codec.
950 * @fs: sampling rate.
951 * @fll_param: Pointer to structure of FLL parameters.
952 *
953 * Calculate FLL parameters to configure codec.
954 *
955 * Returns 0 for success or negative error code.
956 */
957 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
958 struct nau8825_fll *fll_param)
959 {
960 u64 fvco;
961 unsigned int fref, i;
962
963 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
964 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
965 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
966 */
967 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
968 fref = fll_in / fll_pre_scalar[i].param;
969 if (fref <= NAU_FREF_MAX)
970 break;
971 }
972 if (i == ARRAY_SIZE(fll_pre_scalar))
973 return -EINVAL;
974 fll_param->clk_ref_div = fll_pre_scalar[i].val;
975
976 /* Choose the FLL ratio based on FREF */
977 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
978 if (fref >= fll_ratio[i].param)
979 break;
980 }
981 if (i == ARRAY_SIZE(fll_ratio))
982 return -EINVAL;
983 fll_param->ratio = fll_ratio[i].val;
984
985 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
986 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
987 * guaranteed across the full range of operation.
988 * FDCO = freq_out * 2 * mclk_src_scaling
989 */
990 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
991 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
992 if (NAU_FVCO_MIN < fvco && fvco < NAU_FVCO_MAX)
993 break;
994 }
995 if (i == ARRAY_SIZE(mclk_src_scaling))
996 return -EINVAL;
997 fll_param->mclk_src = mclk_src_scaling[i].val;
998
999 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1000 * input based on FDCO, FREF and FLL ratio.
1001 */
1002 fvco = div_u64(fvco << 16, fref * fll_param->ratio);
1003 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1004 fll_param->fll_frac = fvco & 0xFFFF;
1005 return 0;
1006 }
1007
1008 static void nau8825_fll_apply(struct nau8825 *nau8825,
1009 struct nau8825_fll *fll_param)
1010 {
1011 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1012 NAU8825_CLK_MCLK_SRC_MASK, fll_param->mclk_src);
1013 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1014 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1015 /* FLL 16-bit fractional input */
1016 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1017 /* FLL 10-bit integer input */
1018 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1019 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1020 /* FLL pre-scaler */
1021 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1022 NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
1023 /* select divided VCO input */
1024 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1025 NAU8825_FLL_FILTER_SW_MASK, 0x0000);
1026 /* FLL sigma delta modulator enable */
1027 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1028 NAU8825_SDM_EN_MASK, NAU8825_SDM_EN);
1029 }
1030
1031 /* freq_out must be 256*Fs in order to achieve the best performance */
1032 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1033 unsigned int freq_in, unsigned int freq_out)
1034 {
1035 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1036 struct nau8825_fll fll_param;
1037 int ret, fs;
1038
1039 fs = freq_out / 256;
1040 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1041 if (ret < 0) {
1042 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1043 return ret;
1044 }
1045 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1046 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1047 fll_param.fll_int, fll_param.clk_ref_div);
1048
1049 nau8825_fll_apply(nau8825, &fll_param);
1050 mdelay(2);
1051 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1052 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1053 return 0;
1054 }
1055
1056 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
1057 unsigned int freq)
1058 {
1059 struct regmap *regmap = nau8825->regmap;
1060 int ret;
1061
1062 switch (clk_id) {
1063 case NAU8825_CLK_MCLK:
1064 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1065 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
1066 regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1067
1068 /* We selected MCLK source but the clock itself managed externally */
1069 if (!nau8825->mclk)
1070 break;
1071
1072 if (!nau8825->mclk_freq) {
1073 ret = clk_prepare_enable(nau8825->mclk);
1074 if (ret) {
1075 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1076 return ret;
1077 }
1078 }
1079
1080 if (nau8825->mclk_freq != freq) {
1081 nau8825->mclk_freq = freq;
1082
1083 freq = clk_round_rate(nau8825->mclk, freq);
1084 ret = clk_set_rate(nau8825->mclk, freq);
1085 if (ret) {
1086 dev_err(nau8825->dev, "Unable to set mclk rate\n");
1087 return ret;
1088 }
1089 }
1090
1091 break;
1092 case NAU8825_CLK_INTERNAL:
1093 regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
1094 NAU8825_DCO_EN);
1095 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1096 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1097
1098 if (nau8825->mclk_freq) {
1099 clk_disable_unprepare(nau8825->mclk);
1100 nau8825->mclk_freq = 0;
1101 }
1102
1103 break;
1104 default:
1105 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
1106 return -EINVAL;
1107 }
1108
1109 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1110 clk_id);
1111 return 0;
1112 }
1113
1114 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1115 int source, unsigned int freq, int dir)
1116 {
1117 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1118
1119 return nau8825_configure_sysclk(nau8825, clk_id, freq);
1120 }
1121
1122 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
1123 enum snd_soc_bias_level level)
1124 {
1125 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1126 int ret;
1127
1128 switch (level) {
1129 case SND_SOC_BIAS_ON:
1130 break;
1131
1132 case SND_SOC_BIAS_PREPARE:
1133 break;
1134
1135 case SND_SOC_BIAS_STANDBY:
1136 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1137 if (nau8825->mclk_freq) {
1138 ret = clk_prepare_enable(nau8825->mclk);
1139 if (ret) {
1140 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1141 return ret;
1142 }
1143 }
1144
1145 ret = regcache_sync(nau8825->regmap);
1146 if (ret) {
1147 dev_err(codec->dev,
1148 "Failed to sync cache: %d\n", ret);
1149 return ret;
1150 }
1151 }
1152
1153 break;
1154
1155 case SND_SOC_BIAS_OFF:
1156 if (nau8825->mclk_freq)
1157 clk_disable_unprepare(nau8825->mclk);
1158
1159 regcache_mark_dirty(nau8825->regmap);
1160 break;
1161 }
1162 return 0;
1163 }
1164
1165 static struct snd_soc_codec_driver nau8825_codec_driver = {
1166 .probe = nau8825_codec_probe,
1167 .set_sysclk = nau8825_set_sysclk,
1168 .set_pll = nau8825_set_pll,
1169 .set_bias_level = nau8825_set_bias_level,
1170 .suspend_bias_off = true,
1171
1172 .controls = nau8825_controls,
1173 .num_controls = ARRAY_SIZE(nau8825_controls),
1174 .dapm_widgets = nau8825_dapm_widgets,
1175 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
1176 .dapm_routes = nau8825_dapm_routes,
1177 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
1178 };
1179
1180 static void nau8825_reset_chip(struct regmap *regmap)
1181 {
1182 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
1183 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
1184 }
1185
1186 static void nau8825_print_device_properties(struct nau8825 *nau8825)
1187 {
1188 int i;
1189 struct device *dev = nau8825->dev;
1190
1191 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
1192 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
1193 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
1194 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
1195 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
1196 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
1197
1198 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
1199 for (i = 0; i < nau8825->sar_threshold_num; i++)
1200 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
1201 nau8825->sar_threshold[i]);
1202
1203 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
1204 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
1205 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
1206 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
1207 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
1208 dev_dbg(dev, "jack-insert-debounce: %d\n",
1209 nau8825->jack_insert_debounce);
1210 dev_dbg(dev, "jack-eject-debounce: %d\n",
1211 nau8825->jack_eject_debounce);
1212 }
1213
1214 static int nau8825_read_device_properties(struct device *dev,
1215 struct nau8825 *nau8825) {
1216
1217 nau8825->jkdet_enable = device_property_read_bool(dev,
1218 "nuvoton,jkdet-enable");
1219 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
1220 "nuvoton,jkdet-pull-enable");
1221 nau8825->jkdet_pull_up = device_property_read_bool(dev,
1222 "nuvoton,jkdet-pull-up");
1223 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1224 &nau8825->jkdet_polarity);
1225 device_property_read_u32(dev, "nuvoton,micbias-voltage",
1226 &nau8825->micbias_voltage);
1227 device_property_read_u32(dev, "nuvoton,vref-impedance",
1228 &nau8825->vref_impedance);
1229 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1230 &nau8825->sar_threshold_num);
1231 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1232 nau8825->sar_threshold, nau8825->sar_threshold_num);
1233 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1234 &nau8825->sar_hysteresis);
1235 device_property_read_u32(dev, "nuvoton,sar-voltage",
1236 &nau8825->sar_voltage);
1237 device_property_read_u32(dev, "nuvoton,sar-compare-time",
1238 &nau8825->sar_compare_time);
1239 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1240 &nau8825->sar_sampling_time);
1241 device_property_read_u32(dev, "nuvoton,short-key-debounce",
1242 &nau8825->key_debounce);
1243 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1244 &nau8825->jack_insert_debounce);
1245 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1246 &nau8825->jack_eject_debounce);
1247
1248 nau8825->mclk = devm_clk_get(dev, "mclk");
1249 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
1250 return -EPROBE_DEFER;
1251 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
1252 /* The MCLK is managed externally or not used at all */
1253 nau8825->mclk = NULL;
1254 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
1255 } else if (IS_ERR(nau8825->mclk)) {
1256 return -EINVAL;
1257 }
1258
1259 return 0;
1260 }
1261
1262 static int nau8825_setup_irq(struct nau8825 *nau8825)
1263 {
1264 struct regmap *regmap = nau8825->regmap;
1265 int ret;
1266
1267 /* IRQ Output Enable */
1268 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1269 NAU8825_IRQ_OUTPUT_EN, NAU8825_IRQ_OUTPUT_EN);
1270
1271 /* Enable internal VCO needed for interruptions */
1272 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1273
1274 /* Enable DDACR needed for interrupts
1275 * It is the same as force_enable_pin("DDACR") we do later
1276 */
1277 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1278 NAU8825_ENABLE_DACR, NAU8825_ENABLE_DACR);
1279
1280 /* Chip needs one FSCLK cycle in order to generate interrupts,
1281 * as we cannot guarantee one will be provided by the system. Turning
1282 * master mode on then off enables us to generate that FSCLK cycle
1283 * with a minimum of contention on the clock bus.
1284 */
1285 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1286 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1287 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1288 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1289
1290 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
1291 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1292 "nau8825", nau8825);
1293
1294 if (ret) {
1295 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
1296 nau8825->irq, ret);
1297 return ret;
1298 }
1299
1300 return 0;
1301 }
1302
1303 static int nau8825_i2c_probe(struct i2c_client *i2c,
1304 const struct i2c_device_id *id)
1305 {
1306 struct device *dev = &i2c->dev;
1307 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
1308 int ret, value;
1309
1310 if (!nau8825) {
1311 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
1312 if (!nau8825)
1313 return -ENOMEM;
1314 ret = nau8825_read_device_properties(dev, nau8825);
1315 if (ret)
1316 return ret;
1317 }
1318
1319 i2c_set_clientdata(i2c, nau8825);
1320
1321 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
1322 if (IS_ERR(nau8825->regmap))
1323 return PTR_ERR(nau8825->regmap);
1324 nau8825->dev = dev;
1325 nau8825->irq = i2c->irq;
1326
1327 nau8825_print_device_properties(nau8825);
1328
1329 nau8825_reset_chip(nau8825->regmap);
1330 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
1331 if (ret < 0) {
1332 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
1333 ret);
1334 return ret;
1335 }
1336 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
1337 NAU8825_SOFTWARE_ID_NAU8825) {
1338 dev_err(dev, "Not a NAU8825 chip\n");
1339 return -ENODEV;
1340 }
1341
1342 nau8825_init_regs(nau8825);
1343
1344 if (i2c->irq)
1345 nau8825_setup_irq(nau8825);
1346
1347 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
1348 &nau8825_dai, 1);
1349 }
1350
1351 static int nau8825_i2c_remove(struct i2c_client *client)
1352 {
1353 snd_soc_unregister_codec(&client->dev);
1354 return 0;
1355 }
1356
1357 #ifdef CONFIG_PM_SLEEP
1358 static int nau8825_suspend(struct device *dev)
1359 {
1360 struct i2c_client *client = to_i2c_client(dev);
1361 struct nau8825 *nau8825 = dev_get_drvdata(dev);
1362
1363 disable_irq(client->irq);
1364 regcache_cache_only(nau8825->regmap, true);
1365 regcache_mark_dirty(nau8825->regmap);
1366
1367 return 0;
1368 }
1369
1370 static int nau8825_resume(struct device *dev)
1371 {
1372 struct i2c_client *client = to_i2c_client(dev);
1373 struct nau8825 *nau8825 = dev_get_drvdata(dev);
1374
1375 regcache_cache_only(nau8825->regmap, false);
1376 regcache_sync(nau8825->regmap);
1377 enable_irq(client->irq);
1378
1379 return 0;
1380 }
1381 #endif
1382
1383 static const struct dev_pm_ops nau8825_pm = {
1384 SET_SYSTEM_SLEEP_PM_OPS(nau8825_suspend, nau8825_resume)
1385 };
1386
1387 static const struct i2c_device_id nau8825_i2c_ids[] = {
1388 { "nau8825", 0 },
1389 { }
1390 };
1391
1392 #ifdef CONFIG_OF
1393 static const struct of_device_id nau8825_of_ids[] = {
1394 { .compatible = "nuvoton,nau8825", },
1395 {}
1396 };
1397 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
1398 #endif
1399
1400 #ifdef CONFIG_ACPI
1401 static const struct acpi_device_id nau8825_acpi_match[] = {
1402 { "10508825", 0 },
1403 {},
1404 };
1405 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
1406 #endif
1407
1408 static struct i2c_driver nau8825_driver = {
1409 .driver = {
1410 .name = "nau8825",
1411 .of_match_table = of_match_ptr(nau8825_of_ids),
1412 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
1413 .pm = &nau8825_pm,
1414 },
1415 .probe = nau8825_i2c_probe,
1416 .remove = nau8825_i2c_remove,
1417 .id_table = nau8825_i2c_ids,
1418 };
1419 module_i2c_driver(nau8825_driver);
1420
1421 MODULE_DESCRIPTION("ASoC nau8825 driver");
1422 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
1423 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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