sound/soc/codecs/wm8961.c

   1 /*
   2  * wm8961.c  --  WM8961 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-10 Wolfson Microelectronics, plc
   5  *
   6  * Author: Mark Brown
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Currently unimplemented features:
  13  *  - ALC
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/pm.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regmap.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30
  31 #include "wm8961.h"
  32
  33 #define WM8961_MAX_REGISTER                     0xFC
  34
  35 static const struct reg_default wm8961_reg_defaults[] = {
  36         {  0, 0x009F },     /* R0   - Left Input volume */
  37         {  1, 0x009F },     /* R1   - Right Input volume */
  38         {  2, 0x0000 },     /* R2   - LOUT1 volume */
  39         {  3, 0x0000 },     /* R3   - ROUT1 volume */
  40         {  4, 0x0020 },     /* R4   - Clocking1 */
  41         {  5, 0x0008 },     /* R5   - ADC & DAC Control 1 */
  42         {  6, 0x0000 },     /* R6   - ADC & DAC Control 2 */
  43         {  7, 0x000A },     /* R7   - Audio Interface 0 */
  44         {  8, 0x01F4 },     /* R8   - Clocking2 */
  45         {  9, 0x0000 },     /* R9   - Audio Interface 1 */
  46         { 10, 0x00FF },     /* R10  - Left DAC volume */
  47         { 11, 0x00FF },     /* R11  - Right DAC volume */
  48
  49         { 14, 0x0040 },     /* R14  - Audio Interface 2 */
  50
  51         { 17, 0x007B },     /* R17  - ALC1 */
  52         { 18, 0x0000 },     /* R18  - ALC2 */
  53         { 19, 0x0032 },     /* R19  - ALC3 */
  54         { 20, 0x0000 },     /* R20  - Noise Gate */
  55         { 21, 0x00C0 },     /* R21  - Left ADC volume */
  56         { 22, 0x00C0 },     /* R22  - Right ADC volume */
  57         { 23, 0x0120 },     /* R23  - Additional control(1) */
  58         { 24, 0x0000 },     /* R24  - Additional control(2) */
  59         { 25, 0x0000 },     /* R25  - Pwr Mgmt (1) */
  60         { 26, 0x0000 },     /* R26  - Pwr Mgmt (2) */
  61         { 27, 0x0000 },     /* R27  - Additional Control (3) */
  62         { 28, 0x0000 },     /* R28  - Anti-pop */
  63
  64         { 30, 0x005F },     /* R30  - Clocking 3 */
  65
  66         { 32, 0x0000 },     /* R32  - ADCL signal path */
  67         { 33, 0x0000 },     /* R33  - ADCR signal path */
  68
  69         { 40, 0x0000 },     /* R40  - LOUT2 volume */
  70         { 41, 0x0000 },     /* R41  - ROUT2 volume */
  71
  72         { 47, 0x0000 },     /* R47  - Pwr Mgmt (3) */
  73         { 48, 0x0023 },     /* R48  - Additional Control (4) */
  74         { 49, 0x0000 },     /* R49  - Class D Control 1 */
  75
  76         { 51, 0x0003 },     /* R51  - Class D Control 2 */
  77
  78         { 56, 0x0106 },     /* R56  - Clocking 4 */
  79         { 57, 0x0000 },     /* R57  - DSP Sidetone 0 */
  80         { 58, 0x0000 },     /* R58  - DSP Sidetone 1 */
  81
  82         { 60, 0x0000 },     /* R60  - DC Servo 0 */
  83         { 61, 0x0000 },     /* R61  - DC Servo 1 */
  84
  85         { 63, 0x015E },     /* R63  - DC Servo 3 */
  86
  87         { 65, 0x0010 },     /* R65  - DC Servo 5 */
  88
  89         { 68, 0x0003 },     /* R68  - Analogue PGA Bias */
  90         { 69, 0x0000 },     /* R69  - Analogue HP 0 */
  91
  92         { 71, 0x01FB },     /* R71  - Analogue HP 2 */
  93         { 72, 0x0000 },     /* R72  - Charge Pump 1 */
  94
  95         { 82, 0x0000 },     /* R82  - Charge Pump B */
  96
  97         { 87, 0x0000 },     /* R87  - Write Sequencer 1 */
  98         { 88, 0x0000 },     /* R88  - Write Sequencer 2 */
  99         { 89, 0x0000 },     /* R89  - Write Sequencer 3 */
 100         { 90, 0x0000 },     /* R90  - Write Sequencer 4 */
 101         { 91, 0x0000 },     /* R91  - Write Sequencer 5 */
 102         { 92, 0x0000 },     /* R92  - Write Sequencer 6 */
 103         { 93, 0x0000 },     /* R93  - Write Sequencer 7 */
 104
 105         { 252, 0x0001 },     /* R252 - General test 1 */
 106 };
 107
 108 struct wm8961_priv {
 109         struct regmap *regmap;
 110         int sysclk;
 111 };
 112
 113 static bool wm8961_volatile(struct device *dev, unsigned int reg)
 114 {
 115         switch (reg) {
 116         case WM8961_SOFTWARE_RESET:
 117         case WM8961_WRITE_SEQUENCER_7:
 118         case WM8961_DC_SERVO_1:
 119                 return true;
 120
 121         default:
 122                 return false;
 123         }
 124 }
 125
 126 static bool wm8961_readable(struct device *dev, unsigned int reg)
 127 {
 128         switch (reg) {
 129         case WM8961_LEFT_INPUT_VOLUME:
 130         case WM8961_RIGHT_INPUT_VOLUME:
 131         case WM8961_LOUT1_VOLUME:
 132         case WM8961_ROUT1_VOLUME:
 133         case WM8961_CLOCKING1:
 134         case WM8961_ADC_DAC_CONTROL_1:
 135         case WM8961_ADC_DAC_CONTROL_2:
 136         case WM8961_AUDIO_INTERFACE_0:
 137         case WM8961_CLOCKING2:
 138         case WM8961_AUDIO_INTERFACE_1:
 139         case WM8961_LEFT_DAC_VOLUME:
 140         case WM8961_RIGHT_DAC_VOLUME:
 141         case WM8961_AUDIO_INTERFACE_2:
 142         case WM8961_SOFTWARE_RESET:
 143         case WM8961_ALC1:
 144         case WM8961_ALC2:
 145         case WM8961_ALC3:
 146         case WM8961_NOISE_GATE:
 147         case WM8961_LEFT_ADC_VOLUME:
 148         case WM8961_RIGHT_ADC_VOLUME:
 149         case WM8961_ADDITIONAL_CONTROL_1:
 150         case WM8961_ADDITIONAL_CONTROL_2:
 151         case WM8961_PWR_MGMT_1:
 152         case WM8961_PWR_MGMT_2:
 153         case WM8961_ADDITIONAL_CONTROL_3:
 154         case WM8961_ANTI_POP:
 155         case WM8961_CLOCKING_3:
 156         case WM8961_ADCL_SIGNAL_PATH:
 157         case WM8961_ADCR_SIGNAL_PATH:
 158         case WM8961_LOUT2_VOLUME:
 159         case WM8961_ROUT2_VOLUME:
 160         case WM8961_PWR_MGMT_3:
 161         case WM8961_ADDITIONAL_CONTROL_4:
 162         case WM8961_CLASS_D_CONTROL_1:
 163         case WM8961_CLASS_D_CONTROL_2:
 164         case WM8961_CLOCKING_4:
 165         case WM8961_DSP_SIDETONE_0:
 166         case WM8961_DSP_SIDETONE_1:
 167         case WM8961_DC_SERVO_0:
 168         case WM8961_DC_SERVO_1:
 169         case WM8961_DC_SERVO_3:
 170         case WM8961_DC_SERVO_5:
 171         case WM8961_ANALOGUE_PGA_BIAS:
 172         case WM8961_ANALOGUE_HP_0:
 173         case WM8961_ANALOGUE_HP_2:
 174         case WM8961_CHARGE_PUMP_1:
 175         case WM8961_CHARGE_PUMP_B:
 176         case WM8961_WRITE_SEQUENCER_1:
 177         case WM8961_WRITE_SEQUENCER_2:
 178         case WM8961_WRITE_SEQUENCER_3:
 179         case WM8961_WRITE_SEQUENCER_4:
 180         case WM8961_WRITE_SEQUENCER_5:
 181         case WM8961_WRITE_SEQUENCER_6:
 182         case WM8961_WRITE_SEQUENCER_7:
 183         case WM8961_GENERAL_TEST_1:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 /*
 191  * The headphone output supports special anti-pop sequences giving
 192  * silent power up and power down.
 193  */
 194 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
 195                            struct snd_kcontrol *kcontrol, int event)
 196 {
 197         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 198         u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
 199         u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
 200         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 201         u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 202         int timeout = 500;
 203
 204         if (event & SND_SOC_DAPM_POST_PMU) {
 205                 /* Make sure the output is shorted */
 206                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 207                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 208
 209                 /* Enable the charge pump */
 210                 cp_reg |= WM8961_CP_ENA;
 211                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
 212                 mdelay(5);
 213
 214                 /* Enable the PGA */
 215                 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
 216                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 217
 218                 /* Enable the amplifier */
 219                 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
 220                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 221
 222                 /* Second stage enable */
 223                 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
 224                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 225
 226                 /* Enable the DC servo & trigger startup */
 227                 dcs_reg |=
 228                         WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
 229                         WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
 230                 dev_dbg(codec->dev, "Enabling DC servo\n");
 231
 232                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 233                 do {
 234                         msleep(1);
 235                         dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 236                 } while (--timeout &&
 237                          dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 238                                 WM8961_DCS_TRIG_STARTUP_HPL));
 239                 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 240                                WM8961_DCS_TRIG_STARTUP_HPL))
 241                         dev_err(codec->dev, "DC servo timed out\n");
 242                 else
 243                         dev_dbg(codec->dev, "DC servo startup complete\n");
 244
 245                 /* Enable the output stage */
 246                 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
 247                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 248
 249                 /* Remove the short on the output stage */
 250                 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
 251                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 252         }
 253
 254         if (event & SND_SOC_DAPM_PRE_PMD) {
 255                 /* Short the output */
 256                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 257                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 258
 259                 /* Disable the output stage */
 260                 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
 261                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 262
 263                 /* Disable DC offset cancellation */
 264                 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
 265                              WM8961_DCS_ENA_CHAN_HPL);
 266                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 267
 268                 /* Finish up */
 269                 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
 270                             WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
 271                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 272
 273                 /* Disable the PGA */
 274                 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
 275                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 276
 277                 /* Disable the charge pump */
 278                 dev_dbg(codec->dev, "Disabling charge pump\n");
 279                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
 280                              cp_reg & ~WM8961_CP_ENA);
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
 287                             struct snd_kcontrol *kcontrol, int event)
 288 {
 289         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 290         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 291         u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
 292
 293         if (event & SND_SOC_DAPM_POST_PMU) {
 294                 /* Enable the PGA */
 295                 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
 296                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 297
 298                 /* Enable the amplifier */
 299                 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
 300                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 301         }
 302
 303         if (event & SND_SOC_DAPM_PRE_PMD) {
 304                 /* Disable the amplifier */
 305                 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
 306                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 307
 308                 /* Disable the PGA */
 309                 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
 310                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 311         }
 312
 313         return 0;
 314 }
 315
 316 static const char *adc_hpf_text[] = {
 317         "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
 318 };
 319
 320 static SOC_ENUM_SINGLE_DECL(adc_hpf,
 321                             WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);
 322
 323 static const char *dac_deemph_text[] = {
 324         "None", "32kHz", "44.1kHz", "48kHz",
 325 };
 326
 327 static SOC_ENUM_SINGLE_DECL(dac_deemph,
 328                             WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);
 329
 330 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 331 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
 332 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 333 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 334 static const DECLARE_TLV_DB_RANGE(boost_tlv,
 335         0, 0, TLV_DB_SCALE_ITEM(0,  0, 0),
 336         1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
 337         2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
 338         3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)
 339 );
 340 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
 341
 342 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
 343 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 344                  0, 127, 0, out_tlv),
 345 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
 346                6, 3, 7, 0, hp_sec_tlv),
 347 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 348              7, 1, 0),
 349
 350 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 351                  0, 127, 0, out_tlv),
 352 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 353            7, 1, 0),
 354 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
 355
 356 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
 357 SOC_ENUM("DAC Deemphasis", dac_deemph),
 358 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
 359
 360 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
 361                  WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
 362
 363 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
 364 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 365
 366 SOC_DOUBLE_R_TLV("Capture Volume",
 367                  WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
 368                  1, 119, 0, adc_tlv),
 369 SOC_DOUBLE_R_TLV("Capture Boost Volume",
 370                  WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
 371                  4, 3, 0, boost_tlv),
 372 SOC_DOUBLE_R_TLV("Capture PGA Volume",
 373                  WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 374                  0, 62, 0, pga_tlv),
 375 SOC_DOUBLE_R("Capture PGA ZC Switch",
 376              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 377              6, 1, 1),
 378 SOC_DOUBLE_R("Capture PGA Switch",
 379              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 380              7, 1, 1),
 381 };
 382
 383 static const char *sidetone_text[] = {
 384         "None", "Left", "Right"
 385 };
 386
 387 static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
 388                             WM8961_DSP_SIDETONE_0, 2, sidetone_text);
 389
 390 static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
 391                             WM8961_DSP_SIDETONE_1, 2, sidetone_text);
 392
 393 static const struct snd_kcontrol_new dacl_mux =
 394         SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
 395
 396 static const struct snd_kcontrol_new dacr_mux =
 397         SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
 398
 399 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
 400 SND_SOC_DAPM_INPUT("LINPUT"),
 401 SND_SOC_DAPM_INPUT("RINPUT"),
 402
 403 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
 404
 405 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
 406 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
 407
 408 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
 409 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
 410
 411 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
 412
 413 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
 414 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
 415
 416 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
 417 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
 418
 419 /* Handle as a mono path for DCS */
 420 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
 421                    4, 0, NULL, 0, wm8961_hp_event,
 422                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 423 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
 424                    4, 0, NULL, 0, wm8961_spk_event,
 425                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 426
 427 SND_SOC_DAPM_OUTPUT("HP_L"),
 428 SND_SOC_DAPM_OUTPUT("HP_R"),
 429 SND_SOC_DAPM_OUTPUT("SPK_LN"),
 430 SND_SOC_DAPM_OUTPUT("SPK_LP"),
 431 SND_SOC_DAPM_OUTPUT("SPK_RN"),
 432 SND_SOC_DAPM_OUTPUT("SPK_RP"),
 433 };
 434
 435
 436 static const struct snd_soc_dapm_route audio_paths[] = {
 437         { "DACL", NULL, "CLK_DSP" },
 438         { "DACL", NULL, "DACL Sidetone" },
 439         { "DACR", NULL, "CLK_DSP" },
 440         { "DACR", NULL, "DACR Sidetone" },
 441
 442         { "DACL Sidetone", "Left", "ADCL" },
 443         { "DACL Sidetone", "Right", "ADCR" },
 444
 445         { "DACR Sidetone", "Left", "ADCL" },
 446         { "DACR Sidetone", "Right", "ADCR" },
 447
 448         { "HP_L", NULL, "Headphone Output" },
 449         { "HP_R", NULL, "Headphone Output" },
 450         { "Headphone Output", NULL, "DACL" },
 451         { "Headphone Output", NULL, "DACR" },
 452
 453         { "SPK_LN", NULL, "Speaker Output" },
 454         { "SPK_LP", NULL, "Speaker Output" },
 455         { "SPK_RN", NULL, "Speaker Output" },
 456         { "SPK_RP", NULL, "Speaker Output" },
 457
 458         { "Speaker Output", NULL, "DACL" },
 459         { "Speaker Output", NULL, "DACR" },
 460
 461         { "ADCL", NULL, "Left Input" },
 462         { "ADCL", NULL, "CLK_DSP" },
 463         { "ADCR", NULL, "Right Input" },
 464         { "ADCR", NULL, "CLK_DSP" },
 465
 466         { "Left Input", NULL, "LINPUT" },
 467         { "Right Input", NULL, "RINPUT" },
 468
 469 };
 470
 471 /* Values for CLK_SYS_RATE */
 472 static struct {
 473         int ratio;
 474         u16 val;
 475 } wm8961_clk_sys_ratio[] = {
 476         {  64,  0 },
 477         {  128, 1 },
 478         {  192, 2 },
 479         {  256, 3 },
 480         {  384, 4 },
 481         {  512, 5 },
 482         {  768, 6 },
 483         { 1024, 7 },
 484         { 1408, 8 },
 485         { 1536, 9 },
 486 };
 487
 488 /* Values for SAMPLE_RATE */
 489 static struct {
 490         int rate;
 491         u16 val;
 492 } wm8961_srate[] = {
 493         { 48000, 0 },
 494         { 44100, 0 },
 495         { 32000, 1 },
 496         { 22050, 2 },
 497         { 24000, 2 },
 498         { 16000, 3 },
 499         { 11250, 4 },
 500         { 12000, 4 },
 501         {  8000, 5 },
 502 };
 503
 504 static int wm8961_hw_params(struct snd_pcm_substream *substream,
 505                             struct snd_pcm_hw_params *params,
 506                             struct snd_soc_dai *dai)
 507 {
 508         struct snd_soc_codec *codec = dai->codec;
 509         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 510         int i, best, target, fs;
 511         u16 reg;
 512
 513         fs = params_rate(params);
 514
 515         if (!wm8961->sysclk) {
 516                 dev_err(codec->dev, "MCLK has not been specified\n");
 517                 return -EINVAL;
 518         }
 519
 520         /* Find the closest sample rate for the filters */
 521         best = 0;
 522         for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
 523                 if (abs(wm8961_srate[i].rate - fs) <
 524                     abs(wm8961_srate[best].rate - fs))
 525                         best = i;
 526         }
 527         reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
 528         reg &= ~WM8961_SAMPLE_RATE_MASK;
 529         reg |= wm8961_srate[best].val;
 530         snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
 531         dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
 532                 wm8961_srate[best].rate, fs);
 533
 534         /* Select a CLK_SYS/fs ratio equal to or higher than required */
 535         target = wm8961->sysclk / fs;
 536
 537         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
 538                 dev_err(codec->dev,
 539                         "SYSCLK must be at least 64*fs for DAC\n");
 540                 return -EINVAL;
 541         }
 542         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
 543                 dev_err(codec->dev,
 544                         "SYSCLK must be at least 256*fs for ADC\n");
 545                 return -EINVAL;
 546         }
 547
 548         for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
 549                 if (wm8961_clk_sys_ratio[i].ratio >= target)
 550                         break;
 551         }
 552         if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
 553                 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
 554                 return -EINVAL;
 555         }
 556         dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
 557                 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
 558                 wm8961->sysclk / fs);
 559
 560         reg = snd_soc_read(codec, WM8961_CLOCKING_4);
 561         reg &= ~WM8961_CLK_SYS_RATE_MASK;
 562         reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
 563         snd_soc_write(codec, WM8961_CLOCKING_4, reg);
 564
 565         reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 566         reg &= ~WM8961_WL_MASK;
 567         switch (params_width(params)) {
 568         case 16:
 569                 break;
 570         case 20:
 571                 reg |= 1 << WM8961_WL_SHIFT;
 572                 break;
 573         case 24:
 574                 reg |= 2 << WM8961_WL_SHIFT;
 575                 break;
 576         case 32:
 577                 reg |= 3 << WM8961_WL_SHIFT;
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582         snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
 583
 584         /* Sloping stop-band filter is recommended for <= 24kHz */
 585         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
 586         if (fs <= 24000)
 587                 reg |= WM8961_DACSLOPE;
 588         else
 589                 reg &= ~WM8961_DACSLOPE;
 590         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 591
 592         return 0;
 593 }
 594
 595 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 596                              unsigned int freq,
 597                              int dir)
 598 {
 599         struct snd_soc_codec *codec = dai->codec;
 600         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 601         u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
 602
 603         if (freq > 33000000) {
 604                 dev_err(codec->dev, "MCLK must be <33MHz\n");
 605                 return -EINVAL;
 606         }
 607
 608         if (freq > 16500000) {
 609                 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
 610                 reg |= WM8961_MCLKDIV;
 611                 freq /= 2;
 612         } else {
 613                 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
 614                 reg &= ~WM8961_MCLKDIV;
 615         }
 616
 617         snd_soc_write(codec, WM8961_CLOCKING1, reg);
 618
 619         wm8961->sysclk = freq;
 620
 621         return 0;
 622 }
 623
 624 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 625 {
 626         struct snd_soc_codec *codec = dai->codec;
 627         u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 628
 629         aif &= ~(WM8961_BCLKINV | WM8961_LRP |
 630                  WM8961_MS | WM8961_FORMAT_MASK);
 631
 632         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 633         case SND_SOC_DAIFMT_CBM_CFM:
 634                 aif |= WM8961_MS;
 635                 break;
 636         case SND_SOC_DAIFMT_CBS_CFS:
 637                 break;
 638         default:
 639                 return -EINVAL;
 640         }
 641
 642         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 643         case SND_SOC_DAIFMT_RIGHT_J:
 644                 break;
 645
 646         case SND_SOC_DAIFMT_LEFT_J:
 647                 aif |= 1;
 648                 break;
 649
 650         case SND_SOC_DAIFMT_I2S:
 651                 aif |= 2;
 652                 break;
 653
 654         case SND_SOC_DAIFMT_DSP_B:
 655                 aif |= WM8961_LRP;
 656         case SND_SOC_DAIFMT_DSP_A:
 657                 aif |= 3;
 658                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 659                 case SND_SOC_DAIFMT_NB_NF:
 660                 case SND_SOC_DAIFMT_IB_NF:
 661                         break;
 662                 default:
 663                         return -EINVAL;
 664                 }
 665                 break;
 666
 667         default:
 668                 return -EINVAL;
 669         }
 670
 671         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 672         case SND_SOC_DAIFMT_NB_NF:
 673                 break;
 674         case SND_SOC_DAIFMT_NB_IF:
 675                 aif |= WM8961_LRP;
 676                 break;
 677         case SND_SOC_DAIFMT_IB_NF:
 678                 aif |= WM8961_BCLKINV;
 679                 break;
 680         case SND_SOC_DAIFMT_IB_IF:
 681                 aif |= WM8961_BCLKINV | WM8961_LRP;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686
 687         return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
 688 }
 689
 690 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
 691 {
 692         struct snd_soc_codec *codec = dai->codec;
 693         u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
 694
 695         if (tristate)
 696                 reg |= WM8961_TRIS;
 697         else
 698                 reg &= ~WM8961_TRIS;
 699
 700         return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
 701 }
 702
 703 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
 704 {
 705         struct snd_soc_codec *codec = dai->codec;
 706         u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
 707
 708         if (mute)
 709                 reg |= WM8961_DACMU;
 710         else
 711                 reg &= ~WM8961_DACMU;
 712
 713         msleep(17);
 714
 715         return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
 716 }
 717
 718 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
 719 {
 720         struct snd_soc_codec *codec = dai->codec;
 721         u16 reg;
 722
 723         switch (div_id) {
 724         case WM8961_BCLK:
 725                 reg = snd_soc_read(codec, WM8961_CLOCKING2);
 726                 reg &= ~WM8961_BCLKDIV_MASK;
 727                 reg |= div;
 728                 snd_soc_write(codec, WM8961_CLOCKING2, reg);
 729                 break;
 730
 731         case WM8961_LRCLK:
 732                 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
 733                 reg &= ~WM8961_LRCLK_RATE_MASK;
 734                 reg |= div;
 735                 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
 736                 break;
 737
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
 746                                  enum snd_soc_bias_level level)
 747 {
 748         u16 reg;
 749
 750         /* This is all slightly unusual since we have no bypass paths
 751          * and the output amplifier structure means we can just slam
 752          * the biases straight up rather than having to ramp them
 753          * slowly.
 754          */
 755         switch (level) {
 756         case SND_SOC_BIAS_ON:
 757                 break;
 758
 759         case SND_SOC_BIAS_PREPARE:
 760                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
 761                         /* Enable bias generation */
 762                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 763                         reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
 764                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 765
 766                         /* VMID=2*50k, VREF */
 767                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 768                         reg &= ~WM8961_VMIDSEL_MASK;
 769                         reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
 770                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 771                 }
 772                 break;
 773
 774         case SND_SOC_BIAS_STANDBY:
 775                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) {
 776                         /* VREF off */
 777                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 778                         reg &= ~WM8961_VREF;
 779                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 780
 781                         /* Bias generation off */
 782                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 783                         reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
 784                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 785
 786                         /* VMID off */
 787                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 788                         reg &= ~WM8961_VMIDSEL_MASK;
 789                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 790                 }
 791                 break;
 792
 793         case SND_SOC_BIAS_OFF:
 794                 break;
 795         }
 796
 797         return 0;
 798 }
 799
 800
 801 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
 802
 803 #define WM8961_FORMATS \
 804         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 805         SNDRV_PCM_FMTBIT_S24_LE)
 806
 807 static const struct snd_soc_dai_ops wm8961_dai_ops = {
 808         .hw_params = wm8961_hw_params,
 809         .set_sysclk = wm8961_set_sysclk,
 810         .set_fmt = wm8961_set_fmt,
 811         .digital_mute = wm8961_digital_mute,
 812         .set_tristate = wm8961_set_tristate,
 813         .set_clkdiv = wm8961_set_clkdiv,
 814 };
 815
 816 static struct snd_soc_dai_driver wm8961_dai = {
 817         .name = "wm8961-hifi",
 818         .playback = {
 819                 .stream_name = "HiFi Playback",
 820                 .channels_min = 1,
 821                 .channels_max = 2,
 822                 .rates = WM8961_RATES,
 823                 .formats = WM8961_FORMATS,},
 824         .capture = {
 825                 .stream_name = "HiFi Capture",
 826                 .channels_min = 1,
 827                 .channels_max = 2,
 828                 .rates = WM8961_RATES,
 829                 .formats = WM8961_FORMATS,},
 830         .ops = &wm8961_dai_ops,
 831 };
 832
 833 static int wm8961_probe(struct snd_soc_codec *codec)
 834 {
 835         u16 reg;
 836
 837         /* Enable class W */
 838         reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
 839         reg |= WM8961_CP_DYN_PWR_MASK;
 840         snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
 841
 842         /* Latch volume update bits (right channel only, we always
 843          * write both out) and default ZC on. */
 844         reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
 845         snd_soc_write(codec, WM8961_ROUT1_VOLUME,
 846                      reg | WM8961_LO1ZC | WM8961_OUT1VU);
 847         snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
 848         reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
 849         snd_soc_write(codec, WM8961_ROUT2_VOLUME,
 850                      reg | WM8961_SPKRZC | WM8961_SPKVU);
 851         snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
 852
 853         reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
 854         snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
 855         reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
 856         snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
 857
 858         /* Use soft mute by default */
 859         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
 860         reg |= WM8961_DACSMM;
 861         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 862
 863         /* Use automatic clocking mode by default; for now this is all
 864          * we support.
 865          */
 866         reg = snd_soc_read(codec, WM8961_CLOCKING_3);
 867         reg &= ~WM8961_MANUAL_MODE;
 868         snd_soc_write(codec, WM8961_CLOCKING_3, reg);
 869
 870         return 0;
 871 }
 872
 873 #ifdef CONFIG_PM
 874
 875 static int wm8961_resume(struct snd_soc_codec *codec)
 876 {
 877         snd_soc_cache_sync(codec);
 878
 879         return 0;
 880 }
 881 #else
 882 #define wm8961_resume NULL
 883 #endif
 884
 885 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
 886         .probe =        wm8961_probe,
 887         .resume =       wm8961_resume,
 888         .set_bias_level = wm8961_set_bias_level,
 889         .suspend_bias_off = true,
 890
 891         .controls = wm8961_snd_controls,
 892         .num_controls = ARRAY_SIZE(wm8961_snd_controls),
 893         .dapm_widgets = wm8961_dapm_widgets,
 894         .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets),
 895         .dapm_routes = audio_paths,
 896         .num_dapm_routes = ARRAY_SIZE(audio_paths),
 897 };
 898
 899 static const struct regmap_config wm8961_regmap = {
 900         .reg_bits = 8,
 901         .val_bits = 16,
 902         .max_register = WM8961_MAX_REGISTER,
 903
 904         .reg_defaults = wm8961_reg_defaults,
 905         .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
 906         .cache_type = REGCACHE_RBTREE,
 907
 908         .volatile_reg = wm8961_volatile,
 909         .readable_reg = wm8961_readable,
 910 };
 911
 912 static int wm8961_i2c_probe(struct i2c_client *i2c,
 913                             const struct i2c_device_id *id)
 914 {
 915         struct wm8961_priv *wm8961;
 916         unsigned int val;
 917         int ret;
 918
 919         wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
 920                               GFP_KERNEL);
 921         if (wm8961 == NULL)
 922                 return -ENOMEM;
 923
 924         wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
 925         if (IS_ERR(wm8961->regmap))
 926                 return PTR_ERR(wm8961->regmap);
 927
 928         ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
 929         if (ret != 0) {
 930                 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
 931                 return ret;
 932         }
 933
 934         if (val != 0x1801) {
 935                 dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
 936                 return -EINVAL;
 937         }
 938
 939         /* This isn't volatile - readback doesn't correspond to write */
 940         regcache_cache_bypass(wm8961->regmap, true);
 941         ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
 942         regcache_cache_bypass(wm8961->regmap, false);
 943
 944         if (ret != 0) {
 945                 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
 946                 return ret;
 947         }
 948
 949         dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
 950                  (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
 951                  ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
 952                  + 'A');
 953
 954         ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
 955         if (ret != 0) {
 956                 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
 957                 return ret;
 958         }
 959
 960         i2c_set_clientdata(i2c, wm8961);
 961
 962         ret = snd_soc_register_codec(&i2c->dev,
 963                         &soc_codec_dev_wm8961, &wm8961_dai, 1);
 964
 965         return ret;
 966 }
 967
 968 static int wm8961_i2c_remove(struct i2c_client *client)
 969 {
 970         snd_soc_unregister_codec(&client->dev);
 971
 972         return 0;
 973 }
 974
 975 static const struct i2c_device_id wm8961_i2c_id[] = {
 976         { "wm8961", 0 },
 977         { }
 978 };
 979 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
 980
 981 static struct i2c_driver wm8961_i2c_driver = {
 982         .driver = {
 983                 .name = "wm8961",
 984         },
 985         .probe =    wm8961_i2c_probe,
 986         .remove =   wm8961_i2c_remove,
 987         .id_table = wm8961_i2c_id,
 988 };
 989
 990 module_i2c_driver(wm8961_i2c_driver);
 991
 992 MODULE_DESCRIPTION("ASoC WM8961 driver");
 993 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 994 MODULE_LICENSE("GPL");