sound/soc/intel/atom/sst/sst_acpi.c

   1 /*
   2  * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  *
   6  *  Authors:    Ramesh Babu K V <Ramesh.Babu@intel.com>
   7  *  Authors:    Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/fs.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/io.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/pm_qos.h>
  31 #include <linux/dmi.h>
  32 #include <linux/acpi.h>
  33 #include <asm/platform_sst_audio.h>
  34 #include <sound/core.h>
  35 #include <sound/soc.h>
  36 #include <sound/compress_driver.h>
  37 #include <acpi/acbuffer.h>
  38 #include <acpi/platform/acenv.h>
  39 #include <acpi/platform/aclinux.h>
  40 #include <acpi/actypes.h>
  41 #include <acpi/acpi_bus.h>
  42 #include <asm/cpu_device_id.h>
  43 #include <asm/iosf_mbi.h>
  44 #include "../sst-mfld-platform.h"
  45 #include "../../common/sst-dsp.h"
  46 #include "../../common/sst-acpi.h"
  47 #include "sst.h"
  48
  49 /* LPE viewpoint addresses */
  50 #define SST_BYT_IRAM_PHY_START  0xff2c0000
  51 #define SST_BYT_IRAM_PHY_END    0xff2d4000
  52 #define SST_BYT_DRAM_PHY_START  0xff300000
  53 #define SST_BYT_DRAM_PHY_END    0xff320000
  54 #define SST_BYT_IMR_VIRT_START  0xc0000000 /* virtual addr in LPE */
  55 #define SST_BYT_IMR_VIRT_END    0xc01fffff
  56 #define SST_BYT_SHIM_PHY_ADDR   0xff340000
  57 #define SST_BYT_MBOX_PHY_ADDR   0xff344000
  58 #define SST_BYT_DMA0_PHY_ADDR   0xff298000
  59 #define SST_BYT_DMA1_PHY_ADDR   0xff29c000
  60 #define SST_BYT_SSP0_PHY_ADDR   0xff2a0000
  61 #define SST_BYT_SSP2_PHY_ADDR   0xff2a2000
  62
  63 #define BYT_FW_MOD_TABLE_OFFSET 0x80000
  64 #define BYT_FW_MOD_TABLE_SIZE   0x100
  65 #define BYT_FW_MOD_OFFSET       (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)
  66
  67 static const struct sst_info byt_fwparse_info = {
  68         .use_elf        = false,
  69         .max_streams    = 25,
  70         .iram_start     = SST_BYT_IRAM_PHY_START,
  71         .iram_end       = SST_BYT_IRAM_PHY_END,
  72         .iram_use       = true,
  73         .dram_start     = SST_BYT_DRAM_PHY_START,
  74         .dram_end       = SST_BYT_DRAM_PHY_END,
  75         .dram_use       = true,
  76         .imr_start      = SST_BYT_IMR_VIRT_START,
  77         .imr_end        = SST_BYT_IMR_VIRT_END,
  78         .imr_use        = true,
  79         .mailbox_start  = SST_BYT_MBOX_PHY_ADDR,
  80         .num_probes     = 0,
  81         .lpe_viewpt_rqd  = true,
  82 };
  83
  84 static const struct sst_ipc_info byt_ipc_info = {
  85         .ipc_offset = 0,
  86         .mbox_recv_off = 0x400,
  87 };
  88
  89 static const struct sst_lib_dnld_info  byt_lib_dnld_info = {
  90         .mod_base           = SST_BYT_IMR_VIRT_START,
  91         .mod_end            = SST_BYT_IMR_VIRT_END,
  92         .mod_table_offset   = BYT_FW_MOD_TABLE_OFFSET,
  93         .mod_table_size     = BYT_FW_MOD_TABLE_SIZE,
  94         .mod_ddr_dnld       = false,
  95 };
  96
  97 static const struct sst_res_info byt_rvp_res_info = {
  98         .shim_offset = 0x140000,
  99         .shim_size = 0x000100,
 100         .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
 101         .ssp0_offset = 0xa0000,
 102         .ssp0_size = 0x1000,
 103         .dma0_offset = 0x98000,
 104         .dma0_size = 0x4000,
 105         .dma1_offset = 0x9c000,
 106         .dma1_size = 0x4000,
 107         .iram_offset = 0x0c0000,
 108         .iram_size = 0x14000,
 109         .dram_offset = 0x100000,
 110         .dram_size = 0x28000,
 111         .mbox_offset = 0x144000,
 112         .mbox_size = 0x1000,
 113         .acpi_lpe_res_index = 0,
 114         .acpi_ddr_index = 2,
 115         .acpi_ipc_irq_index = 5,
 116 };
 117
 118 /* BYTCR has different BIOS from BYT */
 119 static const struct sst_res_info bytcr_res_info = {
 120         .shim_offset = 0x140000,
 121         .shim_size = 0x000100,
 122         .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
 123         .ssp0_offset = 0xa0000,
 124         .ssp0_size = 0x1000,
 125         .dma0_offset = 0x98000,
 126         .dma0_size = 0x4000,
 127         .dma1_offset = 0x9c000,
 128         .dma1_size = 0x4000,
 129         .iram_offset = 0x0c0000,
 130         .iram_size = 0x14000,
 131         .dram_offset = 0x100000,
 132         .dram_size = 0x28000,
 133         .mbox_offset = 0x144000,
 134         .mbox_size = 0x1000,
 135         .acpi_lpe_res_index = 0,
 136         .acpi_ddr_index = 2,
 137         .acpi_ipc_irq_index = 0
 138 };
 139
 140 static struct sst_platform_info byt_rvp_platform_data = {
 141         .probe_data = &byt_fwparse_info,
 142         .ipc_info = &byt_ipc_info,
 143         .lib_info = &byt_lib_dnld_info,
 144         .res_info = &byt_rvp_res_info,
 145         .platform = "sst-mfld-platform",
 146 };
 147
 148 /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,
 149  * so pdata is same as Baytrail.
 150  */
 151 static struct sst_platform_info chv_platform_data = {
 152         .probe_data = &byt_fwparse_info,
 153         .ipc_info = &byt_ipc_info,
 154         .lib_info = &byt_lib_dnld_info,
 155         .res_info = &byt_rvp_res_info,
 156         .platform = "sst-mfld-platform",
 157 };
 158
 159 static int sst_platform_get_resources(struct intel_sst_drv *ctx)
 160 {
 161         struct resource *rsrc;
 162         struct platform_device *pdev = to_platform_device(ctx->dev);
 163
 164         /* All ACPI resource request here */
 165         /* Get Shim addr */
 166         rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
 167                                         ctx->pdata->res_info->acpi_lpe_res_index);
 168         if (!rsrc) {
 169                 dev_err(ctx->dev, "Invalid SHIM base from IFWI");
 170                 return -EIO;
 171         }
 172         dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
 173                                         (unsigned int)resource_size(rsrc));
 174
 175         ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
 176         ctx->iram_end =  ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
 177         dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
 178         ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base,
 179                                          ctx->pdata->res_info->iram_size);
 180         if (!ctx->iram) {
 181                 dev_err(ctx->dev, "unable to map IRAM");
 182                 return -EIO;
 183         }
 184
 185         ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
 186         ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
 187         dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
 188         ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base,
 189                                          ctx->pdata->res_info->dram_size);
 190         if (!ctx->dram) {
 191                 dev_err(ctx->dev, "unable to map DRAM");
 192                 return -EIO;
 193         }
 194
 195         ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
 196         dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
 197         ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add,
 198                                         ctx->pdata->res_info->shim_size);
 199         if (!ctx->shim) {
 200                 dev_err(ctx->dev, "unable to map SHIM");
 201                 return -EIO;
 202         }
 203
 204         /* reassign physical address to LPE viewpoint address */
 205         ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
 206
 207         /* Get mailbox addr */
 208         ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
 209         dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
 210         ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add,
 211                                             ctx->pdata->res_info->mbox_size);
 212         if (!ctx->mailbox) {
 213                 dev_err(ctx->dev, "unable to map mailbox");
 214                 return -EIO;
 215         }
 216
 217         /* reassign physical address to LPE viewpoint address */
 218         ctx->mailbox_add = ctx->info.mailbox_start;
 219
 220         rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
 221                                         ctx->pdata->res_info->acpi_ddr_index);
 222         if (!rsrc) {
 223                 dev_err(ctx->dev, "Invalid DDR base from IFWI");
 224                 return -EIO;
 225         }
 226         ctx->ddr_base = rsrc->start;
 227         ctx->ddr_end = rsrc->end;
 228         dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
 229         ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base,
 230                                         resource_size(rsrc));
 231         if (!ctx->ddr) {
 232                 dev_err(ctx->dev, "unable to map DDR");
 233                 return -EIO;
 234         }
 235
 236         /* Find the IRQ */
 237         ctx->irq_num = platform_get_irq(pdev,
 238                                 ctx->pdata->res_info->acpi_ipc_irq_index);
 239         return 0;
 240 }
 241
 242
 243 static int is_byt_cr(struct device *dev, bool *bytcr)
 244 {
 245         int status = 0;
 246
 247         if (IS_ENABLED(CONFIG_IOSF_MBI)) {
 248                 static const struct x86_cpu_id cpu_ids[] = {
 249                         { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
 250                         {}
 251                 };
 252                 int status;
 253                 u32 bios_status;
 254
 255                 if (!x86_match_cpu(cpu_ids) || !iosf_mbi_available()) {
 256                         /* bail silently */
 257                         return status;
 258                 }
 259
 260                 status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
 261                                        MBI_REG_READ, /* 0x10 */
 262                                        0x006, /* BIOS_CONFIG */
 263                                        &bios_status);
 264
 265                 if (status) {
 266                         dev_err(dev, "could not read PUNIT BIOS_CONFIG\n");
 267                 } else {
 268                         /* bits 26:27 mirror PMIC options */
 269                         bios_status = (bios_status >> 26) & 3;
 270
 271                         if ((bios_status == 1) || (bios_status == 3))
 272                                 *bytcr = true;
 273                         else
 274                                 dev_info(dev, "BYT-CR not detected\n");
 275                 }
 276         } else {
 277                 dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n");
 278         }
 279         return status;
 280 }
 281
 282
 283 static int sst_acpi_probe(struct platform_device *pdev)
 284 {
 285         struct device *dev = &pdev->dev;
 286         int ret = 0;
 287         struct intel_sst_drv *ctx;
 288         const struct acpi_device_id *id;
 289         struct sst_acpi_mach *mach;
 290         struct platform_device *mdev;
 291         struct platform_device *plat_dev;
 292         struct sst_platform_info *pdata;
 293         unsigned int dev_id;
 294         bool bytcr = false;
 295
 296         id = acpi_match_device(dev->driver->acpi_match_table, dev);
 297         if (!id)
 298                 return -ENODEV;
 299         dev_dbg(dev, "for %s", id->id);
 300
 301         mach = (struct sst_acpi_mach *)id->driver_data;
 302         mach = sst_acpi_find_machine(mach);
 303         if (mach == NULL) {
 304                 dev_err(dev, "No matching machine driver found\n");
 305                 return -ENODEV;
 306         }
 307         if (mach->machine_quirk)
 308                 mach = mach->machine_quirk(mach);
 309
 310         pdata = mach->pdata;
 311
 312         ret = kstrtouint(id->id, 16, &dev_id);
 313         if (ret < 0) {
 314                 dev_err(dev, "Unique device id conversion error: %d\n", ret);
 315                 return ret;
 316         }
 317
 318         dev_dbg(dev, "ACPI device id: %x\n", dev_id);
 319
 320         ret = sst_alloc_drv_context(&ctx, dev, dev_id);
 321         if (ret < 0)
 322                 return ret;
 323
 324         ret = is_byt_cr(dev, &bytcr);
 325         if (!((ret < 0) || (bytcr == false))) {
 326                 dev_info(dev, "Detected Baytrail-CR platform\n");
 327
 328                 /* override resource info */
 329                 byt_rvp_platform_data.res_info = &bytcr_res_info;
 330         }
 331
 332         plat_dev = platform_device_register_data(dev, pdata->platform, -1,
 333                                                 NULL, 0);
 334         if (IS_ERR(plat_dev)) {
 335                 dev_err(dev, "Failed to create machine device: %s\n",
 336                         pdata->platform);
 337                 return PTR_ERR(plat_dev);
 338         }
 339
 340         /*
 341          * Create platform device for sst machine driver,
 342          * pass machine info as pdata
 343          */
 344         mdev = platform_device_register_data(dev, mach->drv_name, -1,
 345                                         (const void *)mach, sizeof(*mach));
 346         if (IS_ERR(mdev)) {
 347                 dev_err(dev, "Failed to create machine device: %s\n",
 348                         mach->drv_name);
 349                 return PTR_ERR(mdev);
 350         }
 351
 352         /* Fill sst platform data */
 353         ctx->pdata = pdata;
 354         strcpy(ctx->firmware_name, mach->fw_filename);
 355
 356         ret = sst_platform_get_resources(ctx);
 357         if (ret)
 358                 return ret;
 359
 360         ret = sst_context_init(ctx);
 361         if (ret < 0)
 362                 return ret;
 363
 364         /* need to save shim registers in BYT */
 365         ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64),
 366                                         GFP_KERNEL);
 367         if (!ctx->shim_regs64) {
 368                 ret = -ENOMEM;
 369                 goto do_sst_cleanup;
 370         }
 371
 372         sst_configure_runtime_pm(ctx);
 373         platform_set_drvdata(pdev, ctx);
 374         return ret;
 375
 376 do_sst_cleanup:
 377         sst_context_cleanup(ctx);
 378         platform_set_drvdata(pdev, NULL);
 379         dev_err(ctx->dev, "failed with %d\n", ret);
 380         return ret;
 381 }
 382
 383 /**
 384 * intel_sst_remove - remove function
 385 *
 386 * @pdev:        platform device structure
 387 *
 388 * This function is called by OS when a device is unloaded
 389 * This frees the interrupt etc
 390 */
 391 static int sst_acpi_remove(struct platform_device *pdev)
 392 {
 393         struct intel_sst_drv *ctx;
 394
 395         ctx = platform_get_drvdata(pdev);
 396         sst_context_cleanup(ctx);
 397         platform_set_drvdata(pdev, NULL);
 398         return 0;
 399 }
 400
 401 static unsigned long cht_machine_id;
 402
 403 #define CHT_SURFACE_MACH 1
 404
 405 static int cht_surface_quirk_cb(const struct dmi_system_id *id)
 406 {
 407         cht_machine_id = CHT_SURFACE_MACH;
 408         return 1;
 409 }
 410
 411
 412 static const struct dmi_system_id cht_table[] = {
 413         {
 414                 .callback = cht_surface_quirk_cb,
 415                 .matches = {
 416                         DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
 417                         DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
 418                 },
 419         },
 420 };
 421
 422
 423 static struct sst_acpi_mach cht_surface_mach = {
 424         "10EC5640", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
 425                                                                 &chv_platform_data };
 426
 427 static struct sst_acpi_mach *cht_quirk(void *arg)
 428 {
 429         struct sst_acpi_mach *mach = arg;
 430
 431         dmi_check_system(cht_table);
 432
 433         if (cht_machine_id == CHT_SURFACE_MACH)
 434                 return &cht_surface_mach;
 435         else
 436                 return mach;
 437 }
 438
 439 static struct sst_acpi_mach sst_acpi_bytcr[] = {
 440         {"10EC5640", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
 441                                                 &byt_rvp_platform_data },
 442         {"10EC5642", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
 443                                                 &byt_rvp_platform_data },
 444         {"INTCCFFD", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
 445                                                 &byt_rvp_platform_data },
 446         {"10EC5651", "bytcr_rt5651", "intel/fw_sst_0f28.bin", "bytcr_rt5651", NULL,
 447                                                 &byt_rvp_platform_data },
 448         {},
 449 };
 450
 451 /* Cherryview-based platforms: CherryTrail and Braswell */
 452 static struct sst_acpi_mach sst_acpi_chv[] = {
 453         {"10EC5670", "cht-bsw-rt5672", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
 454                                                 &chv_platform_data },
 455         {"10EC5645", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
 456                                                 &chv_platform_data },
 457         {"10EC5650", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
 458                                                 &chv_platform_data },
 459         {"193C9890", "cht-bsw-max98090", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
 460                                                 &chv_platform_data },
 461         /* some CHT-T platforms rely on RT5640, use Baytrail machine driver */
 462         {"10EC5640", "bytcr_rt5640", "intel/fw_sst_22a8.bin", "bytcr_rt5640", cht_quirk,
 463                                                 &chv_platform_data },
 464
 465         {},
 466 };
 467
 468 static const struct acpi_device_id sst_acpi_ids[] = {
 469         { "80860F28", (unsigned long)&sst_acpi_bytcr},
 470         { "808622A8", (unsigned long) &sst_acpi_chv},
 471         { },
 472 };
 473
 474 MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);
 475
 476 static struct platform_driver sst_acpi_driver = {
 477         .driver = {
 478                 .name                   = "intel_sst_acpi",
 479                 .acpi_match_table       = ACPI_PTR(sst_acpi_ids),
 480                 .pm                     = &intel_sst_pm,
 481         },
 482         .probe  = sst_acpi_probe,
 483         .remove = sst_acpi_remove,
 484 };
 485
 486 module_platform_driver(sst_acpi_driver);
 487
 488 MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");
 489 MODULE_AUTHOR("Ramesh Babu K V");
 490 MODULE_AUTHOR("Omair Mohammed Abdullah");
 491 MODULE_LICENSE("GPL v2");
 492 MODULE_ALIAS("sst");