1 # The MIT License (MIT)
3 # Copyright (C) 2016 - Julien Desfossez <jdesfossez@efficios.com>
4 # Antoine Busque <abusque@efficios.com>
6 # Permission is hereby granted, free of charge, to any person obtaining a copy
7 # of this software and associated documentation files (the "Software"), to deal
8 # in the Software without restriction, including without limitation the rights
9 # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 # copies of the Software, and to permit persons to whom the Software is
11 # furnished to do so, subject to the following conditions:
13 # The above copyright notice and this permission notice shall be included in
14 # all copies or substantial portions of the Software.
16 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 from babeltrace
import CTFWriter
, CTFStringEncoding
33 self
._trace
_root
= tempfile
.mkdtemp()
34 self
.trace_path
= os
.path
.join(self
.trace_root
, "kernel")
36 self
.create_stream_class()
37 self
.define_base_types()
43 return self
._trace
_root
46 shutil
.rmtree(self
.trace_root
)
49 self
.writer
.flush_metadata()
52 def create_writer(self
):
53 self
.clock
= CTFWriter
.Clock("A_clock")
54 self
.clock
.description
= "Simple clock"
55 self
.writer
= CTFWriter
.Writer(self
.trace_path
)
56 self
.writer
.add_clock(self
.clock
)
57 self
.writer
.add_environment_field("Python_version",
58 str(sys
.version_info
))
59 self
.writer
.add_environment_field("tracer_major", 2)
60 self
.writer
.add_environment_field("tracer_minor", 8)
61 self
.writer
.add_environment_field("tracer_patchlevel", 0)
63 def create_stream_class(self
):
64 self
.stream_class
= CTFWriter
.StreamClass("test_stream")
65 self
.stream_class
.clock
= self
.clock
67 def define_base_types(self
):
68 self
.char8_type
= CTFWriter
.IntegerFieldDeclaration(8)
69 self
.char8_type
.signed
= True
70 self
.char8_type
.encoding
= CTFStringEncoding
.UTF8
71 self
.char8_type
.alignment
= 8
73 self
.int16_type
= CTFWriter
.IntegerFieldDeclaration(16)
74 self
.int16_type
.signed
= True
75 self
.int16_type
.alignment
= 8
77 self
.uint16_type
= CTFWriter
.IntegerFieldDeclaration(16)
78 self
.uint16_type
.signed
= False
79 self
.uint16_type
.alignment
= 8
81 self
.int32_type
= CTFWriter
.IntegerFieldDeclaration(32)
82 self
.int32_type
.signed
= True
83 self
.int32_type
.alignment
= 8
85 self
.uint32_type
= CTFWriter
.IntegerFieldDeclaration(32)
86 self
.uint32_type
.signed
= False
87 self
.uint32_type
.alignment
= 8
89 self
.int64_type
= CTFWriter
.IntegerFieldDeclaration(64)
90 self
.int64_type
.signed
= True
91 self
.int64_type
.alignment
= 8
93 self
.uint64_type
= CTFWriter
.IntegerFieldDeclaration(64)
94 self
.uint64_type
.signed
= False
95 self
.uint64_type
.alignment
= 8
97 self
.array16_type
= CTFWriter
.ArrayFieldDeclaration(self
.char8_type
,
100 self
.string_type
= CTFWriter
.StringFieldDeclaration()
102 def add_event(self
, event
):
103 event
.add_field(self
.uint32_type
, "_cpu_id")
104 self
.stream_class
.add_event_class(event
)
106 def define_sched_switch(self
):
107 self
.sched_switch
= CTFWriter
.EventClass("sched_switch")
108 self
.sched_switch
.add_field(self
.array16_type
, "_prev_comm")
109 self
.sched_switch
.add_field(self
.int32_type
, "_prev_tid")
110 self
.sched_switch
.add_field(self
.int32_type
, "_prev_prio")
111 self
.sched_switch
.add_field(self
.int64_type
, "_prev_state")
112 self
.sched_switch
.add_field(self
.array16_type
, "_next_comm")
113 self
.sched_switch
.add_field(self
.int32_type
, "_next_tid")
114 self
.sched_switch
.add_field(self
.int32_type
, "_next_prio")
115 self
.add_event(self
.sched_switch
)
117 def define_softirq_raise(self
):
118 self
.softirq_raise
= CTFWriter
.EventClass("softirq_raise")
119 self
.softirq_raise
.add_field(self
.uint32_type
, "_vec")
120 self
.add_event(self
.softirq_raise
)
122 def define_softirq_entry(self
):
123 self
.softirq_entry
= CTFWriter
.EventClass("softirq_entry")
124 self
.softirq_entry
.add_field(self
.uint32_type
, "_vec")
125 self
.add_event(self
.softirq_entry
)
127 def define_softirq_exit(self
):
128 self
.softirq_exit
= CTFWriter
.EventClass("softirq_exit")
129 self
.softirq_exit
.add_field(self
.uint32_type
, "_vec")
130 self
.add_event(self
.softirq_exit
)
132 def define_irq_handler_entry(self
):
133 self
.irq_handler_entry
= CTFWriter
.EventClass("irq_handler_entry")
134 self
.irq_handler_entry
.add_field(self
.int32_type
, "_irq")
135 self
.irq_handler_entry
.add_field(self
.string_type
, "_name")
136 self
.add_event(self
.irq_handler_entry
)
138 def define_irq_handler_exit(self
):
139 self
.irq_handler_exit
= CTFWriter
.EventClass("irq_handler_exit")
140 self
.irq_handler_exit
.add_field(self
.int32_type
, "_irq")
141 self
.irq_handler_exit
.add_field(self
.int32_type
, "_ret")
142 self
.add_event(self
.irq_handler_exit
)
144 def define_syscall_entry_write(self
):
145 self
.syscall_entry_write
= CTFWriter
.EventClass("syscall_entry_write")
146 self
.syscall_entry_write
.add_field(self
.uint32_type
, "_fd")
147 self
.syscall_entry_write
.add_field(self
.uint64_type
, "_buf")
148 self
.syscall_entry_write
.add_field(self
.uint64_type
, "_count")
149 self
.add_event(self
.syscall_entry_write
)
151 def define_syscall_exit_write(self
):
152 self
.syscall_exit_write
= CTFWriter
.EventClass("syscall_exit_write")
153 self
.syscall_exit_write
.add_field(self
.int64_type
, "_ret")
154 self
.add_event(self
.syscall_exit_write
)
156 def define_syscall_entry_read(self
):
157 self
.syscall_entry_read
= CTFWriter
.EventClass("syscall_entry_read")
158 self
.syscall_entry_read
.add_field(self
.uint32_type
, "_fd")
159 self
.syscall_entry_read
.add_field(self
.uint64_type
, "_count")
160 self
.add_event(self
.syscall_entry_read
)
162 def define_syscall_exit_read(self
):
163 self
.syscall_exit_read
= CTFWriter
.EventClass("syscall_exit_read")
164 self
.syscall_exit_read
.add_field(self
.uint64_type
, "_buf")
165 self
.syscall_exit_read
.add_field(self
.int64_type
, "_ret")
166 self
.add_event(self
.syscall_exit_read
)
168 def define_syscall_entry_open(self
):
169 self
.syscall_entry_open
= CTFWriter
.EventClass("syscall_entry_open")
170 self
.syscall_entry_open
.add_field(self
.string_type
, "_filename")
171 self
.syscall_entry_open
.add_field(self
.int32_type
, "_flags")
172 self
.syscall_entry_open
.add_field(self
.uint16_type
, "_mode")
173 self
.add_event(self
.syscall_entry_open
)
175 def define_syscall_exit_open(self
):
176 self
.syscall_exit_open
= CTFWriter
.EventClass("syscall_exit_open")
177 self
.syscall_exit_open
.add_field(self
.int64_type
, "_ret")
178 self
.add_event(self
.syscall_exit_open
)
180 def define_lttng_statedump_process_state(self
):
181 self
.lttng_statedump_process_state
= CTFWriter
.EventClass(
182 "lttng_statedump_process_state")
183 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_tid")
184 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_vtid")
185 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_pid")
186 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_vpid")
187 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_ppid")
188 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_vppid")
189 self
.lttng_statedump_process_state
.add_field(self
.array16_type
,
191 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_type")
192 self
.lttng_statedump_process_state
.add_field(self
.int32_type
, "_mode")
193 self
.lttng_statedump_process_state
.add_field(self
.int32_type
,
195 self
.lttng_statedump_process_state
.add_field(self
.int32_type
,
197 self
.lttng_statedump_process_state
.add_field(self
.int32_type
,
199 self
.add_event(self
.lttng_statedump_process_state
)
201 def define_lttng_statedump_file_descriptor(self
):
202 self
.lttng_statedump_file_descriptor
= CTFWriter
.EventClass(
203 "lttng_statedump_file_descriptor")
204 self
.lttng_statedump_file_descriptor
.add_field(self
.int32_type
, "_pid")
205 self
.lttng_statedump_file_descriptor
.add_field(self
.int32_type
, "_fd")
206 self
.lttng_statedump_file_descriptor
.add_field(self
.uint32_type
,
208 self
.lttng_statedump_file_descriptor
.add_field(self
.uint32_type
,
210 self
.lttng_statedump_file_descriptor
.add_field(self
.string_type
,
212 self
.add_event(self
.lttng_statedump_file_descriptor
)
214 def define_sched_wakeup(self
):
215 self
.sched_wakeup
= CTFWriter
.EventClass("sched_wakeup")
216 self
.sched_wakeup
.add_field(self
.array16_type
, "_comm")
217 self
.sched_wakeup
.add_field(self
.int32_type
, "_tid")
218 self
.sched_wakeup
.add_field(self
.int32_type
, "_prio")
219 self
.sched_wakeup
.add_field(self
.int32_type
, "_success")
220 self
.sched_wakeup
.add_field(self
.int32_type
, "_target_cpu")
221 self
.add_event(self
.sched_wakeup
)
223 def define_sched_waking(self
):
224 self
.sched_waking
= CTFWriter
.EventClass("sched_waking")
225 self
.sched_waking
.add_field(self
.array16_type
, "_comm")
226 self
.sched_waking
.add_field(self
.int32_type
, "_tid")
227 self
.sched_waking
.add_field(self
.int32_type
, "_prio")
228 self
.sched_waking
.add_field(self
.int32_type
, "_target_cpu")
229 self
.add_event(self
.sched_waking
)
231 def define_block_rq_complete(self
):
232 self
.block_rq_complete
= CTFWriter
.EventClass("block_rq_complete")
233 self
.block_rq_complete
.add_field(self
.uint32_type
, "_dev")
234 self
.block_rq_complete
.add_field(self
.uint64_type
, "_sector")
235 self
.block_rq_complete
.add_field(self
.uint32_type
, "_nr_sector")
236 self
.block_rq_complete
.add_field(self
.int32_type
, "_errors")
237 self
.block_rq_complete
.add_field(self
.uint32_type
, "_rwbs")
238 self
.block_rq_complete
.add_field(self
.uint64_type
, "__cmd_length")
239 self
.block_rq_complete
.add_field(self
.array16_type
, "_cmd")
240 self
.add_event(self
.block_rq_complete
)
242 def define_block_rq_issue(self
):
243 self
.block_rq_issue
= CTFWriter
.EventClass("block_rq_issue")
244 self
.block_rq_issue
.add_field(self
.uint32_type
, "_dev")
245 self
.block_rq_issue
.add_field(self
.uint64_type
, "_sector")
246 self
.block_rq_issue
.add_field(self
.uint32_type
, "_nr_sector")
247 self
.block_rq_issue
.add_field(self
.uint32_type
, "_bytes")
248 self
.block_rq_issue
.add_field(self
.int32_type
, "_tid")
249 self
.block_rq_issue
.add_field(self
.uint32_type
, "_rwbs")
250 self
.block_rq_issue
.add_field(self
.uint64_type
, "__cmd_length")
251 self
.block_rq_issue
.add_field(self
.array16_type
, "_cmd")
252 self
.block_rq_issue
.add_field(self
.array16_type
, "_comm")
253 self
.add_event(self
.block_rq_issue
)
255 def define_net_dev_xmit(self
):
256 self
.net_dev_xmit
= CTFWriter
.EventClass("net_dev_xmit")
257 self
.net_dev_xmit
.add_field(self
.uint64_type
, "_skbaddr")
258 self
.net_dev_xmit
.add_field(self
.int32_type
, "_rc")
259 self
.net_dev_xmit
.add_field(self
.uint32_type
, "_len")
260 self
.net_dev_xmit
.add_field(self
.string_type
, "_name")
261 self
.add_event(self
.net_dev_xmit
)
263 def define_netif_receive_skb(self
):
264 self
.netif_receive_skb
= CTFWriter
.EventClass("netif_receive_skb")
265 self
.netif_receive_skb
.add_field(self
.uint64_type
, "_skbaddr")
266 self
.netif_receive_skb
.add_field(self
.uint32_type
, "_len")
267 self
.netif_receive_skb
.add_field(self
.string_type
, "_name")
268 self
.add_event(self
.netif_receive_skb
)
270 def define_events(self
):
271 self
.define_sched_switch()
272 self
.define_softirq_raise()
273 self
.define_softirq_entry()
274 self
.define_softirq_exit()
275 self
.define_irq_handler_entry()
276 self
.define_irq_handler_exit()
277 self
.define_syscall_entry_write()
278 self
.define_syscall_exit_write()
279 self
.define_syscall_entry_read()
280 self
.define_syscall_exit_read()
281 self
.define_syscall_entry_open()
282 self
.define_syscall_exit_open()
283 self
.define_lttng_statedump_process_state()
284 self
.define_lttng_statedump_file_descriptor()
285 self
.define_sched_wakeup()
286 self
.define_sched_waking()
287 self
.define_block_rq_complete()
288 self
.define_block_rq_issue()
289 self
.define_net_dev_xmit()
290 self
.define_netif_receive_skb()
292 def create_stream(self
):
293 self
.stream
= self
.writer
.create_stream(self
.stream_class
)
295 def set_char_array(self
, event
, string
):
297 string
= string
[0:16]
299 string
= "%s" % (string
+ "\0" * (16 - len(string
)))
301 for i
, char
in enumerate(string
):
302 event
.field(i
).value
= ord(char
)
304 def set_int(self
, event
, value
):
307 def set_string(self
, event
, value
):
310 def write_softirq_raise(self
, time_ms
, cpu_id
, vec
):
311 event
= CTFWriter
.Event(self
.softirq_raise
)
312 self
.clock
.time
= time_ms
* 1000000
313 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
314 self
.set_int(event
.payload("_vec"), vec
)
315 self
.stream
.append_event(event
)
318 def write_softirq_entry(self
, time_ms
, cpu_id
, vec
):
319 event
= CTFWriter
.Event(self
.softirq_entry
)
320 self
.clock
.time
= time_ms
* 1000000
321 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
322 self
.set_int(event
.payload("_vec"), vec
)
323 self
.stream
.append_event(event
)
326 def write_softirq_exit(self
, time_ms
, cpu_id
, vec
):
327 event
= CTFWriter
.Event(self
.softirq_exit
)
328 self
.clock
.time
= time_ms
* 1000000
329 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
330 self
.set_int(event
.payload("_vec"), vec
)
331 self
.stream
.append_event(event
)
334 def write_irq_handler_entry(self
, time_ms
, cpu_id
, irq
, name
):
335 event
= CTFWriter
.Event(self
.irq_handler_entry
)
336 self
.clock
.time
= time_ms
* 1000000
337 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
338 self
.set_int(event
.payload("_irq"), irq
)
339 self
.set_string(event
.payload("_name"), name
)
340 self
.stream
.append_event(event
)
343 def write_irq_handler_exit(self
, time_ms
, cpu_id
, irq
, ret
):
344 event
= CTFWriter
.Event(self
.irq_handler_exit
)
345 self
.clock
.time
= time_ms
* 1000000
346 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
347 self
.set_int(event
.payload("_irq"), irq
)
348 self
.set_int(event
.payload("_ret"), ret
)
349 self
.stream
.append_event(event
)
352 def write_syscall_write(self
, time_ms
, cpu_id
, delay
, fd
, buf
, count
, ret
):
353 event_entry
= CTFWriter
.Event(self
.syscall_entry_write
)
354 self
.clock
.time
= time_ms
* 1000000
355 self
.set_int(event_entry
.payload("_cpu_id"), cpu_id
)
356 self
.set_int(event_entry
.payload("_fd"), fd
)
357 self
.set_int(event_entry
.payload("_buf"), buf
)
358 self
.set_int(event_entry
.payload("_count"), count
)
359 self
.stream
.append_event(event_entry
)
361 event_exit
= CTFWriter
.Event(self
.syscall_exit_write
)
362 self
.clock
.time
= (time_ms
+ delay
) * 1000000
363 self
.set_int(event_exit
.payload("_cpu_id"), cpu_id
)
364 self
.set_int(event_exit
.payload("_ret"), ret
)
365 self
.stream
.append_event(event_exit
)
368 def write_syscall_read(self
, time_ms
, cpu_id
, delay
, fd
, buf
, count
, ret
):
369 event_entry
= CTFWriter
.Event(self
.syscall_entry_read
)
370 self
.clock
.time
= time_ms
* 1000000
371 self
.set_int(event_entry
.payload("_cpu_id"), cpu_id
)
372 self
.set_int(event_entry
.payload("_fd"), fd
)
373 self
.set_int(event_entry
.payload("_count"), count
)
374 self
.stream
.append_event(event_entry
)
376 event_exit
= CTFWriter
.Event(self
.syscall_exit_read
)
377 self
.clock
.time
= (time_ms
+ delay
) * 1000000
378 self
.set_int(event_exit
.payload("_cpu_id"), cpu_id
)
379 self
.set_int(event_exit
.payload("_buf"), buf
)
380 self
.set_int(event_exit
.payload("_ret"), ret
)
381 self
.stream
.append_event(event_exit
)
384 def write_syscall_open(self
, time_ms
, cpu_id
, delay
, filename
, flags
,
386 event
= CTFWriter
.Event(self
.syscall_entry_open
)
387 self
.clock
.time
= time_ms
* 1000000
388 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
389 self
.set_string(event
.payload("_filename"), filename
)
390 self
.set_int(event
.payload("_flags"), flags
)
391 self
.set_int(event
.payload("_mode"), mode
)
392 self
.stream
.append_event(event
)
395 event
= CTFWriter
.Event(self
.syscall_exit_open
)
396 self
.clock
.time
= (time_ms
+ delay
) * 1000000
397 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
398 self
.set_int(event
.payload("_ret"), ret
)
399 self
.stream
.append_event(event
)
402 def write_lttng_statedump_file_descriptor(self
, time_ms
, cpu_id
, pid
, fd
,
403 flags
, fmode
, filename
):
404 event
= CTFWriter
.Event(self
.lttng_statedump_file_descriptor
)
405 self
.clock
.time
= time_ms
* 1000000
406 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
407 self
.set_int(event
.payload("_pid"), pid
)
408 self
.set_int(event
.payload("_fd"), fd
)
409 self
.set_int(event
.payload("_flags"), flags
)
410 self
.set_int(event
.payload("_fmode"), fmode
)
411 self
.set_string(event
.payload("_filename"), filename
)
412 self
.stream
.append_event(event
)
415 def write_lttng_statedump_process_state(self
, time_ms
, cpu_id
, tid
, vtid
,
416 pid
, vpid
, ppid
, vppid
, name
, type,
417 mode
, submode
, status
, ns_level
):
418 event
= CTFWriter
.Event(self
.lttng_statedump_process_state
)
419 self
.clock
.time
= time_ms
* 1000000
420 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
421 self
.set_int(event
.payload("_tid"), tid
)
422 self
.set_int(event
.payload("_vtid"), vtid
)
423 self
.set_int(event
.payload("_pid"), pid
)
424 self
.set_int(event
.payload("_vpid"), vpid
)
425 self
.set_int(event
.payload("_ppid"), ppid
)
426 self
.set_int(event
.payload("_vppid"), vppid
)
427 self
.set_char_array(event
.payload("_name"), name
)
428 self
.set_int(event
.payload("_type"), type)
429 self
.set_int(event
.payload("_mode"), mode
)
430 self
.set_int(event
.payload("_submode"), submode
)
431 self
.set_int(event
.payload("_status"), status
)
432 self
.set_int(event
.payload("_ns_level"), ns_level
)
433 self
.stream
.append_event(event
)
436 def write_sched_wakeup(self
, time_ms
, cpu_id
, comm
, tid
, prio
, target_cpu
):
437 event
= CTFWriter
.Event(self
.sched_wakeup
)
438 self
.clock
.time
= time_ms
* 1000000
439 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
440 self
.set_char_array(event
.payload("_comm"), comm
)
441 self
.set_int(event
.payload("_tid"), tid
)
442 self
.set_int(event
.payload("_prio"), prio
)
443 self
.set_int(event
.payload("_target_cpu"), target_cpu
)
444 self
.stream
.append_event(event
)
447 def write_sched_waking(self
, time_ms
, cpu_id
, comm
, tid
, prio
, target_cpu
):
448 event
= CTFWriter
.Event(self
.sched_waking
)
449 self
.clock
.time
= time_ms
* 1000000
450 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
451 self
.set_char_array(event
.payload("_comm"), comm
)
452 self
.set_int(event
.payload("_tid"), tid
)
453 self
.set_int(event
.payload("_prio"), prio
)
454 self
.set_int(event
.payload("_target_cpu"), target_cpu
)
455 self
.stream
.append_event(event
)
458 def write_block_rq_complete(self
, time_ms
, cpu_id
, dev
, sector
, nr_sector
,
459 errors
, rwbs
, _cmd_length
, cmd
):
460 event
= CTFWriter
.Event(self
.block_rq_complete
)
461 self
.clock
.time
= time_ms
* 1000000
462 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
463 self
.set_int(event
.payload("_dev"), dev
)
464 self
.set_int(event
.payload("_sector"), sector
)
465 self
.set_int(event
.payload("_nr_sector"), nr_sector
)
466 self
.set_int(event
.payload("_errors"), errors
)
467 self
.set_int(event
.payload("_rwbs"), rwbs
)
468 self
.set_int(event
.payload("__cmd_length"), _cmd_length
)
469 self
.set_char_array(event
.payload("_cmd"), cmd
)
470 self
.stream
.append_event(event
)
473 def write_block_rq_issue(self
, time_ms
, cpu_id
, dev
, sector
, nr_sector
,
474 bytes
, tid
, rwbs
, _cmd_length
, cmd
, comm
):
475 event
= CTFWriter
.Event(self
.block_rq_issue
)
476 self
.clock
.time
= time_ms
* 1000000
477 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
478 self
.set_int(event
.payload("_dev"), dev
)
479 self
.set_int(event
.payload("_sector"), sector
)
480 self
.set_int(event
.payload("_nr_sector"), nr_sector
)
481 self
.set_int(event
.payload("_bytes"), bytes
)
482 self
.set_int(event
.payload("_tid"), tid
)
483 self
.set_int(event
.payload("_rwbs"), rwbs
)
484 self
.set_int(event
.payload("__cmd_length"), _cmd_length
)
485 self
.set_char_array(event
.payload("_cmd"), cmd
)
486 self
.set_char_array(event
.payload("_comm"), comm
)
487 self
.stream
.append_event(event
)
490 def write_net_dev_xmit(self
, time_ms
, cpu_id
, skbaddr
, rc
, len, name
):
491 event
= CTFWriter
.Event(self
.net_dev_xmit
)
492 self
.clock
.time
= time_ms
* 1000000
493 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
494 self
.set_int(event
.payload("_skbaddr"), skbaddr
)
495 self
.set_int(event
.payload("_rc"), rc
)
496 self
.set_int(event
.payload("_len"), len)
497 self
.set_string(event
.payload("_name"), name
)
498 self
.stream
.append_event(event
)
501 def write_netif_receive_skb(self
, time_ms
, cpu_id
, skbaddr
, len, name
):
502 event
= CTFWriter
.Event(self
.netif_receive_skb
)
503 self
.clock
.time
= time_ms
* 1000000
504 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
505 self
.set_int(event
.payload("_skbaddr"), skbaddr
)
506 self
.set_int(event
.payload("_len"), len)
507 self
.set_string(event
.payload("_name"), name
)
508 self
.stream
.append_event(event
)
511 def write_sched_switch(self
, time_ms
, cpu_id
, prev_comm
, prev_tid
,
512 next_comm
, next_tid
, prev_prio
=20, prev_state
=1,
514 event
= CTFWriter
.Event(self
.sched_switch
)
515 self
.clock
.time
= time_ms
* 1000000
516 self
.set_char_array(event
.payload("_prev_comm"), prev_comm
)
517 self
.set_int(event
.payload("_prev_tid"), prev_tid
)
518 self
.set_int(event
.payload("_prev_prio"), prev_prio
)
519 self
.set_int(event
.payload("_prev_state"), prev_state
)
520 self
.set_char_array(event
.payload("_next_comm"), next_comm
)
521 self
.set_int(event
.payload("_next_tid"), next_tid
)
522 self
.set_int(event
.payload("_next_prio"), next_prio
)
523 self
.set_int(event
.payload("_cpu_id"), cpu_id
)
524 self
.stream
.append_event(event
)
527 def sched_switch_50pc(self
, start_time_ms
, end_time_ms
, cpu_id
, period
,
528 comm1
, tid1
, comm2
, tid2
):
529 current
= start_time_ms
530 while current
< end_time_ms
:
531 self
.write_sched_switch(current
, cpu_id
, comm1
, tid1
, comm2
, tid2
)
533 self
.write_sched_switch(current
, cpu_id
, comm2
, tid2
, comm1
, tid1
)