2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/rculist.h>
28 #include <linux/uaccess.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
33 #include <trace/events/kvm.h>
35 #include <kvm/iodev.h>
38 * How the whole thing works (courtesy of Christoffer Dall):
40 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
41 * something is pending on the CPU interface.
42 * - Interrupts that are pending on the distributor are stored on the
43 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
44 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
46 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
48 * - To calculate the oracle, we need info for each cpu from
49 * compute_pending_for_cpu, which considers:
50 * - PPI: dist->irq_pending & dist->irq_enable
51 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
52 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
53 * registers, stored on each vcpu. We only keep one bit of
54 * information per interrupt, making sure that only one vcpu can
55 * accept the interrupt.
56 * - If any of the above state changes, we must recalculate the oracle.
57 * - The same is true when injecting an interrupt, except that we only
58 * consider a single interrupt at a time. The irq_spi_cpu array
59 * contains the target CPU for each SPI.
61 * The handling of level interrupts adds some extra complexity. We
62 * need to track when the interrupt has been EOIed, so we can sample
63 * the 'line' again. This is achieved as such:
65 * - When a level interrupt is moved onto a vcpu, the corresponding
66 * bit in irq_queued is set. As long as this bit is set, the line
67 * will be ignored for further interrupts. The interrupt is injected
68 * into the vcpu with the GICH_LR_EOI bit set (generate a
69 * maintenance interrupt on EOI).
70 * - When the interrupt is EOIed, the maintenance interrupt fires,
71 * and clears the corresponding bit in irq_queued. This allows the
72 * interrupt line to be sampled again.
73 * - Note that level-triggered interrupts can also be set to pending from
74 * writes to GICD_ISPENDRn and lowering the external input line does not
75 * cause the interrupt to become inactive in such a situation.
76 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
77 * inactive as long as the external input line is held high.
80 * Initialization rules: there are multiple stages to the vgic
81 * initialization, both for the distributor and the CPU interfaces.
85 * - kvm_vgic_early_init(): initialization of static data that doesn't
86 * depend on any sizing information or emulation type. No allocation
89 * - vgic_init(): allocation and initialization of the generic data
90 * structures that depend on sizing information (number of CPUs,
91 * number of interrupts). Also initializes the vcpu specific data
92 * structures. Can be executed lazily for GICv2.
93 * [to be renamed to kvm_vgic_init??]
97 * - kvm_vgic_cpu_early_init(): initialization of static data that
98 * doesn't depend on any sizing information or emulation type. No
99 * allocation is allowed there.
104 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
105 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
106 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
107 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
108 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
110 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
);
112 static const struct vgic_ops
*vgic_ops
;
113 static const struct vgic_params
*vgic
;
115 static void add_sgi_source(struct kvm_vcpu
*vcpu
, int irq
, int source
)
117 vcpu
->kvm
->arch
.vgic
.vm_ops
.add_sgi_source(vcpu
, irq
, source
);
120 static bool queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
122 return vcpu
->kvm
->arch
.vgic
.vm_ops
.queue_sgi(vcpu
, irq
);
125 int kvm_vgic_map_resources(struct kvm
*kvm
)
127 return kvm
->arch
.vgic
.vm_ops
.map_resources(kvm
, vgic
);
131 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
132 * extracts u32s out of them.
134 * This does not work on 64-bit BE systems, because the bitmap access
135 * will store two consecutive 32-bit words with the higher-addressed
136 * register's bits at the lower index and the lower-addressed register's
137 * bits at the higher index.
139 * Therefore, swizzle the register index when accessing the 32-bit word
140 * registers to access the right register's value.
142 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
143 #define REG_OFFSET_SWIZZLE 1
145 #define REG_OFFSET_SWIZZLE 0
148 static int vgic_init_bitmap(struct vgic_bitmap
*b
, int nr_cpus
, int nr_irqs
)
152 nr_longs
= nr_cpus
+ BITS_TO_LONGS(nr_irqs
- VGIC_NR_PRIVATE_IRQS
);
154 b
->private = kzalloc(sizeof(unsigned long) * nr_longs
, GFP_KERNEL
);
158 b
->shared
= b
->private + nr_cpus
;
163 static void vgic_free_bitmap(struct vgic_bitmap
*b
)
171 * Call this function to convert a u64 value to an unsigned long * bitmask
172 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
174 * Warning: Calling this function may modify *val.
176 static unsigned long *u64_to_bitmask(u64
*val
)
178 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
179 *val
= (*val
>> 32) | (*val
<< 32);
181 return (unsigned long *)val
;
184 u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
, int cpuid
, u32 offset
)
188 return (u32
*)(x
->private + cpuid
) + REG_OFFSET_SWIZZLE
;
190 return (u32
*)(x
->shared
) + ((offset
- 1) ^ REG_OFFSET_SWIZZLE
);
193 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
196 if (irq
< VGIC_NR_PRIVATE_IRQS
)
197 return test_bit(irq
, x
->private + cpuid
);
199 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
);
202 void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
207 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
208 reg
= x
->private + cpuid
;
211 irq
-= VGIC_NR_PRIVATE_IRQS
;
220 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
222 return x
->private + cpuid
;
225 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
230 static int vgic_init_bytemap(struct vgic_bytemap
*x
, int nr_cpus
, int nr_irqs
)
234 size
= nr_cpus
* VGIC_NR_PRIVATE_IRQS
;
235 size
+= nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
237 x
->private = kzalloc(size
, GFP_KERNEL
);
241 x
->shared
= x
->private + nr_cpus
* VGIC_NR_PRIVATE_IRQS
/ sizeof(u32
);
245 static void vgic_free_bytemap(struct vgic_bytemap
*b
)
252 u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
256 if (offset
< VGIC_NR_PRIVATE_IRQS
) {
258 offset
+= cpuid
* VGIC_NR_PRIVATE_IRQS
;
261 offset
-= VGIC_NR_PRIVATE_IRQS
;
264 return reg
+ (offset
/ sizeof(u32
));
267 #define VGIC_CFG_LEVEL 0
268 #define VGIC_CFG_EDGE 1
270 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
272 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
275 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
276 return irq_val
== VGIC_CFG_EDGE
;
279 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
281 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
283 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
286 static int vgic_irq_is_queued(struct kvm_vcpu
*vcpu
, int irq
)
288 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
290 return vgic_bitmap_get_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
);
293 static int vgic_irq_is_active(struct kvm_vcpu
*vcpu
, int irq
)
295 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
297 return vgic_bitmap_get_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
);
300 static void vgic_irq_set_queued(struct kvm_vcpu
*vcpu
, int irq
)
302 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
304 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 1);
307 static void vgic_irq_clear_queued(struct kvm_vcpu
*vcpu
, int irq
)
309 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
311 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 0);
314 static void vgic_irq_set_active(struct kvm_vcpu
*vcpu
, int irq
)
316 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
318 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 1);
321 static void vgic_irq_clear_active(struct kvm_vcpu
*vcpu
, int irq
)
323 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
325 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 0);
328 static int vgic_dist_irq_get_level(struct kvm_vcpu
*vcpu
, int irq
)
330 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
332 return vgic_bitmap_get_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
);
335 static void vgic_dist_irq_set_level(struct kvm_vcpu
*vcpu
, int irq
)
337 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
339 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 1);
342 static void vgic_dist_irq_clear_level(struct kvm_vcpu
*vcpu
, int irq
)
344 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
346 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 0);
349 static int vgic_dist_irq_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
351 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
353 return vgic_bitmap_get_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
);
356 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
358 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
360 vgic_bitmap_set_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
, 0);
361 if (!vgic_dist_irq_get_level(vcpu
, irq
)) {
362 vgic_dist_irq_clear_pending(vcpu
, irq
);
363 if (!compute_pending_for_cpu(vcpu
))
364 clear_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
368 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
370 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
372 return vgic_bitmap_get_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
);
375 void vgic_dist_irq_set_pending(struct kvm_vcpu
*vcpu
, int irq
)
377 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
379 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 1);
382 void vgic_dist_irq_clear_pending(struct kvm_vcpu
*vcpu
, int irq
)
384 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
386 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 0);
389 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
391 if (irq
< VGIC_NR_PRIVATE_IRQS
)
392 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
394 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
395 vcpu
->arch
.vgic_cpu
.pending_shared
);
398 void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
400 if (irq
< VGIC_NR_PRIVATE_IRQS
)
401 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
403 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
404 vcpu
->arch
.vgic_cpu
.pending_shared
);
407 static bool vgic_can_sample_irq(struct kvm_vcpu
*vcpu
, int irq
)
409 return !vgic_irq_is_queued(vcpu
, irq
);
413 * vgic_reg_access - access vgic register
414 * @mmio: pointer to the data describing the mmio access
415 * @reg: pointer to the virtual backing of vgic distributor data
416 * @offset: least significant 2 bits used for word offset
417 * @mode: ACCESS_ mode (see defines above)
419 * Helper to make vgic register access easier using one of the access
420 * modes defined for vgic register access
421 * (read,raz,write-ignored,setbit,clearbit,write)
423 void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
424 phys_addr_t offset
, int mode
)
426 int word_offset
= (offset
& 3) * 8;
427 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
431 * Any alignment fault should have been delivered to the guest
432 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
438 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
442 if (mmio
->is_write
) {
443 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
444 switch (ACCESS_WRITE_MASK(mode
)) {
445 case ACCESS_WRITE_IGNORED
:
448 case ACCESS_WRITE_SETBIT
:
452 case ACCESS_WRITE_CLEARBIT
:
456 case ACCESS_WRITE_VALUE
:
457 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
462 switch (ACCESS_READ_MASK(mode
)) {
463 case ACCESS_READ_RAZ
:
467 case ACCESS_READ_VALUE
:
468 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
473 bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
476 vgic_reg_access(mmio
, NULL
, offset
,
477 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
481 bool vgic_handle_enable_reg(struct kvm
*kvm
, struct kvm_exit_mmio
*mmio
,
482 phys_addr_t offset
, int vcpu_id
, int access
)
485 int mode
= ACCESS_READ_VALUE
| access
;
486 struct kvm_vcpu
*target_vcpu
= kvm_get_vcpu(kvm
, vcpu_id
);
488 reg
= vgic_bitmap_get_reg(&kvm
->arch
.vgic
.irq_enabled
, vcpu_id
, offset
);
489 vgic_reg_access(mmio
, reg
, offset
, mode
);
490 if (mmio
->is_write
) {
491 if (access
& ACCESS_WRITE_CLEARBIT
) {
492 if (offset
< 4) /* Force SGI enabled */
494 vgic_retire_disabled_irqs(target_vcpu
);
496 vgic_update_state(kvm
);
503 bool vgic_handle_set_pending_reg(struct kvm
*kvm
,
504 struct kvm_exit_mmio
*mmio
,
505 phys_addr_t offset
, int vcpu_id
)
509 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
;
510 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
512 reg
= vgic_bitmap_get_reg(&dist
->irq_cfg
, vcpu_id
, offset
);
513 level_mask
= (~(*reg
));
515 /* Mark both level and edge triggered irqs as pending */
516 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
518 vgic_reg_access(mmio
, reg
, offset
, mode
);
520 if (mmio
->is_write
) {
521 /* Set the soft-pending flag only for level-triggered irqs */
522 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
524 vgic_reg_access(mmio
, reg
, offset
, mode
);
527 /* Ignore writes to SGIs */
530 *reg
|= orig
& 0xffff;
533 vgic_update_state(kvm
);
541 * If a mapped interrupt's state has been modified by the guest such that it
542 * is no longer active or pending, without it have gone through the sync path,
543 * then the map->active field must be cleared so the interrupt can be taken
546 static void vgic_handle_clear_mapped_irq(struct kvm_vcpu
*vcpu
)
548 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
549 struct list_head
*root
;
550 struct irq_phys_map_entry
*entry
;
551 struct irq_phys_map
*map
;
556 root
= &vgic_cpu
->irq_phys_map_list
;
557 list_for_each_entry_rcu(entry
, root
, entry
) {
560 if (!vgic_dist_irq_is_pending(vcpu
, map
->virt_irq
) &&
561 !vgic_irq_is_active(vcpu
, map
->virt_irq
))
568 bool vgic_handle_clear_pending_reg(struct kvm
*kvm
,
569 struct kvm_exit_mmio
*mmio
,
570 phys_addr_t offset
, int vcpu_id
)
574 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
;
575 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
577 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
579 vgic_reg_access(mmio
, reg
, offset
, mode
);
580 if (mmio
->is_write
) {
581 /* Re-set level triggered level-active interrupts */
582 level_active
= vgic_bitmap_get_reg(&dist
->irq_level
,
584 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
585 *reg
|= *level_active
;
587 /* Ignore writes to SGIs */
590 *reg
|= orig
& 0xffff;
593 /* Clear soft-pending flags */
594 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
596 vgic_reg_access(mmio
, reg
, offset
, mode
);
598 vgic_handle_clear_mapped_irq(kvm_get_vcpu(kvm
, vcpu_id
));
599 vgic_update_state(kvm
);
605 bool vgic_handle_set_active_reg(struct kvm
*kvm
,
606 struct kvm_exit_mmio
*mmio
,
607 phys_addr_t offset
, int vcpu_id
)
610 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
612 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
613 vgic_reg_access(mmio
, reg
, offset
,
614 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
616 if (mmio
->is_write
) {
617 vgic_update_state(kvm
);
624 bool vgic_handle_clear_active_reg(struct kvm
*kvm
,
625 struct kvm_exit_mmio
*mmio
,
626 phys_addr_t offset
, int vcpu_id
)
629 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
631 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
632 vgic_reg_access(mmio
, reg
, offset
,
633 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
635 if (mmio
->is_write
) {
636 vgic_handle_clear_mapped_irq(kvm_get_vcpu(kvm
, vcpu_id
));
637 vgic_update_state(kvm
);
644 static u32
vgic_cfg_expand(u16 val
)
650 * Turn a 16bit value like abcd...mnop into a 32bit word
651 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
653 for (i
= 0; i
< 16; i
++)
654 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
659 static u16
vgic_cfg_compress(u32 val
)
665 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
666 * abcd...mnop which is what we really care about.
668 for (i
= 0; i
< 16; i
++)
669 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
675 * The distributor uses 2 bits per IRQ for the CFG register, but the
676 * LSB is always 0. As such, we only keep the upper bit, and use the
677 * two above functions to compress/expand the bits
679 bool vgic_handle_cfg_reg(u32
*reg
, struct kvm_exit_mmio
*mmio
,
689 val
= vgic_cfg_expand(val
);
690 vgic_reg_access(mmio
, &val
, offset
,
691 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
692 if (mmio
->is_write
) {
693 /* Ignore writes to read-only SGI and PPI bits */
697 val
= vgic_cfg_compress(val
);
702 *reg
&= 0xffff << 16;
711 * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor
712 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
714 * Move any IRQs that have already been assigned to LRs back to the
715 * emulated distributor state so that the complete emulated state can be read
716 * from the main emulation structures without investigating the LRs.
718 void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
720 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
723 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
724 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
727 * There are three options for the state bits:
731 * 11: pending and active
733 BUG_ON(!(lr
.state
& LR_STATE_MASK
));
735 /* Reestablish SGI source for pending and active IRQs */
736 if (lr
.irq
< VGIC_NR_SGIS
)
737 add_sgi_source(vcpu
, lr
.irq
, lr
.source
);
740 * If the LR holds an active (10) or a pending and active (11)
741 * interrupt then move the active state to the
742 * distributor tracking bit.
744 if (lr
.state
& LR_STATE_ACTIVE
) {
745 vgic_irq_set_active(vcpu
, lr
.irq
);
746 lr
.state
&= ~LR_STATE_ACTIVE
;
750 * Reestablish the pending state on the distributor and the
751 * CPU interface. It may have already been pending, but that
752 * is fine, then we are only setting a few bits that were
755 if (lr
.state
& LR_STATE_PENDING
) {
756 vgic_dist_irq_set_pending(vcpu
, lr
.irq
);
757 lr
.state
&= ~LR_STATE_PENDING
;
760 vgic_set_lr(vcpu
, i
, lr
);
763 * Mark the LR as free for other use.
765 BUG_ON(lr
.state
& LR_STATE_MASK
);
766 vgic_retire_lr(i
, lr
.irq
, vcpu
);
767 vgic_irq_clear_queued(vcpu
, lr
.irq
);
769 /* Finally update the VGIC state. */
770 vgic_update_state(vcpu
->kvm
);
775 struct vgic_io_range
*vgic_find_range(const struct vgic_io_range
*ranges
,
776 int len
, gpa_t offset
)
778 while (ranges
->len
) {
779 if (offset
>= ranges
->base
&&
780 (offset
+ len
) <= (ranges
->base
+ ranges
->len
))
788 static bool vgic_validate_access(const struct vgic_dist
*dist
,
789 const struct vgic_io_range
*range
,
790 unsigned long offset
)
794 if (!range
->bits_per_irq
)
795 return true; /* Not an irq-based access */
797 irq
= offset
* 8 / range
->bits_per_irq
;
798 if (irq
>= dist
->nr_irqs
)
805 * Call the respective handler function for the given range.
806 * We split up any 64 bit accesses into two consecutive 32 bit
807 * handler calls and merge the result afterwards.
808 * We do this in a little endian fashion regardless of the host's
809 * or guest's endianness, because the GIC is always LE and the rest of
810 * the code (vgic_reg_access) also puts it in a LE fashion already.
811 * At this point we have already identified the handle function, so
812 * range points to that one entry and offset is relative to this.
814 static bool call_range_handler(struct kvm_vcpu
*vcpu
,
815 struct kvm_exit_mmio
*mmio
,
816 unsigned long offset
,
817 const struct vgic_io_range
*range
)
819 struct kvm_exit_mmio mmio32
;
822 if (likely(mmio
->len
<= 4))
823 return range
->handle_mmio(vcpu
, mmio
, offset
);
826 * Any access bigger than 4 bytes (that we currently handle in KVM)
827 * is actually 8 bytes long, caused by a 64-bit access
831 mmio32
.is_write
= mmio
->is_write
;
832 mmio32
.private = mmio
->private;
834 mmio32
.phys_addr
= mmio
->phys_addr
+ 4;
835 mmio32
.data
= &((u32
*)mmio
->data
)[1];
836 ret
= range
->handle_mmio(vcpu
, &mmio32
, offset
+ 4);
838 mmio32
.phys_addr
= mmio
->phys_addr
;
839 mmio32
.data
= &((u32
*)mmio
->data
)[0];
840 ret
|= range
->handle_mmio(vcpu
, &mmio32
, offset
);
846 * vgic_handle_mmio_access - handle an in-kernel MMIO access
847 * This is called by the read/write KVM IO device wrappers below.
848 * @vcpu: pointer to the vcpu performing the access
849 * @this: pointer to the KVM IO device in charge
850 * @addr: guest physical address of the access
851 * @len: size of the access
852 * @val: pointer to the data region
853 * @is_write: read or write access
855 * returns true if the MMIO access could be performed
857 static int vgic_handle_mmio_access(struct kvm_vcpu
*vcpu
,
858 struct kvm_io_device
*this, gpa_t addr
,
859 int len
, void *val
, bool is_write
)
861 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
862 struct vgic_io_device
*iodev
= container_of(this,
863 struct vgic_io_device
, dev
);
864 struct kvm_run
*run
= vcpu
->run
;
865 const struct vgic_io_range
*range
;
866 struct kvm_exit_mmio mmio
;
870 offset
= addr
- iodev
->addr
;
871 range
= vgic_find_range(iodev
->reg_ranges
, len
, offset
);
872 if (unlikely(!range
|| !range
->handle_mmio
)) {
873 pr_warn("Unhandled access %d %08llx %d\n", is_write
, addr
, len
);
877 mmio
.phys_addr
= addr
;
879 mmio
.is_write
= is_write
;
881 mmio
.private = iodev
->redist_vcpu
;
883 spin_lock(&dist
->lock
);
884 offset
-= range
->base
;
885 if (vgic_validate_access(dist
, range
, offset
)) {
886 updated_state
= call_range_handler(vcpu
, &mmio
, offset
, range
);
890 updated_state
= false;
892 spin_unlock(&dist
->lock
);
893 run
->mmio
.is_write
= is_write
;
895 run
->mmio
.phys_addr
= addr
;
896 memcpy(run
->mmio
.data
, val
, len
);
898 kvm_handle_mmio_return(vcpu
, run
);
901 vgic_kick_vcpus(vcpu
->kvm
);
906 static int vgic_handle_mmio_read(struct kvm_vcpu
*vcpu
,
907 struct kvm_io_device
*this,
908 gpa_t addr
, int len
, void *val
)
910 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, val
, false);
913 static int vgic_handle_mmio_write(struct kvm_vcpu
*vcpu
,
914 struct kvm_io_device
*this,
915 gpa_t addr
, int len
, const void *val
)
917 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, (void *)val
,
921 struct kvm_io_device_ops vgic_io_ops
= {
922 .read
= vgic_handle_mmio_read
,
923 .write
= vgic_handle_mmio_write
,
927 * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus
928 * @kvm: The VM structure pointer
929 * @base: The (guest) base address for the register frame
930 * @len: Length of the register frame window
931 * @ranges: Describing the handler functions for each register
932 * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call
933 * @iodev: Points to memory to be passed on to the handler
935 * @iodev stores the parameters of this function to be usable by the handler
936 * respectively the dispatcher function (since the KVM I/O bus framework lacks
937 * an opaque parameter). Initialization is done in this function, but the
938 * reference should be valid and unique for the whole VGIC lifetime.
939 * If the register frame is not mapped for a specific VCPU, pass -1 to
942 int vgic_register_kvm_io_dev(struct kvm
*kvm
, gpa_t base
, int len
,
943 const struct vgic_io_range
*ranges
,
945 struct vgic_io_device
*iodev
)
947 struct kvm_vcpu
*vcpu
= NULL
;
950 if (redist_vcpu_id
>= 0)
951 vcpu
= kvm_get_vcpu(kvm
, redist_vcpu_id
);
955 iodev
->reg_ranges
= ranges
;
956 iodev
->redist_vcpu
= vcpu
;
958 kvm_iodevice_init(&iodev
->dev
, &vgic_io_ops
);
960 mutex_lock(&kvm
->slots_lock
);
962 ret
= kvm_io_bus_register_dev(kvm
, KVM_MMIO_BUS
, base
, len
,
964 mutex_unlock(&kvm
->slots_lock
);
966 /* Mark the iodev as invalid if registration fails. */
968 iodev
->dev
.ops
= NULL
;
973 static int vgic_nr_shared_irqs(struct vgic_dist
*dist
)
975 return dist
->nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
978 static int compute_active_for_cpu(struct kvm_vcpu
*vcpu
)
980 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
981 unsigned long *active
, *enabled
, *act_percpu
, *act_shared
;
982 unsigned long active_private
, active_shared
;
983 int nr_shared
= vgic_nr_shared_irqs(dist
);
986 vcpu_id
= vcpu
->vcpu_id
;
987 act_percpu
= vcpu
->arch
.vgic_cpu
.active_percpu
;
988 act_shared
= vcpu
->arch
.vgic_cpu
.active_shared
;
990 active
= vgic_bitmap_get_cpu_map(&dist
->irq_active
, vcpu_id
);
991 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
992 bitmap_and(act_percpu
, active
, enabled
, VGIC_NR_PRIVATE_IRQS
);
994 active
= vgic_bitmap_get_shared_map(&dist
->irq_active
);
995 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
996 bitmap_and(act_shared
, active
, enabled
, nr_shared
);
997 bitmap_and(act_shared
, act_shared
,
998 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
1001 active_private
= find_first_bit(act_percpu
, VGIC_NR_PRIVATE_IRQS
);
1002 active_shared
= find_first_bit(act_shared
, nr_shared
);
1004 return (active_private
< VGIC_NR_PRIVATE_IRQS
||
1005 active_shared
< nr_shared
);
1008 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
1010 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1011 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
1012 unsigned long pending_private
, pending_shared
;
1013 int nr_shared
= vgic_nr_shared_irqs(dist
);
1016 vcpu_id
= vcpu
->vcpu_id
;
1017 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
1018 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
1020 if (!dist
->enabled
) {
1021 bitmap_zero(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
1022 bitmap_zero(pend_shared
, nr_shared
);
1026 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_pending
, vcpu_id
);
1027 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
1028 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
1030 pending
= vgic_bitmap_get_shared_map(&dist
->irq_pending
);
1031 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
1032 bitmap_and(pend_shared
, pending
, enabled
, nr_shared
);
1033 bitmap_and(pend_shared
, pend_shared
,
1034 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
1037 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
1038 pending_shared
= find_first_bit(pend_shared
, nr_shared
);
1039 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
1040 pending_shared
< vgic_nr_shared_irqs(dist
));
1044 * Update the interrupt state and determine which CPUs have pending
1045 * or active interrupts. Must be called with distributor lock held.
1047 void vgic_update_state(struct kvm
*kvm
)
1049 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1050 struct kvm_vcpu
*vcpu
;
1053 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1054 if (compute_pending_for_cpu(vcpu
))
1055 set_bit(c
, dist
->irq_pending_on_cpu
);
1057 if (compute_active_for_cpu(vcpu
))
1058 set_bit(c
, dist
->irq_active_on_cpu
);
1060 clear_bit(c
, dist
->irq_active_on_cpu
);
1064 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1066 return vgic_ops
->get_lr(vcpu
, lr
);
1069 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1072 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
1075 static void vgic_sync_lr_elrsr(struct kvm_vcpu
*vcpu
, int lr
,
1078 vgic_ops
->sync_lr_elrsr(vcpu
, lr
, vlr
);
1081 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
1083 return vgic_ops
->get_elrsr(vcpu
);
1086 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
1088 return vgic_ops
->get_eisr(vcpu
);
1091 static inline void vgic_clear_eisr(struct kvm_vcpu
*vcpu
)
1093 vgic_ops
->clear_eisr(vcpu
);
1096 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1098 return vgic_ops
->get_interrupt_status(vcpu
);
1101 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1103 vgic_ops
->enable_underflow(vcpu
);
1106 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1108 vgic_ops
->disable_underflow(vcpu
);
1111 void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1113 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1116 void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1118 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1121 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1123 vgic_ops
->enable(vcpu
);
1126 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1128 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1129 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1132 * We must transfer the pending state back to the distributor before
1133 * retiring the LR, otherwise we may loose edge-triggered interrupts.
1135 if (vlr
.state
& LR_STATE_PENDING
) {
1136 vgic_dist_irq_set_pending(vcpu
, irq
);
1141 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1142 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1143 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1144 vgic_sync_lr_elrsr(vcpu
, lr_nr
, vlr
);
1148 * An interrupt may have been disabled after being made pending on the
1149 * CPU interface (the classic case is a timer running while we're
1150 * rebooting the guest - the interrupt would kick as soon as the CPU
1151 * interface gets enabled, with deadly consequences).
1153 * The solution is to examine already active LRs, and check the
1154 * interrupt is still enabled. If not, just retire it.
1156 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1158 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1161 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic
->nr_lr
) {
1162 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1164 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1165 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1166 if (vgic_irq_is_queued(vcpu
, vlr
.irq
))
1167 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1172 static void vgic_queue_irq_to_lr(struct kvm_vcpu
*vcpu
, int irq
,
1173 int lr_nr
, struct vgic_lr vlr
)
1175 if (vgic_irq_is_active(vcpu
, irq
)) {
1176 vlr
.state
|= LR_STATE_ACTIVE
;
1177 kvm_debug("Set active, clear distributor: 0x%x\n", vlr
.state
);
1178 vgic_irq_clear_active(vcpu
, irq
);
1179 vgic_update_state(vcpu
->kvm
);
1181 WARN_ON(!vgic_dist_irq_is_pending(vcpu
, irq
));
1182 vlr
.state
|= LR_STATE_PENDING
;
1183 kvm_debug("Set pending: 0x%x\n", vlr
.state
);
1186 if (!vgic_irq_is_edge(vcpu
, irq
))
1187 vlr
.state
|= LR_EOI_INT
;
1189 if (vlr
.irq
>= VGIC_NR_SGIS
) {
1190 struct irq_phys_map
*map
;
1191 map
= vgic_irq_map_search(vcpu
, irq
);
1194 vlr
.hwirq
= map
->phys_irq
;
1196 vlr
.state
&= ~LR_EOI_INT
;
1199 * Make sure we're not going to sample this
1200 * again, as a HW-backed interrupt cannot be
1201 * in the PENDING_ACTIVE stage.
1203 vgic_irq_set_queued(vcpu
, irq
);
1207 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1208 vgic_sync_lr_elrsr(vcpu
, lr_nr
, vlr
);
1212 * Queue an interrupt to a CPU virtual interface. Return true on success,
1213 * or false if it wasn't possible to queue it.
1214 * sgi_source must be zero for any non-SGI interrupts.
1216 bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1218 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1219 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1223 /* Sanitize the input... */
1224 BUG_ON(sgi_source_id
& ~7);
1225 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1226 BUG_ON(irq
>= dist
->nr_irqs
);
1228 kvm_debug("Queue IRQ%d\n", irq
);
1230 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1232 /* Do we have an active interrupt for the same CPUID? */
1233 if (lr
!= LR_EMPTY
) {
1234 vlr
= vgic_get_lr(vcpu
, lr
);
1235 if (vlr
.source
== sgi_source_id
) {
1236 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1237 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1238 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1243 /* Try to use another LR for this interrupt */
1244 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1246 if (lr
>= vgic
->nr_lr
)
1249 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1250 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1251 set_bit(lr
, vgic_cpu
->lr_used
);
1254 vlr
.source
= sgi_source_id
;
1256 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1261 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1263 if (!vgic_can_sample_irq(vcpu
, irq
))
1264 return true; /* level interrupt, already queued */
1266 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1267 if (vgic_irq_is_edge(vcpu
, irq
)) {
1268 vgic_dist_irq_clear_pending(vcpu
, irq
);
1269 vgic_cpu_irq_clear(vcpu
, irq
);
1271 vgic_irq_set_queued(vcpu
, irq
);
1281 * Fill the list registers with pending interrupts before running the
1284 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1286 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1287 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1288 unsigned long *pa_percpu
, *pa_shared
;
1291 int nr_shared
= vgic_nr_shared_irqs(dist
);
1293 vcpu_id
= vcpu
->vcpu_id
;
1295 pa_percpu
= vcpu
->arch
.vgic_cpu
.pend_act_percpu
;
1296 pa_shared
= vcpu
->arch
.vgic_cpu
.pend_act_shared
;
1298 bitmap_or(pa_percpu
, vgic_cpu
->pending_percpu
, vgic_cpu
->active_percpu
,
1299 VGIC_NR_PRIVATE_IRQS
);
1300 bitmap_or(pa_shared
, vgic_cpu
->pending_shared
, vgic_cpu
->active_shared
,
1303 * We may not have any pending interrupt, or the interrupts
1304 * may have been serviced from another vcpu. In all cases,
1307 if (!kvm_vgic_vcpu_pending_irq(vcpu
) && !kvm_vgic_vcpu_active_irq(vcpu
))
1311 for_each_set_bit(i
, pa_percpu
, VGIC_NR_SGIS
) {
1312 if (!queue_sgi(vcpu
, i
))
1317 for_each_set_bit_from(i
, pa_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1318 if (!vgic_queue_hwirq(vcpu
, i
))
1323 for_each_set_bit(i
, pa_shared
, nr_shared
) {
1324 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1333 vgic_enable_underflow(vcpu
);
1335 vgic_disable_underflow(vcpu
);
1337 * We're about to run this VCPU, and we've consumed
1338 * everything the distributor had in store for
1339 * us. Claim we don't have anything pending. We'll
1340 * adjust that if needed while exiting.
1342 clear_bit(vcpu_id
, dist
->irq_pending_on_cpu
);
1346 static int process_level_irq(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr vlr
)
1348 int level_pending
= 0;
1352 vgic_set_lr(vcpu
, lr
, vlr
);
1355 * If the IRQ was EOIed (called from vgic_process_maintenance) or it
1356 * went from active to non-active (called from vgic_sync_hwirq) it was
1357 * also ACKed and we we therefore assume we can clear the soft pending
1358 * state (should it had been set) for this interrupt.
1360 * Note: if the IRQ soft pending state was set after the IRQ was
1361 * acked, it actually shouldn't be cleared, but we have no way of
1362 * knowing that unless we start trapping ACKs when the soft-pending
1365 vgic_dist_irq_clear_soft_pend(vcpu
, vlr
.irq
);
1368 * Tell the gic to start sampling the line of this interrupt again.
1370 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1372 /* Any additional pending interrupt? */
1373 if (vgic_dist_irq_get_level(vcpu
, vlr
.irq
)) {
1374 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1377 vgic_dist_irq_clear_pending(vcpu
, vlr
.irq
);
1378 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1382 * Despite being EOIed, the LR may not have
1383 * been marked as empty.
1385 vgic_sync_lr_elrsr(vcpu
, lr
, vlr
);
1387 return level_pending
;
1390 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1392 u32 status
= vgic_get_interrupt_status(vcpu
);
1393 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1394 struct kvm
*kvm
= vcpu
->kvm
;
1395 int level_pending
= 0;
1397 kvm_debug("STATUS = %08x\n", status
);
1399 if (status
& INT_STATUS_EOI
) {
1401 * Some level interrupts have been EOIed. Clear their
1404 u64 eisr
= vgic_get_eisr(vcpu
);
1405 unsigned long *eisr_ptr
= u64_to_bitmask(&eisr
);
1408 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1409 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1411 WARN_ON(vgic_irq_is_edge(vcpu
, vlr
.irq
));
1412 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1416 * kvm_notify_acked_irq calls kvm_set_irq()
1417 * to reset the IRQ level, which grabs the dist->lock
1418 * so we call this before taking the dist->lock.
1420 kvm_notify_acked_irq(kvm
, 0,
1421 vlr
.irq
- VGIC_NR_PRIVATE_IRQS
);
1423 spin_lock(&dist
->lock
);
1424 level_pending
|= process_level_irq(vcpu
, lr
, vlr
);
1425 spin_unlock(&dist
->lock
);
1429 if (status
& INT_STATUS_UNDERFLOW
)
1430 vgic_disable_underflow(vcpu
);
1433 * In the next iterations of the vcpu loop, if we sync the vgic state
1434 * after flushing it, but before entering the guest (this happens for
1435 * pending signals and vmid rollovers), then make sure we don't pick
1436 * up any old maintenance interrupts here.
1438 vgic_clear_eisr(vcpu
);
1440 return level_pending
;
1444 * Save the physical active state, and reset it to inactive.
1446 * Return 1 if HW interrupt went from active to inactive, and 0 otherwise.
1448 static int vgic_sync_hwirq(struct kvm_vcpu
*vcpu
, struct vgic_lr vlr
)
1450 struct irq_phys_map
*map
;
1453 if (!(vlr
.state
& LR_HW
))
1456 map
= vgic_irq_map_search(vcpu
, vlr
.irq
);
1459 ret
= irq_get_irqchip_state(map
->irq
,
1460 IRQCHIP_STATE_ACTIVE
,
1471 /* Sync back the VGIC state after a guest run */
1472 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1474 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1475 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1477 unsigned long *elrsr_ptr
;
1481 level_pending
= vgic_process_maintenance(vcpu
);
1482 elrsr
= vgic_get_elrsr(vcpu
);
1483 elrsr_ptr
= u64_to_bitmask(&elrsr
);
1485 /* Deal with HW interrupts, and clear mappings for empty LRs */
1486 for (lr
= 0; lr
< vgic
->nr_lr
; lr
++) {
1489 if (!test_bit(lr
, vgic_cpu
->lr_used
))
1492 vlr
= vgic_get_lr(vcpu
, lr
);
1493 if (vgic_sync_hwirq(vcpu
, vlr
)) {
1495 * So this is a HW interrupt that the guest
1496 * EOI-ed. Clean the LR state and allow the
1497 * interrupt to be sampled again.
1501 vgic_set_lr(vcpu
, lr
, vlr
);
1502 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1503 set_bit(lr
, elrsr_ptr
);
1506 if (!test_bit(lr
, elrsr_ptr
))
1509 clear_bit(lr
, vgic_cpu
->lr_used
);
1511 BUG_ON(vlr
.irq
>= dist
->nr_irqs
);
1512 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1515 /* Check if we still have something up our sleeve... */
1516 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1517 if (level_pending
|| pending
< vgic
->nr_lr
)
1518 set_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1521 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1523 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1525 if (!irqchip_in_kernel(vcpu
->kvm
))
1528 spin_lock(&dist
->lock
);
1529 __kvm_vgic_flush_hwstate(vcpu
);
1530 spin_unlock(&dist
->lock
);
1533 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1535 if (!irqchip_in_kernel(vcpu
->kvm
))
1538 __kvm_vgic_sync_hwstate(vcpu
);
1541 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1543 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1545 if (!irqchip_in_kernel(vcpu
->kvm
))
1548 return test_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1551 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu
*vcpu
)
1553 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1555 if (!irqchip_in_kernel(vcpu
->kvm
))
1558 return test_bit(vcpu
->vcpu_id
, dist
->irq_active_on_cpu
);
1562 void vgic_kick_vcpus(struct kvm
*kvm
)
1564 struct kvm_vcpu
*vcpu
;
1568 * We've injected an interrupt, time to find out who deserves
1571 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1572 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1573 kvm_vcpu_kick(vcpu
);
1577 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1579 int edge_triggered
= vgic_irq_is_edge(vcpu
, irq
);
1582 * Only inject an interrupt if:
1583 * - edge triggered and we have a rising edge
1584 * - level triggered and we change level
1586 if (edge_triggered
) {
1587 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1588 return level
> state
;
1590 int state
= vgic_dist_irq_get_level(vcpu
, irq
);
1591 return level
!= state
;
1595 static int vgic_update_irq_pending(struct kvm
*kvm
, int cpuid
,
1596 struct irq_phys_map
*map
,
1597 unsigned int irq_num
, bool level
)
1599 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1600 struct kvm_vcpu
*vcpu
;
1601 int edge_triggered
, level_triggered
;
1603 bool ret
= true, can_inject
= true;
1605 if (irq_num
>= min(kvm
->arch
.vgic
.nr_irqs
, 1020))
1608 spin_lock(&dist
->lock
);
1610 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1611 edge_triggered
= vgic_irq_is_edge(vcpu
, irq_num
);
1612 level_triggered
= !edge_triggered
;
1614 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1619 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1620 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1621 if (cpuid
== VCPU_NOT_ALLOCATED
) {
1622 /* Pretend we use CPU0, and prevent injection */
1626 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1629 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1632 if (level_triggered
)
1633 vgic_dist_irq_set_level(vcpu
, irq_num
);
1634 vgic_dist_irq_set_pending(vcpu
, irq_num
);
1636 if (level_triggered
) {
1637 vgic_dist_irq_clear_level(vcpu
, irq_num
);
1638 if (!vgic_dist_irq_soft_pend(vcpu
, irq_num
)) {
1639 vgic_dist_irq_clear_pending(vcpu
, irq_num
);
1640 vgic_cpu_irq_clear(vcpu
, irq_num
);
1641 if (!compute_pending_for_cpu(vcpu
))
1642 clear_bit(cpuid
, dist
->irq_pending_on_cpu
);
1650 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1652 if (!enabled
|| !can_inject
) {
1657 if (!vgic_can_sample_irq(vcpu
, irq_num
)) {
1659 * Level interrupt in progress, will be picked up
1667 vgic_cpu_irq_set(vcpu
, irq_num
);
1668 set_bit(cpuid
, dist
->irq_pending_on_cpu
);
1672 spin_unlock(&dist
->lock
);
1675 /* kick the specified vcpu */
1676 kvm_vcpu_kick(kvm_get_vcpu(kvm
, cpuid
));
1682 static int vgic_lazy_init(struct kvm
*kvm
)
1686 if (unlikely(!vgic_initialized(kvm
))) {
1688 * We only provide the automatic initialization of the VGIC
1689 * for the legacy case of a GICv2. Any other type must
1690 * be explicitly initialized once setup with the respective
1693 if (kvm
->arch
.vgic
.vgic_model
!= KVM_DEV_TYPE_ARM_VGIC_V2
)
1696 mutex_lock(&kvm
->lock
);
1697 ret
= vgic_init(kvm
);
1698 mutex_unlock(&kvm
->lock
);
1705 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1706 * @kvm: The VM structure pointer
1707 * @cpuid: The CPU for PPIs
1708 * @irq_num: The IRQ number that is assigned to the device. This IRQ
1709 * must not be mapped to a HW interrupt.
1710 * @level: Edge-triggered: true: to trigger the interrupt
1711 * false: to ignore the call
1712 * Level-sensitive true: raise the input signal
1713 * false: lower the input signal
1715 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1716 * level-sensitive interrupts. You can think of the level parameter as 1
1717 * being HIGH and 0 being LOW and all devices being active-HIGH.
1719 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1722 struct irq_phys_map
*map
;
1725 ret
= vgic_lazy_init(kvm
);
1729 map
= vgic_irq_map_search(kvm_get_vcpu(kvm
, cpuid
), irq_num
);
1733 return vgic_update_irq_pending(kvm
, cpuid
, NULL
, irq_num
, level
);
1737 * kvm_vgic_inject_mapped_irq - Inject a physically mapped IRQ to the vgic
1738 * @kvm: The VM structure pointer
1739 * @cpuid: The CPU for PPIs
1740 * @map: Pointer to a irq_phys_map structure describing the mapping
1741 * @level: Edge-triggered: true: to trigger the interrupt
1742 * false: to ignore the call
1743 * Level-sensitive true: raise the input signal
1744 * false: lower the input signal
1746 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1747 * level-sensitive interrupts. You can think of the level parameter as 1
1748 * being HIGH and 0 being LOW and all devices being active-HIGH.
1750 int kvm_vgic_inject_mapped_irq(struct kvm
*kvm
, int cpuid
,
1751 struct irq_phys_map
*map
, bool level
)
1755 ret
= vgic_lazy_init(kvm
);
1759 return vgic_update_irq_pending(kvm
, cpuid
, map
, map
->virt_irq
, level
);
1762 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1765 * We cannot rely on the vgic maintenance interrupt to be
1766 * delivered synchronously. This means we can only use it to
1767 * exit the VM, and we perform the handling of EOIed
1768 * interrupts on the exit path (see vgic_process_maintenance).
1773 static struct list_head
*vgic_get_irq_phys_map_list(struct kvm_vcpu
*vcpu
,
1776 if (virt_irq
< VGIC_NR_PRIVATE_IRQS
)
1777 return &vcpu
->arch
.vgic_cpu
.irq_phys_map_list
;
1779 return &vcpu
->kvm
->arch
.vgic
.irq_phys_map_list
;
1783 * kvm_vgic_map_phys_irq - map a virtual IRQ to a physical IRQ
1784 * @vcpu: The VCPU pointer
1785 * @virt_irq: The virtual irq number
1786 * @irq: The Linux IRQ number
1788 * Establish a mapping between a guest visible irq (@virt_irq) and a
1789 * Linux irq (@irq). On injection, @virt_irq will be associated with
1790 * the physical interrupt represented by @irq. This mapping can be
1791 * established multiple times as long as the parameters are the same.
1793 * Returns a valid pointer on success, and an error pointer otherwise
1795 struct irq_phys_map
*kvm_vgic_map_phys_irq(struct kvm_vcpu
*vcpu
,
1796 int virt_irq
, int irq
)
1798 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1799 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1800 struct irq_phys_map
*map
;
1801 struct irq_phys_map_entry
*entry
;
1802 struct irq_desc
*desc
;
1803 struct irq_data
*data
;
1806 desc
= irq_to_desc(irq
);
1808 kvm_err("%s: no interrupt descriptor\n", __func__
);
1809 return ERR_PTR(-EINVAL
);
1812 data
= irq_desc_get_irq_data(desc
);
1813 while (data
->parent_data
)
1814 data
= data
->parent_data
;
1816 phys_irq
= data
->hwirq
;
1818 /* Create a new mapping */
1819 entry
= kzalloc(sizeof(*entry
), GFP_KERNEL
);
1821 return ERR_PTR(-ENOMEM
);
1823 spin_lock(&dist
->irq_phys_map_lock
);
1825 /* Try to match an existing mapping */
1826 map
= vgic_irq_map_search(vcpu
, virt_irq
);
1828 /* Make sure this mapping matches */
1829 if (map
->phys_irq
!= phys_irq
||
1831 map
= ERR_PTR(-EINVAL
);
1833 /* Found an existing, valid mapping */
1838 map
->virt_irq
= virt_irq
;
1839 map
->phys_irq
= phys_irq
;
1842 list_add_tail_rcu(&entry
->entry
, root
);
1845 spin_unlock(&dist
->irq_phys_map_lock
);
1846 /* If we've found a hit in the existing list, free the useless
1848 if (IS_ERR(map
) || map
!= &entry
->map
)
1853 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
1856 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1857 struct irq_phys_map_entry
*entry
;
1858 struct irq_phys_map
*map
;
1862 list_for_each_entry_rcu(entry
, root
, entry
) {
1864 if (map
->virt_irq
== virt_irq
) {
1875 static void vgic_free_phys_irq_map_rcu(struct rcu_head
*rcu
)
1877 struct irq_phys_map_entry
*entry
;
1879 entry
= container_of(rcu
, struct irq_phys_map_entry
, rcu
);
1884 * kvm_vgic_get_phys_irq_active - Return the active state of a mapped IRQ
1886 * Return the logical active state of a mapped interrupt. This doesn't
1887 * necessarily reflects the current HW state.
1889 bool kvm_vgic_get_phys_irq_active(struct irq_phys_map
*map
)
1896 * kvm_vgic_set_phys_irq_active - Set the active state of a mapped IRQ
1898 * Set the logical active state of a mapped interrupt. This doesn't
1899 * immediately affects the HW state.
1901 void kvm_vgic_set_phys_irq_active(struct irq_phys_map
*map
, bool active
)
1904 map
->active
= active
;
1908 * kvm_vgic_unmap_phys_irq - Remove a virtual to physical IRQ mapping
1909 * @vcpu: The VCPU pointer
1910 * @map: The pointer to a mapping obtained through kvm_vgic_map_phys_irq
1912 * Remove an existing mapping between virtual and physical interrupts.
1914 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu
*vcpu
, struct irq_phys_map
*map
)
1916 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1917 struct irq_phys_map_entry
*entry
;
1918 struct list_head
*root
;
1923 root
= vgic_get_irq_phys_map_list(vcpu
, map
->virt_irq
);
1925 spin_lock(&dist
->irq_phys_map_lock
);
1927 list_for_each_entry(entry
, root
, entry
) {
1928 if (&entry
->map
== map
) {
1929 list_del_rcu(&entry
->entry
);
1930 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1935 spin_unlock(&dist
->irq_phys_map_lock
);
1940 static void vgic_destroy_irq_phys_map(struct kvm
*kvm
, struct list_head
*root
)
1942 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1943 struct irq_phys_map_entry
*entry
;
1945 spin_lock(&dist
->irq_phys_map_lock
);
1947 list_for_each_entry(entry
, root
, entry
) {
1948 list_del_rcu(&entry
->entry
);
1949 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1952 spin_unlock(&dist
->irq_phys_map_lock
);
1955 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
)
1957 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1959 kfree(vgic_cpu
->pending_shared
);
1960 kfree(vgic_cpu
->active_shared
);
1961 kfree(vgic_cpu
->pend_act_shared
);
1962 kfree(vgic_cpu
->vgic_irq_lr_map
);
1963 vgic_destroy_irq_phys_map(vcpu
->kvm
, &vgic_cpu
->irq_phys_map_list
);
1964 vgic_cpu
->pending_shared
= NULL
;
1965 vgic_cpu
->active_shared
= NULL
;
1966 vgic_cpu
->pend_act_shared
= NULL
;
1967 vgic_cpu
->vgic_irq_lr_map
= NULL
;
1970 static int vgic_vcpu_init_maps(struct kvm_vcpu
*vcpu
, int nr_irqs
)
1972 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1974 int sz
= (nr_irqs
- VGIC_NR_PRIVATE_IRQS
) / 8;
1975 vgic_cpu
->pending_shared
= kzalloc(sz
, GFP_KERNEL
);
1976 vgic_cpu
->active_shared
= kzalloc(sz
, GFP_KERNEL
);
1977 vgic_cpu
->pend_act_shared
= kzalloc(sz
, GFP_KERNEL
);
1978 vgic_cpu
->vgic_irq_lr_map
= kmalloc(nr_irqs
, GFP_KERNEL
);
1980 if (!vgic_cpu
->pending_shared
1981 || !vgic_cpu
->active_shared
1982 || !vgic_cpu
->pend_act_shared
1983 || !vgic_cpu
->vgic_irq_lr_map
) {
1984 kvm_vgic_vcpu_destroy(vcpu
);
1988 memset(vgic_cpu
->vgic_irq_lr_map
, LR_EMPTY
, nr_irqs
);
1991 * Store the number of LRs per vcpu, so we don't have to go
1992 * all the way to the distributor structure to find out. Only
1993 * assembly code should use this one.
1995 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
2001 * kvm_vgic_vcpu_early_init - Earliest possible per-vcpu vgic init stage
2003 * No memory allocation should be performed here, only static init.
2005 void kvm_vgic_vcpu_early_init(struct kvm_vcpu
*vcpu
)
2007 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
2008 INIT_LIST_HEAD(&vgic_cpu
->irq_phys_map_list
);
2012 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
2014 * The host's GIC naturally limits the maximum amount of VCPUs a guest
2017 int kvm_vgic_get_max_vcpus(void)
2019 return vgic
->max_gic_vcpus
;
2022 void kvm_vgic_destroy(struct kvm
*kvm
)
2024 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
2025 struct kvm_vcpu
*vcpu
;
2028 kvm_for_each_vcpu(i
, vcpu
, kvm
)
2029 kvm_vgic_vcpu_destroy(vcpu
);
2031 vgic_free_bitmap(&dist
->irq_enabled
);
2032 vgic_free_bitmap(&dist
->irq_level
);
2033 vgic_free_bitmap(&dist
->irq_pending
);
2034 vgic_free_bitmap(&dist
->irq_soft_pend
);
2035 vgic_free_bitmap(&dist
->irq_queued
);
2036 vgic_free_bitmap(&dist
->irq_cfg
);
2037 vgic_free_bytemap(&dist
->irq_priority
);
2038 if (dist
->irq_spi_target
) {
2039 for (i
= 0; i
< dist
->nr_cpus
; i
++)
2040 vgic_free_bitmap(&dist
->irq_spi_target
[i
]);
2042 kfree(dist
->irq_sgi_sources
);
2043 kfree(dist
->irq_spi_cpu
);
2044 kfree(dist
->irq_spi_mpidr
);
2045 kfree(dist
->irq_spi_target
);
2046 kfree(dist
->irq_pending_on_cpu
);
2047 kfree(dist
->irq_active_on_cpu
);
2048 vgic_destroy_irq_phys_map(kvm
, &dist
->irq_phys_map_list
);
2049 dist
->irq_sgi_sources
= NULL
;
2050 dist
->irq_spi_cpu
= NULL
;
2051 dist
->irq_spi_target
= NULL
;
2052 dist
->irq_pending_on_cpu
= NULL
;
2053 dist
->irq_active_on_cpu
= NULL
;
2058 * Allocate and initialize the various data structures. Must be called
2059 * with kvm->lock held!
2061 int vgic_init(struct kvm
*kvm
)
2063 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
2064 struct kvm_vcpu
*vcpu
;
2065 int nr_cpus
, nr_irqs
;
2066 int ret
, i
, vcpu_id
;
2068 if (vgic_initialized(kvm
))
2071 nr_cpus
= dist
->nr_cpus
= atomic_read(&kvm
->online_vcpus
);
2072 if (!nr_cpus
) /* No vcpus? Can't be good... */
2076 * If nobody configured the number of interrupts, use the
2080 dist
->nr_irqs
= VGIC_NR_IRQS_LEGACY
;
2082 nr_irqs
= dist
->nr_irqs
;
2084 ret
= vgic_init_bitmap(&dist
->irq_enabled
, nr_cpus
, nr_irqs
);
2085 ret
|= vgic_init_bitmap(&dist
->irq_level
, nr_cpus
, nr_irqs
);
2086 ret
|= vgic_init_bitmap(&dist
->irq_pending
, nr_cpus
, nr_irqs
);
2087 ret
|= vgic_init_bitmap(&dist
->irq_soft_pend
, nr_cpus
, nr_irqs
);
2088 ret
|= vgic_init_bitmap(&dist
->irq_queued
, nr_cpus
, nr_irqs
);
2089 ret
|= vgic_init_bitmap(&dist
->irq_active
, nr_cpus
, nr_irqs
);
2090 ret
|= vgic_init_bitmap(&dist
->irq_cfg
, nr_cpus
, nr_irqs
);
2091 ret
|= vgic_init_bytemap(&dist
->irq_priority
, nr_cpus
, nr_irqs
);
2096 dist
->irq_sgi_sources
= kzalloc(nr_cpus
* VGIC_NR_SGIS
, GFP_KERNEL
);
2097 dist
->irq_spi_cpu
= kzalloc(nr_irqs
- VGIC_NR_PRIVATE_IRQS
, GFP_KERNEL
);
2098 dist
->irq_spi_target
= kzalloc(sizeof(*dist
->irq_spi_target
) * nr_cpus
,
2100 dist
->irq_pending_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2102 dist
->irq_active_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2104 if (!dist
->irq_sgi_sources
||
2105 !dist
->irq_spi_cpu
||
2106 !dist
->irq_spi_target
||
2107 !dist
->irq_pending_on_cpu
||
2108 !dist
->irq_active_on_cpu
) {
2113 for (i
= 0; i
< nr_cpus
; i
++)
2114 ret
|= vgic_init_bitmap(&dist
->irq_spi_target
[i
],
2120 ret
= kvm
->arch
.vgic
.vm_ops
.init_model(kvm
);
2124 kvm_for_each_vcpu(vcpu_id
, vcpu
, kvm
) {
2125 ret
= vgic_vcpu_init_maps(vcpu
, nr_irqs
);
2127 kvm_err("VGIC: Failed to allocate vcpu memory\n");
2132 * Enable all SGIs and configure all private IRQs as
2135 for (i
= 0; i
< VGIC_NR_PRIVATE_IRQS
; i
++) {
2136 if (i
< VGIC_NR_SGIS
)
2137 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
2138 vcpu
->vcpu_id
, i
, 1);
2139 if (i
< VGIC_NR_PRIVATE_IRQS
)
2140 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
2150 kvm_vgic_destroy(kvm
);
2155 static int init_vgic_model(struct kvm
*kvm
, int type
)
2158 case KVM_DEV_TYPE_ARM_VGIC_V2
:
2159 vgic_v2_init_emulation(kvm
);
2161 #ifdef CONFIG_ARM_GIC_V3
2162 case KVM_DEV_TYPE_ARM_VGIC_V3
:
2163 vgic_v3_init_emulation(kvm
);
2170 if (atomic_read(&kvm
->online_vcpus
) > kvm
->arch
.max_vcpus
)
2177 * kvm_vgic_early_init - Earliest possible vgic initialization stage
2179 * No memory allocation should be performed here, only static init.
2181 void kvm_vgic_early_init(struct kvm
*kvm
)
2183 spin_lock_init(&kvm
->arch
.vgic
.lock
);
2184 spin_lock_init(&kvm
->arch
.vgic
.irq_phys_map_lock
);
2185 INIT_LIST_HEAD(&kvm
->arch
.vgic
.irq_phys_map_list
);
2188 int kvm_vgic_create(struct kvm
*kvm
, u32 type
)
2190 int i
, vcpu_lock_idx
= -1, ret
;
2191 struct kvm_vcpu
*vcpu
;
2193 mutex_lock(&kvm
->lock
);
2195 if (irqchip_in_kernel(kvm
)) {
2201 * This function is also called by the KVM_CREATE_IRQCHIP handler,
2202 * which had no chance yet to check the availability of the GICv2
2203 * emulation. So check this here again. KVM_CREATE_DEVICE does
2204 * the proper checks already.
2206 if (type
== KVM_DEV_TYPE_ARM_VGIC_V2
&& !vgic
->can_emulate_gicv2
) {
2212 * Any time a vcpu is run, vcpu_load is called which tries to grab the
2213 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
2214 * that no other VCPUs are run while we create the vgic.
2217 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2218 if (!mutex_trylock(&vcpu
->mutex
))
2223 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2224 if (vcpu
->arch
.has_run_once
)
2229 ret
= init_vgic_model(kvm
, type
);
2233 kvm
->arch
.vgic
.in_kernel
= true;
2234 kvm
->arch
.vgic
.vgic_model
= type
;
2235 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
2236 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
2237 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
2238 kvm
->arch
.vgic
.vgic_redist_base
= VGIC_ADDR_UNDEF
;
2241 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
2242 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
2243 mutex_unlock(&vcpu
->mutex
);
2247 mutex_unlock(&kvm
->lock
);
2251 static int vgic_ioaddr_overlap(struct kvm
*kvm
)
2253 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
2254 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
2256 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
2258 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
2259 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
2264 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
2265 phys_addr_t addr
, phys_addr_t size
)
2269 if (addr
& ~KVM_PHYS_MASK
)
2272 if (addr
& (SZ_4K
- 1))
2275 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
2277 if (addr
+ size
< addr
)
2281 ret
= vgic_ioaddr_overlap(kvm
);
2283 *ioaddr
= VGIC_ADDR_UNDEF
;
2289 * kvm_vgic_addr - set or get vgic VM base addresses
2290 * @kvm: pointer to the vm struct
2291 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
2292 * @addr: pointer to address value
2293 * @write: if true set the address in the VM address space, if false read the
2296 * Set or get the vgic base addresses for the distributor and the virtual CPU
2297 * interface in the VM physical address space. These addresses are properties
2298 * of the emulated core/SoC and therefore user space initially knows this
2301 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
2304 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
2306 phys_addr_t
*addr_ptr
, block_size
;
2307 phys_addr_t alignment
;
2309 mutex_lock(&kvm
->lock
);
2311 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2312 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2313 addr_ptr
= &vgic
->vgic_dist_base
;
2314 block_size
= KVM_VGIC_V2_DIST_SIZE
;
2317 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2318 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2319 addr_ptr
= &vgic
->vgic_cpu_base
;
2320 block_size
= KVM_VGIC_V2_CPU_SIZE
;
2323 #ifdef CONFIG_ARM_GIC_V3
2324 case KVM_VGIC_V3_ADDR_TYPE_DIST
:
2325 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2326 addr_ptr
= &vgic
->vgic_dist_base
;
2327 block_size
= KVM_VGIC_V3_DIST_SIZE
;
2330 case KVM_VGIC_V3_ADDR_TYPE_REDIST
:
2331 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2332 addr_ptr
= &vgic
->vgic_redist_base
;
2333 block_size
= KVM_VGIC_V3_REDIST_SIZE
;
2342 if (vgic
->vgic_model
!= type_needed
) {
2348 if (!IS_ALIGNED(*addr
, alignment
))
2351 r
= vgic_ioaddr_assign(kvm
, addr_ptr
, *addr
,
2358 mutex_unlock(&kvm
->lock
);
2362 int vgic_set_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2366 switch (attr
->group
) {
2367 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2368 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2370 unsigned long type
= (unsigned long)attr
->attr
;
2372 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
2375 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
2376 return (r
== -ENODEV
) ? -ENXIO
: r
;
2378 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2379 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2383 if (get_user(val
, uaddr
))
2388 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2389 * - at most 1024 interrupts
2390 * - a multiple of 32 interrupts
2392 if (val
< (VGIC_NR_PRIVATE_IRQS
+ 32) ||
2393 val
> VGIC_MAX_IRQS
||
2397 mutex_lock(&dev
->kvm
->lock
);
2399 if (vgic_ready(dev
->kvm
) || dev
->kvm
->arch
.vgic
.nr_irqs
)
2402 dev
->kvm
->arch
.vgic
.nr_irqs
= val
;
2404 mutex_unlock(&dev
->kvm
->lock
);
2408 case KVM_DEV_ARM_VGIC_GRP_CTRL
: {
2409 switch (attr
->attr
) {
2410 case KVM_DEV_ARM_VGIC_CTRL_INIT
:
2411 r
= vgic_init(dev
->kvm
);
2421 int vgic_get_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2425 switch (attr
->group
) {
2426 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2427 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2429 unsigned long type
= (unsigned long)attr
->attr
;
2431 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
2433 return (r
== -ENODEV
) ? -ENXIO
: r
;
2435 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
2439 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2440 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2442 r
= put_user(dev
->kvm
->arch
.vgic
.nr_irqs
, uaddr
);
2451 int vgic_has_attr_regs(const struct vgic_io_range
*ranges
, phys_addr_t offset
)
2453 if (vgic_find_range(ranges
, 4, offset
))
2459 static void vgic_init_maintenance_interrupt(void *info
)
2461 enable_percpu_irq(vgic
->maint_irq
, 0);
2464 static int vgic_cpu_notify(struct notifier_block
*self
,
2465 unsigned long action
, void *cpu
)
2469 case CPU_STARTING_FROZEN
:
2470 vgic_init_maintenance_interrupt(NULL
);
2473 case CPU_DYING_FROZEN
:
2474 disable_percpu_irq(vgic
->maint_irq
);
2481 static struct notifier_block vgic_cpu_nb
= {
2482 .notifier_call
= vgic_cpu_notify
,
2485 static const struct of_device_id vgic_ids
[] = {
2486 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
2487 { .compatible
= "arm,cortex-a7-gic", .data
= vgic_v2_probe
, },
2488 { .compatible
= "arm,gic-400", .data
= vgic_v2_probe
, },
2489 { .compatible
= "arm,gic-v3", .data
= vgic_v3_probe
, },
2493 int kvm_vgic_hyp_init(void)
2495 const struct of_device_id
*matched_id
;
2496 const int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
2497 const struct vgic_params
**);
2498 struct device_node
*vgic_node
;
2501 vgic_node
= of_find_matching_node_and_match(NULL
,
2502 vgic_ids
, &matched_id
);
2504 kvm_err("error: no compatible GIC node found\n");
2508 vgic_probe
= matched_id
->data
;
2509 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
2513 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
2514 "vgic", kvm_get_running_vcpus());
2516 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
2520 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
2522 kvm_err("Cannot register vgic CPU notifier\n");
2526 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
2531 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());
2535 int kvm_irq_map_gsi(struct kvm
*kvm
,
2536 struct kvm_kernel_irq_routing_entry
*entries
,
2542 int kvm_irq_map_chip_pin(struct kvm
*kvm
, unsigned irqchip
, unsigned pin
)
2547 int kvm_set_irq(struct kvm
*kvm
, int irq_source_id
,
2548 u32 irq
, int level
, bool line_status
)
2550 unsigned int spi
= irq
+ VGIC_NR_PRIVATE_IRQS
;
2552 trace_kvm_set_irq(irq
, level
, irq_source_id
);
2554 BUG_ON(!vgic_initialized(kvm
));
2556 return kvm_vgic_inject_irq(kvm
, 0, spi
, level
);
2559 /* MSI not implemented yet */
2560 int kvm_set_msi(struct kvm_kernel_irq_routing_entry
*e
,
2561 struct kvm
*kvm
, int irq_source_id
,
2562 int level
, bool line_status
)