2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_pending vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_pending & dist->irq_enable
49 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_queued is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_queued. This allows the
69 * interrupt line to be sampled again.
72 #define VGIC_ADDR_UNDEF (-1)
73 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
75 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76 #define IMPLEMENTER_ARM 0x43b
77 #define GICC_ARCH_VERSION_V2 0x2
79 #define ACCESS_READ_VALUE (1 << 0)
80 #define ACCESS_READ_RAZ (0 << 0)
81 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
82 #define ACCESS_WRITE_IGNORED (0 << 1)
83 #define ACCESS_WRITE_SETBIT (1 << 1)
84 #define ACCESS_WRITE_CLEARBIT (2 << 1)
85 #define ACCESS_WRITE_VALUE (3 << 1)
86 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
88 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
89 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
90 static void vgic_update_state(struct kvm
*kvm
);
91 static void vgic_kick_vcpus(struct kvm
*kvm
);
92 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
);
93 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
94 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
95 static void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
);
96 static void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
);
98 static const struct vgic_ops
*vgic_ops
;
99 static const struct vgic_params
*vgic
;
102 * struct vgic_bitmap contains unions that provide two views of
103 * the same data. In one case it is an array of registers of
104 * u32's, and in the other case it is a bitmap of unsigned
107 * This does not work on 64-bit BE systems, because the bitmap access
108 * will store two consecutive 32-bit words with the higher-addressed
109 * register's bits at the lower index and the lower-addressed register's
110 * bits at the higher index.
112 * Therefore, swizzle the register index when accessing the 32-bit word
113 * registers to access the right register's value.
115 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
116 #define REG_OFFSET_SWIZZLE 1
118 #define REG_OFFSET_SWIZZLE 0
121 static u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
,
122 int cpuid
, u32 offset
)
126 return x
->percpu
[cpuid
].reg
+ (offset
^ REG_OFFSET_SWIZZLE
);
128 return x
->shared
.reg
+ ((offset
- 1) ^ REG_OFFSET_SWIZZLE
);
131 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
134 if (irq
< VGIC_NR_PRIVATE_IRQS
)
135 return test_bit(irq
, x
->percpu
[cpuid
].reg_ul
);
137 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
.reg_ul
);
140 static void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
145 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
146 reg
= x
->percpu
[cpuid
].reg_ul
;
148 reg
= x
->shared
.reg_ul
;
149 irq
-= VGIC_NR_PRIVATE_IRQS
;
158 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
160 if (unlikely(cpuid
>= VGIC_MAX_CPUS
))
162 return x
->percpu
[cpuid
].reg_ul
;
165 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
167 return x
->shared
.reg_ul
;
170 static u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
173 BUG_ON(offset
> (VGIC_NR_IRQS
/ 4));
175 return x
->percpu
[cpuid
] + offset
;
177 return x
->shared
+ offset
- 8;
180 #define VGIC_CFG_LEVEL 0
181 #define VGIC_CFG_EDGE 1
183 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
185 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
188 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
189 return irq_val
== VGIC_CFG_EDGE
;
192 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
194 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
196 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
199 static int vgic_irq_is_queued(struct kvm_vcpu
*vcpu
, int irq
)
201 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
203 return vgic_bitmap_get_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
);
206 static void vgic_irq_set_queued(struct kvm_vcpu
*vcpu
, int irq
)
208 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
210 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 1);
213 static void vgic_irq_clear_queued(struct kvm_vcpu
*vcpu
, int irq
)
215 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
217 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 0);
220 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
222 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
224 return vgic_bitmap_get_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
);
227 static void vgic_dist_irq_set_pending(struct kvm_vcpu
*vcpu
, int irq
)
229 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
231 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 1);
234 static void vgic_dist_irq_clear_pending(struct kvm_vcpu
*vcpu
, int irq
)
236 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
238 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 0);
241 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
243 if (irq
< VGIC_NR_PRIVATE_IRQS
)
244 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
246 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
247 vcpu
->arch
.vgic_cpu
.pending_shared
);
250 static void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
252 if (irq
< VGIC_NR_PRIVATE_IRQS
)
253 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
255 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
256 vcpu
->arch
.vgic_cpu
.pending_shared
);
259 static bool vgic_can_sample_irq(struct kvm_vcpu
*vcpu
, int irq
)
261 return vgic_irq_is_edge(vcpu
, irq
) || !vgic_irq_is_queued(vcpu
, irq
);
264 static u32
mmio_data_read(struct kvm_exit_mmio
*mmio
, u32 mask
)
266 return le32_to_cpu(*((u32
*)mmio
->data
)) & mask
;
269 static void mmio_data_write(struct kvm_exit_mmio
*mmio
, u32 mask
, u32 value
)
271 *((u32
*)mmio
->data
) = cpu_to_le32(value
) & mask
;
275 * vgic_reg_access - access vgic register
276 * @mmio: pointer to the data describing the mmio access
277 * @reg: pointer to the virtual backing of vgic distributor data
278 * @offset: least significant 2 bits used for word offset
279 * @mode: ACCESS_ mode (see defines above)
281 * Helper to make vgic register access easier using one of the access
282 * modes defined for vgic register access
283 * (read,raz,write-ignored,setbit,clearbit,write)
285 static void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
286 phys_addr_t offset
, int mode
)
288 int word_offset
= (offset
& 3) * 8;
289 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
293 * Any alignment fault should have been delivered to the guest
294 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
300 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
304 if (mmio
->is_write
) {
305 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
306 switch (ACCESS_WRITE_MASK(mode
)) {
307 case ACCESS_WRITE_IGNORED
:
310 case ACCESS_WRITE_SETBIT
:
314 case ACCESS_WRITE_CLEARBIT
:
318 case ACCESS_WRITE_VALUE
:
319 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
324 switch (ACCESS_READ_MASK(mode
)) {
325 case ACCESS_READ_RAZ
:
329 case ACCESS_READ_VALUE
:
330 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
335 static bool handle_mmio_misc(struct kvm_vcpu
*vcpu
,
336 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
339 u32 word_offset
= offset
& 3;
341 switch (offset
& ~3) {
342 case 0: /* GICD_CTLR */
343 reg
= vcpu
->kvm
->arch
.vgic
.enabled
;
344 vgic_reg_access(mmio
, ®
, word_offset
,
345 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
346 if (mmio
->is_write
) {
347 vcpu
->kvm
->arch
.vgic
.enabled
= reg
& 1;
348 vgic_update_state(vcpu
->kvm
);
353 case 4: /* GICD_TYPER */
354 reg
= (atomic_read(&vcpu
->kvm
->online_vcpus
) - 1) << 5;
355 reg
|= (VGIC_NR_IRQS
>> 5) - 1;
356 vgic_reg_access(mmio
, ®
, word_offset
,
357 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
360 case 8: /* GICD_IIDR */
361 reg
= (PRODUCT_ID_KVM
<< 24) | (IMPLEMENTER_ARM
<< 0);
362 vgic_reg_access(mmio
, ®
, word_offset
,
363 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
370 static bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
,
371 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
373 vgic_reg_access(mmio
, NULL
, offset
,
374 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
378 static bool handle_mmio_set_enable_reg(struct kvm_vcpu
*vcpu
,
379 struct kvm_exit_mmio
*mmio
,
382 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
383 vcpu
->vcpu_id
, offset
);
384 vgic_reg_access(mmio
, reg
, offset
,
385 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
386 if (mmio
->is_write
) {
387 vgic_update_state(vcpu
->kvm
);
394 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu
*vcpu
,
395 struct kvm_exit_mmio
*mmio
,
398 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
399 vcpu
->vcpu_id
, offset
);
400 vgic_reg_access(mmio
, reg
, offset
,
401 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
402 if (mmio
->is_write
) {
403 if (offset
< 4) /* Force SGI enabled */
405 vgic_retire_disabled_irqs(vcpu
);
406 vgic_update_state(vcpu
->kvm
);
413 static bool handle_mmio_set_pending_reg(struct kvm_vcpu
*vcpu
,
414 struct kvm_exit_mmio
*mmio
,
417 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_pending
,
418 vcpu
->vcpu_id
, offset
);
419 vgic_reg_access(mmio
, reg
, offset
,
420 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
421 if (mmio
->is_write
) {
422 vgic_update_state(vcpu
->kvm
);
429 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu
*vcpu
,
430 struct kvm_exit_mmio
*mmio
,
433 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_pending
,
434 vcpu
->vcpu_id
, offset
);
435 vgic_reg_access(mmio
, reg
, offset
,
436 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
437 if (mmio
->is_write
) {
438 vgic_update_state(vcpu
->kvm
);
445 static bool handle_mmio_priority_reg(struct kvm_vcpu
*vcpu
,
446 struct kvm_exit_mmio
*mmio
,
449 u32
*reg
= vgic_bytemap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_priority
,
450 vcpu
->vcpu_id
, offset
);
451 vgic_reg_access(mmio
, reg
, offset
,
452 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
456 #define GICD_ITARGETSR_SIZE 32
457 #define GICD_CPUTARGETS_BITS 8
458 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
459 static u32
vgic_get_target_reg(struct kvm
*kvm
, int irq
)
461 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
465 irq
-= VGIC_NR_PRIVATE_IRQS
;
467 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++)
468 val
|= 1 << (dist
->irq_spi_cpu
[irq
+ i
] + i
* 8);
473 static void vgic_set_target_reg(struct kvm
*kvm
, u32 val
, int irq
)
475 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
476 struct kvm_vcpu
*vcpu
;
481 irq
-= VGIC_NR_PRIVATE_IRQS
;
484 * Pick the LSB in each byte. This ensures we target exactly
485 * one vcpu per IRQ. If the byte is null, assume we target
488 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++) {
489 int shift
= i
* GICD_CPUTARGETS_BITS
;
490 target
= ffs((val
>> shift
) & 0xffU
);
491 target
= target
? (target
- 1) : 0;
492 dist
->irq_spi_cpu
[irq
+ i
] = target
;
493 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
494 bmap
= vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[c
]);
496 set_bit(irq
+ i
, bmap
);
498 clear_bit(irq
+ i
, bmap
);
503 static bool handle_mmio_target_reg(struct kvm_vcpu
*vcpu
,
504 struct kvm_exit_mmio
*mmio
,
509 /* We treat the banked interrupts targets as read-only */
511 u32 roreg
= 1 << vcpu
->vcpu_id
;
513 roreg
|= roreg
<< 16;
515 vgic_reg_access(mmio
, &roreg
, offset
,
516 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
520 reg
= vgic_get_target_reg(vcpu
->kvm
, offset
& ~3U);
521 vgic_reg_access(mmio
, ®
, offset
,
522 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
523 if (mmio
->is_write
) {
524 vgic_set_target_reg(vcpu
->kvm
, reg
, offset
& ~3U);
525 vgic_update_state(vcpu
->kvm
);
532 static u32
vgic_cfg_expand(u16 val
)
538 * Turn a 16bit value like abcd...mnop into a 32bit word
539 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
541 for (i
= 0; i
< 16; i
++)
542 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
547 static u16
vgic_cfg_compress(u32 val
)
553 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
554 * abcd...mnop which is what we really care about.
556 for (i
= 0; i
< 16; i
++)
557 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
563 * The distributor uses 2 bits per IRQ for the CFG register, but the
564 * LSB is always 0. As such, we only keep the upper bit, and use the
565 * two above functions to compress/expand the bits
567 static bool handle_mmio_cfg_reg(struct kvm_vcpu
*vcpu
,
568 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
573 reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_cfg
,
574 vcpu
->vcpu_id
, offset
>> 1);
581 val
= vgic_cfg_expand(val
);
582 vgic_reg_access(mmio
, &val
, offset
,
583 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
584 if (mmio
->is_write
) {
586 *reg
= ~0U; /* Force PPIs/SGIs to 1 */
590 val
= vgic_cfg_compress(val
);
595 *reg
&= 0xffff << 16;
603 static bool handle_mmio_sgi_reg(struct kvm_vcpu
*vcpu
,
604 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
607 vgic_reg_access(mmio
, ®
, offset
,
608 ACCESS_READ_RAZ
| ACCESS_WRITE_VALUE
);
609 if (mmio
->is_write
) {
610 vgic_dispatch_sgi(vcpu
, reg
);
611 vgic_update_state(vcpu
->kvm
);
619 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
620 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
622 * Move any pending IRQs that have already been assigned to LRs back to the
623 * emulated distributor state so that the complete emulated state can be read
624 * from the main emulation structures without investigating the LRs.
626 * Note that IRQs in the active state in the LRs get their pending state moved
627 * to the distributor but the active state stays in the LRs, because we don't
628 * track the active state on the distributor side.
630 static void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
632 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
633 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
634 int vcpu_id
= vcpu
->vcpu_id
;
637 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
638 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
641 * There are three options for the state bits:
645 * 11: pending and active
647 * If the LR holds only an active interrupt (not pending) then
648 * just leave it alone.
650 if ((lr
.state
& LR_STATE_MASK
) == LR_STATE_ACTIVE
)
654 * Reestablish the pending state on the distributor and the
655 * CPU interface. It may have already been pending, but that
656 * is fine, then we are only setting a few bits that were
659 vgic_dist_irq_set_pending(vcpu
, lr
.irq
);
660 if (lr
.irq
< VGIC_NR_SGIS
)
661 dist
->irq_sgi_sources
[vcpu_id
][lr
.irq
] |= 1 << lr
.source
;
662 lr
.state
&= ~LR_STATE_PENDING
;
663 vgic_set_lr(vcpu
, i
, lr
);
666 * If there's no state left on the LR (it could still be
667 * active), then the LR does not hold any useful info and can
668 * be marked as free for other use.
670 if (!(lr
.state
& LR_STATE_MASK
))
671 vgic_retire_lr(i
, lr
.irq
, vcpu
);
673 /* Finally update the VGIC state. */
674 vgic_update_state(vcpu
->kvm
);
678 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
679 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
680 struct kvm_exit_mmio
*mmio
,
683 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
685 int min_sgi
= (offset
& ~0x3) * 4;
686 int max_sgi
= min_sgi
+ 3;
687 int vcpu_id
= vcpu
->vcpu_id
;
690 /* Copy source SGIs from distributor side */
691 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
692 int shift
= 8 * (sgi
- min_sgi
);
693 reg
|= (u32
)dist
->irq_sgi_sources
[vcpu_id
][sgi
] << shift
;
696 mmio_data_write(mmio
, ~0, reg
);
700 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
701 struct kvm_exit_mmio
*mmio
,
702 phys_addr_t offset
, bool set
)
704 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
706 int min_sgi
= (offset
& ~0x3) * 4;
707 int max_sgi
= min_sgi
+ 3;
708 int vcpu_id
= vcpu
->vcpu_id
;
710 bool updated
= false;
712 reg
= mmio_data_read(mmio
, ~0);
714 /* Clear pending SGIs on the distributor */
715 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
716 u8 mask
= reg
>> (8 * (sgi
- min_sgi
));
718 if ((dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
) != mask
)
720 dist
->irq_sgi_sources
[vcpu_id
][sgi
] |= mask
;
722 if (dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
)
724 dist
->irq_sgi_sources
[vcpu_id
][sgi
] &= ~mask
;
729 vgic_update_state(vcpu
->kvm
);
734 static bool handle_mmio_sgi_set(struct kvm_vcpu
*vcpu
,
735 struct kvm_exit_mmio
*mmio
,
739 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
741 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, true);
744 static bool handle_mmio_sgi_clear(struct kvm_vcpu
*vcpu
,
745 struct kvm_exit_mmio
*mmio
,
749 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
751 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, false);
755 * I would have liked to use the kvm_bus_io_*() API instead, but it
756 * cannot cope with banked registers (only the VM pointer is passed
757 * around, and we need the vcpu). One of these days, someone please
763 bool (*handle_mmio
)(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
767 static const struct mmio_range vgic_dist_ranges
[] = {
769 .base
= GIC_DIST_CTRL
,
771 .handle_mmio
= handle_mmio_misc
,
774 .base
= GIC_DIST_IGROUP
,
775 .len
= VGIC_NR_IRQS
/ 8,
776 .handle_mmio
= handle_mmio_raz_wi
,
779 .base
= GIC_DIST_ENABLE_SET
,
780 .len
= VGIC_NR_IRQS
/ 8,
781 .handle_mmio
= handle_mmio_set_enable_reg
,
784 .base
= GIC_DIST_ENABLE_CLEAR
,
785 .len
= VGIC_NR_IRQS
/ 8,
786 .handle_mmio
= handle_mmio_clear_enable_reg
,
789 .base
= GIC_DIST_PENDING_SET
,
790 .len
= VGIC_NR_IRQS
/ 8,
791 .handle_mmio
= handle_mmio_set_pending_reg
,
794 .base
= GIC_DIST_PENDING_CLEAR
,
795 .len
= VGIC_NR_IRQS
/ 8,
796 .handle_mmio
= handle_mmio_clear_pending_reg
,
799 .base
= GIC_DIST_ACTIVE_SET
,
800 .len
= VGIC_NR_IRQS
/ 8,
801 .handle_mmio
= handle_mmio_raz_wi
,
804 .base
= GIC_DIST_ACTIVE_CLEAR
,
805 .len
= VGIC_NR_IRQS
/ 8,
806 .handle_mmio
= handle_mmio_raz_wi
,
809 .base
= GIC_DIST_PRI
,
811 .handle_mmio
= handle_mmio_priority_reg
,
814 .base
= GIC_DIST_TARGET
,
816 .handle_mmio
= handle_mmio_target_reg
,
819 .base
= GIC_DIST_CONFIG
,
820 .len
= VGIC_NR_IRQS
/ 4,
821 .handle_mmio
= handle_mmio_cfg_reg
,
824 .base
= GIC_DIST_SOFTINT
,
826 .handle_mmio
= handle_mmio_sgi_reg
,
829 .base
= GIC_DIST_SGI_PENDING_CLEAR
,
831 .handle_mmio
= handle_mmio_sgi_clear
,
834 .base
= GIC_DIST_SGI_PENDING_SET
,
836 .handle_mmio
= handle_mmio_sgi_set
,
842 struct mmio_range
*find_matching_range(const struct mmio_range
*ranges
,
843 struct kvm_exit_mmio
*mmio
,
846 const struct mmio_range
*r
= ranges
;
849 if (offset
>= r
->base
&&
850 (offset
+ mmio
->len
) <= (r
->base
+ r
->len
))
859 * vgic_handle_mmio - handle an in-kernel MMIO access
860 * @vcpu: pointer to the vcpu performing the access
861 * @run: pointer to the kvm_run structure
862 * @mmio: pointer to the data describing the access
864 * returns true if the MMIO access has been performed in kernel space,
865 * and false if it needs to be emulated in user space.
867 bool vgic_handle_mmio(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
868 struct kvm_exit_mmio
*mmio
)
870 const struct mmio_range
*range
;
871 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
872 unsigned long base
= dist
->vgic_dist_base
;
874 unsigned long offset
;
876 if (!irqchip_in_kernel(vcpu
->kvm
) ||
877 mmio
->phys_addr
< base
||
878 (mmio
->phys_addr
+ mmio
->len
) > (base
+ KVM_VGIC_V2_DIST_SIZE
))
881 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
883 kvm_inject_dabt(vcpu
, mmio
->phys_addr
);
887 offset
= mmio
->phys_addr
- base
;
888 range
= find_matching_range(vgic_dist_ranges
, mmio
, offset
);
889 if (unlikely(!range
|| !range
->handle_mmio
)) {
890 pr_warn("Unhandled access %d %08llx %d\n",
891 mmio
->is_write
, mmio
->phys_addr
, mmio
->len
);
895 spin_lock(&vcpu
->kvm
->arch
.vgic
.lock
);
896 offset
= mmio
->phys_addr
- range
->base
- base
;
897 updated_state
= range
->handle_mmio(vcpu
, mmio
, offset
);
898 spin_unlock(&vcpu
->kvm
->arch
.vgic
.lock
);
899 kvm_prepare_mmio(run
, mmio
);
900 kvm_handle_mmio_return(vcpu
, run
);
903 vgic_kick_vcpus(vcpu
->kvm
);
908 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
)
910 struct kvm
*kvm
= vcpu
->kvm
;
911 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
912 int nrcpus
= atomic_read(&kvm
->online_vcpus
);
914 int sgi
, mode
, c
, vcpu_id
;
916 vcpu_id
= vcpu
->vcpu_id
;
919 target_cpus
= (reg
>> 16) & 0xff;
920 mode
= (reg
>> 24) & 3;
929 target_cpus
= ((1 << nrcpus
) - 1) & ~(1 << vcpu_id
) & 0xff;
933 target_cpus
= 1 << vcpu_id
;
937 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
938 if (target_cpus
& 1) {
939 /* Flag the SGI as pending */
940 vgic_dist_irq_set_pending(vcpu
, sgi
);
941 dist
->irq_sgi_sources
[c
][sgi
] |= 1 << vcpu_id
;
942 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi
, vcpu_id
, c
);
949 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
951 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
952 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
953 unsigned long pending_private
, pending_shared
;
956 vcpu_id
= vcpu
->vcpu_id
;
957 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
958 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
960 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_pending
, vcpu_id
);
961 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
962 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
964 pending
= vgic_bitmap_get_shared_map(&dist
->irq_pending
);
965 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
966 bitmap_and(pend_shared
, pending
, enabled
, VGIC_NR_SHARED_IRQS
);
967 bitmap_and(pend_shared
, pend_shared
,
968 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
969 VGIC_NR_SHARED_IRQS
);
971 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
972 pending_shared
= find_first_bit(pend_shared
, VGIC_NR_SHARED_IRQS
);
973 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
974 pending_shared
< VGIC_NR_SHARED_IRQS
);
978 * Update the interrupt state and determine which CPUs have pending
979 * interrupts. Must be called with distributor lock held.
981 static void vgic_update_state(struct kvm
*kvm
)
983 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
984 struct kvm_vcpu
*vcpu
;
987 if (!dist
->enabled
) {
988 set_bit(0, &dist
->irq_pending_on_cpu
);
992 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
993 if (compute_pending_for_cpu(vcpu
)) {
994 pr_debug("CPU%d has pending interrupts\n", c
);
995 set_bit(c
, &dist
->irq_pending_on_cpu
);
1000 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1002 return vgic_ops
->get_lr(vcpu
, lr
);
1005 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1008 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
1011 static void vgic_sync_lr_elrsr(struct kvm_vcpu
*vcpu
, int lr
,
1014 vgic_ops
->sync_lr_elrsr(vcpu
, lr
, vlr
);
1017 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
1019 return vgic_ops
->get_elrsr(vcpu
);
1022 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
1024 return vgic_ops
->get_eisr(vcpu
);
1027 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1029 return vgic_ops
->get_interrupt_status(vcpu
);
1032 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1034 vgic_ops
->enable_underflow(vcpu
);
1037 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1039 vgic_ops
->disable_underflow(vcpu
);
1042 static inline void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1044 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1047 static void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1049 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1052 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1054 vgic_ops
->enable(vcpu
);
1057 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1059 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1060 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1063 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1064 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1065 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1069 * An interrupt may have been disabled after being made pending on the
1070 * CPU interface (the classic case is a timer running while we're
1071 * rebooting the guest - the interrupt would kick as soon as the CPU
1072 * interface gets enabled, with deadly consequences).
1074 * The solution is to examine already active LRs, and check the
1075 * interrupt is still enabled. If not, just retire it.
1077 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1079 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1082 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic
->nr_lr
) {
1083 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1085 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1086 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1087 if (vgic_irq_is_queued(vcpu
, vlr
.irq
))
1088 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1094 * Queue an interrupt to a CPU virtual interface. Return true on success,
1095 * or false if it wasn't possible to queue it.
1097 static bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1099 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1103 /* Sanitize the input... */
1104 BUG_ON(sgi_source_id
& ~7);
1105 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1106 BUG_ON(irq
>= VGIC_NR_IRQS
);
1108 kvm_debug("Queue IRQ%d\n", irq
);
1110 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1112 /* Do we have an active interrupt for the same CPUID? */
1113 if (lr
!= LR_EMPTY
) {
1114 vlr
= vgic_get_lr(vcpu
, lr
);
1115 if (vlr
.source
== sgi_source_id
) {
1116 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1117 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1118 vlr
.state
|= LR_STATE_PENDING
;
1119 vgic_set_lr(vcpu
, lr
, vlr
);
1124 /* Try to use another LR for this interrupt */
1125 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1127 if (lr
>= vgic
->nr_lr
)
1130 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1131 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1132 set_bit(lr
, vgic_cpu
->lr_used
);
1135 vlr
.source
= sgi_source_id
;
1136 vlr
.state
= LR_STATE_PENDING
;
1137 if (!vgic_irq_is_edge(vcpu
, irq
))
1138 vlr
.state
|= LR_EOI_INT
;
1140 vgic_set_lr(vcpu
, lr
, vlr
);
1145 static bool vgic_queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
1147 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1148 unsigned long sources
;
1149 int vcpu_id
= vcpu
->vcpu_id
;
1152 sources
= dist
->irq_sgi_sources
[vcpu_id
][irq
];
1154 for_each_set_bit(c
, &sources
, VGIC_MAX_CPUS
) {
1155 if (vgic_queue_irq(vcpu
, c
, irq
))
1156 clear_bit(c
, &sources
);
1159 dist
->irq_sgi_sources
[vcpu_id
][irq
] = sources
;
1162 * If the sources bitmap has been cleared it means that we
1163 * could queue all the SGIs onto link registers (see the
1164 * clear_bit above), and therefore we are done with them in
1165 * our emulated gic and can get rid of them.
1168 vgic_dist_irq_clear_pending(vcpu
, irq
);
1169 vgic_cpu_irq_clear(vcpu
, irq
);
1176 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1178 if (!vgic_can_sample_irq(vcpu
, irq
))
1179 return true; /* level interrupt, already queued */
1181 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1182 if (vgic_irq_is_edge(vcpu
, irq
)) {
1183 vgic_dist_irq_clear_pending(vcpu
, irq
);
1184 vgic_cpu_irq_clear(vcpu
, irq
);
1186 vgic_irq_set_queued(vcpu
, irq
);
1196 * Fill the list registers with pending interrupts before running the
1199 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1201 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1202 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1206 vcpu_id
= vcpu
->vcpu_id
;
1209 * We may not have any pending interrupt, or the interrupts
1210 * may have been serviced from another vcpu. In all cases,
1213 if (!kvm_vgic_vcpu_pending_irq(vcpu
)) {
1214 pr_debug("CPU%d has no pending interrupt\n", vcpu_id
);
1219 for_each_set_bit(i
, vgic_cpu
->pending_percpu
, VGIC_NR_SGIS
) {
1220 if (!vgic_queue_sgi(vcpu
, i
))
1225 for_each_set_bit_from(i
, vgic_cpu
->pending_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1226 if (!vgic_queue_hwirq(vcpu
, i
))
1231 for_each_set_bit(i
, vgic_cpu
->pending_shared
, VGIC_NR_SHARED_IRQS
) {
1232 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1238 vgic_enable_underflow(vcpu
);
1240 vgic_disable_underflow(vcpu
);
1242 * We're about to run this VCPU, and we've consumed
1243 * everything the distributor had in store for
1244 * us. Claim we don't have anything pending. We'll
1245 * adjust that if needed while exiting.
1247 clear_bit(vcpu_id
, &dist
->irq_pending_on_cpu
);
1251 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1253 u32 status
= vgic_get_interrupt_status(vcpu
);
1254 bool level_pending
= false;
1256 kvm_debug("STATUS = %08x\n", status
);
1258 if (status
& INT_STATUS_EOI
) {
1260 * Some level interrupts have been EOIed. Clear their
1263 u64 eisr
= vgic_get_eisr(vcpu
);
1264 unsigned long *eisr_ptr
= (unsigned long *)&eisr
;
1267 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1268 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1270 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1271 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1273 vgic_set_lr(vcpu
, lr
, vlr
);
1275 /* Any additional pending interrupt? */
1276 if (vgic_dist_irq_is_pending(vcpu
, vlr
.irq
)) {
1277 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1278 level_pending
= true;
1280 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1284 * Despite being EOIed, the LR may not have
1285 * been marked as empty.
1287 vgic_sync_lr_elrsr(vcpu
, lr
, vlr
);
1291 if (status
& INT_STATUS_UNDERFLOW
)
1292 vgic_disable_underflow(vcpu
);
1294 return level_pending
;
1298 * Sync back the VGIC state after a guest run. The distributor lock is
1299 * needed so we don't get preempted in the middle of the state processing.
1301 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1303 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1304 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1306 unsigned long *elrsr_ptr
;
1310 level_pending
= vgic_process_maintenance(vcpu
);
1311 elrsr
= vgic_get_elrsr(vcpu
);
1312 elrsr_ptr
= (unsigned long *)&elrsr
;
1314 /* Clear mappings for empty LRs */
1315 for_each_set_bit(lr
, elrsr_ptr
, vgic
->nr_lr
) {
1318 if (!test_and_clear_bit(lr
, vgic_cpu
->lr_used
))
1321 vlr
= vgic_get_lr(vcpu
, lr
);
1323 BUG_ON(vlr
.irq
>= VGIC_NR_IRQS
);
1324 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1327 /* Check if we still have something up our sleeve... */
1328 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1329 if (level_pending
|| pending
< vgic
->nr_lr
)
1330 set_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1333 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1335 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1337 if (!irqchip_in_kernel(vcpu
->kvm
))
1340 spin_lock(&dist
->lock
);
1341 __kvm_vgic_flush_hwstate(vcpu
);
1342 spin_unlock(&dist
->lock
);
1345 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1347 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1349 if (!irqchip_in_kernel(vcpu
->kvm
))
1352 spin_lock(&dist
->lock
);
1353 __kvm_vgic_sync_hwstate(vcpu
);
1354 spin_unlock(&dist
->lock
);
1357 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1359 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1361 if (!irqchip_in_kernel(vcpu
->kvm
))
1364 return test_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1367 static void vgic_kick_vcpus(struct kvm
*kvm
)
1369 struct kvm_vcpu
*vcpu
;
1373 * We've injected an interrupt, time to find out who deserves
1376 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1377 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1378 kvm_vcpu_kick(vcpu
);
1382 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1384 int edge_triggered
= vgic_irq_is_edge(vcpu
, irq
);
1385 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1388 * Only inject an interrupt if:
1389 * - edge triggered and we have a rising edge
1390 * - level triggered and we change level
1393 return level
> state
;
1395 return level
!= state
;
1398 static bool vgic_update_irq_pending(struct kvm
*kvm
, int cpuid
,
1399 unsigned int irq_num
, bool level
)
1401 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1402 struct kvm_vcpu
*vcpu
;
1403 int edge_triggered
, level_triggered
;
1407 spin_lock(&dist
->lock
);
1409 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1410 edge_triggered
= vgic_irq_is_edge(vcpu
, irq_num
);
1411 level_triggered
= !edge_triggered
;
1413 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1418 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1419 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1420 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1423 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1426 vgic_dist_irq_set_pending(vcpu
, irq_num
);
1428 vgic_dist_irq_clear_pending(vcpu
, irq_num
);
1430 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1437 if (!vgic_can_sample_irq(vcpu
, irq_num
)) {
1439 * Level interrupt in progress, will be picked up
1447 vgic_cpu_irq_set(vcpu
, irq_num
);
1448 set_bit(cpuid
, &dist
->irq_pending_on_cpu
);
1452 spin_unlock(&dist
->lock
);
1458 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1459 * @kvm: The VM structure pointer
1460 * @cpuid: The CPU for PPIs
1461 * @irq_num: The IRQ number that is assigned to the device
1462 * @level: Edge-triggered: true: to trigger the interrupt
1463 * false: to ignore the call
1464 * Level-sensitive true: activates an interrupt
1465 * false: deactivates an interrupt
1467 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1468 * level-sensitive interrupts. You can think of the level parameter as 1
1469 * being HIGH and 0 being LOW and all devices being active-HIGH.
1471 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1474 if (vgic_update_irq_pending(kvm
, cpuid
, irq_num
, level
))
1475 vgic_kick_vcpus(kvm
);
1480 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1483 * We cannot rely on the vgic maintenance interrupt to be
1484 * delivered synchronously. This means we can only use it to
1485 * exit the VM, and we perform the handling of EOIed
1486 * interrupts on the exit path (see vgic_process_maintenance).
1492 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1493 * @vcpu: pointer to the vcpu struct
1495 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1496 * this vcpu and enable the VGIC for this VCPU
1498 int kvm_vgic_vcpu_init(struct kvm_vcpu
*vcpu
)
1500 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1501 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1504 if (vcpu
->vcpu_id
>= VGIC_MAX_CPUS
)
1507 for (i
= 0; i
< VGIC_NR_IRQS
; i
++) {
1508 if (i
< VGIC_NR_PPIS
)
1509 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
1510 vcpu
->vcpu_id
, i
, 1);
1511 if (i
< VGIC_NR_PRIVATE_IRQS
)
1512 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
1513 vcpu
->vcpu_id
, i
, VGIC_CFG_EDGE
);
1515 vgic_cpu
->vgic_irq_lr_map
[i
] = LR_EMPTY
;
1519 * Store the number of LRs per vcpu, so we don't have to go
1520 * all the way to the distributor structure to find out. Only
1521 * assembly code should use this one.
1523 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
1531 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1532 * @kvm: pointer to the kvm struct
1534 * Map the virtual CPU interface into the VM before running any VCPUs. We
1535 * can't do this at creation time, because user space must first set the
1536 * virtual CPU interface address in the guest physical address space. Also
1537 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1539 int kvm_vgic_init(struct kvm
*kvm
)
1543 if (!irqchip_in_kernel(kvm
))
1546 mutex_lock(&kvm
->lock
);
1548 if (vgic_initialized(kvm
))
1551 if (IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_dist_base
) ||
1552 IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_cpu_base
)) {
1553 kvm_err("Need to set vgic cpu and dist addresses first\n");
1558 ret
= kvm_phys_addr_ioremap(kvm
, kvm
->arch
.vgic
.vgic_cpu_base
,
1559 vgic
->vcpu_base
, KVM_VGIC_V2_CPU_SIZE
);
1561 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1565 for (i
= VGIC_NR_PRIVATE_IRQS
; i
< VGIC_NR_IRQS
; i
+= 4)
1566 vgic_set_target_reg(kvm
, 0, i
);
1568 kvm
->arch
.vgic
.ready
= true;
1570 mutex_unlock(&kvm
->lock
);
1574 int kvm_vgic_create(struct kvm
*kvm
)
1576 int i
, vcpu_lock_idx
= -1, ret
= 0;
1577 struct kvm_vcpu
*vcpu
;
1579 mutex_lock(&kvm
->lock
);
1581 if (kvm
->arch
.vgic
.vctrl_base
) {
1587 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1588 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1589 * that no other VCPUs are run while we create the vgic.
1591 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1592 if (!mutex_trylock(&vcpu
->mutex
))
1597 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1598 if (vcpu
->arch
.has_run_once
) {
1604 spin_lock_init(&kvm
->arch
.vgic
.lock
);
1605 kvm
->arch
.vgic
.in_kernel
= true;
1606 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
1607 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
1608 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
1611 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
1612 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
1613 mutex_unlock(&vcpu
->mutex
);
1617 mutex_unlock(&kvm
->lock
);
1621 static int vgic_ioaddr_overlap(struct kvm
*kvm
)
1623 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
1624 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
1626 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
1628 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
1629 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
1634 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
1635 phys_addr_t addr
, phys_addr_t size
)
1639 if (addr
& ~KVM_PHYS_MASK
)
1642 if (addr
& (SZ_4K
- 1))
1645 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
1647 if (addr
+ size
< addr
)
1651 ret
= vgic_ioaddr_overlap(kvm
);
1653 *ioaddr
= VGIC_ADDR_UNDEF
;
1659 * kvm_vgic_addr - set or get vgic VM base addresses
1660 * @kvm: pointer to the vm struct
1661 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1662 * @addr: pointer to address value
1663 * @write: if true set the address in the VM address space, if false read the
1666 * Set or get the vgic base addresses for the distributor and the virtual CPU
1667 * interface in the VM physical address space. These addresses are properties
1668 * of the emulated core/SoC and therefore user space initially knows this
1671 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
1674 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
1676 mutex_lock(&kvm
->lock
);
1678 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
1680 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_dist_base
,
1681 *addr
, KVM_VGIC_V2_DIST_SIZE
);
1683 *addr
= vgic
->vgic_dist_base
;
1686 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
1688 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_cpu_base
,
1689 *addr
, KVM_VGIC_V2_CPU_SIZE
);
1691 *addr
= vgic
->vgic_cpu_base
;
1698 mutex_unlock(&kvm
->lock
);
1702 static bool handle_cpu_mmio_misc(struct kvm_vcpu
*vcpu
,
1703 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1705 bool updated
= false;
1706 struct vgic_vmcr vmcr
;
1710 vgic_get_vmcr(vcpu
, &vmcr
);
1712 switch (offset
& ~0x3) {
1714 vmcr_field
= &vmcr
.ctlr
;
1716 case GIC_CPU_PRIMASK
:
1717 vmcr_field
= &vmcr
.pmr
;
1719 case GIC_CPU_BINPOINT
:
1720 vmcr_field
= &vmcr
.bpr
;
1722 case GIC_CPU_ALIAS_BINPOINT
:
1723 vmcr_field
= &vmcr
.abpr
;
1729 if (!mmio
->is_write
) {
1731 mmio_data_write(mmio
, ~0, reg
);
1733 reg
= mmio_data_read(mmio
, ~0);
1734 if (reg
!= *vmcr_field
) {
1736 vgic_set_vmcr(vcpu
, &vmcr
);
1743 static bool handle_mmio_abpr(struct kvm_vcpu
*vcpu
,
1744 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1746 return handle_cpu_mmio_misc(vcpu
, mmio
, GIC_CPU_ALIAS_BINPOINT
);
1749 static bool handle_cpu_mmio_ident(struct kvm_vcpu
*vcpu
,
1750 struct kvm_exit_mmio
*mmio
,
1759 reg
= (PRODUCT_ID_KVM
<< 20) |
1760 (GICC_ARCH_VERSION_V2
<< 16) |
1761 (IMPLEMENTER_ARM
<< 0);
1762 mmio_data_write(mmio
, ~0, reg
);
1767 * CPU Interface Register accesses - these are not accessed by the VM, but by
1768 * user space for saving and restoring VGIC state.
1770 static const struct mmio_range vgic_cpu_ranges
[] = {
1772 .base
= GIC_CPU_CTRL
,
1774 .handle_mmio
= handle_cpu_mmio_misc
,
1777 .base
= GIC_CPU_ALIAS_BINPOINT
,
1779 .handle_mmio
= handle_mmio_abpr
,
1782 .base
= GIC_CPU_ACTIVEPRIO
,
1784 .handle_mmio
= handle_mmio_raz_wi
,
1787 .base
= GIC_CPU_IDENT
,
1789 .handle_mmio
= handle_cpu_mmio_ident
,
1793 static int vgic_attr_regs_access(struct kvm_device
*dev
,
1794 struct kvm_device_attr
*attr
,
1795 u32
*reg
, bool is_write
)
1797 const struct mmio_range
*r
= NULL
, *ranges
;
1800 struct kvm_vcpu
*vcpu
, *tmp_vcpu
;
1801 struct vgic_dist
*vgic
;
1802 struct kvm_exit_mmio mmio
;
1804 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
1805 cpuid
= (attr
->attr
& KVM_DEV_ARM_VGIC_CPUID_MASK
) >>
1806 KVM_DEV_ARM_VGIC_CPUID_SHIFT
;
1808 mutex_lock(&dev
->kvm
->lock
);
1810 if (cpuid
>= atomic_read(&dev
->kvm
->online_vcpus
)) {
1815 vcpu
= kvm_get_vcpu(dev
->kvm
, cpuid
);
1816 vgic
= &dev
->kvm
->arch
.vgic
;
1819 mmio
.is_write
= is_write
;
1821 mmio_data_write(&mmio
, ~0, *reg
);
1822 switch (attr
->group
) {
1823 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1824 mmio
.phys_addr
= vgic
->vgic_dist_base
+ offset
;
1825 ranges
= vgic_dist_ranges
;
1827 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
1828 mmio
.phys_addr
= vgic
->vgic_cpu_base
+ offset
;
1829 ranges
= vgic_cpu_ranges
;
1834 r
= find_matching_range(ranges
, &mmio
, offset
);
1836 if (unlikely(!r
|| !r
->handle_mmio
)) {
1842 spin_lock(&vgic
->lock
);
1845 * Ensure that no other VCPU is running by checking the vcpu->cpu
1846 * field. If no other VPCUs are running we can safely access the VGIC
1847 * state, because even if another VPU is run after this point, that
1848 * VCPU will not touch the vgic state, because it will block on
1849 * getting the vgic->lock in kvm_vgic_sync_hwstate().
1851 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
) {
1852 if (unlikely(tmp_vcpu
->cpu
!= -1)) {
1854 goto out_vgic_unlock
;
1859 * Move all pending IRQs from the LRs on all VCPUs so the pending
1860 * state can be properly represented in the register state accessible
1863 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
)
1864 vgic_unqueue_irqs(tmp_vcpu
);
1867 r
->handle_mmio(vcpu
, &mmio
, offset
);
1870 *reg
= mmio_data_read(&mmio
, ~0);
1874 spin_unlock(&vgic
->lock
);
1876 mutex_unlock(&dev
->kvm
->lock
);
1880 static int vgic_set_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1884 switch (attr
->group
) {
1885 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1886 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1888 unsigned long type
= (unsigned long)attr
->attr
;
1890 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
1893 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
1894 return (r
== -ENODEV
) ? -ENXIO
: r
;
1897 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1898 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
1899 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
1902 if (get_user(reg
, uaddr
))
1905 return vgic_attr_regs_access(dev
, attr
, ®
, true);
1913 static int vgic_get_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1917 switch (attr
->group
) {
1918 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1919 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1921 unsigned long type
= (unsigned long)attr
->attr
;
1923 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
1925 return (r
== -ENODEV
) ? -ENXIO
: r
;
1927 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
1932 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1933 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
1934 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
1937 r
= vgic_attr_regs_access(dev
, attr
, ®
, false);
1940 r
= put_user(reg
, uaddr
);
1949 static int vgic_has_attr_regs(const struct mmio_range
*ranges
,
1952 struct kvm_exit_mmio dev_attr_mmio
;
1954 dev_attr_mmio
.len
= 4;
1955 if (find_matching_range(ranges
, &dev_attr_mmio
, offset
))
1961 static int vgic_has_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1965 switch (attr
->group
) {
1966 case KVM_DEV_ARM_VGIC_GRP_ADDR
:
1967 switch (attr
->attr
) {
1968 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
1969 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
1973 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1974 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
1975 return vgic_has_attr_regs(vgic_dist_ranges
, offset
);
1976 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
1977 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
1978 return vgic_has_attr_regs(vgic_cpu_ranges
, offset
);
1983 static void vgic_destroy(struct kvm_device
*dev
)
1988 static int vgic_create(struct kvm_device
*dev
, u32 type
)
1990 return kvm_vgic_create(dev
->kvm
);
1993 static struct kvm_device_ops kvm_arm_vgic_v2_ops
= {
1994 .name
= "kvm-arm-vgic",
1995 .create
= vgic_create
,
1996 .destroy
= vgic_destroy
,
1997 .set_attr
= vgic_set_attr
,
1998 .get_attr
= vgic_get_attr
,
1999 .has_attr
= vgic_has_attr
,
2002 static void vgic_init_maintenance_interrupt(void *info
)
2004 enable_percpu_irq(vgic
->maint_irq
, 0);
2007 static int vgic_cpu_notify(struct notifier_block
*self
,
2008 unsigned long action
, void *cpu
)
2012 case CPU_STARTING_FROZEN
:
2013 vgic_init_maintenance_interrupt(NULL
);
2016 case CPU_DYING_FROZEN
:
2017 disable_percpu_irq(vgic
->maint_irq
);
2024 static struct notifier_block vgic_cpu_nb
= {
2025 .notifier_call
= vgic_cpu_notify
,
2028 static const struct of_device_id vgic_ids
[] = {
2029 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
2030 { .compatible
= "arm,gic-v3", .data
= vgic_v3_probe
, },
2034 int kvm_vgic_hyp_init(void)
2036 const struct of_device_id
*matched_id
;
2037 const int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
2038 const struct vgic_params
**);
2039 struct device_node
*vgic_node
;
2042 vgic_node
= of_find_matching_node_and_match(NULL
,
2043 vgic_ids
, &matched_id
);
2045 kvm_err("error: no compatible GIC node found\n");
2049 vgic_probe
= matched_id
->data
;
2050 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
2054 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
2055 "vgic", kvm_get_running_vcpus());
2057 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
2061 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
2063 kvm_err("Cannot register vgic CPU notifier\n");
2067 /* Callback into for arch code for setup */
2068 vgic_arch_setup(vgic
);
2070 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
2072 return kvm_register_device_ops(&kvm_arm_vgic_v2_ops
,
2073 KVM_DEV_TYPE_ARM_VGIC_V2
);
2076 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());