Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an...

[deliverable/binutils-gdb.git] / bfd / bfd-in2.h

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index ceb53d5b4d011a6de90df00d1af2918a7053c961..7c13bc8c91abf291f0206b6608b31955c5ea70d8 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1888,9 +1888,13 @@ enum bfd_architecture
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
 #define bfd_mach_xtensa        1
   bfd_arch_z80,
-#define bfd_mach_z80strict     1 /* No undocumented opcodes.  */
-#define bfd_mach_z80           3 /* With ixl, ixh, iyl, and iyh.  */
-#define bfd_mach_z80full       7 /* All undocumented instructions.  */
+#define bfd_mach_gbz80         0 /* GameBoy Z80 (reduced instruction set) */
+#define bfd_mach_z80strict     1 /* Z80 without undocumented opcodes.  */
+#define bfd_mach_z180          2 /* Z180: successor with additional instructions, but without halves of ix and iy */
+#define bfd_mach_z80           3 /* Z80 with ixl, ixh, iyl, and iyh.  */
+#define bfd_mach_ez80_z80      4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
+#define bfd_mach_ez80_adl      5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
+#define bfd_mach_z80full       7 /* Z80 with all undocumented instructions.  */
 #define bfd_mach_r800          11 /* R800: successor with multiplication.  */
   bfd_arch_lm32,      /* Lattice Mico32.  */
 #define bfd_mach_lm32          1
@@ -5270,6 +5274,24 @@ BFD_RELOC_XTENSA_ASM_EXPAND.  */
 /* 8 bit signed offset in (ix+d) or (iy+d).  */
   BFD_RELOC_Z80_DISP8,
 
+/* First 8 bits of multibyte (32, 24 or 16 bit) value.  */
+  BFD_RELOC_Z80_BYTE0,
+
+/* Second 8 bits of multibyte (32, 24 or 16 bit) value.  */
+  BFD_RELOC_Z80_BYTE1,
+
+/* Third 8 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_BYTE2,
+
+/* Fourth 8 bits of multibyte (32 bit) value.  */
+  BFD_RELOC_Z80_BYTE3,
+
+/* Lowest 16 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_WORD0,
+
+/* Highest 16 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_WORD1,
+
 /* DJNZ offset.  */
   BFD_RELOC_Z8K_DISP7,