bfd/riscv: tighten matching rules in riscv_scan

[deliverable/binutils-gdb.git] / bfd / cpu-riscv.c

diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index 153a84e88354addec75e2ce2c170f57e4b232a62..22067ab29bec74c1e1f5660370163be9a739273a 100644 (file)
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -1,5 +1,5 @@
 /* BFD backend for RISC-V
-   Copyright (C) 2011-2019 Free Software Foundation, Inc.
+   Copyright (C) 2011-2020 Free Software Foundation, Inc.
 
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
@@ -39,11 +39,38 @@ riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
   return a;
 }
 
-#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT)  \
+/* Return TRUE if STRING matches the architecture described by INFO.  */
+
+static bfd_boolean
+riscv_scan (const struct bfd_arch_info *info, const char *string)
+{
+  if (bfd_default_scan (info, string))
+    return TRUE;
+
+  /* The incoming STRING might take the form of riscv:rvXXzzz, where XX is
+     32 or 64, and zzz are one or more extension characters.  As we
+     currently only have 3 architectures defined, 'riscv', 'riscv:rv32',
+     and 'riscv:rv64', we would like to ignore the zzz for the purpose of
+     matching here.
+
+     However, we don't want the default 'riscv' to match over a more
+     specific 'riscv:rv32' or 'riscv:rv64', so in the case of the default
+     architecture (with the shorter 'riscv' name) we don't allow any
+     special matching, but for the 'riscv:rvXX' cases, we allow a match
+     with any additional trailing characters being ignored.  */
+  if (!info->the_default
+      && strncasecmp (string, info->printable_name,
+                      strlen (info->printable_name)) == 0)
+    return TRUE;
+
+  return FALSE;
+}
+
+#define N(BITS, NUMBER, PRINT, DEFAULT, NEXT)                  \
   {                                                            \
-    BITS_WORD, /*  bits in a word */                           \
-    BITS_ADDR, /* bits in an address */                                \
-    8, /* 8 bits in a byte */                                  \
+    BITS,      /* Bits in a word.  */                          \
+    BITS,      /* Bits in an address.  */                      \
+    8,        /* Bits in a byte.  */                           \
     bfd_arch_riscv,                                            \
     NUMBER,                                                    \
     "riscv",                                                   \
@@ -51,9 +78,10 @@ riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
     3,                                                         \
     DEFAULT,                                                   \
     riscv_compatible,                                          \
-    bfd_default_scan,                                          \
+    riscv_scan,                                                        \
     bfd_arch_default_fill,                                     \
     NEXT,                                                      \
+    0 /* Maximum offset of a reloc from the start of an insn.  */\
   }
 
 /* This enum must be kept in the same order as arch_info_struct.  */
@@ -69,11 +97,11 @@ enum
    and each entry except the last should end with NN (my enum value).  */
 static const bfd_arch_info_type arch_info_struct[] =
 {
-  N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
-  N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0)
+  N (64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
+  N (32, bfd_mach_riscv32, "riscv:rv32", FALSE, NULL)
 };
 
 /* The default architecture is riscv:rv64.  */
 
 const bfd_arch_info_type bfd_riscv_arch =
-  N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
+  N (64, 0, "riscv", TRUE, &arch_info_struct[0]);