Add support for RISC-V architecture.

[deliverable/binutils-gdb.git] / binutils / readelf.c

diff --git a/binutils/readelf.c b/binutils/readelf.c
index 69942cf711c652e868a5b8adf1dbc4e5b47c4fa0..114486cc986d63d60d19feb198f4912c34d19f51 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -124,6 +124,7 @@
 #include "elf/metag.h"
 #include "elf/microblaze.h"
 #include "elf/mips.h"
+#include "elf/riscv.h"
 #include "elf/mmix.h"
 #include "elf/mn10200.h"
 #include "elf/mn10300.h"
@@ -775,6 +776,7 @@ guess_is_rela (unsigned int e_machine)
     case EM_OR1K:
     case EM_PPC64:
     case EM_PPC:
+    case EM_RISCV:
     case EM_RL78:
     case EM_RX:
     case EM_S390:
@@ -1314,6 +1316,10 @@ dump_relocations (FILE * file,
          rtype = elf_mips_reloc_type (type);
          break;
 
+       case EM_RISCV:
+         rtype = elf_riscv_reloc_type (type);
+         break;
+
        case EM_ALPHA:
          rtype = elf_alpha_reloc_type (type);
          break;
@@ -2327,6 +2333,7 @@ get_machine_name (unsigned e_machine)
     case EM_CR16:
     case EM_MICROBLAZE:
     case EM_MICROBLAZE_OLD:    return "Xilinx MicroBlaze";
+    case EM_RISCV:             return "RISC-V";
     case EM_RL78:              return "Renesas RL78";
     case EM_RX:                        return "Renesas RX";
     case EM_METAG:             return "Imagination Technologies Meta processor architecture";
@@ -2363,7 +2370,6 @@ get_machine_name (unsigned e_machine)
     case EM_CSR_KALIMBA:       return "CSR Kalimba architecture family";
     case EM_Z80:               return "Zilog Z80";
     case EM_AMDGPU:            return "AMD GPU architecture";
-    case EM_RISCV:             return "RISC-V";
     default:
       snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine);
       return buff;
@@ -3308,6 +3314,13 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
          decode_NDS32_machine_flags (e_flags, buf, sizeof buf);
          break;
 
+       case EM_RISCV:
+         if (e_flags & EF_RISCV_RVC)
+           strcat (buf, ", RVC");
+         if (e_flags & EF_RISCV_SOFT_FLOAT)
+           strcat (buf, ", soft-float ABI");
+         break;
+
        case EM_SH:
          switch ((e_flags & EF_SH_MACH_MASK))
            {
@@ -11788,6 +11801,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
       return reloc_type == 1; /* R_PPC64_ADDR32.  */
     case EM_PPC:
       return reloc_type == 1; /* R_PPC_ADDR32.  */
+    case EM_RISCV:
+      return reloc_type == 1; /* R_RISCV_32.  */
     case EM_RL78:
       return reloc_type == 1; /* R_RL78_DIR32.  */
     case EM_RX:
@@ -11941,6 +11956,8 @@ is_64bit_abs_reloc (unsigned int reloc_type)
       return reloc_type == 80; /* R_PARISC_DIR64.  */
     case EM_PPC64:
       return reloc_type == 38; /* R_PPC64_ADDR64.  */
+    case EM_RISCV:
+      return reloc_type == 2; /* R_RISCV_64.  */
     case EM_SPARC32PLUS:
     case EM_SPARCV9:
     case EM_SPARC:
@@ -12112,6 +12129,7 @@ is_none_reloc (unsigned int reloc_type)
     case EM_PARISC:  /* R_PARISC_NONE.  */
     case EM_PPC64:   /* R_PPC64_NONE.  */
     case EM_PPC:     /* R_PPC_NONE.  */
+    case EM_RISCV:   /* R_RISCV_NONE.  */
     case EM_S390:    /* R_390_NONE.  */
     case EM_S390_OLD:
     case EM_SH:      /* R_SH_NONE.  */