PCI quirk: mmc: Always check for lower base frequency quirk for Ricoh 1180:e823
[deliverable/linux.git] / drivers / pci / quirks.c
index 1196f61a4ab6b2dabab0faacd1cbde65bf53af9a..e5aadf357ae795c3163875ea25375658822ad7f5 100644 (file)
@@ -2745,20 +2745,6 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
        /* disable must be done via function #0 */
        if (PCI_FUNC(dev->devfn))
                return;
-
-       pci_read_config_byte(dev, 0xCB, &disable);
-
-       if (disable & 0x02)
-               return;
-
-       pci_read_config_byte(dev, 0xCA, &write_enable);
-       pci_write_config_byte(dev, 0xCA, 0x57);
-       pci_write_config_byte(dev, 0xCB, disable | 0x02);
-       pci_write_config_byte(dev, 0xCA, write_enable);
-
-       dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
-       dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
-
        /*
         * RICOH 0xe823 SD/MMC card reader fails to recognize
         * certain types of SD/MMC cards. Lowering the SD base
@@ -2781,6 +2767,20 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
 
                dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
        }
+
+       pci_read_config_byte(dev, 0xCB, &disable);
+
+       if (disable & 0x02)
+               return;
+
+       pci_read_config_byte(dev, 0xCA, &write_enable);
+       pci_write_config_byte(dev, 0xCA, 0x57);
+       pci_write_config_byte(dev, 0xCB, disable | 0x02);
+       pci_write_config_byte(dev, 0xCA, write_enable);
+
+       dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
+       dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
+
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
@@ -2822,6 +2822,20 @@ static void __devinit fixup_ti816x_class(struct pci_dev* dev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
 
+/* Some PCIe devices do not work reliably with the claimed maximum
+ * payload size supported.
+ */
+static void __devinit fixup_mpss_256(struct pci_dev *dev)
+{
+       dev->pcie_mpss = 1; /* 256 bytes */
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
+                        PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
+                        PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
+                        PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
+
 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
                          struct pci_fixup *end)
 {
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