+2019-12-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
+ (tls_get_addr): New.
+ (last_insn): New.
+ (align_branch_power): New.
+ (align_branch_kind): New.
+ (align_branch_bit): New.
+ (align_branch): New.
+ (MAX_FUSED_JCC_PADDING_SIZE): New.
+ (align_branch_prefix_size): New.
+ (BRANCH_PADDING): New.
+ (BRANCH_PREFIX): New.
+ (FUSED_JCC_PADDING): New.
+ (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
+ (md_begin): Abort if align_branch_prefix_size <
+ MAX_FUSED_JCC_PADDING_SIZE.
+ (md_assemble): Set last_insn.
+ (maybe_fused_with_jcc_p): New.
+ (add_fused_jcc_padding_frag_p): New.
+ (add_branch_prefix_frag_p): New.
+ (add_branch_padding_frag_p): New.
+ (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
+ BRANCH_PREFIX frag and terminate each frag to align branches.
+ (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
+ relaxable TLS relocations.
+ (output_imm): Likewise.
+ (i386_next_non_empty_frag): New.
+ (i386_next_jcc_frag): New.
+ (i386_classify_machine_dependent_frag): New.
+ (i386_branch_padding_size): New.
+ (i386_generic_table_relax_frag): New.
+ (md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
+ FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
+ (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
+ FUSED_JCC_PADDING frags.
+ (OPTION_MALIGN_BRANCH_BOUNDARY): New.
+ (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
+ (OPTION_MALIGN_BRANCH): New.
+ (md_longopts): Add -malign-branch-boundary=,
+ -malign-branch-prefix-size= and -malign-branch=.
+ (md_parse_option): Handle -malign-branch-boundary=,
+ -malign-branch-prefix-size= and -malign-branch=.
+ (md_show_usage): Display -malign-branch-boundary=,
+ -malign-branch-prefix-size= and -malign-branch=.
+ (i386_target_format): Set tls_get_addr.
+ (i386_cons_align): New.
+ * config/tc-i386.h (i386_cons_align): New.
+ (md_cons_align): New.
+ (i386_generic_table_relax_frag): New.
+ (md_generic_table_relax_frag): New.
+ (i386_tc_frag_data): Add u, padding_address, length,
+ max_prefix_length, prefix_length, default_prefix, cmp_size,
+ classified and branch_type.
+ (TC_FRAG_INIT): Initialize u, padding_address, length,
+ max_prefix_length, prefix_length, default_prefix, cmp_size,
+ classified and branch_type.
+ * doc/c-i386.texi: Document -malign-branch-boundary=,
+ -malign-branch= and -malign-branch-prefix-size=.
+
+2019-12-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * write.c (md_generic_table_relax_frag): New. Defined to
+ relax_frag if not defined.
+ (relax_segment): Call md_generic_table_relax_frag instead of
+ relax_frag.
+
+2019-12-12 Alan Modra <amodra@gmail.com>
+
+ * config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow.
+ * config/tc-metag.c (parse_dalu): Likewise.
+ * config/tc-tic4x.c (md_pcrel_from): Likewise.
+ * config/tc-tic6x.c (tic6x_output_unwinding): Likewise.
+ * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer.
+ Don't use register keyword. Avoid signed overflow and remove now
+ unneccesary char masks. Formatting.
+ * config/tc-ia64.c (operand_match): Don't use shifts to sign extend.
+ * config/tc-mep.c (mep_apply_fix): Likewise.
+ * config/tc-pru.c (md_apply_fix): Likewise.
+ * config/tc-riscv.c (load_const): Likewise.
+ * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially
+ truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16
+ calculation.
+
+2019-12-12 Alan Modra <amodra@gmail.com>
+
+ * config/obj-evax.c (crc32, encode_32, encode_16, decode_16):
+ Remove unnecessary prototypes.
+ (number_of_codings): Delete, use ARRAY_SIZE instead throughout.
+ (codings, decodings): Make arrays of unsigned char.
+ (crc32): Use unsigned variables. Delete unnecessary mask.
+ (encode_32, encode_16): Return unsigned char*, and make static
+ buffer an unsigned char array.
+ (decode_16): Make arg an unsigned char*. Remove useless casts.
+ (shorten_identifier): Use unsigned char crc_chars.
+ (is_truncated_identifier): Make ptr an unsigned char*.
+
+2019-12-11 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/tc-arm.c (warn_on_restrict_it): Add new variable.
+ (it_fsm_post_encode): Check warn_on_restrict_it.
+ (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.
+ * testsuite/gas/arm/armv8-a-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-a-it-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-r-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-r-it-bad.d: Likewise.
+ * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.
+ * testsuite/gas/arm/udf.d: Likewise.
+
+2018-12-11 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Extend SSE check conditional.
+ * testsuite/gas/i386/sse-check.s: Add SSE4a and SHA tests.
+ Extend GFNI tests.
+ * testsuite/gas/i386/sse-check.d: Adjust expectations.
+ * testsuite/gas/i386/sse-check-error.l,
+ testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.
+ * testsuite/gas/i386/sse-check-warn.e: Likewise.
+
2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
projects / deliverable / binutils-gdb.git / blobdiff