+2019-12-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * write.c (md_generic_table_relax_frag): New. Defined to
+ relax_frag if not defined.
+ (relax_segment): Call md_generic_table_relax_frag instead of
+ relax_frag.
+
+2019-12-12 Alan Modra <amodra@gmail.com>
+
+ * config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow.
+ * config/tc-metag.c (parse_dalu): Likewise.
+ * config/tc-tic4x.c (md_pcrel_from): Likewise.
+ * config/tc-tic6x.c (tic6x_output_unwinding): Likewise.
+ * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer.
+ Don't use register keyword. Avoid signed overflow and remove now
+ unneccesary char masks. Formatting.
+ * config/tc-ia64.c (operand_match): Don't use shifts to sign extend.
+ * config/tc-mep.c (mep_apply_fix): Likewise.
+ * config/tc-pru.c (md_apply_fix): Likewise.
+ * config/tc-riscv.c (load_const): Likewise.
+ * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially
+ truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16
+ calculation.
+
+2019-12-12 Alan Modra <amodra@gmail.com>
+
+ * config/obj-evax.c (crc32, encode_32, encode_16, decode_16):
+ Remove unnecessary prototypes.
+ (number_of_codings): Delete, use ARRAY_SIZE instead throughout.
+ (codings, decodings): Make arrays of unsigned char.
+ (crc32): Use unsigned variables. Delete unnecessary mask.
+ (encode_32, encode_16): Return unsigned char*, and make static
+ buffer an unsigned char array.
+ (decode_16): Make arg an unsigned char*. Remove useless casts.
+ (shorten_identifier): Use unsigned char crc_chars.
+ (is_truncated_identifier): Make ptr an unsigned char*.
+
+2019-12-11 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/tc-arm.c (warn_on_restrict_it): Add new variable.
+ (it_fsm_post_encode): Check warn_on_restrict_it.
+ (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.
+ * testsuite/gas/arm/armv8-a-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-a-it-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-r-bad.d: Likewise.
+ * testsuite/gas/arm/armv8-r-it-bad.d: Likewise.
+ * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.
+ * testsuite/gas/arm/udf.d: Likewise.
+
+2018-12-11 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Extend SSE check conditional.
+ * testsuite/gas/i386/sse-check.s: Add SSE4a and SHA tests.
+ Extend GFNI tests.
+ * testsuite/gas/i386/sse-check.d: Adjust expectations.
+ * testsuite/gas/i386/sse-check-error.l,
+ testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.
+ * testsuite/gas/i386/sse-check-warn.e: Likewise.
+
+2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
+
+ * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
+ * testsuite/gas/arm/mve-arch-ext.s: New.
+ * testsuite/gas/arm/mve-arch-ext.d: New.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (O_oword_ptr): Move.
+ (O_xmmword_ptr): Alias to O_oword_ptr.
+ (O_fword_ptr, O_tbyte_ptr, O_ymmword_ptr, O_zmmword_ptr): Adjust
+ expansion.
+ (i386_intel_simplify, i386_intel_operand): Fold O_oword_ptr and
+ O_xmmword_ptr cases, leaving comments.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (O_mmword_ptr): Define.
+ (i386_types): Add mmword entry.
+ (i386_intel_simplify, i386_intel_operand): Add comment.
+ * testsuite/gas/i386/intel-expr.s: Also test mmword and zmmword.
+ * testsuite/gas/i386/intelok.s: Also test "mmword ptr".
+ * testsuite/gas/i386/intel-expr.d, testsuite/gas/i386/intelok.d,
+ testsuite/gas/i386/intelok.e: Adjust expectations.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Set "byte"
+ attribute suffix instead of suffix for floating point insns when
+ handling O_near_ptr / O_far_ptr.
+ * testsuite/gas/i386/intelbad.s: Add FPU tests.
+ * testsuite/gas/i386/intelbad.l: Adjust expectations.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Set "byte"
+ attribute suffix instead of suffix uniformly for insns not
+ possibly accepting "tbyte ptr" explicitly.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Don't set suffix
+ for floating point insns when handling O_fword_ptr.
+
+2019-12-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Don't special
+ case LDS et al when handling O_word_ptr.
+
+2019-12-08 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output.
+ * testsuite/gas/aarch64/dgh.d: Likewise.
+ * testsuite/gas/aarch64/f32mm.d: Likewise.
+ * testsuite/gas/aarch64/f64mm.d: Likewise.
+ * testsuite/gas/aarch64/i8mm.d: Likewise.
+ * testsuite/gas/aarch64/pac_ab_key.d: Likewise.
+ * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
+ * testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.
+ * testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.
+ * testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.
+ * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise.
+ * testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise.
+ * testsuite/gas/aarch64/sve2.d: Likewise.
+
+2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state.
+ * testsuite/gas/aarch64/pac_negate_ra_state.s: New file.
+ * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
+
+2019-12-05 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-aarch64.c (aarch64_features): Drop redundant AES and
+ SHA2 flags from "crypto" entry.
+
+2019-12-05 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-aarch64.c (aarch64_features): Make SHA2 a prereq of
+ SHA3.
+ * testsuite/gas/aarch64/crypto.s
+ * testsuite/gas/aarch64/crypto-directive.d: Refer to crypto.d
+ for actual output.
+ * testsuite/gas/aarch64/illegal-crypto-nofp.l: Relax
+ expectations.
+ * testsuite/gas/aarch64/crypto-directive2.d,
+ testsuite/gas/aarch64/crypto-directive3.d: New.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Handle LFS et al
+ as well as LGDT at al when processing O_tbyte_ptr.
+ * testsuite/gas/i386/intelbad.s: Add LDS et al cases.
+ * testsuite/gas/i386/x86-64-intel64.s,
+ * testsuite/gas/i386/x86-64-opcode.s: Add LFS et al cases.
+ * testsuite/gas/i386/ilp32/x86-64-intel64.d: Add -mintel64
+ command line option and fold expectations with parent dir test.
+ * testsuite/gas/i386/x86-64-intel64.d: Add -mintel64 command
+ line option and adjust expectations.
+ * testsuite/gas/i386/intelbad.l,
+ testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Also handle DWORD
+ with 64-bit mode branches.
+ * testsuite/gas/i386/x86-64-jump.s: Extend Intel syntax branch
+ operand coverage.
+ * testsuite/gas/i386/x86-64-jump.d: Adjust expectations.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (output_insn): Don't consider Cpu* settings
+ when setting GNU_PROPERTY_X86_FEATURE_2_MMX.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/movdir.s: Add Intel syntax case with
+ operand size specifier.
+ * testsuite/gas/i386/x86-64-movdir.s: Add Intel syntax cases
+ with operand size specifier and wit 32-bit operands.
+ * testsuite/gas/i386/movdir-intel.d,
+ testsuite/gas/i386/movdir.d,
+ testsuite/gas/i386/x86-64-movdir-intel.d,
+ testsuite/gas/i386/x86-64-movdir.d: Adjust expectations.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Arrange for insns with a
+ single non-GPR register operand to not have its suffix guessed
+ from GPR operands. Extend DefaultSize handling to cover PUSH/POP
+ of segment registers.
+ * testsuite/gas/i386/general.s: Add PUSH/POP sreg to .code16gcc
+ set of insns.
+ * testsuite/gas/i386/general.l: Adjust expectations.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Exclude SYSRET alongside
+ FLDENV et al.
+ * testsuite/gas/i386/general.s: Expand .code16gcc set of insns.
+ * testsuite/gas/i386/general.l: Adjust expectations.
+
+2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * as.c (flag_dwarf_cie_version): Change initial value to -1, and
+ update comment.
+ * config/tc-riscv.c (riscv_after_parse_args): Set
+ flag_dwarf_cie_version if it has not already been set.
+ * dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if
+ needed.
+ * testsuite/gas/riscv/default-cie-version.d: New file.
+ * testsuite/gas/riscv/default-cie-version.s: New file.
+
+2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * dw2gencfi.c (output_cie): Error on return column overflow.
+ * testsuite/gas/riscv/cie-rtn-col-1.d: New file.
+ * testsuite/gas/riscv/cie-rtn-col-3.d: New file.
+ * testsuite/gas/riscv/cie-rtn-col.s: New file.
+
2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR
projects / deliverable / binutils-gdb.git / blobdiff